OpenWrt – Blame information for rev 4
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Rev | Author | Line No. | Line |
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4 | office | 1 | From d42ebed1aa669c5a897ec0aa5e1ede8d9069894a Mon Sep 17 00:00:00 2001 |
2 | From: Chunfeng Yun <chunfeng.yun@mediatek.com> |
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3 | Date: Thu, 21 Sep 2017 18:31:49 +0800 |
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4 | Subject: [PATCH 125/224] phy: phy-mtk-tphy: add set_mode callback |
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5 | |||
6 | This is used to force PHY with USB OTG function to enter a specific |
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7 | mode, and override OTG IDPIN(or IDDIG) signal. |
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8 | |||
9 | Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> |
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10 | Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> |
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11 | --- |
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12 | drivers/phy/mediatek/phy-mtk-tphy.c | 39 +++++++++++++++++++++++++++++++++++++ |
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13 | 1 file changed, 39 insertions(+) |
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14 | |||
15 | --- a/drivers/phy/mediatek/phy-mtk-tphy.c |
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16 | +++ b/drivers/phy/mediatek/phy-mtk-tphy.c |
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17 | @@ -96,9 +96,11 @@ |
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18 | |||
19 | #define U3P_U2PHYDTM1 0x06C |
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20 | #define P2C_RG_UART_EN BIT(16) |
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21 | +#define P2C_FORCE_IDDIG BIT(9) |
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22 | #define P2C_RG_VBUSVALID BIT(5) |
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23 | #define P2C_RG_SESSEND BIT(4) |
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24 | #define P2C_RG_AVALID BIT(2) |
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25 | +#define P2C_RG_IDDIG BIT(1) |
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26 | |||
27 | #define U3P_U3_CHIP_GPIO_CTLD 0x0c |
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28 | #define P3C_REG_IP_SW_RST BIT(31) |
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29 | @@ -580,6 +582,31 @@ static void u2_phy_instance_exit(struct |
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30 | } |
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31 | } |
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32 | |||
33 | +static void u2_phy_instance_set_mode(struct mtk_tphy *tphy, |
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34 | + struct mtk_phy_instance *instance, |
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35 | + enum phy_mode mode) |
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36 | +{ |
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37 | + struct u2phy_banks *u2_banks = &instance->u2_banks; |
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38 | + u32 tmp; |
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39 | + |
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40 | + tmp = readl(u2_banks->com + U3P_U2PHYDTM1); |
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41 | + switch (mode) { |
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42 | + case PHY_MODE_USB_DEVICE: |
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43 | + tmp |= P2C_FORCE_IDDIG | P2C_RG_IDDIG; |
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44 | + break; |
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45 | + case PHY_MODE_USB_HOST: |
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46 | + tmp |= P2C_FORCE_IDDIG; |
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47 | + tmp &= ~P2C_RG_IDDIG; |
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48 | + break; |
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49 | + case PHY_MODE_USB_OTG: |
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50 | + tmp &= ~(P2C_FORCE_IDDIG | P2C_RG_IDDIG); |
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51 | + break; |
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52 | + default: |
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53 | + return; |
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54 | + } |
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55 | + writel(tmp, u2_banks->com + U3P_U2PHYDTM1); |
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56 | +} |
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57 | + |
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58 | static void pcie_phy_instance_init(struct mtk_tphy *tphy, |
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59 | struct mtk_phy_instance *instance) |
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60 | { |
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61 | @@ -876,6 +903,17 @@ static int mtk_phy_exit(struct phy *phy) |
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62 | return 0; |
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63 | } |
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64 | |||
65 | +static int mtk_phy_set_mode(struct phy *phy, enum phy_mode mode) |
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66 | +{ |
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67 | + struct mtk_phy_instance *instance = phy_get_drvdata(phy); |
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68 | + struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); |
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69 | + |
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70 | + if (instance->type == PHY_TYPE_USB2) |
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71 | + u2_phy_instance_set_mode(tphy, instance, mode); |
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72 | + |
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73 | + return 0; |
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74 | +} |
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75 | + |
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76 | static struct phy *mtk_phy_xlate(struct device *dev, |
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77 | struct of_phandle_args *args) |
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78 | { |
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79 | @@ -926,6 +964,7 @@ static const struct phy_ops mtk_tphy_ops |
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80 | .exit = mtk_phy_exit, |
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81 | .power_on = mtk_phy_power_on, |
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82 | .power_off = mtk_phy_power_off, |
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83 | + .set_mode = mtk_phy_set_mode, |
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84 | .owner = THIS_MODULE, |
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85 | }; |
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86 |