OpenWrt – Blame information for rev 4
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Rev | Author | Line No. | Line |
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4 | office | 1 | From f452518c982e57538e6d49da0a2c80eef22087ab Mon Sep 17 00:00:00 2001 |
2 | From: Mathias Kresin <dev@kresin.me> |
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3 | Date: Thu, 22 Mar 2018 23:31:39 +0100 |
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4 | Subject: [PATCH 2/2] net: phy: intel-xway: add VR9 v1.1 phy ids |
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5 | |||
6 | The phys embedded into the v1.1 of the VR9 SoC are using different phy |
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7 | ids. Add the phy ids to use the driver for this VR9 version as well. |
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8 | |||
9 | Signed-off-by: Mathias Kresin <dev@kresin.me> |
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10 | Signed-off-by: David S. Miller <davem@davemloft.net> |
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11 | --- |
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12 | drivers/net/phy/intel-xway.c | 28 ++++++++++++++++++++++++++++ |
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13 | 1 file changed, 28 insertions(+) |
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14 | |||
15 | --- a/drivers/net/phy/intel-xway.c |
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16 | +++ b/drivers/net/phy/intel-xway.c |
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17 | @@ -149,6 +149,8 @@ |
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18 | #define PHY_ID_PHY22F_1_4 0xD565A410 |
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19 | #define PHY_ID_PHY11G_1_5 0xD565A401 |
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20 | #define PHY_ID_PHY22F_1_5 0xD565A411 |
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21 | +#define PHY_ID_PHY11G_VR9_1_1 0xD565A408 |
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22 | +#define PHY_ID_PHY22F_VR9_1_1 0xD565A418 |
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23 | #define PHY_ID_PHY11G_VR9_1_2 0xD565A409 |
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24 | #define PHY_ID_PHY22F_VR9_1_2 0xD565A419 |
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25 | |||
26 | @@ -372,6 +374,36 @@ static struct phy_driver xway_gphy[] = { |
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27 | .suspend = genphy_suspend, |
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28 | .resume = genphy_resume, |
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29 | }, { |
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30 | + .phy_id = PHY_ID_PHY11G_VR9_1_1, |
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31 | + .phy_id_mask = 0xffffffff, |
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32 | + .name = "Intel XWAY PHY11G (xRX v1.1 integrated)", |
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33 | + .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause | |
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34 | + SUPPORTED_Asym_Pause), |
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35 | + .flags = PHY_HAS_INTERRUPT, |
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36 | + .config_init = xway_gphy_config_init, |
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37 | + .config_aneg = genphy_config_aneg, |
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38 | + .read_status = genphy_read_status, |
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39 | + .ack_interrupt = xway_gphy_ack_interrupt, |
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40 | + .did_interrupt = xway_gphy_did_interrupt, |
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41 | + .config_intr = xway_gphy_config_intr, |
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42 | + .suspend = genphy_suspend, |
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43 | + .resume = genphy_resume, |
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44 | + }, { |
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45 | + .phy_id = PHY_ID_PHY22F_VR9_1_1, |
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46 | + .phy_id_mask = 0xffffffff, |
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47 | + .name = "Intel XWAY PHY22F (xRX v1.1 integrated)", |
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48 | + .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause | |
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49 | + SUPPORTED_Asym_Pause), |
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50 | + .flags = PHY_HAS_INTERRUPT, |
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51 | + .config_init = xway_gphy_config_init, |
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52 | + .config_aneg = genphy_config_aneg, |
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53 | + .read_status = genphy_read_status, |
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54 | + .ack_interrupt = xway_gphy_ack_interrupt, |
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55 | + .did_interrupt = xway_gphy_did_interrupt, |
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56 | + .config_intr = xway_gphy_config_intr, |
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57 | + .suspend = genphy_suspend, |
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58 | + .resume = genphy_resume, |
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59 | + }, { |
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60 | .phy_id = PHY_ID_PHY11G_VR9_1_2, |
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61 | .phy_id_mask = 0xffffffff, |
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62 | .name = "Intel XWAY PHY11G (xRX v1.2 integrated)", |
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63 | @@ -412,6 +444,8 @@ static struct mdio_device_id __maybe_unu |
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64 | { PHY_ID_PHY22F_1_4, 0xffffffff }, |
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65 | { PHY_ID_PHY11G_1_5, 0xffffffff }, |
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66 | { PHY_ID_PHY22F_1_5, 0xffffffff }, |
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67 | + { PHY_ID_PHY11G_VR9_1_1, 0xffffffff }, |
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68 | + { PHY_ID_PHY22F_VR9_1_1, 0xffffffff }, |
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69 | { PHY_ID_PHY11G_VR9_1_2, 0xffffffff }, |
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70 | { PHY_ID_PHY22F_VR9_1_2, 0xffffffff }, |
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71 | { } |