OpenWrt – Blame information for rev 4
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Rev | Author | Line No. | Line |
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4 | office | 1 | From 870ed9cae083ff8a60a739ef7e74c5a1800533be Mon Sep 17 00:00:00 2001 |
2 | From: John Crispin <blogic@openwrt.org> |
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3 | Date: Tue, 9 Sep 2014 22:45:34 +0200 |
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4 | Subject: [PATCH 28/36] NET: lantiq: various etop fixes |
||
5 | |||
6 | Signed-off-by: John Crispin <blogic@openwrt.org> |
||
7 | --- |
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8 | drivers/net/ethernet/lantiq_etop.c | 555 +++++++++++++++++++++++++----------- |
||
9 | 1 file changed, 389 insertions(+), 166 deletions(-) |
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10 | |||
11 | --- a/drivers/net/ethernet/lantiq_etop.c |
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12 | +++ b/drivers/net/ethernet/lantiq_etop.c |
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13 | @@ -11,7 +11,7 @@ |
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14 | * You should have received a copy of the GNU General Public License |
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15 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
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16 | * |
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17 | - * Copyright (C) 2011 John Crispin <blogic@openwrt.org> |
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18 | + * Copyright (C) 2011-12 John Crispin <blogic@openwrt.org> |
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19 | */ |
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20 | |||
21 | #include <linux/kernel.h> |
||
22 | @@ -30,11 +30,16 @@ |
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23 | #include <linux/mm.h> |
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24 | #include <linux/platform_device.h> |
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25 | #include <linux/ethtool.h> |
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26 | +#include <linux/if_vlan.h> |
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27 | #include <linux/init.h> |
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28 | #include <linux/delay.h> |
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29 | #include <linux/io.h> |
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30 | #include <linux/dma-mapping.h> |
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31 | #include <linux/module.h> |
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32 | +#include <linux/clk.h> |
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33 | +#include <linux/of_net.h> |
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34 | +#include <linux/of_irq.h> |
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35 | +#include <linux/of_platform.h> |
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36 | |||
37 | #include <asm/checksum.h> |
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38 | |||
39 | @@ -42,7 +47,7 @@ |
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40 | #include <xway_dma.h> |
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41 | #include <lantiq_platform.h> |
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42 | |||
43 | -#define LTQ_ETOP_MDIO 0x11804 |
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44 | +#define LTQ_ETOP_MDIO_ACC 0x11804 |
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45 | #define MDIO_REQUEST 0x80000000 |
||
46 | #define MDIO_READ 0x40000000 |
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47 | #define MDIO_ADDR_MASK 0x1f |
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48 | @@ -51,44 +56,91 @@ |
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49 | #define MDIO_REG_OFFSET 0x10 |
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50 | #define MDIO_VAL_MASK 0xffff |
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51 | |||
52 | -#define PPE32_CGEN 0x800 |
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53 | -#define LQ_PPE32_ENET_MAC_CFG 0x1840 |
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54 | +#define LTQ_ETOP_MDIO_CFG 0x11800 |
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55 | +#define MDIO_CFG_MASK 0x6 |
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56 | + |
||
57 | +#define LTQ_ETOP_CFG 0x11808 |
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58 | +#define LTQ_ETOP_IGPLEN 0x11820 |
||
59 | +#define LTQ_ETOP_MAC_CFG 0x11840 |
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60 | |||
61 | #define LTQ_ETOP_ENETS0 0x11850 |
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62 | #define LTQ_ETOP_MAC_DA0 0x1186C |
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63 | #define LTQ_ETOP_MAC_DA1 0x11870 |
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64 | -#define LTQ_ETOP_CFG 0x16020 |
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65 | -#define LTQ_ETOP_IGPLEN 0x16080 |
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66 | + |
||
67 | +#define MAC_CFG_MASK 0xfff |
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68 | +#define MAC_CFG_CGEN (1 << 11) |
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69 | +#define MAC_CFG_DUPLEX (1 << 2) |
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70 | +#define MAC_CFG_SPEED (1 << 1) |
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71 | +#define MAC_CFG_LINK (1 << 0) |
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72 | |||
73 | #define MAX_DMA_CHAN 0x8 |
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74 | #define MAX_DMA_CRC_LEN 0x4 |
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75 | #define MAX_DMA_DATA_LEN 0x600 |
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76 | |||
77 | #define ETOP_FTCU BIT(28) |
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78 | -#define ETOP_MII_MASK 0xf |
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79 | -#define ETOP_MII_NORMAL 0xd |
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80 | -#define ETOP_MII_REVERSE 0xe |
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81 | #define ETOP_PLEN_UNDER 0x40 |
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82 | -#define ETOP_CGEN 0x800 |
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83 | +#define ETOP_CFG_MII0 0x01 |
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84 | |||
85 | -/* use 2 static channels for TX/RX */ |
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86 | -#define LTQ_ETOP_TX_CHANNEL 1 |
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87 | -#define LTQ_ETOP_RX_CHANNEL 6 |
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88 | -#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL) |
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89 | -#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL) |
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90 | +#define ETOP_CFG_MASK 0xfff |
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91 | +#define ETOP_CFG_FEN0 (1 << 8) |
||
92 | +#define ETOP_CFG_SEN0 (1 << 6) |
||
93 | +#define ETOP_CFG_OFF1 (1 << 3) |
||
94 | +#define ETOP_CFG_REMII0 (1 << 1) |
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95 | +#define ETOP_CFG_OFF0 (1 << 0) |
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96 | + |
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97 | +#define LTQ_GBIT_MDIO_CTL 0xCC |
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98 | +#define LTQ_GBIT_MDIO_DATA 0xd0 |
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99 | +#define LTQ_GBIT_GCTL0 0x68 |
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100 | +#define LTQ_GBIT_PMAC_HD_CTL 0x8c |
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101 | +#define LTQ_GBIT_P0_CTL 0x4 |
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102 | +#define LTQ_GBIT_PMAC_RX_IPG 0xa8 |
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103 | +#define LTQ_GBIT_RGMII_CTL 0x78 |
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104 | + |
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105 | +#define PMAC_HD_CTL_AS (1 << 19) |
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106 | +#define PMAC_HD_CTL_RXSH (1 << 22) |
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107 | + |
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108 | +/* Switch Enable (0=disable, 1=enable) */ |
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109 | +#define GCTL0_SE 0x80000000 |
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110 | +/* Disable MDIO auto polling (0=disable, 1=enable) */ |
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111 | +#define PX_CTL_DMDIO 0x00400000 |
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112 | + |
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113 | +/* MDC clock divider, clock = 25MHz/((MDC_CLOCK + 1) * 2) */ |
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114 | +#define MDC_CLOCK_MASK 0xff000000 |
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115 | +#define MDC_CLOCK_OFFSET 24 |
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116 | + |
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117 | +/* register information for the gbit's MDIO bus */ |
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118 | +#define MDIO_XR9_REQUEST 0x00008000 |
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119 | +#define MDIO_XR9_READ 0x00000800 |
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120 | +#define MDIO_XR9_WRITE 0x00000400 |
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121 | +#define MDIO_XR9_REG_MASK 0x1f |
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122 | +#define MDIO_XR9_ADDR_MASK 0x1f |
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123 | +#define MDIO_XR9_RD_MASK 0xffff |
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124 | +#define MDIO_XR9_REG_OFFSET 0 |
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125 | +#define MDIO_XR9_ADDR_OFFSET 5 |
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126 | +#define MDIO_XR9_WR_OFFSET 16 |
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127 | |||
128 | +#define LTQ_DMA_ETOP ((of_machine_is_compatible("lantiq,ase")) ? \ |
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129 | + (INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0)) |
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130 | + |
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131 | +/* the newer xway socks have a embedded 3/7 port gbit multiplexer */ |
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132 | #define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x)) |
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133 | #define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y)) |
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134 | #define ltq_etop_w32_mask(x, y, z) \ |
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135 | ltq_w32_mask(x, y, ltq_etop_membase + (z)) |
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136 | |||
137 | -#define DRV_VERSION "1.0" |
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138 | +#define ltq_gbit_r32(x) ltq_r32(ltq_gbit_membase + (x)) |
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139 | +#define ltq_gbit_w32(x, y) ltq_w32(x, ltq_gbit_membase + (y)) |
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140 | +#define ltq_gbit_w32_mask(x, y, z) \ |
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141 | + ltq_w32_mask(x, y, ltq_gbit_membase + (z)) |
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142 | + |
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143 | +#define DRV_VERSION "1.2" |
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144 | |||
145 | static void __iomem *ltq_etop_membase; |
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146 | +static void __iomem *ltq_gbit_membase; |
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147 | |||
148 | struct ltq_etop_chan { |
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149 | - int idx; |
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150 | int tx_free; |
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151 | + int irq; |
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152 | struct net_device *netdev; |
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153 | struct napi_struct napi; |
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154 | struct ltq_dma_channel dma; |
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155 | @@ -98,21 +150,34 @@ struct ltq_etop_chan { |
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156 | struct ltq_etop_priv { |
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157 | struct net_device *netdev; |
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158 | struct platform_device *pdev; |
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159 | - struct ltq_eth_data *pldata; |
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160 | struct resource *res; |
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161 | |||
162 | struct mii_bus *mii_bus; |
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163 | |||
164 | - struct ltq_etop_chan ch[MAX_DMA_CHAN]; |
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165 | - int tx_free[MAX_DMA_CHAN >> 1]; |
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166 | + struct ltq_etop_chan txch; |
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167 | + struct ltq_etop_chan rxch; |
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168 | + |
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169 | + int tx_irq; |
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170 | + int rx_irq; |
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171 | + |
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172 | + unsigned char mac[6]; |
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173 | + int mii_mode; |
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174 | |||
175 | spinlock_t lock; |
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176 | + |
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177 | + struct clk *clk_ppe; |
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178 | + struct clk *clk_switch; |
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179 | + struct clk *clk_ephy; |
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180 | + struct clk *clk_ephycgu; |
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181 | }; |
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182 | |||
183 | +static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, |
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184 | + int phy_reg, u16 phy_data); |
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185 | + |
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186 | static int |
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187 | ltq_etop_alloc_skb(struct ltq_etop_chan *ch) |
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188 | { |
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189 | - ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN); |
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190 | + ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN); |
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191 | if (!ch->skb[ch->dma.desc]) |
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192 | return -ENOMEM; |
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193 | ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL, |
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194 | @@ -147,8 +212,11 @@ ltq_etop_hw_receive(struct ltq_etop_chan |
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195 | spin_unlock_irqrestore(&priv->lock, flags); |
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196 | |||
197 | skb_put(skb, len); |
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198 | + skb->dev = ch->netdev; |
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199 | skb->protocol = eth_type_trans(skb, ch->netdev); |
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200 | netif_receive_skb(skb); |
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201 | + ch->netdev->stats.rx_packets++; |
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202 | + ch->netdev->stats.rx_bytes += len; |
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203 | } |
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204 | |||
205 | static int |
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206 | @@ -156,7 +224,9 @@ ltq_etop_poll_rx(struct napi_struct *nap |
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207 | { |
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208 | struct ltq_etop_chan *ch = container_of(napi, |
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209 | struct ltq_etop_chan, napi); |
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210 | + struct ltq_etop_priv *priv = netdev_priv(ch->netdev); |
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211 | int work_done = 0; |
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212 | + unsigned long flags; |
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213 | |||
214 | while (work_done < budget) { |
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215 | struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; |
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216 | @@ -168,7 +238,9 @@ ltq_etop_poll_rx(struct napi_struct *nap |
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217 | } |
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218 | if (work_done < budget) { |
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219 | napi_complete_done(&ch->napi, work_done); |
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220 | + spin_lock_irqsave(&priv->lock, flags); |
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221 | ltq_dma_ack_irq(&ch->dma); |
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222 | + spin_unlock_irqrestore(&priv->lock, flags); |
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223 | } |
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224 | return work_done; |
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225 | } |
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226 | @@ -180,12 +252,14 @@ ltq_etop_poll_tx(struct napi_struct *nap |
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227 | container_of(napi, struct ltq_etop_chan, napi); |
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228 | struct ltq_etop_priv *priv = netdev_priv(ch->netdev); |
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229 | struct netdev_queue *txq = |
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230 | - netdev_get_tx_queue(ch->netdev, ch->idx >> 1); |
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231 | + netdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1); |
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232 | unsigned long flags; |
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233 | |||
234 | spin_lock_irqsave(&priv->lock, flags); |
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235 | while ((ch->dma.desc_base[ch->tx_free].ctl & |
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236 | (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { |
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237 | + ch->netdev->stats.tx_packets++; |
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238 | + ch->netdev->stats.tx_bytes += ch->skb[ch->tx_free]->len; |
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239 | dev_kfree_skb_any(ch->skb[ch->tx_free]); |
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240 | ch->skb[ch->tx_free] = NULL; |
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241 | memset(&ch->dma.desc_base[ch->tx_free], 0, |
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242 | @@ -198,7 +272,9 @@ ltq_etop_poll_tx(struct napi_struct *nap |
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243 | if (netif_tx_queue_stopped(txq)) |
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244 | netif_tx_start_queue(txq); |
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245 | napi_complete(&ch->napi); |
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246 | + spin_lock_irqsave(&priv->lock, flags); |
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247 | ltq_dma_ack_irq(&ch->dma); |
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248 | + spin_unlock_irqrestore(&priv->lock, flags); |
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249 | return 1; |
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250 | } |
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251 | |||
252 | @@ -206,9 +282,10 @@ static irqreturn_t |
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253 | ltq_etop_dma_irq(int irq, void *_priv) |
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254 | { |
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255 | struct ltq_etop_priv *priv = _priv; |
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256 | - int ch = irq - LTQ_DMA_CH0_INT; |
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257 | - |
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258 | - napi_schedule(&priv->ch[ch].napi); |
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259 | + if (irq == priv->txch.dma.irq) |
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260 | + napi_schedule(&priv->txch.napi); |
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261 | + else |
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262 | + napi_schedule(&priv->rxch.napi); |
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263 | return IRQ_HANDLED; |
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264 | } |
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265 | |||
266 | @@ -220,7 +297,7 @@ ltq_etop_free_channel(struct net_device |
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267 | ltq_dma_free(&ch->dma); |
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268 | if (ch->dma.irq) |
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269 | free_irq(ch->dma.irq, priv); |
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270 | - if (IS_RX(ch->idx)) { |
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271 | + if (ch == &priv->txch) { |
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272 | int desc; |
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273 | for (desc = 0; desc < LTQ_DESC_NUM; desc++) |
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274 | dev_kfree_skb_any(ch->skb[ch->dma.desc]); |
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275 | @@ -231,65 +308,133 @@ static void |
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276 | ltq_etop_hw_exit(struct net_device *dev) |
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277 | { |
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278 | struct ltq_etop_priv *priv = netdev_priv(dev); |
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279 | - int i; |
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280 | |||
281 | - ltq_pmu_disable(PMU_PPE); |
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282 | - for (i = 0; i < MAX_DMA_CHAN; i++) |
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283 | - if (IS_TX(i) || IS_RX(i)) |
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284 | - ltq_etop_free_channel(dev, &priv->ch[i]); |
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285 | + clk_disable(priv->clk_ppe); |
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286 | + |
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287 | + if (of_machine_is_compatible("lantiq,ar9")) |
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288 | + clk_disable(priv->clk_switch); |
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289 | + |
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290 | + if (of_machine_is_compatible("lantiq,ase")) { |
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291 | + clk_disable(priv->clk_ephy); |
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292 | + clk_disable(priv->clk_ephycgu); |
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293 | + } |
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294 | + |
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295 | + ltq_etop_free_channel(dev, &priv->txch); |
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296 | + ltq_etop_free_channel(dev, &priv->rxch); |
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297 | +} |
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298 | + |
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299 | +static void |
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300 | +ltq_etop_gbit_init(struct net_device *dev) |
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301 | +{ |
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302 | + struct ltq_etop_priv *priv = netdev_priv(dev); |
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303 | + |
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304 | + clk_enable(priv->clk_switch); |
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305 | + |
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306 | + /* enable gbit port0 on the SoC */ |
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307 | + ltq_gbit_w32_mask((1 << 17), (1 << 18), LTQ_GBIT_P0_CTL); |
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308 | + |
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309 | + ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0); |
||
310 | + /* disable MDIO auto polling mode */ |
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311 | + ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL); |
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312 | + /* set 1522 packet size */ |
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313 | + ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0); |
||
314 | + /* disable pmac & dmac headers */ |
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315 | + ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0, |
||
316 | + LTQ_GBIT_PMAC_HD_CTL); |
||
317 | + /* Due to traffic halt when burst length 8, |
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318 | + replace default IPG value with 0x3B */ |
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319 | + ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG); |
||
320 | + /* set mdc clock to 2.5 MHz */ |
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321 | + ltq_gbit_w32_mask(MDC_CLOCK_MASK, 4 << MDC_CLOCK_OFFSET, |
||
322 | + LTQ_GBIT_RGMII_CTL); |
||
323 | } |
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324 | |||
325 | static int |
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326 | ltq_etop_hw_init(struct net_device *dev) |
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327 | { |
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328 | struct ltq_etop_priv *priv = netdev_priv(dev); |
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329 | - int i; |
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330 | + int mii_mode = priv->mii_mode; |
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331 | |||
332 | - ltq_pmu_enable(PMU_PPE); |
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333 | + clk_enable(priv->clk_ppe); |
||
334 | |||
335 | - switch (priv->pldata->mii_mode) { |
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336 | + if (of_machine_is_compatible("lantiq,ar9")) { |
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337 | + ltq_etop_gbit_init(dev); |
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338 | + /* force the etops link to the gbit to MII */ |
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339 | + mii_mode = PHY_INTERFACE_MODE_MII; |
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340 | + } |
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341 | + ltq_etop_w32_mask(MDIO_CFG_MASK, 0, LTQ_ETOP_MDIO_CFG); |
||
342 | + ltq_etop_w32_mask(MAC_CFG_MASK, MAC_CFG_CGEN | MAC_CFG_DUPLEX | |
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343 | + MAC_CFG_SPEED | MAC_CFG_LINK, LTQ_ETOP_MAC_CFG); |
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344 | + |
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345 | + switch (mii_mode) { |
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346 | case PHY_INTERFACE_MODE_RMII: |
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347 | - ltq_etop_w32_mask(ETOP_MII_MASK, |
||
348 | - ETOP_MII_REVERSE, LTQ_ETOP_CFG); |
||
349 | + ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_REMII0 | ETOP_CFG_OFF1 | |
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350 | + ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG); |
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351 | break; |
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352 | |||
353 | case PHY_INTERFACE_MODE_MII: |
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354 | - ltq_etop_w32_mask(ETOP_MII_MASK, |
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355 | - ETOP_MII_NORMAL, LTQ_ETOP_CFG); |
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356 | + ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_OFF1 | |
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357 | + ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG); |
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358 | break; |
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359 | |||
360 | default: |
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361 | + if (of_machine_is_compatible("lantiq,ase")) { |
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362 | + clk_enable(priv->clk_ephy); |
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363 | + /* disable external MII */ |
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364 | + ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG); |
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365 | + /* enable clock for internal PHY */ |
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366 | + clk_enable(priv->clk_ephycgu); |
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367 | + /* we need to write this magic to the internal phy to |
||
368 | + make it work */ |
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369 | + ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020); |
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370 | + pr_info("Selected EPHY mode\n"); |
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371 | + break; |
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372 | + } |
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373 | netdev_err(dev, "unknown mii mode %d\n", |
||
374 | - priv->pldata->mii_mode); |
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375 | + mii_mode); |
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376 | return -ENOTSUPP; |
||
377 | } |
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378 | |||
379 | - /* enable crc generation */ |
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380 | - ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG); |
||
381 | + return 0; |
||
382 | +} |
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383 | + |
||
384 | +static int |
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385 | +ltq_etop_dma_init(struct net_device *dev) |
||
386 | +{ |
||
387 | + struct ltq_etop_priv *priv = netdev_priv(dev); |
||
388 | + int tx = priv->tx_irq - LTQ_DMA_ETOP; |
||
389 | + int rx = priv->rx_irq - LTQ_DMA_ETOP; |
||
390 | + int err; |
||
391 | |||
392 | ltq_dma_init_port(DMA_PORT_ETOP); |
||
393 | |||
394 | - for (i = 0; i < MAX_DMA_CHAN; i++) { |
||
395 | - int irq = LTQ_DMA_CH0_INT + i; |
||
396 | - struct ltq_etop_chan *ch = &priv->ch[i]; |
||
397 | - |
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398 | - ch->idx = ch->dma.nr = i; |
||
399 | - |
||
400 | - if (IS_TX(i)) { |
||
401 | - ltq_dma_alloc_tx(&ch->dma); |
||
402 | - request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv); |
||
403 | - } else if (IS_RX(i)) { |
||
404 | - ltq_dma_alloc_rx(&ch->dma); |
||
405 | - for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM; |
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406 | - ch->dma.desc++) |
||
407 | - if (ltq_etop_alloc_skb(ch)) |
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408 | - return -ENOMEM; |
||
409 | - ch->dma.desc = 0; |
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410 | - request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv); |
||
411 | + priv->txch.dma.nr = tx; |
||
412 | + ltq_dma_alloc_tx(&priv->txch.dma); |
||
413 | + err = request_irq(priv->tx_irq, ltq_etop_dma_irq, 0, "eth_tx", priv); |
||
414 | + if (err) { |
||
415 | + netdev_err(dev, "failed to allocate tx irq\n"); |
||
416 | + goto err_out; |
||
417 | + } |
||
418 | + priv->txch.dma.irq = priv->tx_irq; |
||
419 | + |
||
420 | + priv->rxch.dma.nr = rx; |
||
421 | + ltq_dma_alloc_rx(&priv->rxch.dma); |
||
422 | + for (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM; |
||
423 | + priv->rxch.dma.desc++) { |
||
424 | + if (ltq_etop_alloc_skb(&priv->rxch)) { |
||
425 | + netdev_err(dev, "failed to allocate skbs\n"); |
||
426 | + err = -ENOMEM; |
||
427 | + goto err_out; |
||
428 | } |
||
429 | - ch->dma.irq = irq; |
||
430 | } |
||
431 | - return 0; |
||
432 | + priv->rxch.dma.desc = 0; |
||
433 | + err = request_irq(priv->rx_irq, ltq_etop_dma_irq, 0, "eth_rx", priv); |
||
434 | + if (err) |
||
435 | + netdev_err(dev, "failed to allocate rx irq\n"); |
||
436 | + else |
||
437 | + priv->rxch.dma.irq = priv->rx_irq; |
||
438 | +err_out: |
||
439 | + return err; |
||
440 | } |
||
441 | |||
442 | static void |
||
443 | @@ -308,6 +453,39 @@ static const struct ethtool_ops ltq_etop |
||
444 | }; |
||
445 | |||
446 | static int |
||
447 | +ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr, |
||
448 | + int phy_reg, u16 phy_data) |
||
449 | +{ |
||
450 | + u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE | |
||
451 | + (phy_data << MDIO_XR9_WR_OFFSET) | |
||
452 | + ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) | |
||
453 | + ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET); |
||
454 | + |
||
455 | + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) |
||
456 | + ; |
||
457 | + ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL); |
||
458 | + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) |
||
459 | + ; |
||
460 | + return 0; |
||
461 | +} |
||
462 | + |
||
463 | +static int |
||
464 | +ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg) |
||
465 | +{ |
||
466 | + u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ | |
||
467 | + ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) | |
||
468 | + ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET); |
||
469 | + |
||
470 | + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) |
||
471 | + ; |
||
472 | + ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL); |
||
473 | + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) |
||
474 | + ; |
||
475 | + val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK; |
||
476 | + return val; |
||
477 | +} |
||
478 | + |
||
479 | +static int |
||
480 | ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data) |
||
481 | { |
||
482 | u32 val = MDIO_REQUEST | |
||
483 | @@ -315,9 +493,9 @@ ltq_etop_mdio_wr(struct mii_bus *bus, in |
||
484 | ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) | |
||
485 | phy_data; |
||
486 | |||
487 | - while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) |
||
488 | + while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST) |
||
489 | ; |
||
490 | - ltq_etop_w32(val, LTQ_ETOP_MDIO); |
||
491 | + ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC); |
||
492 | return 0; |
||
493 | } |
||
494 | |||
495 | @@ -328,12 +506,12 @@ ltq_etop_mdio_rd(struct mii_bus *bus, in |
||
496 | ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) | |
||
497 | ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET); |
||
498 | |||
499 | - while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) |
||
500 | + while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST) |
||
501 | ; |
||
502 | - ltq_etop_w32(val, LTQ_ETOP_MDIO); |
||
503 | - while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) |
||
504 | + ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC); |
||
505 | + while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST) |
||
506 | ; |
||
507 | - val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK; |
||
508 | + val = ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_VAL_MASK; |
||
509 | return val; |
||
510 | } |
||
511 | |||
512 | @@ -348,8 +526,18 @@ ltq_etop_mdio_probe(struct net_device *d |
||
513 | { |
||
514 | struct ltq_etop_priv *priv = netdev_priv(dev); |
||
515 | struct phy_device *phydev; |
||
516 | + u32 phy_supported = (SUPPORTED_10baseT_Half |
||
517 | + | SUPPORTED_10baseT_Full |
||
518 | + | SUPPORTED_100baseT_Half |
||
519 | + | SUPPORTED_100baseT_Full |
||
520 | + | SUPPORTED_Autoneg |
||
521 | + | SUPPORTED_MII |
||
522 | + | SUPPORTED_TP); |
||
523 | |||
524 | - phydev = phy_find_first(priv->mii_bus); |
||
525 | + if (of_machine_is_compatible("lantiq,ase")) |
||
526 | + phydev = mdiobus_get_phy(priv->mii_bus, 8); |
||
527 | + else |
||
528 | + phydev = mdiobus_get_phy(priv->mii_bus, 0); |
||
529 | |||
530 | if (!phydev) { |
||
531 | netdev_err(dev, "no PHY found\n"); |
||
532 | @@ -357,21 +545,18 @@ ltq_etop_mdio_probe(struct net_device *d |
||
533 | } |
||
534 | |||
535 | phydev = phy_connect(dev, phydev_name(phydev), |
||
536 | - <q_etop_mdio_link, priv->pldata->mii_mode); |
||
537 | + <q_etop_mdio_link, priv->mii_mode); |
||
538 | |||
539 | if (IS_ERR(phydev)) { |
||
540 | netdev_err(dev, "Could not attach to PHY\n"); |
||
541 | return PTR_ERR(phydev); |
||
542 | } |
||
543 | |||
544 | - phydev->supported &= (SUPPORTED_10baseT_Half |
||
545 | - | SUPPORTED_10baseT_Full |
||
546 | - | SUPPORTED_100baseT_Half |
||
547 | - | SUPPORTED_100baseT_Full |
||
548 | - | SUPPORTED_Autoneg |
||
549 | - | SUPPORTED_MII |
||
550 | - | SUPPORTED_TP); |
||
551 | + if (of_machine_is_compatible("lantiq,ar9")) |
||
552 | + phy_supported |= SUPPORTED_1000baseT_Half |
||
553 | + | SUPPORTED_1000baseT_Full; |
||
554 | |||
555 | + phydev->supported &= phy_supported; |
||
556 | phydev->advertising = phydev->supported; |
||
557 | phy_attached_info(phydev); |
||
558 | |||
559 | @@ -392,8 +577,13 @@ ltq_etop_mdio_init(struct net_device *de |
||
560 | } |
||
561 | |||
562 | priv->mii_bus->priv = dev; |
||
563 | - priv->mii_bus->read = ltq_etop_mdio_rd; |
||
564 | - priv->mii_bus->write = ltq_etop_mdio_wr; |
||
565 | + if (of_machine_is_compatible("lantiq,ar9")) { |
||
566 | + priv->mii_bus->read = ltq_etop_mdio_rd_xr9; |
||
567 | + priv->mii_bus->write = ltq_etop_mdio_wr_xr9; |
||
568 | + } else { |
||
569 | + priv->mii_bus->read = ltq_etop_mdio_rd; |
||
570 | + priv->mii_bus->write = ltq_etop_mdio_wr; |
||
571 | + } |
||
572 | priv->mii_bus->name = "ltq_mii"; |
||
573 | snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", |
||
574 | priv->pdev->name, priv->pdev->id); |
||
575 | @@ -430,17 +620,19 @@ static int |
||
576 | ltq_etop_open(struct net_device *dev) |
||
577 | { |
||
578 | struct ltq_etop_priv *priv = netdev_priv(dev); |
||
579 | - int i; |
||
580 | + unsigned long flags; |
||
581 | |||
582 | - for (i = 0; i < MAX_DMA_CHAN; i++) { |
||
583 | - struct ltq_etop_chan *ch = &priv->ch[i]; |
||
584 | + napi_enable(&priv->txch.napi); |
||
585 | + napi_enable(&priv->rxch.napi); |
||
586 | + |
||
587 | + spin_lock_irqsave(&priv->lock, flags); |
||
588 | + ltq_dma_open(&priv->txch.dma); |
||
589 | + ltq_dma_open(&priv->rxch.dma); |
||
590 | + spin_unlock_irqrestore(&priv->lock, flags); |
||
591 | + |
||
592 | + if (dev->phydev) |
||
593 | + phy_start(dev->phydev); |
||
594 | |||
595 | - if (!IS_TX(i) && (!IS_RX(i))) |
||
596 | - continue; |
||
597 | - ltq_dma_open(&ch->dma); |
||
598 | - napi_enable(&ch->napi); |
||
599 | - } |
||
600 | - phy_start(dev->phydev); |
||
601 | netif_tx_start_all_queues(dev); |
||
602 | return 0; |
||
603 | } |
||
604 | @@ -449,18 +641,19 @@ static int |
||
605 | ltq_etop_stop(struct net_device *dev) |
||
606 | { |
||
607 | struct ltq_etop_priv *priv = netdev_priv(dev); |
||
608 | - int i; |
||
609 | + unsigned long flags; |
||
610 | |||
611 | netif_tx_stop_all_queues(dev); |
||
612 | - phy_stop(dev->phydev); |
||
613 | - for (i = 0; i < MAX_DMA_CHAN; i++) { |
||
614 | - struct ltq_etop_chan *ch = &priv->ch[i]; |
||
615 | - |
||
616 | - if (!IS_RX(i) && !IS_TX(i)) |
||
617 | - continue; |
||
618 | - napi_disable(&ch->napi); |
||
619 | - ltq_dma_close(&ch->dma); |
||
620 | - } |
||
621 | + if (dev->phydev) |
||
622 | + phy_stop(dev->phydev); |
||
623 | + napi_disable(&priv->txch.napi); |
||
624 | + napi_disable(&priv->rxch.napi); |
||
625 | + |
||
626 | + spin_lock_irqsave(&priv->lock, flags); |
||
627 | + ltq_dma_close(&priv->txch.dma); |
||
628 | + ltq_dma_close(&priv->rxch.dma); |
||
629 | + spin_unlock_irqrestore(&priv->lock, flags); |
||
630 | + |
||
631 | return 0; |
||
632 | } |
||
633 | |||
634 | @@ -470,16 +663,16 @@ ltq_etop_tx(struct sk_buff *skb, struct |
||
635 | int queue = skb_get_queue_mapping(skb); |
||
636 | struct netdev_queue *txq = netdev_get_tx_queue(dev, queue); |
||
637 | struct ltq_etop_priv *priv = netdev_priv(dev); |
||
638 | - struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1]; |
||
639 | - struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; |
||
640 | - int len; |
||
641 | + struct ltq_dma_desc *desc = |
||
642 | + &priv->txch.dma.desc_base[priv->txch.dma.desc]; |
||
643 | unsigned long flags; |
||
644 | u32 byte_offset; |
||
645 | + int len; |
||
646 | |||
647 | len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; |
||
648 | |||
649 | - if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) { |
||
650 | - dev_kfree_skb_any(skb); |
||
651 | + if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || |
||
652 | + priv->txch.skb[priv->txch.dma.desc]) { |
||
653 | netdev_err(dev, "tx ring full\n"); |
||
654 | netif_tx_stop_queue(txq); |
||
655 | return NETDEV_TX_BUSY; |
||
656 | @@ -487,7 +680,7 @@ ltq_etop_tx(struct sk_buff *skb, struct |
||
657 | |||
658 | /* dma needs to start on a 16 byte aligned address */ |
||
659 | byte_offset = CPHYSADDR(skb->data) % 16; |
||
660 | - ch->skb[ch->dma.desc] = skb; |
||
661 | + priv->txch.skb[priv->txch.dma.desc] = skb; |
||
662 | |||
663 | netif_trans_update(dev); |
||
664 | |||
665 | @@ -497,11 +690,11 @@ ltq_etop_tx(struct sk_buff *skb, struct |
||
666 | wmb(); |
||
667 | desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP | |
||
668 | LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK); |
||
669 | - ch->dma.desc++; |
||
670 | - ch->dma.desc %= LTQ_DESC_NUM; |
||
671 | + priv->txch.dma.desc++; |
||
672 | + priv->txch.dma.desc %= LTQ_DESC_NUM; |
||
673 | spin_unlock_irqrestore(&priv->lock, flags); |
||
674 | |||
675 | - if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN) |
||
676 | + if (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN) |
||
677 | netif_tx_stop_queue(txq); |
||
678 | |||
679 | return NETDEV_TX_OK; |
||
680 | @@ -515,8 +708,10 @@ ltq_etop_change_mtu(struct net_device *d |
||
681 | |||
682 | dev->mtu = new_mtu; |
||
683 | |||
684 | + int max = ETH_HLEN + VLAN_HLEN + new_mtu + ETH_FCS_LEN; |
||
685 | + |
||
686 | spin_lock_irqsave(&priv->lock, flags); |
||
687 | - ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, LTQ_ETOP_IGPLEN); |
||
688 | + ltq_etop_w32((ETOP_PLEN_UNDER << 16) | max, LTQ_ETOP_IGPLEN); |
||
689 | spin_unlock_irqrestore(&priv->lock, flags); |
||
690 | |||
691 | return 0; |
||
692 | @@ -584,6 +779,9 @@ ltq_etop_init(struct net_device *dev) |
||
693 | if (err) |
||
694 | goto err_hw; |
||
695 | ltq_etop_change_mtu(dev, 1500); |
||
696 | + err = ltq_etop_dma_init(dev); |
||
697 | + if (err) |
||
698 | + goto err_hw; |
||
699 | |||
700 | memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr)); |
||
701 | if (!is_valid_ether_addr(mac.sa_data)) { |
||
702 | @@ -601,9 +799,10 @@ ltq_etop_init(struct net_device *dev) |
||
703 | dev->addr_assign_type = NET_ADDR_RANDOM; |
||
704 | |||
705 | ltq_etop_set_multicast_list(dev); |
||
706 | - err = ltq_etop_mdio_init(dev); |
||
707 | - if (err) |
||
708 | - goto err_netdev; |
||
709 | + if (!ltq_etop_mdio_init(dev)) |
||
710 | + dev->ethtool_ops = <q_etop_ethtool_ops; |
||
711 | + else |
||
712 | + pr_warn("etop: mdio probe failed\n");; |
||
713 | return 0; |
||
714 | |||
715 | err_netdev: |
||
716 | @@ -623,6 +822,9 @@ ltq_etop_tx_timeout(struct net_device *d |
||
717 | err = ltq_etop_hw_init(dev); |
||
718 | if (err) |
||
719 | goto err_hw; |
||
720 | + err = ltq_etop_dma_init(dev); |
||
721 | + if (err) |
||
722 | + goto err_hw; |
||
723 | netif_trans_update(dev); |
||
724 | netif_wake_queue(dev); |
||
725 | return; |
||
726 | @@ -646,14 +848,19 @@ static const struct net_device_ops ltq_e |
||
727 | .ndo_tx_timeout = ltq_etop_tx_timeout, |
||
728 | }; |
||
729 | |||
730 | -static int __init |
||
731 | -ltq_etop_probe(struct platform_device *pdev) |
||
732 | +static int ltq_etop_probe(struct platform_device *pdev) |
||
733 | { |
||
734 | struct net_device *dev; |
||
735 | struct ltq_etop_priv *priv; |
||
736 | - struct resource *res; |
||
737 | + struct resource *res, *gbit_res, irqres[2]; |
||
738 | + const u8 *mac; |
||
739 | int err; |
||
740 | - int i; |
||
741 | + |
||
742 | + err = of_irq_to_resource_table(pdev->dev.of_node, irqres, 2); |
||
743 | + if (err != 2) { |
||
744 | + dev_err(&pdev->dev, "failed to get etop irqs\n"); |
||
745 | + return -EINVAL; |
||
746 | + } |
||
747 | |||
748 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
||
749 | if (!res) { |
||
750 | @@ -679,31 +886,62 @@ ltq_etop_probe(struct platform_device *p |
||
751 | goto err_out; |
||
752 | } |
||
753 | |||
754 | - dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); |
||
755 | - if (!dev) { |
||
756 | - err = -ENOMEM; |
||
757 | - goto err_out; |
||
758 | + if (of_machine_is_compatible("lantiq,ar9")) { |
||
759 | + gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
||
760 | + if (!gbit_res) { |
||
761 | + dev_err(&pdev->dev, "failed to get gbit resource\n"); |
||
762 | + err = -ENOENT; |
||
763 | + goto err_out; |
||
764 | + } |
||
765 | + ltq_gbit_membase = devm_ioremap_nocache(&pdev->dev, |
||
766 | + gbit_res->start, resource_size(gbit_res)); |
||
767 | + if (!ltq_gbit_membase) { |
||
768 | + dev_err(&pdev->dev, "failed to remap gigabit switch %d\n", |
||
769 | + pdev->id); |
||
770 | + err = -ENOMEM; |
||
771 | + goto err_out; |
||
772 | + } |
||
773 | } |
||
774 | + |
||
775 | + dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); |
||
776 | strcpy(dev->name, "eth%d"); |
||
777 | dev->netdev_ops = <q_eth_netdev_ops; |
||
778 | - dev->ethtool_ops = <q_etop_ethtool_ops; |
||
779 | priv = netdev_priv(dev); |
||
780 | priv->res = res; |
||
781 | priv->pdev = pdev; |
||
782 | - priv->pldata = dev_get_platdata(&pdev->dev); |
||
783 | priv->netdev = dev; |
||
784 | + priv->tx_irq = irqres[0].start; |
||
785 | + priv->rx_irq = irqres[1].start; |
||
786 | + priv->mii_mode = of_get_phy_mode(pdev->dev.of_node); |
||
787 | + |
||
788 | + mac = of_get_mac_address(pdev->dev.of_node); |
||
789 | + if (mac) |
||
790 | + memcpy(priv->mac, mac, ETH_ALEN); |
||
791 | + |
||
792 | + priv->clk_ppe = clk_get(&pdev->dev, NULL); |
||
793 | + if (IS_ERR(priv->clk_ppe)) |
||
794 | + return PTR_ERR(priv->clk_ppe); |
||
795 | + if (of_machine_is_compatible("lantiq,ar9")) { |
||
796 | + priv->clk_switch = clk_get(&pdev->dev, "switch"); |
||
797 | + if (IS_ERR(priv->clk_switch)) |
||
798 | + return PTR_ERR(priv->clk_switch); |
||
799 | + } |
||
800 | + if (of_machine_is_compatible("lantiq,ase")) { |
||
801 | + priv->clk_ephy = clk_get(&pdev->dev, "ephy"); |
||
802 | + if (IS_ERR(priv->clk_ephy)) |
||
803 | + return PTR_ERR(priv->clk_ephy); |
||
804 | + priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu"); |
||
805 | + if (IS_ERR(priv->clk_ephycgu)) |
||
806 | + return PTR_ERR(priv->clk_ephycgu); |
||
807 | + } |
||
808 | + |
||
809 | spin_lock_init(&priv->lock); |
||
810 | SET_NETDEV_DEV(dev, &pdev->dev); |
||
811 | |||
812 | - for (i = 0; i < MAX_DMA_CHAN; i++) { |
||
813 | - if (IS_TX(i)) |
||
814 | - netif_napi_add(dev, &priv->ch[i].napi, |
||
815 | - ltq_etop_poll_tx, 8); |
||
816 | - else if (IS_RX(i)) |
||
817 | - netif_napi_add(dev, &priv->ch[i].napi, |
||
818 | - ltq_etop_poll_rx, 32); |
||
819 | - priv->ch[i].netdev = dev; |
||
820 | - } |
||
821 | + netif_napi_add(dev, &priv->txch.napi, ltq_etop_poll_tx, 8); |
||
822 | + netif_napi_add(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32); |
||
823 | + priv->txch.netdev = dev; |
||
824 | + priv->rxch.netdev = dev; |
||
825 | |||
826 | err = register_netdev(dev); |
||
827 | if (err) |
||
828 | @@ -732,31 +970,22 @@ ltq_etop_remove(struct platform_device * |
||
829 | return 0; |
||
830 | } |
||
831 | |||
832 | +static const struct of_device_id ltq_etop_match[] = { |
||
833 | + { .compatible = "lantiq,etop-xway" }, |
||
834 | + {}, |
||
835 | +}; |
||
836 | +MODULE_DEVICE_TABLE(of, ltq_etop_match); |
||
837 | + |
||
838 | static struct platform_driver ltq_mii_driver = { |
||
839 | + .probe = ltq_etop_probe, |
||
840 | .remove = ltq_etop_remove, |
||
841 | .driver = { |
||
842 | .name = "ltq_etop", |
||
843 | + .of_match_table = ltq_etop_match, |
||
844 | }, |
||
845 | }; |
||
846 | |||
847 | -int __init |
||
848 | -init_ltq_etop(void) |
||
849 | -{ |
||
850 | - int ret = platform_driver_probe(<q_mii_driver, ltq_etop_probe); |
||
851 | - |
||
852 | - if (ret) |
||
853 | - pr_err("ltq_etop: Error registering platform driver!"); |
||
854 | - return ret; |
||
855 | -} |
||
856 | - |
||
857 | -static void __exit |
||
858 | -exit_ltq_etop(void) |
||
859 | -{ |
||
860 | - platform_driver_unregister(<q_mii_driver); |
||
861 | -} |
||
862 | - |
||
863 | -module_init(init_ltq_etop); |
||
864 | -module_exit(exit_ltq_etop); |
||
865 | +module_platform_driver(ltq_mii_driver); |
||
866 | |||
867 | MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); |
||
868 | MODULE_DESCRIPTION("Lantiq SoC ETOP"); |