OpenWrt – Blame information for rev 4
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Rev | Author | Line No. | Line |
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4 | office | 1 | From 563fa24db4e529c5a3311928d73a8a90531ee527 Mon Sep 17 00:00:00 2001 |
2 | From: Thomas Pedersen <twp@codeaurora.org> |
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3 | Date: Mon, 16 May 2016 17:58:51 -0700 |
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4 | Subject: [PATCH 02/69] dmaengine: Add ADM driver |
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5 | |||
6 | Original patch by Andy Gross. |
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7 | |||
8 | Add the DMA engine driver for the QCOM Application Data Mover (ADM) DMA |
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9 | controller found in the MSM8x60 and IPQ/APQ8064 platforms. |
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10 | |||
11 | The ADM supports both memory to memory transactions and memory |
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12 | to/from peripheral device transactions. The controller also provides flow |
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13 | control capabilities for transactions to/from peripheral devices. |
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14 | |||
15 | The initial release of this driver supports slave transfers to/from peripherals |
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16 | and also incorporates CRCI (client rate control interface) flow control. |
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17 | |||
18 | Signed-off-by: Andy Gross <agross@codeaurora.org> |
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19 | Signed-off-by: Thomas Pedersen <twp@codeaurora.org> |
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20 | --- |
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21 | drivers/dma/qcom/Kconfig | 10 + |
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22 | drivers/dma/qcom/Makefile | 1 + |
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23 | drivers/dma/qcom/qcom_adm.c | 900 ++++++++++++++++++++++++++++++++++++++++++++ |
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24 | 3 files changed, 911 insertions(+) |
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25 | create mode 100644 drivers/dma/qcom/qcom_adm.c |
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26 | |||
27 | --- a/drivers/dma/qcom/Kconfig |
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28 | +++ b/drivers/dma/qcom/Kconfig |
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29 | @@ -27,3 +27,13 @@ config QCOM_HIDMA |
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30 | (user to kernel, kernel to kernel, etc.). It only supports |
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31 | memcpy interface. The core is not intended for general |
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32 | purpose slave DMA. |
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33 | + |
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34 | +config QCOM_ADM |
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35 | + tristate "Qualcomm ADM support" |
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36 | + depends on ARCH_QCOM || (COMPILE_TEST && OF && ARM) |
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37 | + select DMA_ENGINE |
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38 | + select DMA_VIRTUAL_CHANNELS |
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39 | + ---help--- |
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40 | + Enable support for the Qualcomm ADM DMA controller. This controller |
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41 | + provides DMA capabilities for both general purpose and on-chip |
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42 | + peripheral devices. |
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43 | --- a/drivers/dma/qcom/Makefile |
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44 | +++ b/drivers/dma/qcom/Makefile |
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45 | @@ -4,3 +4,4 @@ obj-$(CONFIG_QCOM_HIDMA_MGMT) += hdma_mg |
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46 | hdma_mgmt-objs := hidma_mgmt.o hidma_mgmt_sys.o |
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47 | obj-$(CONFIG_QCOM_HIDMA) += hdma.o |
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48 | hdma-objs := hidma_ll.o hidma.o hidma_dbg.o |
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49 | +obj-$(CONFIG_QCOM_ADM) += qcom_adm.o |
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50 | --- /dev/null |
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51 | +++ b/drivers/dma/qcom/qcom_adm.c |
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52 | @@ -0,0 +1,914 @@ |
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53 | +/* |
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54 | + * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. |
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55 | + * |
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56 | + * This program is free software; you can redistribute it and/or modify |
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57 | + * it under the terms of the GNU General Public License version 2 and |
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58 | + * only version 2 as published by the Free Software Foundation. |
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59 | + * |
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60 | + * This program is distributed in the hope that it will be useful, |
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61 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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62 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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63 | + * GNU General Public License for more details. |
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64 | + * |
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65 | + */ |
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66 | + |
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67 | +#include <linux/kernel.h> |
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68 | +#include <linux/io.h> |
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69 | +#include <linux/init.h> |
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70 | +#include <linux/slab.h> |
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71 | +#include <linux/module.h> |
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72 | +#include <linux/interrupt.h> |
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73 | +#include <linux/dma-mapping.h> |
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74 | +#include <linux/scatterlist.h> |
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75 | +#include <linux/device.h> |
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76 | +#include <linux/platform_device.h> |
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77 | +#include <linux/of.h> |
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78 | +#include <linux/of_address.h> |
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79 | +#include <linux/of_irq.h> |
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80 | +#include <linux/of_dma.h> |
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81 | +#include <linux/reset.h> |
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82 | +#include <linux/clk.h> |
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83 | +#include <linux/dmaengine.h> |
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84 | + |
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85 | +#include "../dmaengine.h" |
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86 | +#include "../virt-dma.h" |
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87 | + |
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88 | +/* ADM registers - calculated from channel number and security domain */ |
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89 | +#define ADM_CHAN_MULTI 0x4 |
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90 | +#define ADM_CI_MULTI 0x4 |
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91 | +#define ADM_CRCI_MULTI 0x4 |
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92 | +#define ADM_EE_MULTI 0x800 |
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93 | +#define ADM_CHAN_OFFS(chan) (ADM_CHAN_MULTI * chan) |
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94 | +#define ADM_EE_OFFS(ee) (ADM_EE_MULTI * ee) |
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95 | +#define ADM_CHAN_EE_OFFS(chan, ee) (ADM_CHAN_OFFS(chan) + ADM_EE_OFFS(ee)) |
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96 | +#define ADM_CHAN_OFFS(chan) (ADM_CHAN_MULTI * chan) |
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97 | +#define ADM_CI_OFFS(ci) (ADM_CHAN_OFF(ci)) |
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98 | +#define ADM_CH_CMD_PTR(chan, ee) (ADM_CHAN_EE_OFFS(chan, ee)) |
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99 | +#define ADM_CH_RSLT(chan, ee) (0x40 + ADM_CHAN_EE_OFFS(chan, ee)) |
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100 | +#define ADM_CH_FLUSH_STATE0(chan, ee) (0x80 + ADM_CHAN_EE_OFFS(chan, ee)) |
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101 | +#define ADM_CH_STATUS_SD(chan, ee) (0x200 + ADM_CHAN_EE_OFFS(chan, ee)) |
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102 | +#define ADM_CH_CONF(chan) (0x240 + ADM_CHAN_OFFS(chan)) |
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103 | +#define ADM_CH_RSLT_CONF(chan, ee) (0x300 + ADM_CHAN_EE_OFFS(chan, ee)) |
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104 | +#define ADM_SEC_DOMAIN_IRQ_STATUS(ee) (0x380 + ADM_EE_OFFS(ee)) |
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105 | +#define ADM_CI_CONF(ci) (0x390 + ci * ADM_CI_MULTI) |
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106 | +#define ADM_GP_CTL 0x3d8 |
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107 | +#define ADM_CRCI_CTL(crci, ee) (0x400 + crci * ADM_CRCI_MULTI + \ |
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108 | + ADM_EE_OFFS(ee)) |
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109 | + |
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110 | +/* channel status */ |
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111 | +#define ADM_CH_STATUS_VALID BIT(1) |
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112 | + |
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113 | +/* channel result */ |
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114 | +#define ADM_CH_RSLT_VALID BIT(31) |
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115 | +#define ADM_CH_RSLT_ERR BIT(3) |
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116 | +#define ADM_CH_RSLT_FLUSH BIT(2) |
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117 | +#define ADM_CH_RSLT_TPD BIT(1) |
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118 | + |
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119 | +/* channel conf */ |
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120 | +#define ADM_CH_CONF_SHADOW_EN BIT(12) |
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121 | +#define ADM_CH_CONF_MPU_DISABLE BIT(11) |
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122 | +#define ADM_CH_CONF_PERM_MPU_CONF BIT(9) |
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123 | +#define ADM_CH_CONF_FORCE_RSLT_EN BIT(7) |
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124 | +#define ADM_CH_CONF_SEC_DOMAIN(ee) (((ee & 0x3) << 4) | ((ee & 0x4) << 11)) |
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125 | + |
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126 | +/* channel result conf */ |
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127 | +#define ADM_CH_RSLT_CONF_FLUSH_EN BIT(1) |
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128 | +#define ADM_CH_RSLT_CONF_IRQ_EN BIT(0) |
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129 | + |
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130 | +/* CRCI CTL */ |
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131 | +#define ADM_CRCI_CTL_MUX_SEL BIT(18) |
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132 | +#define ADM_CRCI_CTL_RST BIT(17) |
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133 | + |
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134 | +/* CI configuration */ |
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135 | +#define ADM_CI_RANGE_END(x) (x << 24) |
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136 | +#define ADM_CI_RANGE_START(x) (x << 16) |
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137 | +#define ADM_CI_BURST_4_WORDS BIT(2) |
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138 | +#define ADM_CI_BURST_8_WORDS BIT(3) |
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139 | + |
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140 | +/* GP CTL */ |
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141 | +#define ADM_GP_CTL_LP_EN BIT(12) |
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142 | +#define ADM_GP_CTL_LP_CNT(x) (x << 8) |
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143 | + |
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144 | +/* Command pointer list entry */ |
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145 | +#define ADM_CPLE_LP BIT(31) |
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146 | +#define ADM_CPLE_CMD_PTR_LIST BIT(29) |
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147 | + |
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148 | +/* Command list entry */ |
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149 | +#define ADM_CMD_LC BIT(31) |
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150 | +#define ADM_CMD_DST_CRCI(n) (((n) & 0xf) << 7) |
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151 | +#define ADM_CMD_SRC_CRCI(n) (((n) & 0xf) << 3) |
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152 | + |
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153 | +#define ADM_CMD_TYPE_SINGLE 0x0 |
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154 | +#define ADM_CMD_TYPE_BOX 0x3 |
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155 | + |
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156 | +#define ADM_CRCI_MUX_SEL BIT(4) |
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157 | +#define ADM_DESC_ALIGN 8 |
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158 | +#define ADM_MAX_XFER (SZ_64K-1) |
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159 | +#define ADM_MAX_ROWS (SZ_64K-1) |
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160 | +#define ADM_MAX_CHANNELS 16 |
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161 | + |
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162 | +struct adm_desc_hw_box { |
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163 | + u32 cmd; |
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164 | + u32 src_addr; |
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165 | + u32 dst_addr; |
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166 | + u32 row_len; |
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167 | + u32 num_rows; |
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168 | + u32 row_offset; |
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169 | +}; |
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170 | + |
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171 | +struct adm_desc_hw_single { |
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172 | + u32 cmd; |
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173 | + u32 src_addr; |
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174 | + u32 dst_addr; |
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175 | + u32 len; |
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176 | +}; |
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177 | + |
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178 | +struct adm_async_desc { |
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179 | + struct virt_dma_desc vd; |
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180 | + struct adm_device *adev; |
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181 | + |
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182 | + size_t length; |
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183 | + enum dma_transfer_direction dir; |
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184 | + dma_addr_t dma_addr; |
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185 | + size_t dma_len; |
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186 | + |
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187 | + void *cpl; |
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188 | + dma_addr_t cp_addr; |
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189 | + u32 crci; |
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190 | + u32 mux; |
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191 | + u32 blk_size; |
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192 | +}; |
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193 | + |
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194 | +struct adm_chan { |
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195 | + struct virt_dma_chan vc; |
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196 | + struct adm_device *adev; |
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197 | + |
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198 | + /* parsed from DT */ |
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199 | + u32 id; /* channel id */ |
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200 | + |
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201 | + struct adm_async_desc *curr_txd; |
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202 | + struct dma_slave_config slave; |
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203 | + struct list_head node; |
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204 | + |
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205 | + int error; |
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206 | + int initialized; |
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207 | +}; |
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208 | + |
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209 | +static inline struct adm_chan *to_adm_chan(struct dma_chan *common) |
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210 | +{ |
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211 | + return container_of(common, struct adm_chan, vc.chan); |
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212 | +} |
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213 | + |
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214 | +struct adm_device { |
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215 | + void __iomem *regs; |
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216 | + struct device *dev; |
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217 | + struct dma_device common; |
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218 | + struct device_dma_parameters dma_parms; |
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219 | + struct adm_chan *channels; |
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220 | + |
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221 | + u32 ee; |
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222 | + |
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223 | + struct clk *core_clk; |
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224 | + struct clk *iface_clk; |
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225 | + |
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226 | + struct reset_control *clk_reset; |
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227 | + struct reset_control *c0_reset; |
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228 | + struct reset_control *c1_reset; |
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229 | + struct reset_control *c2_reset; |
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230 | + int irq; |
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231 | +}; |
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232 | + |
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233 | +/** |
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234 | + * adm_free_chan - Frees dma resources associated with the specific channel |
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235 | + * |
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236 | + * Free all allocated descriptors associated with this channel |
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237 | + * |
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238 | + */ |
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239 | +static void adm_free_chan(struct dma_chan *chan) |
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240 | +{ |
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241 | + /* free all queued descriptors */ |
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242 | + vchan_free_chan_resources(to_virt_chan(chan)); |
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243 | +} |
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244 | + |
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245 | +/** |
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246 | + * adm_get_blksize - Get block size from burst value |
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247 | + * |
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248 | + */ |
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249 | +static int adm_get_blksize(unsigned int burst) |
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250 | +{ |
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251 | + int ret; |
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252 | + |
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253 | + switch (burst) { |
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254 | + case 16: |
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255 | + case 32: |
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256 | + case 64: |
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257 | + case 128: |
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258 | + ret = ffs(burst>>4) - 1; |
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259 | + break; |
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260 | + case 192: |
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261 | + ret = 4; |
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262 | + break; |
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263 | + case 256: |
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264 | + ret = 5; |
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265 | + break; |
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266 | + default: |
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267 | + ret = -EINVAL; |
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268 | + break; |
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269 | + } |
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270 | + |
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271 | + return ret; |
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272 | +} |
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273 | + |
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274 | +/** |
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275 | + * adm_process_fc_descriptors - Process descriptors for flow controlled xfers |
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276 | + * |
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277 | + * @achan: ADM channel |
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278 | + * @desc: Descriptor memory pointer |
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279 | + * @sg: Scatterlist entry |
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280 | + * @crci: CRCI value |
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281 | + * @burst: Burst size of transaction |
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282 | + * @direction: DMA transfer direction |
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283 | + */ |
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284 | +static void *adm_process_fc_descriptors(struct adm_chan *achan, |
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285 | + void *desc, struct scatterlist *sg, u32 crci, u32 burst, |
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286 | + enum dma_transfer_direction direction) |
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287 | +{ |
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288 | + struct adm_desc_hw_box *box_desc = NULL; |
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289 | + struct adm_desc_hw_single *single_desc; |
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290 | + u32 remainder = sg_dma_len(sg); |
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291 | + u32 rows, row_offset, crci_cmd; |
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292 | + u32 mem_addr = sg_dma_address(sg); |
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293 | + u32 *incr_addr = &mem_addr; |
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294 | + u32 *src, *dst; |
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295 | + |
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296 | + if (direction == DMA_DEV_TO_MEM) { |
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297 | + crci_cmd = ADM_CMD_SRC_CRCI(crci); |
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298 | + row_offset = burst; |
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299 | + src = &achan->slave.src_addr; |
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300 | + dst = &mem_addr; |
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301 | + } else { |
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302 | + crci_cmd = ADM_CMD_DST_CRCI(crci); |
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303 | + row_offset = burst << 16; |
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304 | + src = &mem_addr; |
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305 | + dst = &achan->slave.dst_addr; |
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306 | + } |
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307 | + |
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308 | + while (remainder >= burst) { |
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309 | + box_desc = desc; |
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310 | + box_desc->cmd = ADM_CMD_TYPE_BOX | crci_cmd; |
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311 | + box_desc->row_offset = row_offset; |
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312 | + box_desc->src_addr = *src; |
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313 | + box_desc->dst_addr = *dst; |
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314 | + |
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315 | + rows = remainder / burst; |
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316 | + rows = min_t(u32, rows, ADM_MAX_ROWS); |
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317 | + box_desc->num_rows = rows << 16 | rows; |
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318 | + box_desc->row_len = burst << 16 | burst; |
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319 | + |
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320 | + *incr_addr += burst * rows; |
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321 | + remainder -= burst * rows; |
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322 | + desc += sizeof(*box_desc); |
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323 | + } |
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324 | + |
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325 | + /* if leftover bytes, do one single descriptor */ |
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326 | + if (remainder) { |
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327 | + single_desc = desc; |
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328 | + single_desc->cmd = ADM_CMD_TYPE_SINGLE | crci_cmd; |
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329 | + single_desc->len = remainder; |
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330 | + single_desc->src_addr = *src; |
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331 | + single_desc->dst_addr = *dst; |
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332 | + desc += sizeof(*single_desc); |
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333 | + |
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334 | + if (sg_is_last(sg)) |
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335 | + single_desc->cmd |= ADM_CMD_LC; |
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336 | + } else { |
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337 | + if (box_desc && sg_is_last(sg)) |
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338 | + box_desc->cmd |= ADM_CMD_LC; |
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339 | + } |
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340 | + |
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341 | + return desc; |
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342 | +} |
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343 | + |
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344 | +/** |
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345 | + * adm_process_non_fc_descriptors - Process descriptors for non-fc xfers |
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346 | + * |
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347 | + * @achan: ADM channel |
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348 | + * @desc: Descriptor memory pointer |
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349 | + * @sg: Scatterlist entry |
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350 | + * @direction: DMA transfer direction |
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351 | + */ |
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352 | +static void *adm_process_non_fc_descriptors(struct adm_chan *achan, |
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353 | + void *desc, struct scatterlist *sg, |
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354 | + enum dma_transfer_direction direction) |
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355 | +{ |
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356 | + struct adm_desc_hw_single *single_desc; |
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357 | + u32 remainder = sg_dma_len(sg); |
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358 | + u32 mem_addr = sg_dma_address(sg); |
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359 | + u32 *incr_addr = &mem_addr; |
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360 | + u32 *src, *dst; |
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361 | + |
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362 | + if (direction == DMA_DEV_TO_MEM) { |
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363 | + src = &achan->slave.src_addr; |
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364 | + dst = &mem_addr; |
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365 | + } else { |
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366 | + src = &mem_addr; |
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367 | + dst = &achan->slave.dst_addr; |
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368 | + } |
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369 | + |
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370 | + do { |
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371 | + single_desc = desc; |
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372 | + single_desc->cmd = ADM_CMD_TYPE_SINGLE; |
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373 | + single_desc->src_addr = *src; |
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374 | + single_desc->dst_addr = *dst; |
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375 | + single_desc->len = (remainder > ADM_MAX_XFER) ? |
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376 | + ADM_MAX_XFER : remainder; |
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377 | + |
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378 | + remainder -= single_desc->len; |
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379 | + *incr_addr += single_desc->len; |
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380 | + desc += sizeof(*single_desc); |
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381 | + } while (remainder); |
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382 | + |
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383 | + /* set last command if this is the end of the whole transaction */ |
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384 | + if (sg_is_last(sg)) |
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385 | + single_desc->cmd |= ADM_CMD_LC; |
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386 | + |
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387 | + return desc; |
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388 | +} |
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389 | + |
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390 | +/** |
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391 | + * adm_prep_slave_sg - Prep slave sg transaction |
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392 | + * |
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393 | + * @chan: dma channel |
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394 | + * @sgl: scatter gather list |
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395 | + * @sg_len: length of sg |
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396 | + * @direction: DMA transfer direction |
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397 | + * @flags: DMA flags |
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398 | + * @context: transfer context (unused) |
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399 | + */ |
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400 | +static struct dma_async_tx_descriptor *adm_prep_slave_sg(struct dma_chan *chan, |
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401 | + struct scatterlist *sgl, unsigned int sg_len, |
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402 | + enum dma_transfer_direction direction, unsigned long flags, |
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403 | + void *context) |
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404 | +{ |
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405 | + struct adm_chan *achan = to_adm_chan(chan); |
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406 | + struct adm_device *adev = achan->adev; |
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407 | + struct adm_async_desc *async_desc; |
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408 | + struct scatterlist *sg; |
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409 | + dma_addr_t cple_addr; |
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410 | + u32 i, burst; |
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411 | + u32 single_count = 0, box_count = 0, crci = 0; |
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412 | + void *desc; |
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413 | + u32 *cple; |
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414 | + int blk_size = 0; |
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415 | + |
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416 | + if (!is_slave_direction(direction)) { |
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417 | + dev_err(adev->dev, "invalid dma direction\n"); |
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418 | + return NULL; |
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419 | + } |
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420 | + |
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421 | + /* |
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422 | + * get burst value from slave configuration |
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423 | + */ |
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424 | + burst = (direction == DMA_MEM_TO_DEV) ? |
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425 | + achan->slave.dst_maxburst : |
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426 | + achan->slave.src_maxburst; |
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427 | + |
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428 | + /* if using flow control, validate burst and crci values */ |
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429 | + if (achan->slave.device_fc) { |
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430 | + |
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431 | + blk_size = adm_get_blksize(burst); |
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432 | + if (blk_size < 0) { |
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433 | + dev_err(adev->dev, "invalid burst value: %d\n", |
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434 | + burst); |
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435 | + return ERR_PTR(-EINVAL); |
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436 | + } |
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437 | + |
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438 | + crci = achan->slave.slave_id & 0xf; |
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439 | + if (!crci || achan->slave.slave_id > 0x1f) { |
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440 | + dev_err(adev->dev, "invalid crci value\n"); |
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441 | + return ERR_PTR(-EINVAL); |
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442 | + } |
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443 | + } |
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444 | + |
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445 | + /* iterate through sgs and compute allocation size of structures */ |
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446 | + for_each_sg(sgl, sg, sg_len, i) { |
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447 | + if (achan->slave.device_fc) { |
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448 | + box_count += DIV_ROUND_UP(sg_dma_len(sg) / burst, |
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449 | + ADM_MAX_ROWS); |
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450 | + if (sg_dma_len(sg) % burst) |
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451 | + single_count++; |
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452 | + } else { |
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453 | + single_count += DIV_ROUND_UP(sg_dma_len(sg), |
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454 | + ADM_MAX_XFER); |
||
455 | + } |
||
456 | + } |
||
457 | + |
||
458 | + async_desc = kzalloc(sizeof(*async_desc), GFP_ATOMIC); |
||
459 | + if (!async_desc) |
||
460 | + return ERR_PTR(-ENOMEM); |
||
461 | + |
||
462 | + if (crci) |
||
463 | + async_desc->mux = achan->slave.slave_id & ADM_CRCI_MUX_SEL ? |
||
464 | + ADM_CRCI_CTL_MUX_SEL : 0; |
||
465 | + async_desc->crci = crci; |
||
466 | + async_desc->blk_size = blk_size; |
||
467 | + async_desc->dma_len = single_count * sizeof(struct adm_desc_hw_single) + |
||
468 | + box_count * sizeof(struct adm_desc_hw_box) + |
||
469 | + sizeof(*cple) + 2 * ADM_DESC_ALIGN; |
||
470 | + |
||
471 | + async_desc->cpl = kzalloc(async_desc->dma_len, GFP_ATOMIC); |
||
472 | + if (!async_desc->cpl) |
||
473 | + goto free; |
||
474 | + |
||
475 | + async_desc->adev = adev; |
||
476 | + |
||
477 | + /* both command list entry and descriptors must be 8 byte aligned */ |
||
478 | + cple = PTR_ALIGN(async_desc->cpl, ADM_DESC_ALIGN); |
||
479 | + desc = PTR_ALIGN(cple + 1, ADM_DESC_ALIGN); |
||
480 | + |
||
481 | + for_each_sg(sgl, sg, sg_len, i) { |
||
482 | + async_desc->length += sg_dma_len(sg); |
||
483 | + |
||
484 | + if (achan->slave.device_fc) |
||
485 | + desc = adm_process_fc_descriptors(achan, desc, sg, crci, |
||
486 | + burst, direction); |
||
487 | + else |
||
488 | + desc = adm_process_non_fc_descriptors(achan, desc, sg, |
||
489 | + direction); |
||
490 | + } |
||
491 | + |
||
492 | + async_desc->dma_addr = dma_map_single(adev->dev, async_desc->cpl, |
||
493 | + async_desc->dma_len, |
||
494 | + DMA_TO_DEVICE); |
||
495 | + if (dma_mapping_error(adev->dev, async_desc->dma_addr)) |
||
496 | + goto free; |
||
497 | + |
||
498 | + cple_addr = async_desc->dma_addr + ((void *)cple - async_desc->cpl); |
||
499 | + |
||
500 | + /* init cmd list */ |
||
501 | + dma_sync_single_for_cpu(adev->dev, cple_addr, sizeof(*cple), |
||
502 | + DMA_TO_DEVICE); |
||
503 | + *cple = ADM_CPLE_LP; |
||
504 | + *cple |= (async_desc->dma_addr + ADM_DESC_ALIGN) >> 3; |
||
505 | + dma_sync_single_for_device(adev->dev, cple_addr, sizeof(*cple), |
||
506 | + DMA_TO_DEVICE); |
||
507 | + |
||
508 | + return vchan_tx_prep(&achan->vc, &async_desc->vd, flags); |
||
509 | + |
||
510 | +free: |
||
511 | + kfree(async_desc); |
||
512 | + return ERR_PTR(-ENOMEM); |
||
513 | +} |
||
514 | + |
||
515 | +/** |
||
516 | + * adm_terminate_all - terminate all transactions on a channel |
||
517 | + * @achan: adm dma channel |
||
518 | + * |
||
519 | + * Dequeues and frees all transactions, aborts current transaction |
||
520 | + * No callbacks are done |
||
521 | + * |
||
522 | + */ |
||
523 | +static int adm_terminate_all(struct dma_chan *chan) |
||
524 | +{ |
||
525 | + struct adm_chan *achan = to_adm_chan(chan); |
||
526 | + struct adm_device *adev = achan->adev; |
||
527 | + unsigned long flags; |
||
528 | + LIST_HEAD(head); |
||
529 | + |
||
530 | + spin_lock_irqsave(&achan->vc.lock, flags); |
||
531 | + vchan_get_all_descriptors(&achan->vc, &head); |
||
532 | + |
||
533 | + /* send flush command to terminate current transaction */ |
||
534 | + writel_relaxed(0x0, |
||
535 | + adev->regs + ADM_CH_FLUSH_STATE0(achan->id, adev->ee)); |
||
536 | + |
||
537 | + spin_unlock_irqrestore(&achan->vc.lock, flags); |
||
538 | + |
||
539 | + vchan_dma_desc_free_list(&achan->vc, &head); |
||
540 | + |
||
541 | + return 0; |
||
542 | +} |
||
543 | + |
||
544 | +static int adm_slave_config(struct dma_chan *chan, struct dma_slave_config *cfg) |
||
545 | +{ |
||
546 | + struct adm_chan *achan = to_adm_chan(chan); |
||
547 | + unsigned long flag; |
||
548 | + |
||
549 | + spin_lock_irqsave(&achan->vc.lock, flag); |
||
550 | + memcpy(&achan->slave, cfg, sizeof(struct dma_slave_config)); |
||
551 | + spin_unlock_irqrestore(&achan->vc.lock, flag); |
||
552 | + |
||
553 | + return 0; |
||
554 | +} |
||
555 | + |
||
556 | +/** |
||
557 | + * adm_start_dma - start next transaction |
||
558 | + * @achan - ADM dma channel |
||
559 | + */ |
||
560 | +static void adm_start_dma(struct adm_chan *achan) |
||
561 | +{ |
||
562 | + struct virt_dma_desc *vd = vchan_next_desc(&achan->vc); |
||
563 | + struct adm_device *adev = achan->adev; |
||
564 | + struct adm_async_desc *async_desc; |
||
565 | + |
||
566 | + lockdep_assert_held(&achan->vc.lock); |
||
567 | + |
||
568 | + if (!vd) |
||
569 | + return; |
||
570 | + |
||
571 | + list_del(&vd->node); |
||
572 | + |
||
573 | + /* write next command list out to the CMD FIFO */ |
||
574 | + async_desc = container_of(vd, struct adm_async_desc, vd); |
||
575 | + achan->curr_txd = async_desc; |
||
576 | + |
||
577 | + /* reset channel error */ |
||
578 | + achan->error = 0; |
||
579 | + |
||
580 | + if (!achan->initialized) { |
||
581 | + /* enable interrupts */ |
||
582 | + writel(ADM_CH_CONF_SHADOW_EN | |
||
583 | + ADM_CH_CONF_PERM_MPU_CONF | |
||
584 | + ADM_CH_CONF_MPU_DISABLE | |
||
585 | + ADM_CH_CONF_SEC_DOMAIN(adev->ee), |
||
586 | + adev->regs + ADM_CH_CONF(achan->id)); |
||
587 | + |
||
588 | + writel(ADM_CH_RSLT_CONF_IRQ_EN | ADM_CH_RSLT_CONF_FLUSH_EN, |
||
589 | + adev->regs + ADM_CH_RSLT_CONF(achan->id, adev->ee)); |
||
590 | + |
||
591 | + achan->initialized = 1; |
||
592 | + } |
||
593 | + |
||
594 | + /* set the crci block size if this transaction requires CRCI */ |
||
595 | + if (async_desc->crci) { |
||
596 | + writel(async_desc->mux | async_desc->blk_size, |
||
597 | + adev->regs + ADM_CRCI_CTL(async_desc->crci, adev->ee)); |
||
598 | + } |
||
599 | + |
||
600 | + /* make sure IRQ enable doesn't get reordered */ |
||
601 | + wmb(); |
||
602 | + |
||
603 | + /* write next command list out to the CMD FIFO */ |
||
604 | + writel(ALIGN(async_desc->dma_addr, ADM_DESC_ALIGN) >> 3, |
||
605 | + adev->regs + ADM_CH_CMD_PTR(achan->id, adev->ee)); |
||
606 | +} |
||
607 | + |
||
608 | +/** |
||
609 | + * adm_dma_irq - irq handler for ADM controller |
||
610 | + * @irq: IRQ of interrupt |
||
611 | + * @data: callback data |
||
612 | + * |
||
613 | + * IRQ handler for the bam controller |
||
614 | + */ |
||
615 | +static irqreturn_t adm_dma_irq(int irq, void *data) |
||
616 | +{ |
||
617 | + struct adm_device *adev = data; |
||
618 | + u32 srcs, i; |
||
619 | + struct adm_async_desc *async_desc; |
||
620 | + unsigned long flags; |
||
621 | + |
||
622 | + srcs = readl_relaxed(adev->regs + |
||
623 | + ADM_SEC_DOMAIN_IRQ_STATUS(adev->ee)); |
||
624 | + |
||
625 | + for (i = 0; i < ADM_MAX_CHANNELS; i++) { |
||
626 | + struct adm_chan *achan = &adev->channels[i]; |
||
627 | + u32 status, result; |
||
628 | + |
||
629 | + if (srcs & BIT(i)) { |
||
630 | + status = readl_relaxed(adev->regs + |
||
631 | + ADM_CH_STATUS_SD(i, adev->ee)); |
||
632 | + |
||
633 | + /* if no result present, skip */ |
||
634 | + if (!(status & ADM_CH_STATUS_VALID)) |
||
635 | + continue; |
||
636 | + |
||
637 | + result = readl_relaxed(adev->regs + |
||
638 | + ADM_CH_RSLT(i, adev->ee)); |
||
639 | + |
||
640 | + /* no valid results, skip */ |
||
641 | + if (!(result & ADM_CH_RSLT_VALID)) |
||
642 | + continue; |
||
643 | + |
||
644 | + /* flag error if transaction was flushed or failed */ |
||
645 | + if (result & (ADM_CH_RSLT_ERR | ADM_CH_RSLT_FLUSH)) |
||
646 | + achan->error = 1; |
||
647 | + |
||
648 | + spin_lock_irqsave(&achan->vc.lock, flags); |
||
649 | + async_desc = achan->curr_txd; |
||
650 | + |
||
651 | + achan->curr_txd = NULL; |
||
652 | + |
||
653 | + if (async_desc) { |
||
654 | + vchan_cookie_complete(&async_desc->vd); |
||
655 | + |
||
656 | + /* kick off next DMA */ |
||
657 | + adm_start_dma(achan); |
||
658 | + } |
||
659 | + |
||
660 | + spin_unlock_irqrestore(&achan->vc.lock, flags); |
||
661 | + } |
||
662 | + } |
||
663 | + |
||
664 | + return IRQ_HANDLED; |
||
665 | +} |
||
666 | + |
||
667 | +/** |
||
668 | + * adm_tx_status - returns status of transaction |
||
669 | + * @chan: dma channel |
||
670 | + * @cookie: transaction cookie |
||
671 | + * @txstate: DMA transaction state |
||
672 | + * |
||
673 | + * Return status of dma transaction |
||
674 | + */ |
||
675 | +static enum dma_status adm_tx_status(struct dma_chan *chan, dma_cookie_t cookie, |
||
676 | + struct dma_tx_state *txstate) |
||
677 | +{ |
||
678 | + struct adm_chan *achan = to_adm_chan(chan); |
||
679 | + struct virt_dma_desc *vd; |
||
680 | + enum dma_status ret; |
||
681 | + unsigned long flags; |
||
682 | + size_t residue = 0; |
||
683 | + |
||
684 | + ret = dma_cookie_status(chan, cookie, txstate); |
||
685 | + if (ret == DMA_COMPLETE || !txstate) |
||
686 | + return ret; |
||
687 | + |
||
688 | + spin_lock_irqsave(&achan->vc.lock, flags); |
||
689 | + |
||
690 | + vd = vchan_find_desc(&achan->vc, cookie); |
||
691 | + if (vd) |
||
692 | + residue = container_of(vd, struct adm_async_desc, vd)->length; |
||
693 | + |
||
694 | + spin_unlock_irqrestore(&achan->vc.lock, flags); |
||
695 | + |
||
696 | + /* |
||
697 | + * residue is either the full length if it is in the issued list, or 0 |
||
698 | + * if it is in progress. We have no reliable way of determining |
||
699 | + * anything inbetween |
||
700 | + */ |
||
701 | + dma_set_residue(txstate, residue); |
||
702 | + |
||
703 | + if (achan->error) |
||
704 | + return DMA_ERROR; |
||
705 | + |
||
706 | + return ret; |
||
707 | +} |
||
708 | + |
||
709 | +/** |
||
710 | + * adm_issue_pending - starts pending transactions |
||
711 | + * @chan: dma channel |
||
712 | + * |
||
713 | + * Issues all pending transactions and starts DMA |
||
714 | + */ |
||
715 | +static void adm_issue_pending(struct dma_chan *chan) |
||
716 | +{ |
||
717 | + struct adm_chan *achan = to_adm_chan(chan); |
||
718 | + unsigned long flags; |
||
719 | + |
||
720 | + spin_lock_irqsave(&achan->vc.lock, flags); |
||
721 | + |
||
722 | + if (vchan_issue_pending(&achan->vc) && !achan->curr_txd) |
||
723 | + adm_start_dma(achan); |
||
724 | + spin_unlock_irqrestore(&achan->vc.lock, flags); |
||
725 | +} |
||
726 | + |
||
727 | +/** |
||
728 | + * adm_dma_free_desc - free descriptor memory |
||
729 | + * @vd: virtual descriptor |
||
730 | + * |
||
731 | + */ |
||
732 | +static void adm_dma_free_desc(struct virt_dma_desc *vd) |
||
733 | +{ |
||
734 | + struct adm_async_desc *async_desc = container_of(vd, |
||
735 | + struct adm_async_desc, vd); |
||
736 | + |
||
737 | + dma_unmap_single(async_desc->adev->dev, async_desc->dma_addr, |
||
738 | + async_desc->dma_len, DMA_TO_DEVICE); |
||
739 | + kfree(async_desc->cpl); |
||
740 | + kfree(async_desc); |
||
741 | +} |
||
742 | + |
||
743 | +static void adm_channel_init(struct adm_device *adev, struct adm_chan *achan, |
||
744 | + u32 index) |
||
745 | +{ |
||
746 | + achan->id = index; |
||
747 | + achan->adev = adev; |
||
748 | + |
||
749 | + vchan_init(&achan->vc, &adev->common); |
||
750 | + achan->vc.desc_free = adm_dma_free_desc; |
||
751 | +} |
||
752 | + |
||
753 | +static int adm_dma_probe(struct platform_device *pdev) |
||
754 | +{ |
||
755 | + struct adm_device *adev; |
||
756 | + struct resource *iores; |
||
757 | + int ret; |
||
758 | + u32 i; |
||
759 | + |
||
760 | + adev = devm_kzalloc(&pdev->dev, sizeof(*adev), GFP_KERNEL); |
||
761 | + if (!adev) |
||
762 | + return -ENOMEM; |
||
763 | + |
||
764 | + adev->dev = &pdev->dev; |
||
765 | + |
||
766 | + iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
||
767 | + adev->regs = devm_ioremap_resource(&pdev->dev, iores); |
||
768 | + if (IS_ERR(adev->regs)) |
||
769 | + return PTR_ERR(adev->regs); |
||
770 | + |
||
771 | + adev->irq = platform_get_irq(pdev, 0); |
||
772 | + if (adev->irq < 0) |
||
773 | + return adev->irq; |
||
774 | + |
||
775 | + ret = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &adev->ee); |
||
776 | + if (ret) { |
||
777 | + dev_err(adev->dev, "Execution environment unspecified\n"); |
||
778 | + return ret; |
||
779 | + } |
||
780 | + |
||
781 | + adev->core_clk = devm_clk_get(adev->dev, "core"); |
||
782 | + if (IS_ERR(adev->core_clk)) |
||
783 | + return PTR_ERR(adev->core_clk); |
||
784 | + |
||
785 | + ret = clk_prepare_enable(adev->core_clk); |
||
786 | + if (ret) { |
||
787 | + dev_err(adev->dev, "failed to prepare/enable core clock\n"); |
||
788 | + return ret; |
||
789 | + } |
||
790 | + |
||
791 | + adev->iface_clk = devm_clk_get(adev->dev, "iface"); |
||
792 | + if (IS_ERR(adev->iface_clk)) { |
||
793 | + ret = PTR_ERR(adev->iface_clk); |
||
794 | + goto err_disable_core_clk; |
||
795 | + } |
||
796 | + |
||
797 | + ret = clk_prepare_enable(adev->iface_clk); |
||
798 | + if (ret) { |
||
799 | + dev_err(adev->dev, "failed to prepare/enable iface clock\n"); |
||
800 | + goto err_disable_core_clk; |
||
801 | + } |
||
802 | + |
||
803 | + adev->clk_reset = devm_reset_control_get(&pdev->dev, "clk"); |
||
804 | + if (IS_ERR(adev->clk_reset)) { |
||
805 | + dev_err(adev->dev, "failed to get ADM0 reset\n"); |
||
806 | + ret = PTR_ERR(adev->clk_reset); |
||
807 | + goto err_disable_clks; |
||
808 | + } |
||
809 | + |
||
810 | + adev->c0_reset = devm_reset_control_get(&pdev->dev, "c0"); |
||
811 | + if (IS_ERR(adev->c0_reset)) { |
||
812 | + dev_err(adev->dev, "failed to get ADM0 C0 reset\n"); |
||
813 | + ret = PTR_ERR(adev->c0_reset); |
||
814 | + goto err_disable_clks; |
||
815 | + } |
||
816 | + |
||
817 | + adev->c1_reset = devm_reset_control_get(&pdev->dev, "c1"); |
||
818 | + if (IS_ERR(adev->c1_reset)) { |
||
819 | + dev_err(adev->dev, "failed to get ADM0 C1 reset\n"); |
||
820 | + ret = PTR_ERR(adev->c1_reset); |
||
821 | + goto err_disable_clks; |
||
822 | + } |
||
823 | + |
||
824 | + adev->c2_reset = devm_reset_control_get(&pdev->dev, "c2"); |
||
825 | + if (IS_ERR(adev->c2_reset)) { |
||
826 | + dev_err(adev->dev, "failed to get ADM0 C2 reset\n"); |
||
827 | + ret = PTR_ERR(adev->c2_reset); |
||
828 | + goto err_disable_clks; |
||
829 | + } |
||
830 | + |
||
831 | + reset_control_assert(adev->clk_reset); |
||
832 | + reset_control_assert(adev->c0_reset); |
||
833 | + reset_control_assert(adev->c1_reset); |
||
834 | + reset_control_assert(adev->c2_reset); |
||
835 | + |
||
836 | + reset_control_deassert(adev->clk_reset); |
||
837 | + reset_control_deassert(adev->c0_reset); |
||
838 | + reset_control_deassert(adev->c1_reset); |
||
839 | + reset_control_deassert(adev->c2_reset); |
||
840 | + |
||
841 | + adev->channels = devm_kcalloc(adev->dev, ADM_MAX_CHANNELS, |
||
842 | + sizeof(*adev->channels), GFP_KERNEL); |
||
843 | + |
||
844 | + if (!adev->channels) { |
||
845 | + ret = -ENOMEM; |
||
846 | + goto err_disable_clks; |
||
847 | + } |
||
848 | + |
||
849 | + /* allocate and initialize channels */ |
||
850 | + INIT_LIST_HEAD(&adev->common.channels); |
||
851 | + |
||
852 | + for (i = 0; i < ADM_MAX_CHANNELS; i++) |
||
853 | + adm_channel_init(adev, &adev->channels[i], i); |
||
854 | + |
||
855 | + /* reset CRCIs */ |
||
856 | + for (i = 0; i < 16; i++) |
||
857 | + writel(ADM_CRCI_CTL_RST, adev->regs + |
||
858 | + ADM_CRCI_CTL(i, adev->ee)); |
||
859 | + |
||
860 | + /* configure client interfaces */ |
||
861 | + writel(ADM_CI_RANGE_START(0x40) | ADM_CI_RANGE_END(0xb0) | |
||
862 | + ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(0)); |
||
863 | + writel(ADM_CI_RANGE_START(0x2a) | ADM_CI_RANGE_END(0x2c) | |
||
864 | + ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(1)); |
||
865 | + writel(ADM_CI_RANGE_START(0x12) | ADM_CI_RANGE_END(0x28) | |
||
866 | + ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(2)); |
||
867 | + writel(ADM_GP_CTL_LP_EN | ADM_GP_CTL_LP_CNT(0xf), |
||
868 | + adev->regs + ADM_GP_CTL); |
||
869 | + |
||
870 | + ret = devm_request_irq(adev->dev, adev->irq, adm_dma_irq, |
||
871 | + 0, "adm_dma", adev); |
||
872 | + if (ret) |
||
873 | + goto err_disable_clks; |
||
874 | + |
||
875 | + platform_set_drvdata(pdev, adev); |
||
876 | + |
||
877 | + adev->common.dev = adev->dev; |
||
878 | + adev->common.dev->dma_parms = &adev->dma_parms; |
||
879 | + |
||
880 | + /* set capabilities */ |
||
881 | + dma_cap_zero(adev->common.cap_mask); |
||
882 | + dma_cap_set(DMA_SLAVE, adev->common.cap_mask); |
||
883 | + dma_cap_set(DMA_PRIVATE, adev->common.cap_mask); |
||
884 | + |
||
885 | + /* initialize dmaengine apis */ |
||
886 | + adev->common.directions = BIT(DMA_DEV_TO_MEM | DMA_MEM_TO_DEV); |
||
887 | + adev->common.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; |
||
888 | + adev->common.src_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES; |
||
889 | + adev->common.dst_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES; |
||
890 | + adev->common.device_free_chan_resources = adm_free_chan; |
||
891 | + adev->common.device_prep_slave_sg = adm_prep_slave_sg; |
||
892 | + adev->common.device_issue_pending = adm_issue_pending; |
||
893 | + adev->common.device_tx_status = adm_tx_status; |
||
894 | + adev->common.device_terminate_all = adm_terminate_all; |
||
895 | + adev->common.device_config = adm_slave_config; |
||
896 | + |
||
897 | + ret = dma_async_device_register(&adev->common); |
||
898 | + if (ret) { |
||
899 | + dev_err(adev->dev, "failed to register dma async device\n"); |
||
900 | + goto err_disable_clks; |
||
901 | + } |
||
902 | + |
||
903 | + ret = of_dma_controller_register(pdev->dev.of_node, |
||
904 | + of_dma_xlate_by_chan_id, |
||
905 | + &adev->common); |
||
906 | + if (ret) |
||
907 | + goto err_unregister_dma; |
||
908 | + |
||
909 | + return 0; |
||
910 | + |
||
911 | +err_unregister_dma: |
||
912 | + dma_async_device_unregister(&adev->common); |
||
913 | +err_disable_clks: |
||
914 | + clk_disable_unprepare(adev->iface_clk); |
||
915 | +err_disable_core_clk: |
||
916 | + clk_disable_unprepare(adev->core_clk); |
||
917 | + |
||
918 | + return ret; |
||
919 | +} |
||
920 | + |
||
921 | +static int adm_dma_remove(struct platform_device *pdev) |
||
922 | +{ |
||
923 | + struct adm_device *adev = platform_get_drvdata(pdev); |
||
924 | + struct adm_chan *achan; |
||
925 | + u32 i; |
||
926 | + |
||
927 | + of_dma_controller_free(pdev->dev.of_node); |
||
928 | + dma_async_device_unregister(&adev->common); |
||
929 | + |
||
930 | + for (i = 0; i < ADM_MAX_CHANNELS; i++) { |
||
931 | + achan = &adev->channels[i]; |
||
932 | + |
||
933 | + /* mask IRQs for this channel/EE pair */ |
||
934 | + writel(0, adev->regs + ADM_CH_RSLT_CONF(achan->id, adev->ee)); |
||
935 | + |
||
936 | + adm_terminate_all(&adev->channels[i].vc.chan); |
||
937 | + } |
||
938 | + |
||
939 | + devm_free_irq(adev->dev, adev->irq, adev); |
||
940 | + |
||
941 | + clk_disable_unprepare(adev->core_clk); |
||
942 | + clk_disable_unprepare(adev->iface_clk); |
||
943 | + |
||
944 | + return 0; |
||
945 | +} |
||
946 | + |
||
947 | +static const struct of_device_id adm_of_match[] = { |
||
948 | + { .compatible = "qcom,adm", }, |
||
949 | + {} |
||
950 | +}; |
||
951 | +MODULE_DEVICE_TABLE(of, adm_of_match); |
||
952 | + |
||
953 | +static struct platform_driver adm_dma_driver = { |
||
954 | + .probe = adm_dma_probe, |
||
955 | + .remove = adm_dma_remove, |
||
956 | + .driver = { |
||
957 | + .name = "adm-dma-engine", |
||
958 | + .of_match_table = adm_of_match, |
||
959 | + }, |
||
960 | +}; |
||
961 | + |
||
962 | +module_platform_driver(adm_dma_driver); |
||
963 | + |
||
964 | +MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>"); |
||
965 | +MODULE_DESCRIPTION("QCOM ADM DMA engine driver"); |
||
966 | +MODULE_LICENSE("GPL v2"); |