OpenWrt – Blame information for rev 4
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Rev | Author | Line No. | Line |
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4 | office | 1 | /* |
2 | * B53 register definitions |
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3 | * |
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4 | * Copyright (C) 2004 Broadcom Corporation |
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5 | * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org> |
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6 | * |
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7 | * Permission to use, copy, modify, and/or distribute this software for any |
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8 | * purpose with or without fee is hereby granted, provided that the above |
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9 | * copyright notice and this permission notice appear in all copies. |
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10 | * |
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11 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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12 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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13 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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14 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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15 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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16 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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17 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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18 | */ |
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19 | |||
20 | #ifndef __B53_REGS_H |
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21 | #define __B53_REGS_H |
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22 | |||
23 | /* Management Port (SMP) Page offsets */ |
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24 | #define B53_CTRL_PAGE 0x00 /* Control */ |
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25 | #define B53_STAT_PAGE 0x01 /* Status */ |
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26 | #define B53_MGMT_PAGE 0x02 /* Management Mode */ |
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27 | #define B53_MIB_AC_PAGE 0x03 /* MIB Autocast */ |
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28 | #define B53_ARLCTRL_PAGE 0x04 /* ARL Control */ |
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29 | #define B53_ARLIO_PAGE 0x05 /* ARL Access */ |
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30 | #define B53_FRAMEBUF_PAGE 0x06 /* Management frame access */ |
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31 | #define B53_MEM_ACCESS_PAGE 0x08 /* Memory access */ |
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32 | |||
33 | /* PHY Registers */ |
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34 | #define B53_PORT_MII_PAGE(i) (0x10 + (i)) /* Port i MII Registers */ |
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35 | #define B53_IM_PORT_PAGE 0x18 /* Inverse MII Port (to EMAC) */ |
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36 | #define B53_ALL_PORT_PAGE 0x19 /* All ports MII (broadcast) */ |
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37 | |||
38 | /* MIB registers */ |
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39 | #define B53_MIB_PAGE(i) (0x20 + (i)) |
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40 | |||
41 | /* Quality of Service (QoS) Registers */ |
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42 | #define B53_QOS_PAGE 0x30 |
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43 | |||
44 | /* Port VLAN Page */ |
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45 | #define B53_PVLAN_PAGE 0x31 |
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46 | |||
47 | /* VLAN Registers */ |
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48 | #define B53_VLAN_PAGE 0x34 |
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49 | |||
50 | /* Jumbo Frame Registers */ |
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51 | #define B53_JUMBO_PAGE 0x40 |
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52 | |||
53 | /* CFP Configuration Registers Page */ |
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54 | #define B53_CFP_PAGE 0xa1 |
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55 | |||
56 | /************************************************************************* |
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57 | * Control Page registers |
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58 | *************************************************************************/ |
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59 | |||
60 | /* Port Control Register (8 bit) */ |
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61 | #define B53_PORT_CTRL(i) (0x00 + (i)) |
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62 | #define PORT_CTRL_RX_DISABLE BIT(0) |
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63 | #define PORT_CTRL_TX_DISABLE BIT(1) |
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64 | #define PORT_CTRL_RX_BCST_EN BIT(2) /* Broadcast RX (P8 only) */ |
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65 | #define PORT_CTRL_RX_MCST_EN BIT(3) /* Multicast RX (P8 only) */ |
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66 | #define PORT_CTRL_RX_UCST_EN BIT(4) /* Unicast RX (P8 only) */ |
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67 | #define PORT_CTRL_STP_STATE_S 5 |
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68 | #define PORT_CTRL_STP_STATE_MASK (0x7 << PORT_CTRL_STP_STATE_S) |
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69 | |||
70 | /* SMP Control Register (8 bit) */ |
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71 | #define B53_SMP_CTRL 0x0a |
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72 | |||
73 | /* Switch Mode Control Register (8 bit) */ |
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74 | #define B53_SWITCH_MODE 0x0b |
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75 | #define SM_SW_FWD_MODE BIT(0) /* 1 = Managed Mode */ |
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76 | #define SM_SW_FWD_EN BIT(1) /* Forwarding Enable */ |
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77 | |||
78 | /* IMP Port state override register (8 bit) */ |
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79 | #define B53_PORT_OVERRIDE_CTRL 0x0e |
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80 | #define PORT_OVERRIDE_LINK BIT(0) |
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81 | #define PORT_OVERRIDE_FULL_DUPLEX BIT(1) /* 0 = Half Duplex */ |
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82 | #define PORT_OVERRIDE_SPEED_S 2 |
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83 | #define PORT_OVERRIDE_SPEED_10M (0 << PORT_OVERRIDE_SPEED_S) |
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84 | #define PORT_OVERRIDE_SPEED_100M (1 << PORT_OVERRIDE_SPEED_S) |
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85 | #define PORT_OVERRIDE_SPEED_1000M (2 << PORT_OVERRIDE_SPEED_S) |
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86 | #define PORT_OVERRIDE_RV_MII_25 BIT(4) /* BCM5325 only */ |
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87 | #define PORT_OVERRIDE_RX_FLOW BIT(4) |
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88 | #define PORT_OVERRIDE_TX_FLOW BIT(5) |
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89 | #define PORT_OVERRIDE_SPEED_2000M BIT(6) /* BCM5301X only, requires setting 1000M */ |
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90 | #define PORT_OVERRIDE_EN BIT(7) /* Use the register contents */ |
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91 | |||
92 | /* Power-down mode control */ |
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93 | #define B53_PD_MODE_CTRL_25 0x0f |
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94 | |||
95 | /* IP Multicast control (8 bit) */ |
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96 | #define B53_IP_MULTICAST_CTRL 0x21 |
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97 | #define B53_IPMC_FWD_EN BIT(1) |
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98 | #define B53_UC_FWD_EN BIT(6) |
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99 | #define B53_MC_FWD_EN BIT(7) |
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100 | |||
101 | /* (16 bit) */ |
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102 | #define B53_UC_FLOOD_MASK 0x32 |
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103 | #define B53_MC_FLOOD_MASK 0x34 |
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104 | #define B53_IPMC_FLOOD_MASK 0x36 |
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105 | |||
106 | /* |
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107 | * Override Ports 0-7 State on devices with xMII interfaces (8 bit) |
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108 | * |
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109 | * For port 8 still use B53_PORT_OVERRIDE_CTRL |
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110 | * Please note that not all ports are available on every hardware, e.g. BCM5301X |
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111 | * don't include overriding port 6, BCM63xx also have some limitations. |
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112 | */ |
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113 | #define B53_GMII_PORT_OVERRIDE_CTRL(i) (0x58 + (i)) |
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114 | #define GMII_PO_LINK BIT(0) |
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115 | #define GMII_PO_FULL_DUPLEX BIT(1) /* 0 = Half Duplex */ |
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116 | #define GMII_PO_SPEED_S 2 |
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117 | #define GMII_PO_SPEED_10M (0 << GMII_PO_SPEED_S) |
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118 | #define GMII_PO_SPEED_100M (1 << GMII_PO_SPEED_S) |
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119 | #define GMII_PO_SPEED_1000M (2 << GMII_PO_SPEED_S) |
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120 | #define GMII_PO_RX_FLOW BIT(4) |
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121 | #define GMII_PO_TX_FLOW BIT(5) |
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122 | #define GMII_PO_EN BIT(6) /* Use the register contents */ |
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123 | #define GMII_PO_SPEED_2000M BIT(7) /* BCM5301X only, requires setting 1000M */ |
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124 | |||
125 | /* Software reset register (8 bit) */ |
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126 | #define B53_SOFTRESET 0x79 |
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127 | |||
128 | /* Fast Aging Control register (8 bit) */ |
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129 | #define B53_FAST_AGE_CTRL 0x88 |
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130 | #define FAST_AGE_STATIC BIT(0) |
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131 | #define FAST_AGE_DYNAMIC BIT(1) |
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132 | #define FAST_AGE_PORT BIT(2) |
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133 | #define FAST_AGE_VLAN BIT(3) |
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134 | #define FAST_AGE_STP BIT(4) |
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135 | #define FAST_AGE_MC BIT(5) |
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136 | #define FAST_AGE_DONE BIT(7) |
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137 | |||
138 | /************************************************************************* |
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139 | * Status Page registers |
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140 | *************************************************************************/ |
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141 | |||
142 | /* Link Status Summary Register (16bit) */ |
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143 | #define B53_LINK_STAT 0x00 |
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144 | |||
145 | /* Link Status Change Register (16 bit) */ |
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146 | #define B53_LINK_STAT_CHANGE 0x02 |
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147 | |||
148 | /* Port Speed Summary Register (16 bit for FE, 32 bit for GE) */ |
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149 | #define B53_SPEED_STAT 0x04 |
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150 | #define SPEED_PORT_FE(reg, port) (((reg) >> (port)) & 1) |
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151 | #define SPEED_PORT_GE(reg, port) (((reg) >> 2 * (port)) & 3) |
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152 | #define SPEED_STAT_10M 0 |
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153 | #define SPEED_STAT_100M 1 |
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154 | #define SPEED_STAT_1000M 2 |
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155 | |||
156 | /* Duplex Status Summary (16 bit) */ |
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157 | #define B53_DUPLEX_STAT_FE 0x06 |
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158 | #define B53_DUPLEX_STAT_GE 0x08 |
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159 | #define B53_DUPLEX_STAT_63XX 0x0c |
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160 | |||
161 | /* Revision ID register for BCM5325 */ |
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162 | #define B53_REV_ID_25 0x50 |
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163 | |||
164 | /* Strap Value (48 bit) */ |
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165 | #define B53_STRAP_VALUE 0x70 |
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166 | #define SV_GMII_CTRL_115 BIT(27) |
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167 | |||
168 | /************************************************************************* |
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169 | * Management Mode Page Registers |
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170 | *************************************************************************/ |
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171 | |||
172 | /* Global Management Config Register (8 bit) */ |
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173 | #define B53_GLOBAL_CONFIG 0x00 |
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174 | #define GC_RESET_MIB 0x01 |
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175 | #define GC_RX_BPDU_EN 0x02 |
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176 | #define GC_MIB_AC_HDR_EN 0x10 |
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177 | #define GC_MIB_AC_EN 0x20 |
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178 | #define GC_FRM_MGMT_PORT_M 0xC0 |
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179 | #define GC_FRM_MGMT_PORT_04 0x00 |
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180 | #define GC_FRM_MGMT_PORT_MII 0x80 |
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181 | |||
182 | /* Broadcom Header control register (8 bit) */ |
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183 | #define B53_BRCM_HDR 0x03 |
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184 | #define BRCM_HDR_P8_EN BIT(0) /* Enable tagging on port 8 */ |
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185 | #define BRCM_HDR_P5_EN BIT(1) /* Enable tagging on port 5 */ |
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186 | |||
187 | /* Device ID register (8 or 32 bit) */ |
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188 | #define B53_DEVICE_ID 0x30 |
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189 | |||
190 | /* Revision ID register (8 bit) */ |
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191 | #define B53_REV_ID 0x40 |
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192 | |||
193 | /************************************************************************* |
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194 | * ARL Access Page Registers |
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195 | *************************************************************************/ |
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196 | |||
197 | /* VLAN Table Access Register (8 bit) */ |
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198 | #define B53_VT_ACCESS 0x80 |
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199 | #define B53_VT_ACCESS_9798 0x60 /* for BCM5397/BCM5398 */ |
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200 | #define B53_VT_ACCESS_63XX 0x60 /* for BCM6328/62/68 */ |
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201 | #define VTA_CMD_WRITE 0 |
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202 | #define VTA_CMD_READ 1 |
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203 | #define VTA_CMD_CLEAR 2 |
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204 | #define VTA_START_CMD BIT(7) |
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205 | |||
206 | /* VLAN Table Index Register (16 bit) */ |
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207 | #define B53_VT_INDEX 0x81 |
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208 | #define B53_VT_INDEX_9798 0x61 |
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209 | #define B53_VT_INDEX_63XX 0x62 |
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210 | |||
211 | /* VLAN Table Entry Register (32 bit) */ |
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212 | #define B53_VT_ENTRY 0x83 |
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213 | #define B53_VT_ENTRY_9798 0x63 |
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214 | #define B53_VT_ENTRY_63XX 0x64 |
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215 | #define VTE_MEMBERS 0x1ff |
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216 | #define VTE_UNTAG_S 9 |
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217 | #define VTE_UNTAG (0x1ff << 9) |
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218 | |||
219 | /************************************************************************* |
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220 | * Port VLAN Registers |
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221 | *************************************************************************/ |
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222 | |||
223 | /* Port VLAN mask (16 bit) IMP port is always 8, also on 5325 & co */ |
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224 | #define B53_PVLAN_PORT_MASK(i) ((i) * 2) |
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225 | |||
226 | /************************************************************************* |
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227 | * 802.1Q Page Registers |
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228 | *************************************************************************/ |
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229 | |||
230 | /* Global QoS Control (8 bit) */ |
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231 | #define B53_QOS_GLOBAL_CTL 0x00 |
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232 | |||
233 | /* Enable 802.1Q for individual Ports (16 bit) */ |
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234 | #define B53_802_1P_EN 0x04 |
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235 | |||
236 | /************************************************************************* |
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237 | * VLAN Page Registers |
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238 | *************************************************************************/ |
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239 | |||
240 | /* VLAN Control 0 (8 bit) */ |
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241 | #define B53_VLAN_CTRL0 0x00 |
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242 | #define VC0_8021PF_CTRL_MASK 0x3 |
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243 | #define VC0_8021PF_CTRL_NONE 0x0 |
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244 | #define VC0_8021PF_CTRL_CHANGE_PRI 0x1 |
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245 | #define VC0_8021PF_CTRL_CHANGE_VID 0x2 |
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246 | #define VC0_8021PF_CTRL_CHANGE_BOTH 0x3 |
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247 | #define VC0_8021QF_CTRL_MASK 0xc |
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248 | #define VC0_8021QF_CTRL_CHANGE_PRI 0x1 |
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249 | #define VC0_8021QF_CTRL_CHANGE_VID 0x2 |
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250 | #define VC0_8021QF_CTRL_CHANGE_BOTH 0x3 |
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251 | #define VC0_RESERVED_1 BIT(1) |
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252 | #define VC0_DROP_VID_MISS BIT(4) |
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253 | #define VC0_VID_HASH_VID BIT(5) |
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254 | #define VC0_VID_CHK_EN BIT(6) /* Use VID,DA or VID,SA */ |
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255 | #define VC0_VLAN_EN BIT(7) /* 802.1Q VLAN Enabled */ |
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256 | |||
257 | /* VLAN Control 1 (8 bit) */ |
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258 | #define B53_VLAN_CTRL1 0x01 |
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259 | #define VC1_RX_MCST_TAG_EN BIT(1) |
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260 | #define VC1_RX_MCST_FWD_EN BIT(2) |
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261 | #define VC1_RX_MCST_UNTAG_EN BIT(3) |
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262 | |||
263 | /* VLAN Control 2 (8 bit) */ |
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264 | #define B53_VLAN_CTRL2 0x02 |
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265 | |||
266 | /* VLAN Control 3 (8 bit when BCM5325, 16 bit else) */ |
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267 | #define B53_VLAN_CTRL3 0x03 |
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268 | #define B53_VLAN_CTRL3_63XX 0x04 |
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269 | #define VC3_MAXSIZE_1532 BIT(6) /* 5325 only */ |
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270 | #define VC3_HIGH_8BIT_EN BIT(7) /* 5325 only */ |
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271 | |||
272 | /* VLAN Control 4 (8 bit) */ |
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273 | #define B53_VLAN_CTRL4 0x05 |
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274 | #define B53_VLAN_CTRL4_25 0x04 |
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275 | #define B53_VLAN_CTRL4_63XX 0x06 |
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276 | #define VC4_ING_VID_CHECK_S 6 |
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277 | #define VC4_ING_VID_CHECK_MASK (0x3 << VC4_ING_VID_CHECK_S) |
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278 | #define VC4_ING_VID_VIO_FWD 0 /* forward, but do not learn */ |
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279 | #define VC4_ING_VID_VIO_DROP 1 /* drop VID violations */ |
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280 | #define VC4_NO_ING_VID_CHK 2 /* do not check */ |
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281 | #define VC4_ING_VID_VIO_TO_IMP 3 /* redirect to MII port */ |
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282 | |||
283 | /* VLAN Control 5 (8 bit) */ |
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284 | #define B53_VLAN_CTRL5 0x06 |
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285 | #define B53_VLAN_CTRL5_25 0x05 |
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286 | #define B53_VLAN_CTRL5_63XX 0x07 |
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287 | #define VC5_VID_FFF_EN BIT(2) |
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288 | #define VC5_DROP_VTABLE_MISS BIT(3) |
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289 | |||
290 | /* VLAN Control 6 (8 bit) */ |
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291 | #define B53_VLAN_CTRL6 0x07 |
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292 | #define B53_VLAN_CTRL6_63XX 0x08 |
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293 | |||
294 | /* VLAN Table Access Register (16 bit) */ |
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295 | #define B53_VLAN_TABLE_ACCESS_25 0x06 /* BCM5325E/5350 */ |
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296 | #define B53_VLAN_TABLE_ACCESS_65 0x08 /* BCM5365 */ |
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297 | #define VTA_VID_LOW_MASK_25 0xf |
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298 | #define VTA_VID_LOW_MASK_65 0xff |
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299 | #define VTA_VID_HIGH_S_25 4 |
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300 | #define VTA_VID_HIGH_S_65 8 |
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301 | #define VTA_VID_HIGH_MASK_25 (0xff << VTA_VID_HIGH_S_25E) |
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302 | #define VTA_VID_HIGH_MASK_65 (0xf << VTA_VID_HIGH_S_65) |
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303 | #define VTA_RW_STATE BIT(12) |
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304 | #define VTA_RW_STATE_RD 0 |
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305 | #define VTA_RW_STATE_WR BIT(12) |
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306 | #define VTA_RW_OP_EN BIT(13) |
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307 | |||
308 | /* VLAN Read/Write Registers for (16/32 bit) */ |
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309 | #define B53_VLAN_WRITE_25 0x08 |
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310 | #define B53_VLAN_WRITE_65 0x0a |
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311 | #define B53_VLAN_READ 0x0c |
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312 | #define VA_MEMBER_MASK 0x3f |
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313 | #define VA_UNTAG_S_25 6 |
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314 | #define VA_UNTAG_MASK_25 0x3f |
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315 | #define VA_UNTAG_S_65 7 |
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316 | #define VA_UNTAG_MASK_65 0x1f |
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317 | #define VA_VID_HIGH_S 12 |
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318 | #define VA_VID_HIGH_MASK (0xffff << VA_VID_HIGH_S) |
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319 | #define VA_VALID_25 BIT(20) |
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320 | #define VA_VALID_25_R4 BIT(24) |
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321 | #define VA_VALID_65 BIT(14) |
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322 | |||
323 | /* VLAN Port Default Tag (16 bit) */ |
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324 | #define B53_VLAN_PORT_DEF_TAG(i) (0x10 + 2 * (i)) |
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325 | |||
326 | /************************************************************************* |
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327 | * Jumbo Frame Page Registers |
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328 | *************************************************************************/ |
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329 | |||
330 | /* Jumbo Enable Port Mask (bit i == port i enabled) (32 bit) */ |
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331 | #define B53_JUMBO_PORT_MASK 0x01 |
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332 | #define B53_JUMBO_PORT_MASK_63XX 0x04 |
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333 | #define JPM_10_100_JUMBO_EN BIT(24) /* GigE always enabled */ |
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334 | |||
335 | /* Good Frame Max Size without 802.1Q TAG (16 bit) */ |
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336 | #define B53_JUMBO_MAX_SIZE 0x05 |
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337 | #define B53_JUMBO_MAX_SIZE_63XX 0x08 |
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338 | #define JMS_MIN_SIZE 1518 |
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339 | #define JMS_MAX_SIZE 9724 |
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340 | |||
341 | /************************************************************************* |
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342 | * CFP Configuration Page Registers |
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343 | *************************************************************************/ |
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344 | |||
345 | /* CFP Control Register with ports map (8 bit) */ |
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346 | #define B53_CFP_CTRL 0x00 |
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347 | |||
348 | #endif /* !__B53_REGS_H */ |