OpenWrt – Blame information for rev 4
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Rev | Author | Line No. | Line |
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4 | office | 1 | From: Xo Wang <xow@google.com> |
2 | Date: Fri, 21 Oct 2016 10:20:13 -0700 |
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3 | Subject: [PATCH] net: phy: broadcom: Add support for BCM54612E |
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4 | |||
5 | This PHY has internal delays enabled after reset. This clears the |
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6 | internal delay enables unless the interface specifically requests them. |
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7 | |||
8 | Signed-off-by: Xo Wang <xow@google.com> |
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9 | Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> |
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10 | Reviewed-by: Joel Stanley <joel@jms.id.au> |
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11 | Signed-off-by: David S. Miller <davem@davemloft.net> |
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12 | --- |
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13 | |||
14 | --- a/drivers/net/phy/broadcom.c |
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15 | +++ b/drivers/net/phy/broadcom.c |
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16 | @@ -337,6 +337,41 @@ static int bcm5481_config_aneg(struct ph |
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17 | return ret; |
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18 | } |
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19 | |||
20 | +static int bcm54612e_config_aneg(struct phy_device *phydev) |
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21 | +{ |
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22 | + int ret; |
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23 | + |
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24 | + /* First, auto-negotiate. */ |
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25 | + ret = genphy_config_aneg(phydev); |
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26 | + |
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27 | + /* Clear TX internal delay unless requested. */ |
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28 | + if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) && |
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29 | + (phydev->interface != PHY_INTERFACE_MODE_RGMII_TXID)) { |
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30 | + /* Disable TXD to GTXCLK clock delay (default set) */ |
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31 | + /* Bit 9 is the only field in shadow register 00011 */ |
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32 | + bcm_phy_write_shadow(phydev, 0x03, 0); |
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33 | + } |
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34 | + |
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35 | + /* Clear RX internal delay unless requested. */ |
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36 | + if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) && |
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37 | + (phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) { |
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38 | + u16 reg; |
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39 | + |
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40 | + /* Errata: reads require filling in the write selector field */ |
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41 | + bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC, |
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42 | + MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC); |
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43 | + reg = phy_read(phydev, MII_BCM54XX_AUX_CTL); |
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44 | + /* Disable RXD to RXC delay (default set) */ |
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45 | + reg &= ~MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW; |
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46 | + /* Clear shadow selector field */ |
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47 | + reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK; |
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48 | + bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC, |
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49 | + MII_BCM54XX_AUXCTL_MISC_WREN | reg); |
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50 | + } |
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51 | + |
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52 | + return ret; |
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53 | +} |
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54 | + |
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55 | static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set) |
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56 | { |
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57 | int val; |
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58 | @@ -485,6 +520,18 @@ static struct phy_driver broadcom_driver |
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59 | .ack_interrupt = bcm_phy_ack_intr, |
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60 | .config_intr = bcm_phy_config_intr, |
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61 | }, { |
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62 | + .phy_id = PHY_ID_BCM54612E, |
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63 | + .phy_id_mask = 0xfffffff0, |
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64 | + .name = "Broadcom BCM54612E", |
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65 | + .features = PHY_GBIT_FEATURES | |
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66 | + SUPPORTED_Pause | SUPPORTED_Asym_Pause, |
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67 | + .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, |
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68 | + .config_init = bcm54xx_config_init, |
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69 | + .config_aneg = bcm54612e_config_aneg, |
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70 | + .read_status = genphy_read_status, |
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71 | + .ack_interrupt = bcm_phy_ack_intr, |
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72 | + .config_intr = bcm_phy_config_intr, |
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73 | +}, { |
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74 | .phy_id = PHY_ID_BCM54616S, |
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75 | .phy_id_mask = 0xfffffff0, |
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76 | .name = "Broadcom BCM54616S", |
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77 | @@ -600,6 +647,7 @@ static struct mdio_device_id __maybe_unu |
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78 | { PHY_ID_BCM5411, 0xfffffff0 }, |
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79 | { PHY_ID_BCM5421, 0xfffffff0 }, |
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80 | { PHY_ID_BCM5461, 0xfffffff0 }, |
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81 | + { PHY_ID_BCM54612E, 0xfffffff0 }, |
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82 | { PHY_ID_BCM54616S, 0xfffffff0 }, |
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83 | { PHY_ID_BCM5464, 0xfffffff0 }, |
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84 | { PHY_ID_BCM5481, 0xfffffff0 }, |
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85 | --- a/include/linux/brcmphy.h |
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86 | +++ b/include/linux/brcmphy.h |
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87 | @@ -18,6 +18,7 @@ |
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88 | #define PHY_ID_BCM5421 0x002060e0 |
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89 | #define PHY_ID_BCM5464 0x002060b0 |
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90 | #define PHY_ID_BCM5461 0x002060c0 |
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91 | +#define PHY_ID_BCM54612E 0x03625e60 |
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92 | #define PHY_ID_BCM54616S 0x03625d10 |
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93 | #define PHY_ID_BCM57780 0x03625d90 |
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94 |