OpenWrt – Blame information for rev 4
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Rev | Author | Line No. | Line |
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4 | office | 1 | From 6d5af7093aea4f18e040e73db2ad99aaa0c0f77e Mon Sep 17 00:00:00 2001 |
2 | From: Linus Walleij <linus.walleij@linaro.org> |
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3 | Date: Sun, 19 Nov 2017 11:04:23 +0100 |
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4 | Subject: [PATCH] ARM: dts: Add ethernet to a bunch of platforms |
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5 | |||
6 | These platforms have the PHY defined already so we just |
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7 | need to add a single device node to each of them to activate |
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8 | the ethernet device. |
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9 | |||
10 | The PHY skew/delay settings for pin control is known from a |
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11 | few vendor trees and old OpenWRT patch sets. |
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12 | |||
13 | This is a modified version of upstream commit |
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14 | 95220046a62c00b5afb1aa7c1971989d427db977, |
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15 | just dropping the NAS4220B changes. |
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16 | |||
17 | Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
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18 | --- |
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19 | arch/arm/boot/dts/gemini-dlink-dns-313.dts | 62 ++++++++++++++++++++++++++++++ |
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20 | arch/arm/boot/dts/gemini-wbd222.dts | 7 ++++ |
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21 | 2 files changed, 69 insertions(+) |
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22 | |||
23 | --- a/arch/arm/boot/dts/gemini-dlink-dns-313.dts |
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24 | +++ b/arch/arm/boot/dts/gemini-dlink-dns-313.dts |
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25 | @@ -215,6 +215,56 @@ |
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26 | groups = "gpio1dgrp"; |
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27 | }; |
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28 | }; |
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29 | + pinctrl-gmii { |
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30 | + mux { |
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31 | + function = "gmii"; |
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32 | + groups = "gmii_gmac0_grp"; |
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33 | + }; |
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34 | + /* |
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35 | + * In the vendor Linux tree, these values are set for the C3 |
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36 | + * version of the SL3512 ASIC with the comment "benson suggest" |
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37 | + */ |
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38 | + conf0 { |
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39 | + pins = "R8 GMAC0 RXDV", "U11 GMAC1 RXDV"; |
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40 | + skew-delay = <0>; |
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41 | + }; |
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42 | + conf1 { |
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43 | + pins = "T8 GMAC0 RXC"; |
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44 | + skew-delay = <10>; |
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45 | + }; |
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46 | + conf2 { |
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47 | + pins = "T11 GMAC1 RXC"; |
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48 | + skew-delay = <15>; |
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49 | + }; |
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50 | + conf3 { |
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51 | + pins = "P8 GMAC0 TXEN", "V11 GMAC1 TXEN"; |
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52 | + skew-delay = <7>; |
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53 | + }; |
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54 | + conf4 { |
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55 | + pins = "V7 GMAC0 TXC", "P10 GMAC1 TXC"; |
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56 | + skew-delay = <10>; |
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57 | + }; |
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58 | + conf5 { |
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59 | + /* The data lines all have default skew */ |
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60 | + pins = "U8 GMAC0 RXD0", "V8 GMAC0 RXD1", |
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61 | + "P9 GMAC0 RXD2", "R9 GMAC0 RXD3", |
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62 | + "R11 GMAC1 RXD0", "P11 GMAC1 RXD1", |
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63 | + "V12 GMAC1 RXD2", "U12 GMAC1 RXD3", |
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64 | + "R10 GMAC1 TXD0", "T10 GMAC1 TXD1", |
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65 | + "U10 GMAC1 TXD2", "V10 GMAC1 TXD3"; |
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66 | + skew-delay = <7>; |
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67 | + }; |
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68 | + conf6 { |
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69 | + pins = "U7 GMAC0 TXD0", "T7 GMAC0 TXD1", |
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70 | + "R7 GMAC0 TXD2", "P7 GMAC0 TXD3"; |
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71 | + skew-delay = <5>; |
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72 | + }; |
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73 | + /* Set up drive strength on GMAC0 to 16 mA */ |
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74 | + conf7 { |
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75 | + groups = "gmii_gmac0_grp"; |
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76 | + drive-strength = <16>; |
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77 | + }; |
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78 | + }; |
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79 | }; |
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80 | }; |
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81 | |||
82 | @@ -235,6 +285,18 @@ |
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83 | pinctrl-0 = <&gpio1_default_pins>; |
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84 | }; |
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85 | |||
86 | + ethernet@60000000 { |
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87 | + status = "okay"; |
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88 | + |
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89 | + ethernet-port@0 { |
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90 | + phy-mode = "rgmii"; |
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91 | + phy-handle = <&phy0>; |
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92 | + }; |
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93 | + ethernet-port@1 { |
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94 | + /* Not used in this platform */ |
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95 | + }; |
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96 | + }; |
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97 | + |
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98 | ata@63000000 { |
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99 | status = "okay"; |
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100 | }; |
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101 | --- a/arch/arm/boot/dts/gemini-wbd222.dts |
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102 | +++ b/arch/arm/boot/dts/gemini-wbd222.dts |
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103 | @@ -136,6 +136,13 @@ |
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104 | "gpio0bgrp"; |
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105 | }; |
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106 | }; |
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107 | + pinctrl-gmii { |
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108 | + /* This platform use both the ethernet ports */ |
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109 | + mux { |
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110 | + function = "gmii"; |
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111 | + groups = "gmii_gmac0_grp", "gmii_gmac1_grp"; |
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112 | + }; |
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113 | + }; |
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114 | }; |
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115 | }; |
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116 |