OpenWrt – Blame information for rev 4

Subversion Repositories:
Rev:
Rev Author Line No. Line
4 office 1 From 6d5af7093aea4f18e040e73db2ad99aaa0c0f77e Mon Sep 17 00:00:00 2001
2 From: Linus Walleij <linus.walleij@linaro.org>
3 Date: Sun, 19 Nov 2017 11:04:23 +0100
4 Subject: [PATCH] ARM: dts: Add ethernet to a bunch of platforms
5  
6 These platforms have the PHY defined already so we just
7 need to add a single device node to each of them to activate
8 the ethernet device.
9  
10 The PHY skew/delay settings for pin control is known from a
11 few vendor trees and old OpenWRT patch sets.
12  
13 This is a modified version of upstream commit
14 95220046a62c00b5afb1aa7c1971989d427db977,
15 just dropping the NAS4220B changes.
16  
17 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
18 ---
19 arch/arm/boot/dts/gemini-dlink-dns-313.dts | 62 ++++++++++++++++++++++++++++++
20 arch/arm/boot/dts/gemini-wbd222.dts | 7 ++++
21 2 files changed, 69 insertions(+)
22  
23 --- a/arch/arm/boot/dts/gemini-dlink-dns-313.dts
24 +++ b/arch/arm/boot/dts/gemini-dlink-dns-313.dts
25 @@ -215,6 +215,56 @@
26 groups = "gpio1dgrp";
27 };
28 };
29 + pinctrl-gmii {
30 + mux {
31 + function = "gmii";
32 + groups = "gmii_gmac0_grp";
33 + };
34 + /*
35 + * In the vendor Linux tree, these values are set for the C3
36 + * version of the SL3512 ASIC with the comment "benson suggest"
37 + */
38 + conf0 {
39 + pins = "R8 GMAC0 RXDV", "U11 GMAC1 RXDV";
40 + skew-delay = <0>;
41 + };
42 + conf1 {
43 + pins = "T8 GMAC0 RXC";
44 + skew-delay = <10>;
45 + };
46 + conf2 {
47 + pins = "T11 GMAC1 RXC";
48 + skew-delay = <15>;
49 + };
50 + conf3 {
51 + pins = "P8 GMAC0 TXEN", "V11 GMAC1 TXEN";
52 + skew-delay = <7>;
53 + };
54 + conf4 {
55 + pins = "V7 GMAC0 TXC", "P10 GMAC1 TXC";
56 + skew-delay = <10>;
57 + };
58 + conf5 {
59 + /* The data lines all have default skew */
60 + pins = "U8 GMAC0 RXD0", "V8 GMAC0 RXD1",
61 + "P9 GMAC0 RXD2", "R9 GMAC0 RXD3",
62 + "R11 GMAC1 RXD0", "P11 GMAC1 RXD1",
63 + "V12 GMAC1 RXD2", "U12 GMAC1 RXD3",
64 + "R10 GMAC1 TXD0", "T10 GMAC1 TXD1",
65 + "U10 GMAC1 TXD2", "V10 GMAC1 TXD3";
66 + skew-delay = <7>;
67 + };
68 + conf6 {
69 + pins = "U7 GMAC0 TXD0", "T7 GMAC0 TXD1",
70 + "R7 GMAC0 TXD2", "P7 GMAC0 TXD3";
71 + skew-delay = <5>;
72 + };
73 + /* Set up drive strength on GMAC0 to 16 mA */
74 + conf7 {
75 + groups = "gmii_gmac0_grp";
76 + drive-strength = <16>;
77 + };
78 + };
79 };
80 };
81  
82 @@ -235,6 +285,18 @@
83 pinctrl-0 = <&gpio1_default_pins>;
84 };
85  
86 + ethernet@60000000 {
87 + status = "okay";
88 +
89 + ethernet-port@0 {
90 + phy-mode = "rgmii";
91 + phy-handle = <&phy0>;
92 + };
93 + ethernet-port@1 {
94 + /* Not used in this platform */
95 + };
96 + };
97 +
98 ata@63000000 {
99 status = "okay";
100 };
101 --- a/arch/arm/boot/dts/gemini-wbd222.dts
102 +++ b/arch/arm/boot/dts/gemini-wbd222.dts
103 @@ -136,6 +136,13 @@
104 "gpio0bgrp";
105 };
106 };
107 + pinctrl-gmii {
108 + /* This platform use both the ethernet ports */
109 + mux {
110 + function = "gmii";
111 + groups = "gmii_gmac0_grp", "gmii_gmac1_grp";
112 + };
113 + };
114 };
115 };
116