OpenWrt – Blame information for rev 4
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4 | office | 1 | ;- ---------------------------------------------------------------------------- |
2 | ;- ATMEL Microcontroller Software Support - ROUSSET - |
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3 | ;- ---------------------------------------------------------------------------- |
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4 | ;- The software is delivered "AS IS" without warranty or condition of any |
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5 | ;- kind, either express, implied or statutory. This includes without |
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6 | ;- limitation any warranty or condition with respect to merchantability or |
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7 | ;- fitness for any particular purpose, or against the infringements of |
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8 | ;- intellectual property rights of others. |
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9 | ;- ---------------------------------------------------------------------------- |
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10 | ;- File Name : AT91RM9200.h |
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11 | ;- Object : AT91RM9200 definitions |
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12 | ;- Generated : AT91 SW Application Group 11/19/2003 (17:20:51) |
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13 | ;- |
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14 | ;- CVS Reference : /AT91RM9200.pl/1.16/Fri Feb 07 10:29:51 2003// |
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15 | ;- CVS Reference : /SYS_AT91RM9200.pl/1.2/Fri Jan 17 12:44:37 2003// |
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16 | ;- CVS Reference : /MC_1760A.pl/1.1/Fri Aug 23 14:38:22 2002// |
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17 | ;- CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:47 2002// |
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18 | ;- CVS Reference : /PMC_2636A.pl/1.1.1.1/Fri Jun 28 09:36:48 2002// |
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19 | ;- CVS Reference : /ST_1763B.pl/1.1/Fri Aug 23 14:41:42 2002// |
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20 | ;- CVS Reference : /RTC_1245D.pl/1.2/Fri Jan 31 12:19:06 2003// |
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21 | ;- CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:47 2002// |
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22 | ;- CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003// |
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23 | ;- CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 02 14:45:38 2002// |
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24 | ;- CVS Reference : /MCI_1764A.pl/1.2/Thu Nov 14 17:48:24 2002// |
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25 | ;- CVS Reference : /US_1739C.pl/1.2/Fri Jul 12 07:49:25 2002// |
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26 | ;- CVS Reference : /SPI_AT91RMxxxx.pl/1.3/Tue Nov 26 10:20:29 2002// |
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27 | ;- CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 08 13:26:39 2002// |
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28 | ;- CVS Reference : /TC_1753B.pl/1.2/Fri Jan 31 12:19:55 2003// |
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29 | ;- CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 07 10:30:07 2003// |
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30 | ;- CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:23 2002// |
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31 | ;- CVS Reference : /UHP_xxxxA.pl/1.1/Mon Jul 22 12:21:58 2002// |
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32 | ;- CVS Reference : /EMAC_1794A.pl/1.4/Fri Jan 17 12:11:54 2003// |
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33 | ;- CVS Reference : /EBI_1759B.pl/1.10/Fri Jan 17 12:44:29 2003// |
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34 | ;- CVS Reference : /SMC_1783A.pl/1.3/Thu Oct 31 14:38:17 2002// |
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35 | ;- CVS Reference : /SDRC_1758B.pl/1.2/Thu Oct 03 13:04:41 2002// |
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36 | ;- CVS Reference : /BFC_1757B.pl/1.3/Thu Oct 31 14:38:00 2002// |
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37 | ;- ---------------------------------------------------------------------------- |
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38 | |||
39 | ;- Hardware register definition |
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40 | |||
41 | ;- ***************************************************************************** |
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42 | ;- SOFTWARE API DEFINITION FOR System Peripherals |
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43 | ;- ***************************************************************************** |
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44 | |||
45 | ;- ***************************************************************************** |
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46 | ;- SOFTWARE API DEFINITION FOR Memory Controller Interface |
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47 | ;- ***************************************************************************** |
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48 | ^ 0 ;- AT91S_MC |
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49 | MC_RCR # 4 ;- MC Remap Control Register |
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50 | MC_ASR # 4 ;- MC Abort Status Register |
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51 | MC_AASR # 4 ;- MC Abort Address Status Register |
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52 | # 4 ;- Reserved |
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53 | MC_PUIA # 64 ;- MC Protection Unit Area |
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54 | MC_PUP # 4 ;- MC Protection Unit Peripherals |
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55 | MC_PUER # 4 ;- MC Protection Unit Enable Register |
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56 | ;- -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- |
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57 | AT91C_MC_RCB EQU (0x1:SHL:0) ;- (MC) Remap Command Bit |
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58 | ;- -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- |
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59 | AT91C_MC_UNDADD EQU (0x1:SHL:0) ;- (MC) Undefined Addess Abort Status |
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60 | AT91C_MC_MISADD EQU (0x1:SHL:1) ;- (MC) Misaligned Addess Abort Status |
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61 | AT91C_MC_MPU EQU (0x1:SHL:2) ;- (MC) Memory protection Unit Abort Status |
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62 | AT91C_MC_ABTSZ EQU (0x3:SHL:8) ;- (MC) Abort Size Status |
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63 | AT91C_MC_ABTSZ_BYTE EQU (0x0:SHL:8) ;- (MC) Byte |
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64 | AT91C_MC_ABTSZ_HWORD EQU (0x1:SHL:8) ;- (MC) Half-word |
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65 | AT91C_MC_ABTSZ_WORD EQU (0x2:SHL:8) ;- (MC) Word |
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66 | AT91C_MC_ABTTYP EQU (0x3:SHL:10) ;- (MC) Abort Type Status |
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67 | AT91C_MC_ABTTYP_DATAR EQU (0x0:SHL:10) ;- (MC) Data Read |
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68 | AT91C_MC_ABTTYP_DATAW EQU (0x1:SHL:10) ;- (MC) Data Write |
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69 | AT91C_MC_ABTTYP_FETCH EQU (0x2:SHL:10) ;- (MC) Code Fetch |
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70 | AT91C_MC_MST0 EQU (0x1:SHL:16) ;- (MC) Master 0 Abort Source |
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71 | AT91C_MC_MST1 EQU (0x1:SHL:17) ;- (MC) Master 1 Abort Source |
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72 | AT91C_MC_SVMST0 EQU (0x1:SHL:24) ;- (MC) Saved Master 0 Abort Source |
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73 | AT91C_MC_SVMST1 EQU (0x1:SHL:25) ;- (MC) Saved Master 1 Abort Source |
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74 | ;- -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area -------- |
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75 | AT91C_MC_PROT EQU (0x3:SHL:0) ;- (MC) Protection |
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76 | AT91C_MC_PROT_PNAUNA EQU (0x0) ;- (MC) Privilege: No Access, User: No Access |
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77 | AT91C_MC_PROT_PRWUNA EQU (0x1) ;- (MC) Privilege: Read/Write, User: No Access |
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78 | AT91C_MC_PROT_PRWURO EQU (0x2) ;- (MC) Privilege: Read/Write, User: Read Only |
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79 | AT91C_MC_PROT_PRWURW EQU (0x3) ;- (MC) Privilege: Read/Write, User: Read/Write |
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80 | AT91C_MC_SIZE EQU (0xF:SHL:4) ;- (MC) Internal Area Size |
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81 | AT91C_MC_SIZE_1KB EQU (0x0:SHL:4) ;- (MC) Area size 1KByte |
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82 | AT91C_MC_SIZE_2KB EQU (0x1:SHL:4) ;- (MC) Area size 2KByte |
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83 | AT91C_MC_SIZE_4KB EQU (0x2:SHL:4) ;- (MC) Area size 4KByte |
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84 | AT91C_MC_SIZE_8KB EQU (0x3:SHL:4) ;- (MC) Area size 8KByte |
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85 | AT91C_MC_SIZE_16KB EQU (0x4:SHL:4) ;- (MC) Area size 16KByte |
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86 | AT91C_MC_SIZE_32KB EQU (0x5:SHL:4) ;- (MC) Area size 32KByte |
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87 | AT91C_MC_SIZE_64KB EQU (0x6:SHL:4) ;- (MC) Area size 64KByte |
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88 | AT91C_MC_SIZE_128KB EQU (0x7:SHL:4) ;- (MC) Area size 128KByte |
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89 | AT91C_MC_SIZE_256KB EQU (0x8:SHL:4) ;- (MC) Area size 256KByte |
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90 | AT91C_MC_SIZE_512KB EQU (0x9:SHL:4) ;- (MC) Area size 512KByte |
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91 | AT91C_MC_SIZE_1MB EQU (0xA:SHL:4) ;- (MC) Area size 1MByte |
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92 | AT91C_MC_SIZE_2MB EQU (0xB:SHL:4) ;- (MC) Area size 2MByte |
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93 | AT91C_MC_SIZE_4MB EQU (0xC:SHL:4) ;- (MC) Area size 4MByte |
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94 | AT91C_MC_SIZE_8MB EQU (0xD:SHL:4) ;- (MC) Area size 8MByte |
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95 | AT91C_MC_SIZE_16MB EQU (0xE:SHL:4) ;- (MC) Area size 16MByte |
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96 | AT91C_MC_SIZE_64MB EQU (0xF:SHL:4) ;- (MC) Area size 64MByte |
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97 | AT91C_MC_BA EQU (0x3FFFF:SHL:10) ;- (MC) Internal Area Base Address |
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98 | ;- -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral -------- |
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99 | ;- -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area -------- |
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100 | AT91C_MC_PUEB EQU (0x1:SHL:0) ;- (MC) Protection Unit enable Bit |
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101 | |||
102 | ;- ***************************************************************************** |
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103 | ;- SOFTWARE API DEFINITION FOR Real-time Clock Alarm and Parallel Load Interface |
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104 | ;- ***************************************************************************** |
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105 | ^ 0 ;- AT91S_RTC |
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106 | RTC_CR # 4 ;- Control Register |
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107 | RTC_MR # 4 ;- Mode Register |
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108 | RTC_TIMR # 4 ;- Time Register |
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109 | RTC_CALR # 4 ;- Calendar Register |
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110 | RTC_TIMALR # 4 ;- Time Alarm Register |
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111 | RTC_CALALR # 4 ;- Calendar Alarm Register |
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112 | RTC_SR # 4 ;- Status Register |
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113 | RTC_SCCR # 4 ;- Status Clear Command Register |
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114 | RTC_IER # 4 ;- Interrupt Enable Register |
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115 | RTC_IDR # 4 ;- Interrupt Disable Register |
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116 | RTC_IMR # 4 ;- Interrupt Mask Register |
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117 | RTC_VER # 4 ;- Valid Entry Register |
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118 | ;- -------- RTC_CR : (RTC Offset: 0x0) RTC Control Register -------- |
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119 | AT91C_RTC_UPDTIM EQU (0x1:SHL:0) ;- (RTC) Update Request Time Register |
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120 | AT91C_RTC_UPDCAL EQU (0x1:SHL:1) ;- (RTC) Update Request Calendar Register |
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121 | AT91C_RTC_TIMEVSEL EQU (0x3:SHL:8) ;- (RTC) Time Event Selection |
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122 | AT91C_RTC_TIMEVSEL_MINUTE EQU (0x0:SHL:8) ;- (RTC) Minute change. |
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123 | AT91C_RTC_TIMEVSEL_HOUR EQU (0x1:SHL:8) ;- (RTC) Hour change. |
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124 | AT91C_RTC_TIMEVSEL_DAY24 EQU (0x2:SHL:8) ;- (RTC) Every day at midnight. |
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125 | AT91C_RTC_TIMEVSEL_DAY12 EQU (0x3:SHL:8) ;- (RTC) Every day at noon. |
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126 | AT91C_RTC_CALEVSEL EQU (0x3:SHL:16) ;- (RTC) Calendar Event Selection |
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127 | AT91C_RTC_CALEVSEL_WEEK EQU (0x0:SHL:16) ;- (RTC) Week change (every Monday at time 00:00:00). |
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128 | AT91C_RTC_CALEVSEL_MONTH EQU (0x1:SHL:16) ;- (RTC) Month change (every 01 of each month at time 00:00:00). |
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129 | AT91C_RTC_CALEVSEL_YEAR EQU (0x2:SHL:16) ;- (RTC) Year change (every January 1 at time 00:00:00). |
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130 | ;- -------- RTC_MR : (RTC Offset: 0x4) RTC Mode Register -------- |
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131 | AT91C_RTC_HRMOD EQU (0x1:SHL:0) ;- (RTC) 12-24 hour Mode |
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132 | ;- -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register -------- |
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133 | AT91C_RTC_SEC EQU (0x7F:SHL:0) ;- (RTC) Current Second |
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134 | AT91C_RTC_MIN EQU (0x7F:SHL:8) ;- (RTC) Current Minute |
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135 | AT91C_RTC_HOUR EQU (0x1F:SHL:16) ;- (RTC) Current Hour |
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136 | AT91C_RTC_AMPM EQU (0x1:SHL:22) ;- (RTC) Ante Meridiem, Post Meridiem Indicator |
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137 | ;- -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register -------- |
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138 | AT91C_RTC_CENT EQU (0x3F:SHL:0) ;- (RTC) Current Century |
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139 | AT91C_RTC_YEAR EQU (0xFF:SHL:8) ;- (RTC) Current Year |
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140 | AT91C_RTC_MONTH EQU (0x1F:SHL:16) ;- (RTC) Current Month |
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141 | AT91C_RTC_DAY EQU (0x7:SHL:21) ;- (RTC) Current Day |
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142 | AT91C_RTC_DATE EQU (0x3F:SHL:24) ;- (RTC) Current Date |
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143 | ;- -------- RTC_TIMALR : (RTC Offset: 0x10) RTC Time Alarm Register -------- |
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144 | AT91C_RTC_SECEN EQU (0x1:SHL:7) ;- (RTC) Second Alarm Enable |
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145 | AT91C_RTC_MINEN EQU (0x1:SHL:15) ;- (RTC) Minute Alarm |
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146 | AT91C_RTC_HOUREN EQU (0x1:SHL:23) ;- (RTC) Current Hour |
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147 | ;- -------- RTC_CALALR : (RTC Offset: 0x14) RTC Calendar Alarm Register -------- |
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148 | AT91C_RTC_MONTHEN EQU (0x1:SHL:23) ;- (RTC) Month Alarm Enable |
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149 | AT91C_RTC_DATEEN EQU (0x1:SHL:31) ;- (RTC) Date Alarm Enable |
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150 | ;- -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register -------- |
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151 | AT91C_RTC_ACKUPD EQU (0x1:SHL:0) ;- (RTC) Acknowledge for Update |
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152 | AT91C_RTC_ALARM EQU (0x1:SHL:1) ;- (RTC) Alarm Flag |
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153 | AT91C_RTC_SECEV EQU (0x1:SHL:2) ;- (RTC) Second Event |
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154 | AT91C_RTC_TIMEV EQU (0x1:SHL:3) ;- (RTC) Time Event |
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155 | AT91C_RTC_CALEV EQU (0x1:SHL:4) ;- (RTC) Calendar event |
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156 | ;- -------- RTC_SCCR : (RTC Offset: 0x1c) RTC Status Clear Command Register -------- |
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157 | ;- -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register -------- |
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158 | ;- -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register -------- |
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159 | ;- -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register -------- |
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160 | ;- -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register -------- |
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161 | AT91C_RTC_NVTIM EQU (0x1:SHL:0) ;- (RTC) Non valid Time |
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162 | AT91C_RTC_NVCAL EQU (0x1:SHL:1) ;- (RTC) Non valid Calendar |
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163 | AT91C_RTC_NVTIMALR EQU (0x1:SHL:2) ;- (RTC) Non valid time Alarm |
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164 | AT91C_RTC_NVCALALR EQU (0x1:SHL:3) ;- (RTC) Nonvalid Calendar Alarm |
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165 | |||
166 | ;- ***************************************************************************** |
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167 | ;- SOFTWARE API DEFINITION FOR System Timer Interface |
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168 | ;- ***************************************************************************** |
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169 | ^ 0 ;- AT91S_ST |
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170 | ST_CR # 4 ;- Control Register |
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171 | ST_PIMR # 4 ;- Period Interval Mode Register |
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172 | ST_WDMR # 4 ;- Watchdog Mode Register |
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173 | ST_RTMR # 4 ;- Real-time Mode Register |
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174 | ST_SR # 4 ;- Status Register |
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175 | ST_IER # 4 ;- Interrupt Enable Register |
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176 | ST_IDR # 4 ;- Interrupt Disable Register |
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177 | ST_IMR # 4 ;- Interrupt Mask Register |
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178 | ST_RTAR # 4 ;- Real-time Alarm Register |
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179 | ST_CRTR # 4 ;- Current Real-time Register |
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180 | ;- -------- ST_CR : (ST Offset: 0x0) System Timer Control Register -------- |
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181 | AT91C_ST_WDRST EQU (0x1:SHL:0) ;- (ST) Watchdog Timer Restart |
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182 | ;- -------- ST_PIMR : (ST Offset: 0x4) System Timer Period Interval Mode Register -------- |
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183 | AT91C_ST_PIV EQU (0xFFFF:SHL:0) ;- (ST) Watchdog Timer Restart |
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184 | ;- -------- ST_WDMR : (ST Offset: 0x8) System Timer Watchdog Mode Register -------- |
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185 | AT91C_ST_WDV EQU (0xFFFF:SHL:0) ;- (ST) Watchdog Timer Restart |
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186 | AT91C_ST_RSTEN EQU (0x1:SHL:16) ;- (ST) Reset Enable |
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187 | AT91C_ST_EXTEN EQU (0x1:SHL:17) ;- (ST) External Signal Assertion Enable |
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188 | ;- -------- ST_RTMR : (ST Offset: 0xc) System Timer Real-time Mode Register -------- |
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189 | AT91C_ST_RTPRES EQU (0xFFFF:SHL:0) ;- (ST) Real-time Timer Prescaler Value |
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190 | ;- -------- ST_SR : (ST Offset: 0x10) System Timer Status Register -------- |
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191 | AT91C_ST_PITS EQU (0x1:SHL:0) ;- (ST) Period Interval Timer Interrupt |
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192 | AT91C_ST_WDOVF EQU (0x1:SHL:1) ;- (ST) Watchdog Overflow |
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193 | AT91C_ST_RTTINC EQU (0x1:SHL:2) ;- (ST) Real-time Timer Increment |
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194 | AT91C_ST_ALMS EQU (0x1:SHL:3) ;- (ST) Alarm Status |
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195 | ;- -------- ST_IER : (ST Offset: 0x14) System Timer Interrupt Enable Register -------- |
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196 | ;- -------- ST_IDR : (ST Offset: 0x18) System Timer Interrupt Disable Register -------- |
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197 | ;- -------- ST_IMR : (ST Offset: 0x1c) System Timer Interrupt Mask Register -------- |
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198 | ;- -------- ST_RTAR : (ST Offset: 0x20) System Timer Real-time Alarm Register -------- |
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199 | AT91C_ST_ALMV EQU (0xFFFFF:SHL:0) ;- (ST) Alarm Value Value |
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200 | ;- -------- ST_CRTR : (ST Offset: 0x24) System Timer Current Real-time Register -------- |
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201 | AT91C_ST_CRTV EQU (0xFFFFF:SHL:0) ;- (ST) Current Real-time Value |
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202 | |||
203 | ;- ***************************************************************************** |
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204 | ;- SOFTWARE API DEFINITION FOR Power Management Controler |
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205 | ;- ***************************************************************************** |
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206 | ^ 0 ;- AT91S_PMC |
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207 | PMC_SCER # 4 ;- System Clock Enable Register |
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208 | PMC_SCDR # 4 ;- System Clock Disable Register |
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209 | PMC_SCSR # 4 ;- System Clock Status Register |
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210 | # 4 ;- Reserved |
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211 | PMC_PCER # 4 ;- Peripheral Clock Enable Register |
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212 | PMC_PCDR # 4 ;- Peripheral Clock Disable Register |
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213 | PMC_PCSR # 4 ;- Peripheral Clock Status Register |
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214 | # 20 ;- Reserved |
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215 | PMC_MCKR # 4 ;- Master Clock Register |
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216 | # 12 ;- Reserved |
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217 | PMC_PCKR # 32 ;- Programmable Clock Register |
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218 | PMC_IER # 4 ;- Interrupt Enable Register |
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219 | PMC_IDR # 4 ;- Interrupt Disable Register |
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220 | PMC_SR # 4 ;- Status Register |
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221 | PMC_IMR # 4 ;- Interrupt Mask Register |
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222 | ;- -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- |
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223 | AT91C_PMC_PCK EQU (0x1:SHL:0) ;- (PMC) Processor Clock |
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224 | AT91C_PMC_UDP EQU (0x1:SHL:1) ;- (PMC) USB Device Port Clock |
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225 | AT91C_PMC_MCKUDP EQU (0x1:SHL:2) ;- (PMC) USB Device Port Master Clock Automatic Disable on Suspend |
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226 | AT91C_PMC_UHP EQU (0x1:SHL:4) ;- (PMC) USB Host Port Clock |
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227 | AT91C_PMC_PCK0 EQU (0x1:SHL:8) ;- (PMC) Programmable Clock Output |
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228 | AT91C_PMC_PCK1 EQU (0x1:SHL:9) ;- (PMC) Programmable Clock Output |
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229 | AT91C_PMC_PCK2 EQU (0x1:SHL:10) ;- (PMC) Programmable Clock Output |
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230 | AT91C_PMC_PCK3 EQU (0x1:SHL:11) ;- (PMC) Programmable Clock Output |
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231 | AT91C_PMC_PCK4 EQU (0x1:SHL:12) ;- (PMC) Programmable Clock Output |
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232 | AT91C_PMC_PCK5 EQU (0x1:SHL:13) ;- (PMC) Programmable Clock Output |
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233 | AT91C_PMC_PCK6 EQU (0x1:SHL:14) ;- (PMC) Programmable Clock Output |
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234 | AT91C_PMC_PCK7 EQU (0x1:SHL:15) ;- (PMC) Programmable Clock Output |
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235 | ;- -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- |
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236 | ;- -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- |
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237 | ;- -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- |
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238 | AT91C_PMC_CSS EQU (0x3:SHL:0) ;- (PMC) Programmable Clock Selection |
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239 | AT91C_PMC_CSS_SLOW_CLK EQU (0x0) ;- (PMC) Slow Clock is selected |
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240 | AT91C_PMC_CSS_MAIN_CLK EQU (0x1) ;- (PMC) Main Clock is selected |
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241 | AT91C_PMC_CSS_PLLA_CLK EQU (0x2) ;- (PMC) Clock from PLL A is selected |
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242 | AT91C_PMC_CSS_PLLB_CLK EQU (0x3) ;- (PMC) Clock from PLL B is selected |
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243 | AT91C_PMC_PRES EQU (0x7:SHL:2) ;- (PMC) Programmable Clock Prescaler |
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244 | AT91C_PMC_PRES_CLK EQU (0x0:SHL:2) ;- (PMC) Selected clock |
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245 | AT91C_PMC_PRES_CLK_2 EQU (0x1:SHL:2) ;- (PMC) Selected clock divided by 2 |
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246 | AT91C_PMC_PRES_CLK_4 EQU (0x2:SHL:2) ;- (PMC) Selected clock divided by 4 |
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247 | AT91C_PMC_PRES_CLK_8 EQU (0x3:SHL:2) ;- (PMC) Selected clock divided by 8 |
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248 | AT91C_PMC_PRES_CLK_16 EQU (0x4:SHL:2) ;- (PMC) Selected clock divided by 16 |
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249 | AT91C_PMC_PRES_CLK_32 EQU (0x5:SHL:2) ;- (PMC) Selected clock divided by 32 |
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250 | AT91C_PMC_PRES_CLK_64 EQU (0x6:SHL:2) ;- (PMC) Selected clock divided by 64 |
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251 | AT91C_PMC_MDIV EQU (0x3:SHL:8) ;- (PMC) Master Clock Division |
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252 | AT91C_PMC_MDIV_1 EQU (0x0:SHL:8) ;- (PMC) The master clock and the processor clock are the same |
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253 | AT91C_PMC_MDIV_2 EQU (0x1:SHL:8) ;- (PMC) The processor clock is twice as fast as the master clock |
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254 | AT91C_PMC_MDIV_3 EQU (0x2:SHL:8) ;- (PMC) The processor clock is three times faster than the master clock |
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255 | AT91C_PMC_MDIV_4 EQU (0x3:SHL:8) ;- (PMC) The processor clock is four times faster than the master clock |
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256 | ;- -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- |
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257 | ;- -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- |
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258 | AT91C_PMC_MOSCS EQU (0x1:SHL:0) ;- (PMC) MOSC Status/Enable/Disable/Mask |
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259 | AT91C_PMC_LOCKA EQU (0x1:SHL:1) ;- (PMC) PLL A Status/Enable/Disable/Mask |
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260 | AT91C_PMC_LOCKB EQU (0x1:SHL:2) ;- (PMC) PLL B Status/Enable/Disable/Mask |
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261 | AT91C_PMC_MCKRDY EQU (0x1:SHL:3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask |
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262 | AT91C_PMC_PCK0RDY EQU (0x1:SHL:8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask |
||
263 | AT91C_PMC_PCK1RDY EQU (0x1:SHL:9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask |
||
264 | AT91C_PMC_PCK2RDY EQU (0x1:SHL:10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask |
||
265 | AT91C_PMC_PCK3RDY EQU (0x1:SHL:11) ;- (PMC) PCK3_RDY Status/Enable/Disable/Mask |
||
266 | AT91C_PMC_PCK4RDY EQU (0x1:SHL:12) ;- (PMC) PCK4_RDY Status/Enable/Disable/Mask |
||
267 | AT91C_PMC_PCK5RDY EQU (0x1:SHL:13) ;- (PMC) PCK5_RDY Status/Enable/Disable/Mask |
||
268 | AT91C_PMC_PCK6RDY EQU (0x1:SHL:14) ;- (PMC) PCK6_RDY Status/Enable/Disable/Mask |
||
269 | AT91C_PMC_PCK7RDY EQU (0x1:SHL:15) ;- (PMC) PCK7_RDY Status/Enable/Disable/Mask |
||
270 | ;- -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- |
||
271 | ;- -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- |
||
272 | ;- -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- |
||
273 | |||
274 | ;- ***************************************************************************** |
||
275 | ;- SOFTWARE API DEFINITION FOR Clock Generator Controler |
||
276 | ;- ***************************************************************************** |
||
277 | ^ 0 ;- AT91S_CKGR |
||
278 | CKGR_MOR # 4 ;- Main Oscillator Register |
||
279 | CKGR_MCFR # 4 ;- Main Clock Frequency Register |
||
280 | CKGR_PLLAR # 4 ;- PLL A Register |
||
281 | CKGR_PLLBR # 4 ;- PLL B Register |
||
282 | ;- -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- |
||
283 | AT91C_CKGR_MOSCEN EQU (0x1:SHL:0) ;- (CKGR) Main Oscillator Enable |
||
284 | AT91C_CKGR_OSCTEST EQU (0x1:SHL:1) ;- (CKGR) Oscillator Test |
||
285 | AT91C_CKGR_OSCOUNT EQU (0xFF:SHL:8) ;- (CKGR) Main Oscillator Start-up Time |
||
286 | ;- -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- |
||
287 | AT91C_CKGR_MAINF EQU (0xFFFF:SHL:0) ;- (CKGR) Main Clock Frequency |
||
288 | AT91C_CKGR_MAINRDY EQU (0x1:SHL:16) ;- (CKGR) Main Clock Ready |
||
289 | ;- -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- |
||
290 | AT91C_CKGR_DIVA EQU (0xFF:SHL:0) ;- (CKGR) Divider Selected |
||
291 | AT91C_CKGR_DIVA_0 EQU (0x0) ;- (CKGR) Divider output is 0 |
||
292 | AT91C_CKGR_DIVA_BYPASS EQU (0x1) ;- (CKGR) Divider is bypassed |
||
293 | AT91C_CKGR_PLLACOUNT EQU (0x3F:SHL:8) ;- (CKGR) PLL A Counter |
||
294 | AT91C_CKGR_OUTA EQU (0x3:SHL:14) ;- (CKGR) PLL A Output Frequency Range |
||
295 | AT91C_CKGR_OUTA_0 EQU (0x0:SHL:14) ;- (CKGR) Please refer to the PLLA datasheet |
||
296 | AT91C_CKGR_OUTA_1 EQU (0x1:SHL:14) ;- (CKGR) Please refer to the PLLA datasheet |
||
297 | AT91C_CKGR_OUTA_2 EQU (0x2:SHL:14) ;- (CKGR) Please refer to the PLLA datasheet |
||
298 | AT91C_CKGR_OUTA_3 EQU (0x3:SHL:14) ;- (CKGR) Please refer to the PLLA datasheet |
||
299 | AT91C_CKGR_MULA EQU (0x7FF:SHL:16) ;- (CKGR) PLL A Multiplier |
||
300 | AT91C_CKGR_SRCA EQU (0x1:SHL:29) ;- (CKGR) PLL A Source |
||
301 | ;- -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- |
||
302 | AT91C_CKGR_DIVB EQU (0xFF:SHL:0) ;- (CKGR) Divider Selected |
||
303 | AT91C_CKGR_DIVB_0 EQU (0x0) ;- (CKGR) Divider output is 0 |
||
304 | AT91C_CKGR_DIVB_BYPASS EQU (0x1) ;- (CKGR) Divider is bypassed |
||
305 | AT91C_CKGR_PLLBCOUNT EQU (0x3F:SHL:8) ;- (CKGR) PLL B Counter |
||
306 | AT91C_CKGR_OUTB EQU (0x3:SHL:14) ;- (CKGR) PLL B Output Frequency Range |
||
307 | AT91C_CKGR_OUTB_0 EQU (0x0:SHL:14) ;- (CKGR) Please refer to the PLLB datasheet |
||
308 | AT91C_CKGR_OUTB_1 EQU (0x1:SHL:14) ;- (CKGR) Please refer to the PLLB datasheet |
||
309 | AT91C_CKGR_OUTB_2 EQU (0x2:SHL:14) ;- (CKGR) Please refer to the PLLB datasheet |
||
310 | AT91C_CKGR_OUTB_3 EQU (0x3:SHL:14) ;- (CKGR) Please refer to the PLLB datasheet |
||
311 | AT91C_CKGR_MULB EQU (0x7FF:SHL:16) ;- (CKGR) PLL B Multiplier |
||
312 | AT91C_CKGR_USB_96M EQU (0x1:SHL:28) ;- (CKGR) Divider for USB Ports |
||
313 | AT91C_CKGR_USB_PLL EQU (0x1:SHL:29) ;- (CKGR) PLL Use |
||
314 | |||
315 | ;- ***************************************************************************** |
||
316 | ;- SOFTWARE API DEFINITION FOR Parallel Input Output Controler |
||
317 | ;- ***************************************************************************** |
||
318 | ^ 0 ;- AT91S_PIO |
||
319 | PIO_PER # 4 ;- PIO Enable Register |
||
320 | PIO_PDR # 4 ;- PIO Disable Register |
||
321 | PIO_PSR # 4 ;- PIO Status Register |
||
322 | # 4 ;- Reserved |
||
323 | PIO_OER # 4 ;- Output Enable Register |
||
324 | PIO_ODR # 4 ;- Output Disable Registerr |
||
325 | PIO_OSR # 4 ;- Output Status Register |
||
326 | # 4 ;- Reserved |
||
327 | PIO_IFER # 4 ;- Input Filter Enable Register |
||
328 | PIO_IFDR # 4 ;- Input Filter Disable Register |
||
329 | PIO_IFSR # 4 ;- Input Filter Status Register |
||
330 | # 4 ;- Reserved |
||
331 | PIO_SODR # 4 ;- Set Output Data Register |
||
332 | PIO_CODR # 4 ;- Clear Output Data Register |
||
333 | PIO_ODSR # 4 ;- Output Data Status Register |
||
334 | PIO_PDSR # 4 ;- Pin Data Status Register |
||
335 | PIO_IER # 4 ;- Interrupt Enable Register |
||
336 | PIO_IDR # 4 ;- Interrupt Disable Register |
||
337 | PIO_IMR # 4 ;- Interrupt Mask Register |
||
338 | PIO_ISR # 4 ;- Interrupt Status Register |
||
339 | PIO_MDER # 4 ;- Multi-driver Enable Register |
||
340 | PIO_MDDR # 4 ;- Multi-driver Disable Register |
||
341 | PIO_MDSR # 4 ;- Multi-driver Status Register |
||
342 | # 4 ;- Reserved |
||
343 | PIO_PPUDR # 4 ;- Pull-up Disable Register |
||
344 | PIO_PPUER # 4 ;- Pull-up Enable Register |
||
345 | PIO_PPUSR # 4 ;- Pad Pull-up Status Register |
||
346 | # 4 ;- Reserved |
||
347 | PIO_ASR # 4 ;- Select A Register |
||
348 | PIO_BSR # 4 ;- Select B Register |
||
349 | PIO_ABSR # 4 ;- AB Select Status Register |
||
350 | # 36 ;- Reserved |
||
351 | PIO_OWER # 4 ;- Output Write Enable Register |
||
352 | PIO_OWDR # 4 ;- Output Write Disable Register |
||
353 | PIO_OWSR # 4 ;- Output Write Status Register |
||
354 | |||
355 | ;- ***************************************************************************** |
||
356 | ;- SOFTWARE API DEFINITION FOR Debug Unit |
||
357 | ;- ***************************************************************************** |
||
358 | ^ 0 ;- AT91S_DBGU |
||
359 | DBGU_CR # 4 ;- Control Register |
||
360 | DBGU_MR # 4 ;- Mode Register |
||
361 | DBGU_IER # 4 ;- Interrupt Enable Register |
||
362 | DBGU_IDR # 4 ;- Interrupt Disable Register |
||
363 | DBGU_IMR # 4 ;- Interrupt Mask Register |
||
364 | DBGU_CSR # 4 ;- Channel Status Register |
||
365 | DBGU_RHR # 4 ;- Receiver Holding Register |
||
366 | DBGU_THR # 4 ;- Transmitter Holding Register |
||
367 | DBGU_BRGR # 4 ;- Baud Rate Generator Register |
||
368 | # 28 ;- Reserved |
||
369 | DBGU_C1R # 4 ;- Chip ID1 Register |
||
370 | DBGU_C2R # 4 ;- Chip ID2 Register |
||
371 | DBGU_FNTR # 4 ;- Force NTRST Register |
||
372 | # 180 ;- Reserved |
||
373 | DBGU_RPR # 4 ;- Receive Pointer Register |
||
374 | DBGU_RCR # 4 ;- Receive Counter Register |
||
375 | DBGU_TPR # 4 ;- Transmit Pointer Register |
||
376 | DBGU_TCR # 4 ;- Transmit Counter Register |
||
377 | DBGU_RNPR # 4 ;- Receive Next Pointer Register |
||
378 | DBGU_RNCR # 4 ;- Receive Next Counter Register |
||
379 | DBGU_TNPR # 4 ;- Transmit Next Pointer Register |
||
380 | DBGU_TNCR # 4 ;- Transmit Next Counter Register |
||
381 | DBGU_PTCR # 4 ;- PDC Transfer Control Register |
||
382 | DBGU_PTSR # 4 ;- PDC Transfer Status Register |
||
383 | ;- -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- |
||
384 | AT91C_US_RSTRX EQU (0x1:SHL:2) ;- (DBGU) Reset Receiver |
||
385 | AT91C_US_RSTTX EQU (0x1:SHL:3) ;- (DBGU) Reset Transmitter |
||
386 | AT91C_US_RXEN EQU (0x1:SHL:4) ;- (DBGU) Receiver Enable |
||
387 | AT91C_US_RXDIS EQU (0x1:SHL:5) ;- (DBGU) Receiver Disable |
||
388 | AT91C_US_TXEN EQU (0x1:SHL:6) ;- (DBGU) Transmitter Enable |
||
389 | AT91C_US_TXDIS EQU (0x1:SHL:7) ;- (DBGU) Transmitter Disable |
||
390 | ;- -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- |
||
391 | AT91C_US_PAR EQU (0x7:SHL:9) ;- (DBGU) Parity type |
||
392 | AT91C_US_PAR_EVEN EQU (0x0:SHL:9) ;- (DBGU) Even Parity |
||
393 | AT91C_US_PAR_ODD EQU (0x1:SHL:9) ;- (DBGU) Odd Parity |
||
394 | AT91C_US_PAR_SPACE EQU (0x2:SHL:9) ;- (DBGU) Parity forced to 0 (Space) |
||
395 | AT91C_US_PAR_MARK EQU (0x3:SHL:9) ;- (DBGU) Parity forced to 1 (Mark) |
||
396 | AT91C_US_PAR_NONE EQU (0x4:SHL:9) ;- (DBGU) No Parity |
||
397 | AT91C_US_PAR_MULTI_DROP EQU (0x6:SHL:9) ;- (DBGU) Multi-drop mode |
||
398 | AT91C_US_CHMODE EQU (0x3:SHL:14) ;- (DBGU) Channel Mode |
||
399 | AT91C_US_CHMODE_NORMAL EQU (0x0:SHL:14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. |
||
400 | AT91C_US_CHMODE_AUTO EQU (0x1:SHL:14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. |
||
401 | AT91C_US_CHMODE_LOCAL EQU (0x2:SHL:14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. |
||
402 | AT91C_US_CHMODE_REMOTE EQU (0x3:SHL:14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. |
||
403 | ;- -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- |
||
404 | AT91C_US_RXRDY EQU (0x1:SHL:0) ;- (DBGU) RXRDY Interrupt |
||
405 | AT91C_US_TXRDY EQU (0x1:SHL:1) ;- (DBGU) TXRDY Interrupt |
||
406 | AT91C_US_ENDRX EQU (0x1:SHL:3) ;- (DBGU) End of Receive Transfer Interrupt |
||
407 | AT91C_US_ENDTX EQU (0x1:SHL:4) ;- (DBGU) End of Transmit Interrupt |
||
408 | AT91C_US_OVRE EQU (0x1:SHL:5) ;- (DBGU) Overrun Interrupt |
||
409 | AT91C_US_FRAME EQU (0x1:SHL:6) ;- (DBGU) Framing Error Interrupt |
||
410 | AT91C_US_PARE EQU (0x1:SHL:7) ;- (DBGU) Parity Error Interrupt |
||
411 | AT91C_US_TXEMPTY EQU (0x1:SHL:9) ;- (DBGU) TXEMPTY Interrupt |
||
412 | AT91C_US_TXBUFE EQU (0x1:SHL:11) ;- (DBGU) TXBUFE Interrupt |
||
413 | AT91C_US_RXBUFF EQU (0x1:SHL:12) ;- (DBGU) RXBUFF Interrupt |
||
414 | AT91C_US_COMM_TX EQU (0x1:SHL:30) ;- (DBGU) COMM_TX Interrupt |
||
415 | AT91C_US_COMM_RX EQU (0x1:SHL:31) ;- (DBGU) COMM_RX Interrupt |
||
416 | ;- -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- |
||
417 | ;- -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- |
||
418 | ;- -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- |
||
419 | ;- -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- |
||
420 | AT91C_US_FORCE_NTRST EQU (0x1:SHL:0) ;- (DBGU) Force NTRST in JTAG |
||
421 | |||
422 | ;- ***************************************************************************** |
||
423 | ;- SOFTWARE API DEFINITION FOR Peripheral Data Controller |
||
424 | ;- ***************************************************************************** |
||
425 | ^ 0 ;- AT91S_PDC |
||
426 | PDC_RPR # 4 ;- Receive Pointer Register |
||
427 | PDC_RCR # 4 ;- Receive Counter Register |
||
428 | PDC_TPR # 4 ;- Transmit Pointer Register |
||
429 | PDC_TCR # 4 ;- Transmit Counter Register |
||
430 | PDC_RNPR # 4 ;- Receive Next Pointer Register |
||
431 | PDC_RNCR # 4 ;- Receive Next Counter Register |
||
432 | PDC_TNPR # 4 ;- Transmit Next Pointer Register |
||
433 | PDC_TNCR # 4 ;- Transmit Next Counter Register |
||
434 | PDC_PTCR # 4 ;- PDC Transfer Control Register |
||
435 | PDC_PTSR # 4 ;- PDC Transfer Status Register |
||
436 | ;- -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- |
||
437 | AT91C_PDC_RXTEN EQU (0x1:SHL:0) ;- (PDC) Receiver Transfer Enable |
||
438 | AT91C_PDC_RXTDIS EQU (0x1:SHL:1) ;- (PDC) Receiver Transfer Disable |
||
439 | AT91C_PDC_TXTEN EQU (0x1:SHL:8) ;- (PDC) Transmitter Transfer Enable |
||
440 | AT91C_PDC_TXTDIS EQU (0x1:SHL:9) ;- (PDC) Transmitter Transfer Disable |
||
441 | ;- -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- |
||
442 | |||
443 | ;- ***************************************************************************** |
||
444 | ;- SOFTWARE API DEFINITION FOR Advanced Interrupt Controller |
||
445 | ;- ***************************************************************************** |
||
446 | ^ 0 ;- AT91S_AIC |
||
447 | AIC_SMR # 128 ;- Source Mode Register |
||
448 | AIC_SVR # 128 ;- Source Vector Register |
||
449 | AIC_IVR # 4 ;- IRQ Vector Register |
||
450 | AIC_FVR # 4 ;- FIQ Vector Register |
||
451 | AIC_ISR # 4 ;- Interrupt Status Register |
||
452 | AIC_IPR # 4 ;- Interrupt Pending Register |
||
453 | AIC_IMR # 4 ;- Interrupt Mask Register |
||
454 | AIC_CISR # 4 ;- Core Interrupt Status Register |
||
455 | # 8 ;- Reserved |
||
456 | AIC_IECR # 4 ;- Interrupt Enable Command Register |
||
457 | AIC_IDCR # 4 ;- Interrupt Disable Command Register |
||
458 | AIC_ICCR # 4 ;- Interrupt Clear Command Register |
||
459 | AIC_ISCR # 4 ;- Interrupt Set Command Register |
||
460 | AIC_EOICR # 4 ;- End of Interrupt Command Register |
||
461 | AIC_SPU # 4 ;- Spurious Vector Register |
||
462 | AIC_DCR # 4 ;- Debug Control Register (Protect) |
||
463 | # 4 ;- Reserved |
||
464 | AIC_FFER # 4 ;- Fast Forcing Enable Register |
||
465 | AIC_FFDR # 4 ;- Fast Forcing Disable Register |
||
466 | AIC_FFSR # 4 ;- Fast Forcing Status Register |
||
467 | ;- -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- |
||
468 | AT91C_AIC_PRIOR EQU (0x7:SHL:0) ;- (AIC) Priority Level |
||
469 | AT91C_AIC_PRIOR_LOWEST EQU (0x0) ;- (AIC) Lowest priority level |
||
470 | AT91C_AIC_PRIOR_HIGHEST EQU (0x7) ;- (AIC) Highest priority level |
||
471 | AT91C_AIC_SRCTYPE EQU (0x3:SHL:5) ;- (AIC) Interrupt Source Type |
||
472 | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE EQU (0x0:SHL:5) ;- (AIC) Internal Sources Code Label Level Sensitive |
||
473 | AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED EQU (0x1:SHL:5) ;- (AIC) Internal Sources Code Label Edge triggered |
||
474 | AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL EQU (0x2:SHL:5) ;- (AIC) External Sources Code Label High-level Sensitive |
||
475 | AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE EQU (0x3:SHL:5) ;- (AIC) External Sources Code Label Positive Edge triggered |
||
476 | ;- -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- |
||
477 | AT91C_AIC_NFIQ EQU (0x1:SHL:0) ;- (AIC) NFIQ Status |
||
478 | AT91C_AIC_NIRQ EQU (0x1:SHL:1) ;- (AIC) NIRQ Status |
||
479 | ;- -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- |
||
480 | AT91C_AIC_DCR_PROT EQU (0x1:SHL:0) ;- (AIC) Protection Mode |
||
481 | AT91C_AIC_DCR_GMSK EQU (0x1:SHL:1) ;- (AIC) General Mask |
||
482 | |||
483 | ;- ***************************************************************************** |
||
484 | ;- SOFTWARE API DEFINITION FOR Serial Parallel Interface |
||
485 | ;- ***************************************************************************** |
||
486 | ^ 0 ;- AT91S_SPI |
||
487 | SPI_CR # 4 ;- Control Register |
||
488 | SPI_MR # 4 ;- Mode Register |
||
489 | SPI_RDR # 4 ;- Receive Data Register |
||
490 | SPI_TDR # 4 ;- Transmit Data Register |
||
491 | SPI_SR # 4 ;- Status Register |
||
492 | SPI_IER # 4 ;- Interrupt Enable Register |
||
493 | SPI_IDR # 4 ;- Interrupt Disable Register |
||
494 | SPI_IMR # 4 ;- Interrupt Mask Register |
||
495 | # 16 ;- Reserved |
||
496 | SPI_CSR # 16 ;- Chip Select Register |
||
497 | # 192 ;- Reserved |
||
498 | SPI_RPR # 4 ;- Receive Pointer Register |
||
499 | SPI_RCR # 4 ;- Receive Counter Register |
||
500 | SPI_TPR # 4 ;- Transmit Pointer Register |
||
501 | SPI_TCR # 4 ;- Transmit Counter Register |
||
502 | SPI_RNPR # 4 ;- Receive Next Pointer Register |
||
503 | SPI_RNCR # 4 ;- Receive Next Counter Register |
||
504 | SPI_TNPR # 4 ;- Transmit Next Pointer Register |
||
505 | SPI_TNCR # 4 ;- Transmit Next Counter Register |
||
506 | SPI_PTCR # 4 ;- PDC Transfer Control Register |
||
507 | SPI_PTSR # 4 ;- PDC Transfer Status Register |
||
508 | ;- -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- |
||
509 | AT91C_SPI_SPIEN EQU (0x1:SHL:0) ;- (SPI) SPI Enable |
||
510 | AT91C_SPI_SPIDIS EQU (0x1:SHL:1) ;- (SPI) SPI Disable |
||
511 | AT91C_SPI_SWRST EQU (0x1:SHL:7) ;- (SPI) SPI Software reset |
||
512 | ;- -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- |
||
513 | AT91C_SPI_MSTR EQU (0x1:SHL:0) ;- (SPI) Master/Slave Mode |
||
514 | AT91C_SPI_PS EQU (0x1:SHL:1) ;- (SPI) Peripheral Select |
||
515 | AT91C_SPI_PS_FIXED EQU (0x0:SHL:1) ;- (SPI) Fixed Peripheral Select |
||
516 | AT91C_SPI_PS_VARIABLE EQU (0x1:SHL:1) ;- (SPI) Variable Peripheral Select |
||
517 | AT91C_SPI_PCSDEC EQU (0x1:SHL:2) ;- (SPI) Chip Select Decode |
||
518 | AT91C_SPI_DIV32 EQU (0x1:SHL:3) ;- (SPI) Clock Selection |
||
519 | AT91C_SPI_MODFDIS EQU (0x1:SHL:4) ;- (SPI) Mode Fault Detection |
||
520 | AT91C_SPI_LLB EQU (0x1:SHL:7) ;- (SPI) Clock Selection |
||
521 | AT91C_SPI_PCS EQU (0xF:SHL:16) ;- (SPI) Peripheral Chip Select |
||
522 | AT91C_SPI_DLYBCS EQU (0xFF:SHL:24) ;- (SPI) Delay Between Chip Selects |
||
523 | ;- -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- |
||
524 | AT91C_SPI_RD EQU (0xFFFF:SHL:0) ;- (SPI) Receive Data |
||
525 | AT91C_SPI_RPCS EQU (0xF:SHL:16) ;- (SPI) Peripheral Chip Select Status |
||
526 | ;- -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- |
||
527 | AT91C_SPI_TD EQU (0xFFFF:SHL:0) ;- (SPI) Transmit Data |
||
528 | AT91C_SPI_TPCS EQU (0xF:SHL:16) ;- (SPI) Peripheral Chip Select Status |
||
529 | ;- -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- |
||
530 | AT91C_SPI_RDRF EQU (0x1:SHL:0) ;- (SPI) Receive Data Register Full |
||
531 | AT91C_SPI_TDRE EQU (0x1:SHL:1) ;- (SPI) Transmit Data Register Empty |
||
532 | AT91C_SPI_MODF EQU (0x1:SHL:2) ;- (SPI) Mode Fault Error |
||
533 | AT91C_SPI_OVRES EQU (0x1:SHL:3) ;- (SPI) Overrun Error Status |
||
534 | AT91C_SPI_SPENDRX EQU (0x1:SHL:4) ;- (SPI) End of Receiver Transfer |
||
535 | AT91C_SPI_SPENDTX EQU (0x1:SHL:5) ;- (SPI) End of Receiver Transfer |
||
536 | AT91C_SPI_RXBUFF EQU (0x1:SHL:6) ;- (SPI) RXBUFF Interrupt |
||
537 | AT91C_SPI_TXBUFE EQU (0x1:SHL:7) ;- (SPI) TXBUFE Interrupt |
||
538 | AT91C_SPI_SPIENS EQU (0x1:SHL:16) ;- (SPI) Enable Status |
||
539 | ;- -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- |
||
540 | ;- -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- |
||
541 | ;- -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- |
||
542 | ;- -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- |
||
543 | AT91C_SPI_CPOL EQU (0x1:SHL:0) ;- (SPI) Clock Polarity |
||
544 | AT91C_SPI_NCPHA EQU (0x1:SHL:1) ;- (SPI) Clock Phase |
||
545 | AT91C_SPI_BITS EQU (0xF:SHL:4) ;- (SPI) Bits Per Transfer |
||
546 | AT91C_SPI_BITS_8 EQU (0x0:SHL:4) ;- (SPI) 8 Bits Per transfer |
||
547 | AT91C_SPI_BITS_9 EQU (0x1:SHL:4) ;- (SPI) 9 Bits Per transfer |
||
548 | AT91C_SPI_BITS_10 EQU (0x2:SHL:4) ;- (SPI) 10 Bits Per transfer |
||
549 | AT91C_SPI_BITS_11 EQU (0x3:SHL:4) ;- (SPI) 11 Bits Per transfer |
||
550 | AT91C_SPI_BITS_12 EQU (0x4:SHL:4) ;- (SPI) 12 Bits Per transfer |
||
551 | AT91C_SPI_BITS_13 EQU (0x5:SHL:4) ;- (SPI) 13 Bits Per transfer |
||
552 | AT91C_SPI_BITS_14 EQU (0x6:SHL:4) ;- (SPI) 14 Bits Per transfer |
||
553 | AT91C_SPI_BITS_15 EQU (0x7:SHL:4) ;- (SPI) 15 Bits Per transfer |
||
554 | AT91C_SPI_BITS_16 EQU (0x8:SHL:4) ;- (SPI) 16 Bits Per transfer |
||
555 | AT91C_SPI_SCBR EQU (0xFF:SHL:8) ;- (SPI) Serial Clock Baud Rate |
||
556 | AT91C_SPI_DLYBS EQU (0xFF:SHL:16) ;- (SPI) Serial Clock Baud Rate |
||
557 | AT91C_SPI_DLYBCT EQU (0xFF:SHL:24) ;- (SPI) Delay Between Consecutive Transfers |
||
558 | |||
559 | ;- ***************************************************************************** |
||
560 | ;- SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface |
||
561 | ;- ***************************************************************************** |
||
562 | ^ 0 ;- AT91S_SSC |
||
563 | SSC_CR # 4 ;- Control Register |
||
564 | SSC_CMR # 4 ;- Clock Mode Register |
||
565 | # 8 ;- Reserved |
||
566 | SSC_RCMR # 4 ;- Receive Clock ModeRegister |
||
567 | SSC_RFMR # 4 ;- Receive Frame Mode Register |
||
568 | SSC_TCMR # 4 ;- Transmit Clock Mode Register |
||
569 | SSC_TFMR # 4 ;- Transmit Frame Mode Register |
||
570 | SSC_RHR # 4 ;- Receive Holding Register |
||
571 | SSC_THR # 4 ;- Transmit Holding Register |
||
572 | # 8 ;- Reserved |
||
573 | SSC_RSHR # 4 ;- Receive Sync Holding Register |
||
574 | SSC_TSHR # 4 ;- Transmit Sync Holding Register |
||
575 | SSC_RC0R # 4 ;- Receive Compare 0 Register |
||
576 | SSC_RC1R # 4 ;- Receive Compare 1 Register |
||
577 | SSC_SR # 4 ;- Status Register |
||
578 | SSC_IER # 4 ;- Interrupt Enable Register |
||
579 | SSC_IDR # 4 ;- Interrupt Disable Register |
||
580 | SSC_IMR # 4 ;- Interrupt Mask Register |
||
581 | # 176 ;- Reserved |
||
582 | SSC_RPR # 4 ;- Receive Pointer Register |
||
583 | SSC_RCR # 4 ;- Receive Counter Register |
||
584 | SSC_TPR # 4 ;- Transmit Pointer Register |
||
585 | SSC_TCR # 4 ;- Transmit Counter Register |
||
586 | SSC_RNPR # 4 ;- Receive Next Pointer Register |
||
587 | SSC_RNCR # 4 ;- Receive Next Counter Register |
||
588 | SSC_TNPR # 4 ;- Transmit Next Pointer Register |
||
589 | SSC_TNCR # 4 ;- Transmit Next Counter Register |
||
590 | SSC_PTCR # 4 ;- PDC Transfer Control Register |
||
591 | SSC_PTSR # 4 ;- PDC Transfer Status Register |
||
592 | ;- -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- |
||
593 | AT91C_SSC_RXEN EQU (0x1:SHL:0) ;- (SSC) Receive Enable |
||
594 | AT91C_SSC_RXDIS EQU (0x1:SHL:1) ;- (SSC) Receive Disable |
||
595 | AT91C_SSC_TXEN EQU (0x1:SHL:8) ;- (SSC) Transmit Enable |
||
596 | AT91C_SSC_TXDIS EQU (0x1:SHL:9) ;- (SSC) Transmit Disable |
||
597 | AT91C_SSC_SWRST EQU (0x1:SHL:15) ;- (SSC) Software Reset |
||
598 | ;- -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- |
||
599 | AT91C_SSC_CKS EQU (0x3:SHL:0) ;- (SSC) Receive/Transmit Clock Selection |
||
600 | AT91C_SSC_CKS_DIV EQU (0x0) ;- (SSC) Divided Clock |
||
601 | AT91C_SSC_CKS_TK EQU (0x1) ;- (SSC) TK Clock signal |
||
602 | AT91C_SSC_CKS_RK EQU (0x2) ;- (SSC) RK pin |
||
603 | AT91C_SSC_CKO EQU (0x7:SHL:2) ;- (SSC) Receive/Transmit Clock Output Mode Selection |
||
604 | AT91C_SSC_CKO_NONE EQU (0x0:SHL:2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only |
||
605 | AT91C_SSC_CKO_CONTINOUS EQU (0x1:SHL:2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output |
||
606 | AT91C_SSC_CKO_DATA_TX EQU (0x2:SHL:2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output |
||
607 | AT91C_SSC_CKI EQU (0x1:SHL:5) ;- (SSC) Receive/Transmit Clock Inversion |
||
608 | AT91C_SSC_CKG EQU (0x3:SHL:6) ;- (SSC) Receive/Transmit Clock Gating Selection |
||
609 | AT91C_SSC_CKG_NONE EQU (0x0:SHL:6) ;- (SSC) Receive/Transmit Clock Gating: None, continuous clock |
||
610 | AT91C_SSC_CKG_LOW EQU (0x1:SHL:6) ;- (SSC) Receive/Transmit Clock enabled only if RF Low |
||
611 | AT91C_SSC_CKG_HIGH EQU (0x2:SHL:6) ;- (SSC) Receive/Transmit Clock enabled only if RF High |
||
612 | AT91C_SSC_START EQU (0xF:SHL:8) ;- (SSC) Receive/Transmit Start Selection |
||
613 | AT91C_SSC_START_CONTINOUS EQU (0x0:SHL:8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. |
||
614 | AT91C_SSC_START_TX EQU (0x1:SHL:8) ;- (SSC) Transmit/Receive start |
||
615 | AT91C_SSC_START_LOW_RF EQU (0x2:SHL:8) ;- (SSC) Detection of a low level on RF input |
||
616 | AT91C_SSC_START_HIGH_RF EQU (0x3:SHL:8) ;- (SSC) Detection of a high level on RF input |
||
617 | AT91C_SSC_START_FALL_RF EQU (0x4:SHL:8) ;- (SSC) Detection of a falling edge on RF input |
||
618 | AT91C_SSC_START_RISE_RF EQU (0x5:SHL:8) ;- (SSC) Detection of a rising edge on RF input |
||
619 | AT91C_SSC_START_LEVEL_RF EQU (0x6:SHL:8) ;- (SSC) Detection of any level change on RF input |
||
620 | AT91C_SSC_START_EDGE_RF EQU (0x7:SHL:8) ;- (SSC) Detection of any edge on RF input |
||
621 | AT91C_SSC_START_0 EQU (0x8:SHL:8) ;- (SSC) Compare 0 |
||
622 | AT91C_SSC_STOP EQU (0x1:SHL:12) ;- (SSC) Receive Stop Selection |
||
623 | AT91C_SSC_STTOUT EQU (0x1:SHL:15) ;- (SSC) Receive/Transmit Start Output Selection |
||
624 | AT91C_SSC_STTDLY EQU (0xFF:SHL:16) ;- (SSC) Receive/Transmit Start Delay |
||
625 | AT91C_SSC_PERIOD EQU (0xFF:SHL:24) ;- (SSC) Receive/Transmit Period Divider Selection |
||
626 | ;- -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- |
||
627 | AT91C_SSC_DATLEN EQU (0x1F:SHL:0) ;- (SSC) Data Length |
||
628 | AT91C_SSC_LOOP EQU (0x1:SHL:5) ;- (SSC) Loop Mode |
||
629 | AT91C_SSC_MSBF EQU (0x1:SHL:7) ;- (SSC) Most Significant Bit First |
||
630 | AT91C_SSC_DATNB EQU (0xF:SHL:8) ;- (SSC) Data Number per Frame |
||
631 | AT91C_SSC_FSLEN EQU (0xF:SHL:16) ;- (SSC) Receive/Transmit Frame Sync length |
||
632 | AT91C_SSC_FSOS EQU (0x7:SHL:20) ;- (SSC) Receive/Transmit Frame Sync Output Selection |
||
633 | AT91C_SSC_FSOS_NONE EQU (0x0:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only |
||
634 | AT91C_SSC_FSOS_NEGATIVE EQU (0x1:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse |
||
635 | AT91C_SSC_FSOS_POSITIVE EQU (0x2:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse |
||
636 | AT91C_SSC_FSOS_LOW EQU (0x3:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer |
||
637 | AT91C_SSC_FSOS_HIGH EQU (0x4:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer |
||
638 | AT91C_SSC_FSOS_TOGGLE EQU (0x5:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer |
||
639 | AT91C_SSC_FSEDGE EQU (0x1:SHL:24) ;- (SSC) Frame Sync Edge Detection |
||
640 | ;- -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- |
||
641 | ;- -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- |
||
642 | AT91C_SSC_DATDEF EQU (0x1:SHL:5) ;- (SSC) Data Default Value |
||
643 | AT91C_SSC_FSDEN EQU (0x1:SHL:23) ;- (SSC) Frame Sync Data Enable |
||
644 | ;- -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- |
||
645 | AT91C_SSC_TXRDY EQU (0x1:SHL:0) ;- (SSC) Transmit Ready |
||
646 | AT91C_SSC_TXEMPTY EQU (0x1:SHL:1) ;- (SSC) Transmit Empty |
||
647 | AT91C_SSC_ENDTX EQU (0x1:SHL:2) ;- (SSC) End Of Transmission |
||
648 | AT91C_SSC_TXBUFE EQU (0x1:SHL:3) ;- (SSC) Transmit Buffer Empty |
||
649 | AT91C_SSC_RXRDY EQU (0x1:SHL:4) ;- (SSC) Receive Ready |
||
650 | AT91C_SSC_OVRUN EQU (0x1:SHL:5) ;- (SSC) Receive Overrun |
||
651 | AT91C_SSC_ENDRX EQU (0x1:SHL:6) ;- (SSC) End of Reception |
||
652 | AT91C_SSC_RXBUFF EQU (0x1:SHL:7) ;- (SSC) Receive Buffer Full |
||
653 | AT91C_SSC_CP0 EQU (0x1:SHL:8) ;- (SSC) Compare 0 |
||
654 | AT91C_SSC_CP1 EQU (0x1:SHL:9) ;- (SSC) Compare 1 |
||
655 | AT91C_SSC_TXSYN EQU (0x1:SHL:10) ;- (SSC) Transmit Sync |
||
656 | AT91C_SSC_RXSYN EQU (0x1:SHL:11) ;- (SSC) Receive Sync |
||
657 | AT91C_SSC_TXENA EQU (0x1:SHL:16) ;- (SSC) Transmit Enable |
||
658 | AT91C_SSC_RXENA EQU (0x1:SHL:17) ;- (SSC) Receive Enable |
||
659 | ;- -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- |
||
660 | ;- -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- |
||
661 | ;- -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- |
||
662 | |||
663 | ;- ***************************************************************************** |
||
664 | ;- SOFTWARE API DEFINITION FOR Usart |
||
665 | ;- ***************************************************************************** |
||
666 | ^ 0 ;- AT91S_USART |
||
667 | US_CR # 4 ;- Control Register |
||
668 | US_MR # 4 ;- Mode Register |
||
669 | US_IER # 4 ;- Interrupt Enable Register |
||
670 | US_IDR # 4 ;- Interrupt Disable Register |
||
671 | US_IMR # 4 ;- Interrupt Mask Register |
||
672 | US_CSR # 4 ;- Channel Status Register |
||
673 | US_RHR # 4 ;- Receiver Holding Register |
||
674 | US_THR # 4 ;- Transmitter Holding Register |
||
675 | US_BRGR # 4 ;- Baud Rate Generator Register |
||
676 | US_RTOR # 4 ;- Receiver Time-out Register |
||
677 | US_TTGR # 4 ;- Transmitter Time-guard Register |
||
678 | # 20 ;- Reserved |
||
679 | US_FIDI # 4 ;- FI_DI_Ratio Register |
||
680 | US_NER # 4 ;- Nb Errors Register |
||
681 | US_XXR # 4 ;- XON_XOFF Register |
||
682 | US_IF # 4 ;- IRDA_FILTER Register |
||
683 | # 176 ;- Reserved |
||
684 | US_RPR # 4 ;- Receive Pointer Register |
||
685 | US_RCR # 4 ;- Receive Counter Register |
||
686 | US_TPR # 4 ;- Transmit Pointer Register |
||
687 | US_TCR # 4 ;- Transmit Counter Register |
||
688 | US_RNPR # 4 ;- Receive Next Pointer Register |
||
689 | US_RNCR # 4 ;- Receive Next Counter Register |
||
690 | US_TNPR # 4 ;- Transmit Next Pointer Register |
||
691 | US_TNCR # 4 ;- Transmit Next Counter Register |
||
692 | US_PTCR # 4 ;- PDC Transfer Control Register |
||
693 | US_PTSR # 4 ;- PDC Transfer Status Register |
||
694 | ;- -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- |
||
695 | AT91C_US_RSTSTA EQU (0x1:SHL:8) ;- (USART) Reset Status Bits |
||
696 | AT91C_US_STTBRK EQU (0x1:SHL:9) ;- (USART) Start Break |
||
697 | AT91C_US_STPBRK EQU (0x1:SHL:10) ;- (USART) Stop Break |
||
698 | AT91C_US_STTTO EQU (0x1:SHL:11) ;- (USART) Start Time-out |
||
699 | AT91C_US_SENDA EQU (0x1:SHL:12) ;- (USART) Send Address |
||
700 | AT91C_US_RSTIT EQU (0x1:SHL:13) ;- (USART) Reset Iterations |
||
701 | AT91C_US_RSTNACK EQU (0x1:SHL:14) ;- (USART) Reset Non Acknowledge |
||
702 | AT91C_US_RETTO EQU (0x1:SHL:15) ;- (USART) Rearm Time-out |
||
703 | AT91C_US_DTREN EQU (0x1:SHL:16) ;- (USART) Data Terminal ready Enable |
||
704 | AT91C_US_DTRDIS EQU (0x1:SHL:17) ;- (USART) Data Terminal ready Disable |
||
705 | AT91C_US_RTSEN EQU (0x1:SHL:18) ;- (USART) Request to Send enable |
||
706 | AT91C_US_RTSDIS EQU (0x1:SHL:19) ;- (USART) Request to Send Disable |
||
707 | ;- -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- |
||
708 | AT91C_US_USMODE EQU (0xF:SHL:0) ;- (USART) Usart mode |
||
709 | AT91C_US_USMODE_NORMAL EQU (0x0) ;- (USART) Normal |
||
710 | AT91C_US_USMODE_RS485 EQU (0x1) ;- (USART) RS485 |
||
711 | AT91C_US_USMODE_HWHSH EQU (0x2) ;- (USART) Hardware Handshaking |
||
712 | AT91C_US_USMODE_MODEM EQU (0x3) ;- (USART) Modem |
||
713 | AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0 |
||
714 | AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1 |
||
715 | AT91C_US_USMODE_IRDA EQU (0x8) ;- (USART) IrDA |
||
716 | AT91C_US_USMODE_SWHSH EQU (0xC) ;- (USART) Software Handshaking |
||
717 | AT91C_US_CLKS EQU (0x3:SHL:4) ;- (USART) Clock Selection (Baud Rate generator Input Clock |
||
718 | AT91C_US_CLKS_CLOCK EQU (0x0:SHL:4) ;- (USART) Clock |
||
719 | AT91C_US_CLKS_FDIV1 EQU (0x1:SHL:4) ;- (USART) fdiv1 |
||
720 | AT91C_US_CLKS_SLOW EQU (0x2:SHL:4) ;- (USART) slow_clock (ARM) |
||
721 | AT91C_US_CLKS_EXT EQU (0x3:SHL:4) ;- (USART) External (SCK) |
||
722 | AT91C_US_CHRL EQU (0x3:SHL:6) ;- (USART) Clock Selection (Baud Rate generator Input Clock |
||
723 | AT91C_US_CHRL_5_BITS EQU (0x0:SHL:6) ;- (USART) Character Length: 5 bits |
||
724 | AT91C_US_CHRL_6_BITS EQU (0x1:SHL:6) ;- (USART) Character Length: 6 bits |
||
725 | AT91C_US_CHRL_7_BITS EQU (0x2:SHL:6) ;- (USART) Character Length: 7 bits |
||
726 | AT91C_US_CHRL_8_BITS EQU (0x3:SHL:6) ;- (USART) Character Length: 8 bits |
||
727 | AT91C_US_SYNC EQU (0x1:SHL:8) ;- (USART) Synchronous Mode Select |
||
728 | AT91C_US_NBSTOP EQU (0x3:SHL:12) ;- (USART) Number of Stop bits |
||
729 | AT91C_US_NBSTOP_1_BIT EQU (0x0:SHL:12) ;- (USART) 1 stop bit |
||
730 | AT91C_US_NBSTOP_15_BIT EQU (0x1:SHL:12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits |
||
731 | AT91C_US_NBSTOP_2_BIT EQU (0x2:SHL:12) ;- (USART) 2 stop bits |
||
732 | AT91C_US_MSBF EQU (0x1:SHL:16) ;- (USART) Bit Order |
||
733 | AT91C_US_MODE9 EQU (0x1:SHL:17) ;- (USART) 9-bit Character length |
||
734 | AT91C_US_CKLO EQU (0x1:SHL:18) ;- (USART) Clock Output Select |
||
735 | AT91C_US_OVER EQU (0x1:SHL:19) ;- (USART) Over Sampling Mode |
||
736 | AT91C_US_INACK EQU (0x1:SHL:20) ;- (USART) Inhibit Non Acknowledge |
||
737 | AT91C_US_DSNACK EQU (0x1:SHL:21) ;- (USART) Disable Successive NACK |
||
738 | AT91C_US_MAX_ITER EQU (0x1:SHL:24) ;- (USART) Number of Repetitions |
||
739 | AT91C_US_FILTER EQU (0x1:SHL:28) ;- (USART) Receive Line Filter |
||
740 | ;- -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- |
||
741 | AT91C_US_RXBRK EQU (0x1:SHL:2) ;- (USART) Break Received/End of Break |
||
742 | AT91C_US_TIMEOUT EQU (0x1:SHL:8) ;- (USART) Receiver Time-out |
||
743 | AT91C_US_ITERATION EQU (0x1:SHL:10) ;- (USART) Max number of Repetitions Reached |
||
744 | AT91C_US_NACK EQU (0x1:SHL:13) ;- (USART) Non Acknowledge |
||
745 | AT91C_US_RIIC EQU (0x1:SHL:16) ;- (USART) Ring INdicator Input Change Flag |
||
746 | AT91C_US_DSRIC EQU (0x1:SHL:17) ;- (USART) Data Set Ready Input Change Flag |
||
747 | AT91C_US_DCDIC EQU (0x1:SHL:18) ;- (USART) Data Carrier Flag |
||
748 | AT91C_US_CTSIC EQU (0x1:SHL:19) ;- (USART) Clear To Send Input Change Flag |
||
749 | ;- -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- |
||
750 | ;- -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- |
||
751 | ;- -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- |
||
752 | AT91C_US_RI EQU (0x1:SHL:20) ;- (USART) Image of RI Input |
||
753 | AT91C_US_DSR EQU (0x1:SHL:21) ;- (USART) Image of DSR Input |
||
754 | AT91C_US_DCD EQU (0x1:SHL:22) ;- (USART) Image of DCD Input |
||
755 | AT91C_US_CTS EQU (0x1:SHL:23) ;- (USART) Image of CTS Input |
||
756 | |||
757 | ;- ***************************************************************************** |
||
758 | ;- SOFTWARE API DEFINITION FOR Two-wire Interface |
||
759 | ;- ***************************************************************************** |
||
760 | ^ 0 ;- AT91S_TWI |
||
761 | TWI_CR # 4 ;- Control Register |
||
762 | TWI_MMR # 4 ;- Master Mode Register |
||
763 | TWI_SMR # 4 ;- Slave Mode Register |
||
764 | TWI_IADR # 4 ;- Internal Address Register |
||
765 | TWI_CWGR # 4 ;- Clock Waveform Generator Register |
||
766 | # 12 ;- Reserved |
||
767 | TWI_SR # 4 ;- Status Register |
||
768 | TWI_IER # 4 ;- Interrupt Enable Register |
||
769 | TWI_IDR # 4 ;- Interrupt Disable Register |
||
770 | TWI_IMR # 4 ;- Interrupt Mask Register |
||
771 | TWI_RHR # 4 ;- Receive Holding Register |
||
772 | TWI_THR # 4 ;- Transmit Holding Register |
||
773 | ;- -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- |
||
774 | AT91C_TWI_START EQU (0x1:SHL:0) ;- (TWI) Send a START Condition |
||
775 | AT91C_TWI_STOP EQU (0x1:SHL:1) ;- (TWI) Send a STOP Condition |
||
776 | AT91C_TWI_MSEN EQU (0x1:SHL:2) ;- (TWI) TWI Master Transfer Enabled |
||
777 | AT91C_TWI_MSDIS EQU (0x1:SHL:3) ;- (TWI) TWI Master Transfer Disabled |
||
778 | AT91C_TWI_SVEN EQU (0x1:SHL:4) ;- (TWI) TWI Slave Transfer Enabled |
||
779 | AT91C_TWI_SVDIS EQU (0x1:SHL:5) ;- (TWI) TWI Slave Transfer Disabled |
||
780 | AT91C_TWI_SWRST EQU (0x1:SHL:7) ;- (TWI) Software Reset |
||
781 | ;- -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- |
||
782 | AT91C_TWI_IADRSZ EQU (0x3:SHL:8) ;- (TWI) Internal Device Address Size |
||
783 | AT91C_TWI_IADRSZ_NO EQU (0x0:SHL:8) ;- (TWI) No internal device address |
||
784 | AT91C_TWI_IADRSZ_1_BYTE EQU (0x1:SHL:8) ;- (TWI) One-byte internal device address |
||
785 | AT91C_TWI_IADRSZ_2_BYTE EQU (0x2:SHL:8) ;- (TWI) Two-byte internal device address |
||
786 | AT91C_TWI_IADRSZ_3_BYTE EQU (0x3:SHL:8) ;- (TWI) Three-byte internal device address |
||
787 | AT91C_TWI_MREAD EQU (0x1:SHL:12) ;- (TWI) Master Read Direction |
||
788 | AT91C_TWI_DADR EQU (0x7F:SHL:16) ;- (TWI) Device Address |
||
789 | ;- -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- |
||
790 | AT91C_TWI_SADR EQU (0x7F:SHL:16) ;- (TWI) Slave Device Address |
||
791 | ;- -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- |
||
792 | AT91C_TWI_CLDIV EQU (0xFF:SHL:0) ;- (TWI) Clock Low Divider |
||
793 | AT91C_TWI_CHDIV EQU (0xFF:SHL:8) ;- (TWI) Clock High Divider |
||
794 | AT91C_TWI_CKDIV EQU (0x7:SHL:16) ;- (TWI) Clock Divider |
||
795 | ;- -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- |
||
796 | AT91C_TWI_TXCOMP EQU (0x1:SHL:0) ;- (TWI) Transmission Completed |
||
797 | AT91C_TWI_RXRDY EQU (0x1:SHL:1) ;- (TWI) Receive holding register ReaDY |
||
798 | AT91C_TWI_TXRDY EQU (0x1:SHL:2) ;- (TWI) Transmit holding register ReaDY |
||
799 | AT91C_TWI_SVREAD EQU (0x1:SHL:3) ;- (TWI) Slave Read |
||
800 | AT91C_TWI_SVACC EQU (0x1:SHL:4) ;- (TWI) Slave Access |
||
801 | AT91C_TWI_GCACC EQU (0x1:SHL:5) ;- (TWI) General Call Access |
||
802 | AT91C_TWI_OVRE EQU (0x1:SHL:6) ;- (TWI) Overrun Error |
||
803 | AT91C_TWI_UNRE EQU (0x1:SHL:7) ;- (TWI) Underrun Error |
||
804 | AT91C_TWI_NACK EQU (0x1:SHL:8) ;- (TWI) Not Acknowledged |
||
805 | AT91C_TWI_ARBLST EQU (0x1:SHL:9) ;- (TWI) Arbitration Lost |
||
806 | ;- -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- |
||
807 | ;- -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- |
||
808 | ;- -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- |
||
809 | |||
810 | ;- ***************************************************************************** |
||
811 | ;- SOFTWARE API DEFINITION FOR Multimedia Card Interface |
||
812 | ;- ***************************************************************************** |
||
813 | ^ 0 ;- AT91S_MCI |
||
814 | MCI_CR # 4 ;- MCI Control Register |
||
815 | MCI_MR # 4 ;- MCI Mode Register |
||
816 | MCI_DTOR # 4 ;- MCI Data Timeout Register |
||
817 | MCI_SDCR # 4 ;- MCI SD Card Register |
||
818 | MCI_ARGR # 4 ;- MCI Argument Register |
||
819 | MCI_CMDR # 4 ;- MCI Command Register |
||
820 | # 8 ;- Reserved |
||
821 | MCI_RSPR # 16 ;- MCI Response Register |
||
822 | MCI_RDR # 4 ;- MCI Receive Data Register |
||
823 | MCI_TDR # 4 ;- MCI Transmit Data Register |
||
824 | # 8 ;- Reserved |
||
825 | MCI_SR # 4 ;- MCI Status Register |
||
826 | MCI_IER # 4 ;- MCI Interrupt Enable Register |
||
827 | MCI_IDR # 4 ;- MCI Interrupt Disable Register |
||
828 | MCI_IMR # 4 ;- MCI Interrupt Mask Register |
||
829 | # 176 ;- Reserved |
||
830 | MCI_RPR # 4 ;- Receive Pointer Register |
||
831 | MCI_RCR # 4 ;- Receive Counter Register |
||
832 | MCI_TPR # 4 ;- Transmit Pointer Register |
||
833 | MCI_TCR # 4 ;- Transmit Counter Register |
||
834 | MCI_RNPR # 4 ;- Receive Next Pointer Register |
||
835 | MCI_RNCR # 4 ;- Receive Next Counter Register |
||
836 | MCI_TNPR # 4 ;- Transmit Next Pointer Register |
||
837 | MCI_TNCR # 4 ;- Transmit Next Counter Register |
||
838 | MCI_PTCR # 4 ;- PDC Transfer Control Register |
||
839 | MCI_PTSR # 4 ;- PDC Transfer Status Register |
||
840 | ;- -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- |
||
841 | AT91C_MCI_MCIEN EQU (0x1:SHL:0) ;- (MCI) Multimedia Interface Enable |
||
842 | AT91C_MCI_MCIDIS EQU (0x1:SHL:1) ;- (MCI) Multimedia Interface Disable |
||
843 | AT91C_MCI_PWSEN EQU (0x1:SHL:2) ;- (MCI) Power Save Mode Enable |
||
844 | AT91C_MCI_PWSDIS EQU (0x1:SHL:3) ;- (MCI) Power Save Mode Disable |
||
845 | ;- -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- |
||
846 | AT91C_MCI_CLKDIV EQU (0x1:SHL:0) ;- (MCI) Clock Divider |
||
847 | AT91C_MCI_PWSDIV EQU (0x1:SHL:8) ;- (MCI) Power Saving Divider |
||
848 | AT91C_MCI_PDCPADV EQU (0x1:SHL:14) ;- (MCI) PDC Padding Value |
||
849 | AT91C_MCI_PDCMODE EQU (0x1:SHL:15) ;- (MCI) PDC Oriented Mode |
||
850 | AT91C_MCI_BLKLEN EQU (0x1:SHL:18) ;- (MCI) Data Block Length |
||
851 | ;- -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- |
||
852 | AT91C_MCI_DTOCYC EQU (0x1:SHL:0) ;- (MCI) Data Timeout Cycle Number |
||
853 | AT91C_MCI_DTOMUL EQU (0x7:SHL:4) ;- (MCI) Data Timeout Multiplier |
||
854 | AT91C_MCI_DTOMUL_1 EQU (0x0:SHL:4) ;- (MCI) DTOCYC x 1 |
||
855 | AT91C_MCI_DTOMUL_16 EQU (0x1:SHL:4) ;- (MCI) DTOCYC x 16 |
||
856 | AT91C_MCI_DTOMUL_128 EQU (0x2:SHL:4) ;- (MCI) DTOCYC x 128 |
||
857 | AT91C_MCI_DTOMUL_256 EQU (0x3:SHL:4) ;- (MCI) DTOCYC x 256 |
||
858 | AT91C_MCI_DTOMUL_1024 EQU (0x4:SHL:4) ;- (MCI) DTOCYC x 1024 |
||
859 | AT91C_MCI_DTOMUL_4096 EQU (0x5:SHL:4) ;- (MCI) DTOCYC x 4096 |
||
860 | AT91C_MCI_DTOMUL_65536 EQU (0x6:SHL:4) ;- (MCI) DTOCYC x 65536 |
||
861 | AT91C_MCI_DTOMUL_1048576 EQU (0x7:SHL:4) ;- (MCI) DTOCYC x 1048576 |
||
862 | ;- -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- |
||
863 | AT91C_MCI_SCDSEL EQU (0x1:SHL:0) ;- (MCI) SD Card Selector |
||
864 | AT91C_MCI_SCDBUS EQU (0x1:SHL:7) ;- (MCI) SD Card Bus Width |
||
865 | ;- -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- |
||
866 | AT91C_MCI_CMDNB EQU (0x1F:SHL:0) ;- (MCI) Command Number |
||
867 | AT91C_MCI_RSPTYP EQU (0x3:SHL:6) ;- (MCI) Response Type |
||
868 | AT91C_MCI_RSPTYP_NO EQU (0x0:SHL:6) ;- (MCI) No response |
||
869 | AT91C_MCI_RSPTYP_48 EQU (0x1:SHL:6) ;- (MCI) 48-bit response |
||
870 | AT91C_MCI_RSPTYP_136 EQU (0x2:SHL:6) ;- (MCI) 136-bit response |
||
871 | AT91C_MCI_SPCMD EQU (0x7:SHL:8) ;- (MCI) Special CMD |
||
872 | AT91C_MCI_SPCMD_NONE EQU (0x0:SHL:8) ;- (MCI) Not a special CMD |
||
873 | AT91C_MCI_SPCMD_INIT EQU (0x1:SHL:8) ;- (MCI) Initialization CMD |
||
874 | AT91C_MCI_SPCMD_SYNC EQU (0x2:SHL:8) ;- (MCI) Synchronized CMD |
||
875 | AT91C_MCI_SPCMD_IT_CMD EQU (0x4:SHL:8) ;- (MCI) Interrupt command |
||
876 | AT91C_MCI_SPCMD_IT_REP EQU (0x5:SHL:8) ;- (MCI) Interrupt response |
||
877 | AT91C_MCI_OPDCMD EQU (0x1:SHL:11) ;- (MCI) Open Drain Command |
||
878 | AT91C_MCI_MAXLAT EQU (0x1:SHL:12) ;- (MCI) Maximum Latency for Command to respond |
||
879 | AT91C_MCI_TRCMD EQU (0x3:SHL:16) ;- (MCI) Transfer CMD |
||
880 | AT91C_MCI_TRCMD_NO EQU (0x0:SHL:16) ;- (MCI) No transfer |
||
881 | AT91C_MCI_TRCMD_START EQU (0x1:SHL:16) ;- (MCI) Start transfer |
||
882 | AT91C_MCI_TRCMD_STOP EQU (0x2:SHL:16) ;- (MCI) Stop transfer |
||
883 | AT91C_MCI_TRDIR EQU (0x1:SHL:18) ;- (MCI) Transfer Direction |
||
884 | AT91C_MCI_TRTYP EQU (0x3:SHL:19) ;- (MCI) Transfer Type |
||
885 | AT91C_MCI_TRTYP_BLOCK EQU (0x0:SHL:19) ;- (MCI) Block Transfer type |
||
886 | AT91C_MCI_TRTYP_MULTIPLE EQU (0x1:SHL:19) ;- (MCI) Multiple Block transfer type |
||
887 | AT91C_MCI_TRTYP_STREAM EQU (0x2:SHL:19) ;- (MCI) Stream transfer type |
||
888 | ;- -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- |
||
889 | AT91C_MCI_CMDRDY EQU (0x1:SHL:0) ;- (MCI) Command Ready flag |
||
890 | AT91C_MCI_RXRDY EQU (0x1:SHL:1) ;- (MCI) RX Ready flag |
||
891 | AT91C_MCI_TXRDY EQU (0x1:SHL:2) ;- (MCI) TX Ready flag |
||
892 | AT91C_MCI_BLKE EQU (0x1:SHL:3) ;- (MCI) Data Block Transfer Ended flag |
||
893 | AT91C_MCI_DTIP EQU (0x1:SHL:4) ;- (MCI) Data Transfer in Progress flag |
||
894 | AT91C_MCI_NOTBUSY EQU (0x1:SHL:5) ;- (MCI) Data Line Not Busy flag |
||
895 | AT91C_MCI_ENDRX EQU (0x1:SHL:6) ;- (MCI) End of RX Buffer flag |
||
896 | AT91C_MCI_ENDTX EQU (0x1:SHL:7) ;- (MCI) End of TX Buffer flag |
||
897 | AT91C_MCI_RXBUFF EQU (0x1:SHL:14) ;- (MCI) RX Buffer Full flag |
||
898 | AT91C_MCI_TXBUFE EQU (0x1:SHL:15) ;- (MCI) TX Buffer Empty flag |
||
899 | AT91C_MCI_RINDE EQU (0x1:SHL:16) ;- (MCI) Response Index Error flag |
||
900 | AT91C_MCI_RDIRE EQU (0x1:SHL:17) ;- (MCI) Response Direction Error flag |
||
901 | AT91C_MCI_RCRCE EQU (0x1:SHL:18) ;- (MCI) Response CRC Error flag |
||
902 | AT91C_MCI_RENDE EQU (0x1:SHL:19) ;- (MCI) Response End Bit Error flag |
||
903 | AT91C_MCI_RTOE EQU (0x1:SHL:20) ;- (MCI) Response Time-out Error flag |
||
904 | AT91C_MCI_DCRCE EQU (0x1:SHL:21) ;- (MCI) data CRC Error flag |
||
905 | AT91C_MCI_DTOE EQU (0x1:SHL:22) ;- (MCI) Data timeout Error flag |
||
906 | AT91C_MCI_OVRE EQU (0x1:SHL:30) ;- (MCI) Overrun flag |
||
907 | AT91C_MCI_UNRE EQU (0x1:SHL:31) ;- (MCI) Underrun flag |
||
908 | ;- -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- |
||
909 | ;- -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- |
||
910 | ;- -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- |
||
911 | |||
912 | ;- ***************************************************************************** |
||
913 | ;- SOFTWARE API DEFINITION FOR USB Device Interface |
||
914 | ;- ***************************************************************************** |
||
915 | ^ 0 ;- AT91S_UDP |
||
916 | UDP_NUM # 4 ;- Frame Number Register |
||
917 | UDP_GLBSTATE # 4 ;- Global State Register |
||
918 | UDP_FADDR # 4 ;- Function Address Register |
||
919 | # 4 ;- Reserved |
||
920 | UDP_IER # 4 ;- Interrupt Enable Register |
||
921 | UDP_IDR # 4 ;- Interrupt Disable Register |
||
922 | UDP_IMR # 4 ;- Interrupt Mask Register |
||
923 | UDP_ISR # 4 ;- Interrupt Status Register |
||
924 | UDP_ICR # 4 ;- Interrupt Clear Register |
||
925 | # 4 ;- Reserved |
||
926 | UDP_RSTEP # 4 ;- Reset Endpoint Register |
||
927 | # 4 ;- Reserved |
||
928 | UDP_CSR # 32 ;- Endpoint Control and Status Register |
||
929 | UDP_FDR # 32 ;- Endpoint FIFO Data Register |
||
930 | ;- -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- |
||
931 | AT91C_UDP_FRM_NUM EQU (0x7FF:SHL:0) ;- (UDP) Frame Number as Defined in the Packet Field Formats |
||
932 | AT91C_UDP_FRM_ERR EQU (0x1:SHL:16) ;- (UDP) Frame Error |
||
933 | AT91C_UDP_FRM_OK EQU (0x1:SHL:17) ;- (UDP) Frame OK |
||
934 | ;- -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- |
||
935 | AT91C_UDP_FADDEN EQU (0x1:SHL:0) ;- (UDP) Function Address Enable |
||
936 | AT91C_UDP_CONFG EQU (0x1:SHL:1) ;- (UDP) Configured |
||
937 | AT91C_UDP_RMWUPE EQU (0x1:SHL:2) ;- (UDP) Remote Wake Up Enable |
||
938 | AT91C_UDP_RSMINPR EQU (0x1:SHL:3) ;- (UDP) A Resume Has Been Sent to the Host |
||
939 | ;- -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- |
||
940 | AT91C_UDP_FADD EQU (0xFF:SHL:0) ;- (UDP) Function Address Value |
||
941 | AT91C_UDP_FEN EQU (0x1:SHL:8) ;- (UDP) Function Enable |
||
942 | ;- -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- |
||
943 | AT91C_UDP_EPINT0 EQU (0x1:SHL:0) ;- (UDP) Endpoint 0 Interrupt |
||
944 | AT91C_UDP_EPINT1 EQU (0x1:SHL:1) ;- (UDP) Endpoint 0 Interrupt |
||
945 | AT91C_UDP_EPINT2 EQU (0x1:SHL:2) ;- (UDP) Endpoint 2 Interrupt |
||
946 | AT91C_UDP_EPINT3 EQU (0x1:SHL:3) ;- (UDP) Endpoint 3 Interrupt |
||
947 | AT91C_UDP_EPINT4 EQU (0x1:SHL:4) ;- (UDP) Endpoint 4 Interrupt |
||
948 | AT91C_UDP_EPINT5 EQU (0x1:SHL:5) ;- (UDP) Endpoint 5 Interrupt |
||
949 | AT91C_UDP_EPINT6 EQU (0x1:SHL:6) ;- (UDP) Endpoint 6 Interrupt |
||
950 | AT91C_UDP_EPINT7 EQU (0x1:SHL:7) ;- (UDP) Endpoint 7 Interrupt |
||
951 | AT91C_UDP_RXSUSP EQU (0x1:SHL:8) ;- (UDP) USB Suspend Interrupt |
||
952 | AT91C_UDP_RXRSM EQU (0x1:SHL:9) ;- (UDP) USB Resume Interrupt |
||
953 | AT91C_UDP_EXTRSM EQU (0x1:SHL:10) ;- (UDP) USB External Resume Interrupt |
||
954 | AT91C_UDP_SOFINT EQU (0x1:SHL:11) ;- (UDP) USB Start Of frame Interrupt |
||
955 | AT91C_UDP_WAKEUP EQU (0x1:SHL:13) ;- (UDP) USB Resume Interrupt |
||
956 | ;- -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- |
||
957 | ;- -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- |
||
958 | ;- -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- |
||
959 | AT91C_UDP_ENDBUSRES EQU (0x1:SHL:12) ;- (UDP) USB End Of Bus Reset Interrupt |
||
960 | ;- -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- |
||
961 | ;- -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- |
||
962 | AT91C_UDP_EP0 EQU (0x1:SHL:0) ;- (UDP) Reset Endpoint 0 |
||
963 | AT91C_UDP_EP1 EQU (0x1:SHL:1) ;- (UDP) Reset Endpoint 1 |
||
964 | AT91C_UDP_EP2 EQU (0x1:SHL:2) ;- (UDP) Reset Endpoint 2 |
||
965 | AT91C_UDP_EP3 EQU (0x1:SHL:3) ;- (UDP) Reset Endpoint 3 |
||
966 | AT91C_UDP_EP4 EQU (0x1:SHL:4) ;- (UDP) Reset Endpoint 4 |
||
967 | AT91C_UDP_EP5 EQU (0x1:SHL:5) ;- (UDP) Reset Endpoint 5 |
||
968 | AT91C_UDP_EP6 EQU (0x1:SHL:6) ;- (UDP) Reset Endpoint 6 |
||
969 | AT91C_UDP_EP7 EQU (0x1:SHL:7) ;- (UDP) Reset Endpoint 7 |
||
970 | ;- -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- |
||
971 | AT91C_UDP_TXCOMP EQU (0x1:SHL:0) ;- (UDP) Generates an IN packet with data previously written in the DPR |
||
972 | AT91C_UDP_RX_DATA_BK0 EQU (0x1:SHL:1) ;- (UDP) Receive Data Bank 0 |
||
973 | AT91C_UDP_RXSETUP EQU (0x1:SHL:2) ;- (UDP) Sends STALL to the Host (Control endpoints) |
||
974 | AT91C_UDP_ISOERROR EQU (0x1:SHL:3) ;- (UDP) Isochronous error (Isochronous endpoints) |
||
975 | AT91C_UDP_TXPKTRDY EQU (0x1:SHL:4) ;- (UDP) Transmit Packet Ready |
||
976 | AT91C_UDP_FORCESTALL EQU (0x1:SHL:5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). |
||
977 | AT91C_UDP_RX_DATA_BK1 EQU (0x1:SHL:6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). |
||
978 | AT91C_UDP_DIR EQU (0x1:SHL:7) ;- (UDP) Transfer Direction |
||
979 | AT91C_UDP_EPTYPE EQU (0x7:SHL:8) ;- (UDP) Endpoint type |
||
980 | AT91C_UDP_EPTYPE_CTRL EQU (0x0:SHL:8) ;- (UDP) Control |
||
981 | AT91C_UDP_EPTYPE_ISO_OUT EQU (0x1:SHL:8) ;- (UDP) Isochronous OUT |
||
982 | AT91C_UDP_EPTYPE_BULK_OUT EQU (0x2:SHL:8) ;- (UDP) Bulk OUT |
||
983 | AT91C_UDP_EPTYPE_INT_OUT EQU (0x3:SHL:8) ;- (UDP) Interrupt OUT |
||
984 | AT91C_UDP_EPTYPE_ISO_IN EQU (0x5:SHL:8) ;- (UDP) Isochronous IN |
||
985 | AT91C_UDP_EPTYPE_BULK_IN EQU (0x6:SHL:8) ;- (UDP) Bulk IN |
||
986 | AT91C_UDP_EPTYPE_INT_IN EQU (0x7:SHL:8) ;- (UDP) Interrupt IN |
||
987 | AT91C_UDP_DTGLE EQU (0x1:SHL:11) ;- (UDP) Data Toggle |
||
988 | AT91C_UDP_EPEDS EQU (0x1:SHL:15) ;- (UDP) Endpoint Enable Disable |
||
989 | AT91C_UDP_RXBYTECNT EQU (0x7FF:SHL:16) ;- (UDP) Number Of Bytes Available in the FIFO |
||
990 | |||
991 | ;- ***************************************************************************** |
||
992 | ;- SOFTWARE API DEFINITION FOR Timer Counter Channel Interface |
||
993 | ;- ***************************************************************************** |
||
994 | ^ 0 ;- AT91S_TC |
||
995 | TC_CCR # 4 ;- Channel Control Register |
||
996 | TC_CMR # 4 ;- Channel Mode Register |
||
997 | # 8 ;- Reserved |
||
998 | TC_CV # 4 ;- Counter Value |
||
999 | TC_RA # 4 ;- Register A |
||
1000 | TC_RB # 4 ;- Register B |
||
1001 | TC_RC # 4 ;- Register C |
||
1002 | TC_SR # 4 ;- Status Register |
||
1003 | TC_IER # 4 ;- Interrupt Enable Register |
||
1004 | TC_IDR # 4 ;- Interrupt Disable Register |
||
1005 | TC_IMR # 4 ;- Interrupt Mask Register |
||
1006 | ;- -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- |
||
1007 | AT91C_TC_CLKEN EQU (0x1:SHL:0) ;- (TC) Counter Clock Enable Command |
||
1008 | AT91C_TC_CLKDIS EQU (0x1:SHL:1) ;- (TC) Counter Clock Disable Command |
||
1009 | AT91C_TC_SWTRG EQU (0x1:SHL:2) ;- (TC) Software Trigger Command |
||
1010 | ;- -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- |
||
1011 | AT91C_TC_CPCSTOP EQU (0x1:SHL:6) ;- (TC) Counter Clock Stopped with RC Compare |
||
1012 | AT91C_TC_CPCDIS EQU (0x1:SHL:7) ;- (TC) Counter Clock Disable with RC Compare |
||
1013 | AT91C_TC_EEVTEDG EQU (0x3:SHL:8) ;- (TC) External Event Edge Selection |
||
1014 | AT91C_TC_EEVTEDG_NONE EQU (0x0:SHL:8) ;- (TC) Edge: None |
||
1015 | AT91C_TC_EEVTEDG_RISING EQU (0x1:SHL:8) ;- (TC) Edge: rising edge |
||
1016 | AT91C_TC_EEVTEDG_FALLING EQU (0x2:SHL:8) ;- (TC) Edge: falling edge |
||
1017 | AT91C_TC_EEVTEDG_BOTH EQU (0x3:SHL:8) ;- (TC) Edge: each edge |
||
1018 | AT91C_TC_EEVT EQU (0x3:SHL:10) ;- (TC) External Event Selection |
||
1019 | AT91C_TC_EEVT_NONE EQU (0x0:SHL:10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input |
||
1020 | AT91C_TC_EEVT_RISING EQU (0x1:SHL:10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output |
||
1021 | AT91C_TC_EEVT_FALLING EQU (0x2:SHL:10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output |
||
1022 | AT91C_TC_EEVT_BOTH EQU (0x3:SHL:10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output |
||
1023 | AT91C_TC_ENETRG EQU (0x1:SHL:12) ;- (TC) External Event Trigger enable |
||
1024 | AT91C_TC_WAVESEL EQU (0x3:SHL:13) ;- (TC) Waveform Selection |
||
1025 | AT91C_TC_WAVESEL_UP EQU (0x0:SHL:13) ;- (TC) UP mode without atomatic trigger on RC Compare |
||
1026 | AT91C_TC_WAVESEL_UPDOWN EQU (0x1:SHL:13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare |
||
1027 | AT91C_TC_WAVESEL_UP_AUTO EQU (0x2:SHL:13) ;- (TC) UP mode with automatic trigger on RC Compare |
||
1028 | AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3:SHL:13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare |
||
1029 | AT91C_TC_CPCTRG EQU (0x1:SHL:14) ;- (TC) RC Compare Trigger Enable |
||
1030 | AT91C_TC_WAVE EQU (0x1:SHL:15) ;- (TC) |
||
1031 | AT91C_TC_ACPA EQU (0x3:SHL:16) ;- (TC) RA Compare Effect on TIOA |
||
1032 | AT91C_TC_ACPA_NONE EQU (0x0:SHL:16) ;- (TC) Effect: none |
||
1033 | AT91C_TC_ACPA_SET EQU (0x1:SHL:16) ;- (TC) Effect: set |
||
1034 | AT91C_TC_ACPA_CLEAR EQU (0x2:SHL:16) ;- (TC) Effect: clear |
||
1035 | AT91C_TC_ACPA_TOGGLE EQU (0x3:SHL:16) ;- (TC) Effect: toggle |
||
1036 | AT91C_TC_ACPC EQU (0x3:SHL:18) ;- (TC) RC Compare Effect on TIOA |
||
1037 | AT91C_TC_ACPC_NONE EQU (0x0:SHL:18) ;- (TC) Effect: none |
||
1038 | AT91C_TC_ACPC_SET EQU (0x1:SHL:18) ;- (TC) Effect: set |
||
1039 | AT91C_TC_ACPC_CLEAR EQU (0x2:SHL:18) ;- (TC) Effect: clear |
||
1040 | AT91C_TC_ACPC_TOGGLE EQU (0x3:SHL:18) ;- (TC) Effect: toggle |
||
1041 | AT91C_TC_AEEVT EQU (0x3:SHL:20) ;- (TC) External Event Effect on TIOA |
||
1042 | AT91C_TC_AEEVT_NONE EQU (0x0:SHL:20) ;- (TC) Effect: none |
||
1043 | AT91C_TC_AEEVT_SET EQU (0x1:SHL:20) ;- (TC) Effect: set |
||
1044 | AT91C_TC_AEEVT_CLEAR EQU (0x2:SHL:20) ;- (TC) Effect: clear |
||
1045 | AT91C_TC_AEEVT_TOGGLE EQU (0x3:SHL:20) ;- (TC) Effect: toggle |
||
1046 | AT91C_TC_ASWTRG EQU (0x3:SHL:22) ;- (TC) Software Trigger Effect on TIOA |
||
1047 | AT91C_TC_ASWTRG_NONE EQU (0x0:SHL:22) ;- (TC) Effect: none |
||
1048 | AT91C_TC_ASWTRG_SET EQU (0x1:SHL:22) ;- (TC) Effect: set |
||
1049 | AT91C_TC_ASWTRG_CLEAR EQU (0x2:SHL:22) ;- (TC) Effect: clear |
||
1050 | AT91C_TC_ASWTRG_TOGGLE EQU (0x3:SHL:22) ;- (TC) Effect: toggle |
||
1051 | AT91C_TC_BCPB EQU (0x3:SHL:24) ;- (TC) RB Compare Effect on TIOB |
||
1052 | AT91C_TC_BCPB_NONE EQU (0x0:SHL:24) ;- (TC) Effect: none |
||
1053 | AT91C_TC_BCPB_SET EQU (0x1:SHL:24) ;- (TC) Effect: set |
||
1054 | AT91C_TC_BCPB_CLEAR EQU (0x2:SHL:24) ;- (TC) Effect: clear |
||
1055 | AT91C_TC_BCPB_TOGGLE EQU (0x3:SHL:24) ;- (TC) Effect: toggle |
||
1056 | AT91C_TC_BCPC EQU (0x3:SHL:26) ;- (TC) RC Compare Effect on TIOB |
||
1057 | AT91C_TC_BCPC_NONE EQU (0x0:SHL:26) ;- (TC) Effect: none |
||
1058 | AT91C_TC_BCPC_SET EQU (0x1:SHL:26) ;- (TC) Effect: set |
||
1059 | AT91C_TC_BCPC_CLEAR EQU (0x2:SHL:26) ;- (TC) Effect: clear |
||
1060 | AT91C_TC_BCPC_TOGGLE EQU (0x3:SHL:26) ;- (TC) Effect: toggle |
||
1061 | AT91C_TC_BEEVT EQU (0x3:SHL:28) ;- (TC) External Event Effect on TIOB |
||
1062 | AT91C_TC_BEEVT_NONE EQU (0x0:SHL:28) ;- (TC) Effect: none |
||
1063 | AT91C_TC_BEEVT_SET EQU (0x1:SHL:28) ;- (TC) Effect: set |
||
1064 | AT91C_TC_BEEVT_CLEAR EQU (0x2:SHL:28) ;- (TC) Effect: clear |
||
1065 | AT91C_TC_BEEVT_TOGGLE EQU (0x3:SHL:28) ;- (TC) Effect: toggle |
||
1066 | AT91C_TC_BSWTRG EQU (0x3:SHL:30) ;- (TC) Software Trigger Effect on TIOB |
||
1067 | AT91C_TC_BSWTRG_NONE EQU (0x0:SHL:30) ;- (TC) Effect: none |
||
1068 | AT91C_TC_BSWTRG_SET EQU (0x1:SHL:30) ;- (TC) Effect: set |
||
1069 | AT91C_TC_BSWTRG_CLEAR EQU (0x2:SHL:30) ;- (TC) Effect: clear |
||
1070 | AT91C_TC_BSWTRG_TOGGLE EQU (0x3:SHL:30) ;- (TC) Effect: toggle |
||
1071 | ;- -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- |
||
1072 | AT91C_TC_COVFS EQU (0x1:SHL:0) ;- (TC) Counter Overflow |
||
1073 | AT91C_TC_LOVRS EQU (0x1:SHL:1) ;- (TC) Load Overrun |
||
1074 | AT91C_TC_CPAS EQU (0x1:SHL:2) ;- (TC) RA Compare |
||
1075 | AT91C_TC_CPBS EQU (0x1:SHL:3) ;- (TC) RB Compare |
||
1076 | AT91C_TC_CPCS EQU (0x1:SHL:4) ;- (TC) RC Compare |
||
1077 | AT91C_TC_LDRAS EQU (0x1:SHL:5) ;- (TC) RA Loading |
||
1078 | AT91C_TC_LDRBS EQU (0x1:SHL:6) ;- (TC) RB Loading |
||
1079 | AT91C_TC_ETRCS EQU (0x1:SHL:7) ;- (TC) External Trigger |
||
1080 | AT91C_TC_ETRGS EQU (0x1:SHL:16) ;- (TC) Clock Enabling |
||
1081 | AT91C_TC_MTIOA EQU (0x1:SHL:17) ;- (TC) TIOA Mirror |
||
1082 | AT91C_TC_MTIOB EQU (0x1:SHL:18) ;- (TC) TIOA Mirror |
||
1083 | ;- -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- |
||
1084 | ;- -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- |
||
1085 | ;- -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- |
||
1086 | |||
1087 | ;- ***************************************************************************** |
||
1088 | ;- SOFTWARE API DEFINITION FOR Timer Counter Interface |
||
1089 | ;- ***************************************************************************** |
||
1090 | ^ 0 ;- AT91S_TCB |
||
1091 | TCB_TC0 # 48 ;- TC Channel 0 |
||
1092 | # 16 ;- Reserved |
||
1093 | TCB_TC1 # 48 ;- TC Channel 1 |
||
1094 | # 16 ;- Reserved |
||
1095 | TCB_TC2 # 48 ;- TC Channel 2 |
||
1096 | # 16 ;- Reserved |
||
1097 | TCB_BCR # 4 ;- TC Block Control Register |
||
1098 | TCB_BMR # 4 ;- TC Block Mode Register |
||
1099 | ;- -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- |
||
1100 | AT91C_TCB_SYNC EQU (0x1:SHL:0) ;- (TCB) Synchro Command |
||
1101 | ;- -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- |
||
1102 | AT91C_TCB_TC0XC0S EQU (0x1:SHL:0) ;- (TCB) External Clock Signal 0 Selection |
||
1103 | AT91C_TCB_TC0XC0S_TCLK0 EQU (0x0) ;- (TCB) TCLK0 connected to XC0 |
||
1104 | AT91C_TCB_TC0XC0S_NONE EQU (0x1) ;- (TCB) None signal connected to XC0 |
||
1105 | AT91C_TCB_TC0XC0S_TIOA1 EQU (0x2) ;- (TCB) TIOA1 connected to XC0 |
||
1106 | AT91C_TCB_TC0XC0S_TIOA2 EQU (0x3) ;- (TCB) TIOA2 connected to XC0 |
||
1107 | AT91C_TCB_TC1XC1S EQU (0x1:SHL:2) ;- (TCB) External Clock Signal 1 Selection |
||
1108 | AT91C_TCB_TC1XC1S_TCLK1 EQU (0x0:SHL:2) ;- (TCB) TCLK1 connected to XC1 |
||
1109 | AT91C_TCB_TC1XC1S_NONE EQU (0x1:SHL:2) ;- (TCB) None signal connected to XC1 |
||
1110 | AT91C_TCB_TC1XC1S_TIOA0 EQU (0x2:SHL:2) ;- (TCB) TIOA0 connected to XC1 |
||
1111 | AT91C_TCB_TC1XC1S_TIOA2 EQU (0x3:SHL:2) ;- (TCB) TIOA2 connected to XC1 |
||
1112 | AT91C_TCB_TC2XC2S EQU (0x1:SHL:4) ;- (TCB) External Clock Signal 2 Selection |
||
1113 | AT91C_TCB_TC2XC2S_TCLK2 EQU (0x0:SHL:4) ;- (TCB) TCLK2 connected to XC2 |
||
1114 | AT91C_TCB_TC2XC2S_NONE EQU (0x1:SHL:4) ;- (TCB) None signal connected to XC2 |
||
1115 | AT91C_TCB_TC2XC2S_TIOA0 EQU (0x2:SHL:4) ;- (TCB) TIOA0 connected to XC2 |
||
1116 | AT91C_TCB_TC2XC2S_TIOA2 EQU (0x3:SHL:4) ;- (TCB) TIOA2 connected to XC2 |
||
1117 | |||
1118 | ;- ***************************************************************************** |
||
1119 | ;- SOFTWARE API DEFINITION FOR USB Host Interface |
||
1120 | ;- ***************************************************************************** |
||
1121 | ^ 0 ;- AT91S_UHP |
||
1122 | UHP_HcRevision # 4 ;- Revision |
||
1123 | UHP_HcControl # 4 ;- Operating modes for the Host Controller |
||
1124 | UHP_HcCommandStatus # 4 ;- Command & status Register |
||
1125 | UHP_HcInterruptStatus # 4 ;- Interrupt Status Register |
||
1126 | UHP_HcInterruptEnable # 4 ;- Interrupt Enable Register |
||
1127 | UHP_HcInterruptDisable # 4 ;- Interrupt Disable Register |
||
1128 | UHP_HcHCCA # 4 ;- Pointer to the Host Controller Communication Area |
||
1129 | UHP_HcPeriodCurrentED # 4 ;- Current Isochronous or Interrupt Endpoint Descriptor |
||
1130 | UHP_HcControlHeadED # 4 ;- First Endpoint Descriptor of the Control list |
||
1131 | UHP_HcControlCurrentED # 4 ;- Endpoint Control and Status Register |
||
1132 | UHP_HcBulkHeadED # 4 ;- First endpoint register of the Bulk list |
||
1133 | UHP_HcBulkCurrentED # 4 ;- Current endpoint of the Bulk list |
||
1134 | UHP_HcBulkDoneHead # 4 ;- Last completed transfer descriptor |
||
1135 | UHP_HcFmInterval # 4 ;- Bit time between 2 consecutive SOFs |
||
1136 | UHP_HcFmRemaining # 4 ;- Bit time remaining in the current Frame |
||
1137 | UHP_HcFmNumber # 4 ;- Frame number |
||
1138 | UHP_HcPeriodicStart # 4 ;- Periodic Start |
||
1139 | UHP_HcLSThreshold # 4 ;- LS Threshold |
||
1140 | UHP_HcRhDescriptorA # 4 ;- Root Hub characteristics A |
||
1141 | UHP_HcRhDescriptorB # 4 ;- Root Hub characteristics B |
||
1142 | UHP_HcRhStatus # 4 ;- Root Hub Status register |
||
1143 | UHP_HcRhPortStatus # 8 ;- Root Hub Port Status Register |
||
1144 | |||
1145 | ;- ***************************************************************************** |
||
1146 | ;- SOFTWARE API DEFINITION FOR Ethernet MAC |
||
1147 | ;- ***************************************************************************** |
||
1148 | ^ 0 ;- AT91S_EMAC |
||
1149 | EMAC_CTL # 4 ;- Network Control Register |
||
1150 | EMAC_CFG # 4 ;- Network Configuration Register |
||
1151 | EMAC_SR # 4 ;- Network Status Register |
||
1152 | EMAC_TAR # 4 ;- Transmit Address Register |
||
1153 | EMAC_TCR # 4 ;- Transmit Control Register |
||
1154 | EMAC_TSR # 4 ;- Transmit Status Register |
||
1155 | EMAC_RBQP # 4 ;- Receive Buffer Queue Pointer |
||
1156 | # 4 ;- Reserved |
||
1157 | EMAC_RSR # 4 ;- Receive Status Register |
||
1158 | EMAC_ISR # 4 ;- Interrupt Status Register |
||
1159 | EMAC_IER # 4 ;- Interrupt Enable Register |
||
1160 | EMAC_IDR # 4 ;- Interrupt Disable Register |
||
1161 | EMAC_IMR # 4 ;- Interrupt Mask Register |
||
1162 | EMAC_MAN # 4 ;- PHY Maintenance Register |
||
1163 | # 8 ;- Reserved |
||
1164 | EMAC_FRA # 4 ;- Frames Transmitted OK Register |
||
1165 | EMAC_SCOL # 4 ;- Single Collision Frame Register |
||
1166 | EMAC_MCOL # 4 ;- Multiple Collision Frame Register |
||
1167 | EMAC_OK # 4 ;- Frames Received OK Register |
||
1168 | EMAC_SEQE # 4 ;- Frame Check Sequence Error Register |
||
1169 | EMAC_ALE # 4 ;- Alignment Error Register |
||
1170 | EMAC_DTE # 4 ;- Deferred Transmission Frame Register |
||
1171 | EMAC_LCOL # 4 ;- Late Collision Register |
||
1172 | EMAC_ECOL # 4 ;- Excessive Collision Register |
||
1173 | EMAC_CSE # 4 ;- Carrier Sense Error Register |
||
1174 | EMAC_TUE # 4 ;- Transmit Underrun Error Register |
||
1175 | EMAC_CDE # 4 ;- Code Error Register |
||
1176 | EMAC_ELR # 4 ;- Excessive Length Error Register |
||
1177 | EMAC_RJB # 4 ;- Receive Jabber Register |
||
1178 | EMAC_USF # 4 ;- Undersize Frame Register |
||
1179 | EMAC_SQEE # 4 ;- SQE Test Error Register |
||
1180 | EMAC_DRFC # 4 ;- Discarded RX Frame Register |
||
1181 | # 12 ;- Reserved |
||
1182 | EMAC_HSH # 4 ;- Hash Address High[63:32] |
||
1183 | EMAC_HSL # 4 ;- Hash Address Low[31:0] |
||
1184 | EMAC_SA1L # 4 ;- Specific Address 1 Low, First 4 bytes |
||
1185 | EMAC_SA1H # 4 ;- Specific Address 1 High, Last 2 bytes |
||
1186 | EMAC_SA2L # 4 ;- Specific Address 2 Low, First 4 bytes |
||
1187 | EMAC_SA2H # 4 ;- Specific Address 2 High, Last 2 bytes |
||
1188 | EMAC_SA3L # 4 ;- Specific Address 3 Low, First 4 bytes |
||
1189 | EMAC_SA3H # 4 ;- Specific Address 3 High, Last 2 bytes |
||
1190 | EMAC_SA4L # 4 ;- Specific Address 4 Low, First 4 bytes |
||
1191 | EMAC_SA4H # 4 ;- Specific Address 4 High, Last 2 bytesr |
||
1192 | ;- -------- EMAC_CTL : (EMAC Offset: 0x0) -------- |
||
1193 | AT91C_EMAC_LB EQU (0x1:SHL:0) ;- (EMAC) Loopback. Optional. When set, loopback signal is at high level. |
||
1194 | AT91C_EMAC_LBL EQU (0x1:SHL:1) ;- (EMAC) Loopback local. |
||
1195 | AT91C_EMAC_RE EQU (0x1:SHL:2) ;- (EMAC) Receive enable. |
||
1196 | AT91C_EMAC_TE EQU (0x1:SHL:3) ;- (EMAC) Transmit enable. |
||
1197 | AT91C_EMAC_MPE EQU (0x1:SHL:4) ;- (EMAC) Management port enable. |
||
1198 | AT91C_EMAC_CSR EQU (0x1:SHL:5) ;- (EMAC) Clear statistics registers. |
||
1199 | AT91C_EMAC_ISR EQU (0x1:SHL:6) ;- (EMAC) Increment statistics registers. |
||
1200 | AT91C_EMAC_WES EQU (0x1:SHL:7) ;- (EMAC) Write enable for statistics registers. |
||
1201 | AT91C_EMAC_BP EQU (0x1:SHL:8) ;- (EMAC) Back pressure. |
||
1202 | ;- -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- |
||
1203 | AT91C_EMAC_SPD EQU (0x1:SHL:0) ;- (EMAC) Speed. |
||
1204 | AT91C_EMAC_FD EQU (0x1:SHL:1) ;- (EMAC) Full duplex. |
||
1205 | AT91C_EMAC_BR EQU (0x1:SHL:2) ;- (EMAC) Bit rate. |
||
1206 | AT91C_EMAC_CAF EQU (0x1:SHL:4) ;- (EMAC) Copy all frames. |
||
1207 | AT91C_EMAC_NBC EQU (0x1:SHL:5) ;- (EMAC) No broadcast. |
||
1208 | AT91C_EMAC_MTI EQU (0x1:SHL:6) ;- (EMAC) Multicast hash enable |
||
1209 | AT91C_EMAC_UNI EQU (0x1:SHL:7) ;- (EMAC) Unicast hash enable. |
||
1210 | AT91C_EMAC_BIG EQU (0x1:SHL:8) ;- (EMAC) Receive 1522 bytes. |
||
1211 | AT91C_EMAC_EAE EQU (0x1:SHL:9) ;- (EMAC) External address match enable. |
||
1212 | AT91C_EMAC_CLK EQU (0x3:SHL:10) ;- (EMAC) |
||
1213 | AT91C_EMAC_CLK_HCLK_8 EQU (0x0:SHL:10) ;- (EMAC) HCLK divided by 8 |
||
1214 | AT91C_EMAC_CLK_HCLK_16 EQU (0x1:SHL:10) ;- (EMAC) HCLK divided by 16 |
||
1215 | AT91C_EMAC_CLK_HCLK_32 EQU (0x2:SHL:10) ;- (EMAC) HCLK divided by 32 |
||
1216 | AT91C_EMAC_CLK_HCLK_64 EQU (0x3:SHL:10) ;- (EMAC) HCLK divided by 64 |
||
1217 | AT91C_EMAC_RTY EQU (0x1:SHL:12) ;- (EMAC) |
||
1218 | AT91C_EMAC_RMII EQU (0x1:SHL:13) ;- (EMAC) |
||
1219 | ;- -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register -------- |
||
1220 | AT91C_EMAC_MDIO EQU (0x1:SHL:1) ;- (EMAC) |
||
1221 | AT91C_EMAC_IDLE EQU (0x1:SHL:2) ;- (EMAC) |
||
1222 | ;- -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- |
||
1223 | AT91C_EMAC_LEN EQU (0x7FF:SHL:0) ;- (EMAC) |
||
1224 | AT91C_EMAC_NCRC EQU (0x1:SHL:15) ;- (EMAC) |
||
1225 | ;- -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- |
||
1226 | AT91C_EMAC_OVR EQU (0x1:SHL:0) ;- (EMAC) |
||
1227 | AT91C_EMAC_COL EQU (0x1:SHL:1) ;- (EMAC) |
||
1228 | AT91C_EMAC_RLE EQU (0x1:SHL:2) ;- (EMAC) |
||
1229 | AT91C_EMAC_TXIDLE EQU (0x1:SHL:3) ;- (EMAC) |
||
1230 | AT91C_EMAC_BNQ EQU (0x1:SHL:4) ;- (EMAC) |
||
1231 | AT91C_EMAC_COMP EQU (0x1:SHL:5) ;- (EMAC) |
||
1232 | AT91C_EMAC_UND EQU (0x1:SHL:6) ;- (EMAC) |
||
1233 | ;- -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- |
||
1234 | AT91C_EMAC_BNA EQU (0x1:SHL:0) ;- (EMAC) |
||
1235 | AT91C_EMAC_REC EQU (0x1:SHL:1) ;- (EMAC) |
||
1236 | ;- -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- |
||
1237 | AT91C_EMAC_DONE EQU (0x1:SHL:0) ;- (EMAC) |
||
1238 | AT91C_EMAC_RCOM EQU (0x1:SHL:1) ;- (EMAC) |
||
1239 | AT91C_EMAC_RBNA EQU (0x1:SHL:2) ;- (EMAC) |
||
1240 | AT91C_EMAC_TOVR EQU (0x1:SHL:3) ;- (EMAC) |
||
1241 | AT91C_EMAC_TUND EQU (0x1:SHL:4) ;- (EMAC) |
||
1242 | AT91C_EMAC_RTRY EQU (0x1:SHL:5) ;- (EMAC) |
||
1243 | AT91C_EMAC_TBRE EQU (0x1:SHL:6) ;- (EMAC) |
||
1244 | AT91C_EMAC_TCOM EQU (0x1:SHL:7) ;- (EMAC) |
||
1245 | AT91C_EMAC_TIDLE EQU (0x1:SHL:8) ;- (EMAC) |
||
1246 | AT91C_EMAC_LINK EQU (0x1:SHL:9) ;- (EMAC) |
||
1247 | AT91C_EMAC_ROVR EQU (0x1:SHL:10) ;- (EMAC) |
||
1248 | AT91C_EMAC_HRESP EQU (0x1:SHL:11) ;- (EMAC) |
||
1249 | ;- -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- |
||
1250 | ;- -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- |
||
1251 | ;- -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- |
||
1252 | ;- -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- |
||
1253 | AT91C_EMAC_DATA EQU (0xFFFF:SHL:0) ;- (EMAC) |
||
1254 | AT91C_EMAC_CODE EQU (0x3:SHL:16) ;- (EMAC) |
||
1255 | AT91C_EMAC_REGA EQU (0x1F:SHL:18) ;- (EMAC) |
||
1256 | AT91C_EMAC_PHYA EQU (0x1F:SHL:23) ;- (EMAC) |
||
1257 | AT91C_EMAC_RW EQU (0x3:SHL:28) ;- (EMAC) |
||
1258 | AT91C_EMAC_HIGH EQU (0x1:SHL:30) ;- (EMAC) |
||
1259 | AT91C_EMAC_LOW EQU (0x1:SHL:31) ;- (EMAC) |
||
1260 | |||
1261 | ;- ***************************************************************************** |
||
1262 | ;- SOFTWARE API DEFINITION FOR External Bus Interface |
||
1263 | ;- ***************************************************************************** |
||
1264 | ^ 0 ;- AT91S_EBI |
||
1265 | EBI_CSA # 4 ;- Chip Select Assignment Register |
||
1266 | EBI_CFGR # 4 ;- Configuration Register |
||
1267 | ;- -------- EBI_CSA : (EBI Offset: 0x0) Chip Select Assignment Register -------- |
||
1268 | AT91C_EBI_CS0A EQU (0x1:SHL:0) ;- (EBI) Chip Select 0 Assignment |
||
1269 | AT91C_EBI_CS0A_SMC EQU (0x0) ;- (EBI) Chip Select 0 is assigned to the Static Memory Controller. |
||
1270 | AT91C_EBI_CS0A_BFC EQU (0x1) ;- (EBI) Chip Select 0 is assigned to the Burst Flash Controller. |
||
1271 | AT91C_EBI_CS1A EQU (0x1:SHL:1) ;- (EBI) Chip Select 1 Assignment |
||
1272 | AT91C_EBI_CS1A_SMC EQU (0x0:SHL:1) ;- (EBI) Chip Select 1 is assigned to the Static Memory Controller. |
||
1273 | AT91C_EBI_CS1A_SDRAMC EQU (0x1:SHL:1) ;- (EBI) Chip Select 1 is assigned to the SDRAM Controller. |
||
1274 | AT91C_EBI_CS3A EQU (0x1:SHL:3) ;- (EBI) Chip Select 3 Assignment |
||
1275 | AT91C_EBI_CS3A_SMC EQU (0x0:SHL:3) ;- (EBI) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC2. |
||
1276 | AT91C_EBI_CS3A_SMC_SmartMedia EQU (0x1:SHL:3) ;- (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. |
||
1277 | AT91C_EBI_CS4A EQU (0x1:SHL:4) ;- (EBI) Chip Select 4 Assignment |
||
1278 | AT91C_EBI_CS4A_SMC EQU (0x0:SHL:4) ;- (EBI) Chip Select 4 is assigned to the Static Memory Controller and NCS4,NCS5 and NCS6 behave as defined by the SMC2. |
||
1279 | AT91C_EBI_CS4A_SMC_CompactFlash EQU (0x1:SHL:4) ;- (EBI) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic is activated. |
||
1280 | ;- -------- EBI_CFGR : (EBI Offset: 0x4) Configuration Register -------- |
||
1281 | AT91C_EBI_DBPUC EQU (0x1:SHL:0) ;- (EBI) Data Bus Pull-Up Configuration |
||
1282 | AT91C_EBI_EBSEN EQU (0x1:SHL:1) ;- (EBI) Bus Sharing Enable |
||
1283 | |||
1284 | ;- ***************************************************************************** |
||
1285 | ;- SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface |
||
1286 | ;- ***************************************************************************** |
||
1287 | ^ 0 ;- AT91S_SMC2 |
||
1288 | SMC2_CSR # 32 ;- SMC2 Chip Select Register |
||
1289 | ;- -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- |
||
1290 | AT91C_SMC2_NWS EQU (0x7F:SHL:0) ;- (SMC2) Number of Wait States |
||
1291 | AT91C_SMC2_WSEN EQU (0x1:SHL:7) ;- (SMC2) Wait State Enable |
||
1292 | AT91C_SMC2_TDF EQU (0xF:SHL:8) ;- (SMC2) Data Float Time |
||
1293 | AT91C_SMC2_BAT EQU (0x1:SHL:12) ;- (SMC2) Byte Access Type |
||
1294 | AT91C_SMC2_DBW EQU (0x1:SHL:13) ;- (SMC2) Data Bus Width |
||
1295 | AT91C_SMC2_DBW_16 EQU (0x1:SHL:13) ;- (SMC2) 16-bit. |
||
1296 | AT91C_SMC2_DBW_8 EQU (0x2:SHL:13) ;- (SMC2) 8-bit. |
||
1297 | AT91C_SMC2_DRP EQU (0x1:SHL:15) ;- (SMC2) Data Read Protocol |
||
1298 | AT91C_SMC2_ACSS EQU (0x3:SHL:16) ;- (SMC2) Address to Chip Select Setup |
||
1299 | AT91C_SMC2_ACSS_STANDARD EQU (0x0:SHL:16) ;- (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. |
||
1300 | AT91C_SMC2_ACSS_1_CYCLE EQU (0x1:SHL:16) ;- (SMC2) One cycle less at the beginning and the end of the access. |
||
1301 | AT91C_SMC2_ACSS_2_CYCLES EQU (0x2:SHL:16) ;- (SMC2) Two cycles less at the beginning and the end of the access. |
||
1302 | AT91C_SMC2_ACSS_3_CYCLES EQU (0x3:SHL:16) ;- (SMC2) Three cycles less at the beginning and the end of the access. |
||
1303 | AT91C_SMC2_RWSETUP EQU (0x7:SHL:24) ;- (SMC2) Read and Write Signal Setup Time |
||
1304 | AT91C_SMC2_RWHOLD EQU (0x7:SHL:29) ;- (SMC2) Read and Write Signal Hold Time |
||
1305 | |||
1306 | ;- ***************************************************************************** |
||
1307 | ;- SOFTWARE API DEFINITION FOR SDRAM Controller Interface |
||
1308 | ;- ***************************************************************************** |
||
1309 | ^ 0 ;- AT91S_SDRC |
||
1310 | SDRC_MR # 4 ;- SDRAM Controller Mode Register |
||
1311 | SDRC_TR # 4 ;- SDRAM Controller Refresh Timer Register |
||
1312 | SDRC_CR # 4 ;- SDRAM Controller Configuration Register |
||
1313 | SDRC_SRR # 4 ;- SDRAM Controller Self Refresh Register |
||
1314 | SDRC_LPR # 4 ;- SDRAM Controller Low Power Register |
||
1315 | SDRC_IER # 4 ;- SDRAM Controller Interrupt Enable Register |
||
1316 | SDRC_IDR # 4 ;- SDRAM Controller Interrupt Disable Register |
||
1317 | SDRC_IMR # 4 ;- SDRAM Controller Interrupt Mask Register |
||
1318 | SDRC_ISR # 4 ;- SDRAM Controller Interrupt Mask Register |
||
1319 | ;- -------- SDRC_MR : (SDRC Offset: 0x0) SDRAM Controller Mode Register -------- |
||
1320 | AT91C_SDRC_MODE EQU (0xF:SHL:0) ;- (SDRC) Mode |
||
1321 | AT91C_SDRC_MODE_NORMAL_CMD EQU (0x0) ;- (SDRC) Normal Mode |
||
1322 | AT91C_SDRC_MODE_NOP_CMD EQU (0x1) ;- (SDRC) NOP Command |
||
1323 | AT91C_SDRC_MODE_PRCGALL_CMD EQU (0x2) ;- (SDRC) All Banks Precharge Command |
||
1324 | AT91C_SDRC_MODE_LMR_CMD EQU (0x3) ;- (SDRC) Load Mode Register Command |
||
1325 | AT91C_SDRC_MODE_RFSH_CMD EQU (0x4) ;- (SDRC) Refresh Command |
||
1326 | AT91C_SDRC_DBW EQU (0x1:SHL:4) ;- (SDRC) Data Bus Width |
||
1327 | AT91C_SDRC_DBW_32_BITS EQU (0x0:SHL:4) ;- (SDRC) 32 Bits datas bus |
||
1328 | AT91C_SDRC_DBW_16_BITS EQU (0x1:SHL:4) ;- (SDRC) 16 Bits datas bus |
||
1329 | ;- -------- SDRC_TR : (SDRC Offset: 0x4) SDRC Refresh Timer Register -------- |
||
1330 | AT91C_SDRC_COUNT EQU (0xFFF:SHL:0) ;- (SDRC) Refresh Counter |
||
1331 | ;- -------- SDRC_CR : (SDRC Offset: 0x8) SDRAM Configuration Register -------- |
||
1332 | AT91C_SDRC_NC EQU (0x3:SHL:0) ;- (SDRC) Number of Column Bits |
||
1333 | AT91C_SDRC_NC_8 EQU (0x0) ;- (SDRC) 8 Bits |
||
1334 | AT91C_SDRC_NC_9 EQU (0x1) ;- (SDRC) 9 Bits |
||
1335 | AT91C_SDRC_NC_10 EQU (0x2) ;- (SDRC) 10 Bits |
||
1336 | AT91C_SDRC_NC_11 EQU (0x3) ;- (SDRC) 11 Bits |
||
1337 | AT91C_SDRC_NR EQU (0x3:SHL:2) ;- (SDRC) Number of Row Bits |
||
1338 | AT91C_SDRC_NR_11 EQU (0x0:SHL:2) ;- (SDRC) 11 Bits |
||
1339 | AT91C_SDRC_NR_12 EQU (0x1:SHL:2) ;- (SDRC) 12 Bits |
||
1340 | AT91C_SDRC_NR_13 EQU (0x2:SHL:2) ;- (SDRC) 13 Bits |
||
1341 | AT91C_SDRC_NB EQU (0x1:SHL:4) ;- (SDRC) Number of Banks |
||
1342 | AT91C_SDRC_NB_2_BANKS EQU (0x0:SHL:4) ;- (SDRC) 2 banks |
||
1343 | AT91C_SDRC_NB_4_BANKS EQU (0x1:SHL:4) ;- (SDRC) 4 banks |
||
1344 | AT91C_SDRC_CAS EQU (0x3:SHL:5) ;- (SDRC) CAS Latency |
||
1345 | AT91C_SDRC_CAS_2 EQU (0x2:SHL:5) ;- (SDRC) 2 cycles |
||
1346 | AT91C_SDRC_TWR EQU (0xF:SHL:7) ;- (SDRC) Number of Write Recovery Time Cycles |
||
1347 | AT91C_SDRC_TRC EQU (0xF:SHL:11) ;- (SDRC) Number of RAS Cycle Time Cycles |
||
1348 | AT91C_SDRC_TRP EQU (0xF:SHL:15) ;- (SDRC) Number of RAS Precharge Time Cycles |
||
1349 | AT91C_SDRC_TRCD EQU (0xF:SHL:19) ;- (SDRC) Number of RAS to CAS Delay Cycles |
||
1350 | AT91C_SDRC_TRAS EQU (0xF:SHL:23) ;- (SDRC) Number of RAS Active Time Cycles |
||
1351 | AT91C_SDRC_TXSR EQU (0xF:SHL:27) ;- (SDRC) Number of Command Recovery Time Cycles |
||
1352 | ;- -------- SDRC_SRR : (SDRC Offset: 0xc) SDRAM Controller Self-refresh Register -------- |
||
1353 | AT91C_SDRC_SRCB EQU (0x1:SHL:0) ;- (SDRC) Self-refresh Command Bit |
||
1354 | ;- -------- SDRC_LPR : (SDRC Offset: 0x10) SDRAM Controller Low-power Register -------- |
||
1355 | AT91C_SDRC_LPCB EQU (0x1:SHL:0) ;- (SDRC) Low-power Command Bit |
||
1356 | ;- -------- SDRC_IER : (SDRC Offset: 0x14) SDRAM Controller Interrupt Enable Register -------- |
||
1357 | AT91C_SDRC_RES EQU (0x1:SHL:0) ;- (SDRC) Refresh Error Status |
||
1358 | ;- -------- SDRC_IDR : (SDRC Offset: 0x18) SDRAM Controller Interrupt Disable Register -------- |
||
1359 | ;- -------- SDRC_IMR : (SDRC Offset: 0x1c) SDRAM Controller Interrupt Mask Register -------- |
||
1360 | ;- -------- SDRC_ISR : (SDRC Offset: 0x20) SDRAM Controller Interrupt Status Register -------- |
||
1361 | |||
1362 | ;- ***************************************************************************** |
||
1363 | ;- SOFTWARE API DEFINITION FOR Burst Flash Controller Interface |
||
1364 | ;- ***************************************************************************** |
||
1365 | ^ 0 ;- AT91S_BFC |
||
1366 | BFC_MR # 4 ;- BFC Mode Register |
||
1367 | ;- -------- BFC_MR : (BFC Offset: 0x0) BFC Mode Register -------- |
||
1368 | AT91C_BFC_BFCOM EQU (0x3:SHL:0) ;- (BFC) Burst Flash Controller Operating Mode |
||
1369 | AT91C_BFC_BFCOM_DISABLED EQU (0x0) ;- (BFC) NPCS0 is driven by the SMC or remains high. |
||
1370 | AT91C_BFC_BFCOM_ASYNC EQU (0x1) ;- (BFC) Asynchronous |
||
1371 | AT91C_BFC_BFCOM_BURST_READ EQU (0x2) ;- (BFC) Burst Read |
||
1372 | AT91C_BFC_BFCC EQU (0x3:SHL:2) ;- (BFC) Burst Flash Controller Operating Mode |
||
1373 | AT91C_BFC_BFCC_MCK EQU (0x1:SHL:2) ;- (BFC) Master Clock. |
||
1374 | AT91C_BFC_BFCC_MCK_DIV_2 EQU (0x2:SHL:2) ;- (BFC) Master Clock divided by 2. |
||
1375 | AT91C_BFC_BFCC_MCK_DIV_4 EQU (0x3:SHL:2) ;- (BFC) Master Clock divided by 4. |
||
1376 | AT91C_BFC_AVL EQU (0xF:SHL:4) ;- (BFC) Address Valid Latency |
||
1377 | AT91C_BFC_PAGES EQU (0x7:SHL:8) ;- (BFC) Page Size |
||
1378 | AT91C_BFC_PAGES_NO_PAGE EQU (0x0:SHL:8) ;- (BFC) No page handling. |
||
1379 | AT91C_BFC_PAGES_16 EQU (0x1:SHL:8) ;- (BFC) 16 bytes page size. |
||
1380 | AT91C_BFC_PAGES_32 EQU (0x2:SHL:8) ;- (BFC) 32 bytes page size. |
||
1381 | AT91C_BFC_PAGES_64 EQU (0x3:SHL:8) ;- (BFC) 64 bytes page size. |
||
1382 | AT91C_BFC_PAGES_128 EQU (0x4:SHL:8) ;- (BFC) 128 bytes page size. |
||
1383 | AT91C_BFC_PAGES_256 EQU (0x5:SHL:8) ;- (BFC) 256 bytes page size. |
||
1384 | AT91C_BFC_PAGES_512 EQU (0x6:SHL:8) ;- (BFC) 512 bytes page size. |
||
1385 | AT91C_BFC_PAGES_1024 EQU (0x7:SHL:8) ;- (BFC) 1024 bytes page size. |
||
1386 | AT91C_BFC_OEL EQU (0x3:SHL:12) ;- (BFC) Output Enable Latency |
||
1387 | AT91C_BFC_BAAEN EQU (0x1:SHL:16) ;- (BFC) Burst Address Advance Enable |
||
1388 | AT91C_BFC_BFOEH EQU (0x1:SHL:17) ;- (BFC) Burst Flash Output Enable Handling |
||
1389 | AT91C_BFC_MUXEN EQU (0x1:SHL:18) ;- (BFC) Multiplexed Bus Enable |
||
1390 | AT91C_BFC_RDYEN EQU (0x1:SHL:19) ;- (BFC) Ready Enable Mode |
||
1391 | |||
1392 | ;- ***************************************************************************** |
||
1393 | ;- REGISTER ADDRESS DEFINITION FOR AT91RM9200 |
||
1394 | ;- ***************************************************************************** |
||
1395 | ;- ========== Register definition for SYS peripheral ========== |
||
1396 | ;- ========== Register definition for MC peripheral ========== |
||
1397 | AT91C_MC_PUER EQU (0xFFFFFF54) ;- (MC) MC Protection Unit Enable Register |
||
1398 | AT91C_MC_ASR EQU (0xFFFFFF04) ;- (MC) MC Abort Status Register |
||
1399 | AT91C_MC_PUP EQU (0xFFFFFF50) ;- (MC) MC Protection Unit Peripherals |
||
1400 | AT91C_MC_PUIA EQU (0xFFFFFF10) ;- (MC) MC Protection Unit Area |
||
1401 | AT91C_MC_AASR EQU (0xFFFFFF08) ;- (MC) MC Abort Address Status Register |
||
1402 | AT91C_MC_RCR EQU (0xFFFFFF00) ;- (MC) MC Remap Control Register |
||
1403 | ;- ========== Register definition for RTC peripheral ========== |
||
1404 | AT91C_RTC_IMR EQU (0xFFFFFE28) ;- (RTC) Interrupt Mask Register |
||
1405 | AT91C_RTC_IER EQU (0xFFFFFE20) ;- (RTC) Interrupt Enable Register |
||
1406 | AT91C_RTC_SR EQU (0xFFFFFE18) ;- (RTC) Status Register |
||
1407 | AT91C_RTC_TIMALR EQU (0xFFFFFE10) ;- (RTC) Time Alarm Register |
||
1408 | AT91C_RTC_TIMR EQU (0xFFFFFE08) ;- (RTC) Time Register |
||
1409 | AT91C_RTC_CR EQU (0xFFFFFE00) ;- (RTC) Control Register |
||
1410 | AT91C_RTC_VER EQU (0xFFFFFE2C) ;- (RTC) Valid Entry Register |
||
1411 | AT91C_RTC_IDR EQU (0xFFFFFE24) ;- (RTC) Interrupt Disable Register |
||
1412 | AT91C_RTC_SCCR EQU (0xFFFFFE1C) ;- (RTC) Status Clear Command Register |
||
1413 | AT91C_RTC_CALALR EQU (0xFFFFFE14) ;- (RTC) Calendar Alarm Register |
||
1414 | AT91C_RTC_CALR EQU (0xFFFFFE0C) ;- (RTC) Calendar Register |
||
1415 | AT91C_RTC_MR EQU (0xFFFFFE04) ;- (RTC) Mode Register |
||
1416 | ;- ========== Register definition for ST peripheral ========== |
||
1417 | AT91C_ST_CRTR EQU (0xFFFFFD24) ;- (ST) Current Real-time Register |
||
1418 | AT91C_ST_IMR EQU (0xFFFFFD1C) ;- (ST) Interrupt Mask Register |
||
1419 | AT91C_ST_IER EQU (0xFFFFFD14) ;- (ST) Interrupt Enable Register |
||
1420 | AT91C_ST_RTMR EQU (0xFFFFFD0C) ;- (ST) Real-time Mode Register |
||
1421 | AT91C_ST_PIMR EQU (0xFFFFFD04) ;- (ST) Period Interval Mode Register |
||
1422 | AT91C_ST_RTAR EQU (0xFFFFFD20) ;- (ST) Real-time Alarm Register |
||
1423 | AT91C_ST_IDR EQU (0xFFFFFD18) ;- (ST) Interrupt Disable Register |
||
1424 | AT91C_ST_SR EQU (0xFFFFFD10) ;- (ST) Status Register |
||
1425 | AT91C_ST_WDMR EQU (0xFFFFFD08) ;- (ST) Watchdog Mode Register |
||
1426 | AT91C_ST_CR EQU (0xFFFFFD00) ;- (ST) Control Register |
||
1427 | ;- ========== Register definition for PMC peripheral ========== |
||
1428 | AT91C_PMC_SCSR EQU (0xFFFFFC08) ;- (PMC) System Clock Status Register |
||
1429 | AT91C_PMC_SCER EQU (0xFFFFFC00) ;- (PMC) System Clock Enable Register |
||
1430 | AT91C_PMC_IMR EQU (0xFFFFFC6C) ;- (PMC) Interrupt Mask Register |
||
1431 | AT91C_PMC_IDR EQU (0xFFFFFC64) ;- (PMC) Interrupt Disable Register |
||
1432 | AT91C_PMC_PCDR EQU (0xFFFFFC14) ;- (PMC) Peripheral Clock Disable Register |
||
1433 | AT91C_PMC_SCDR EQU (0xFFFFFC04) ;- (PMC) System Clock Disable Register |
||
1434 | AT91C_PMC_SR EQU (0xFFFFFC68) ;- (PMC) Status Register |
||
1435 | AT91C_PMC_IER EQU (0xFFFFFC60) ;- (PMC) Interrupt Enable Register |
||
1436 | AT91C_PMC_MCKR EQU (0xFFFFFC30) ;- (PMC) Master Clock Register |
||
1437 | AT91C_PMC_PCER EQU (0xFFFFFC10) ;- (PMC) Peripheral Clock Enable Register |
||
1438 | AT91C_PMC_PCSR EQU (0xFFFFFC18) ;- (PMC) Peripheral Clock Status Register |
||
1439 | AT91C_PMC_PCKR EQU (0xFFFFFC40) ;- (PMC) Programmable Clock Register |
||
1440 | ;- ========== Register definition for CKGR peripheral ========== |
||
1441 | AT91C_CKGR_PLLBR EQU (0xFFFFFC2C) ;- (CKGR) PLL B Register |
||
1442 | AT91C_CKGR_MCFR EQU (0xFFFFFC24) ;- (CKGR) Main Clock Frequency Register |
||
1443 | AT91C_CKGR_PLLAR EQU (0xFFFFFC28) ;- (CKGR) PLL A Register |
||
1444 | AT91C_CKGR_MOR EQU (0xFFFFFC20) ;- (CKGR) Main Oscillator Register |
||
1445 | ;- ========== Register definition for PIOD peripheral ========== |
||
1446 | AT91C_PIOD_PDSR EQU (0xFFFFFA3C) ;- (PIOD) Pin Data Status Register |
||
1447 | AT91C_PIOD_CODR EQU (0xFFFFFA34) ;- (PIOD) Clear Output Data Register |
||
1448 | AT91C_PIOD_OWER EQU (0xFFFFFAA0) ;- (PIOD) Output Write Enable Register |
||
1449 | AT91C_PIOD_MDER EQU (0xFFFFFA50) ;- (PIOD) Multi-driver Enable Register |
||
1450 | AT91C_PIOD_IMR EQU (0xFFFFFA48) ;- (PIOD) Interrupt Mask Register |
||
1451 | AT91C_PIOD_IER EQU (0xFFFFFA40) ;- (PIOD) Interrupt Enable Register |
||
1452 | AT91C_PIOD_ODSR EQU (0xFFFFFA38) ;- (PIOD) Output Data Status Register |
||
1453 | AT91C_PIOD_SODR EQU (0xFFFFFA30) ;- (PIOD) Set Output Data Register |
||
1454 | AT91C_PIOD_PER EQU (0xFFFFFA00) ;- (PIOD) PIO Enable Register |
||
1455 | AT91C_PIOD_OWDR EQU (0xFFFFFAA4) ;- (PIOD) Output Write Disable Register |
||
1456 | AT91C_PIOD_PPUER EQU (0xFFFFFA64) ;- (PIOD) Pull-up Enable Register |
||
1457 | AT91C_PIOD_MDDR EQU (0xFFFFFA54) ;- (PIOD) Multi-driver Disable Register |
||
1458 | AT91C_PIOD_ISR EQU (0xFFFFFA4C) ;- (PIOD) Interrupt Status Register |
||
1459 | AT91C_PIOD_IDR EQU (0xFFFFFA44) ;- (PIOD) Interrupt Disable Register |
||
1460 | AT91C_PIOD_PDR EQU (0xFFFFFA04) ;- (PIOD) PIO Disable Register |
||
1461 | AT91C_PIOD_ODR EQU (0xFFFFFA14) ;- (PIOD) Output Disable Registerr |
||
1462 | AT91C_PIOD_OWSR EQU (0xFFFFFAA8) ;- (PIOD) Output Write Status Register |
||
1463 | AT91C_PIOD_ABSR EQU (0xFFFFFA78) ;- (PIOD) AB Select Status Register |
||
1464 | AT91C_PIOD_ASR EQU (0xFFFFFA70) ;- (PIOD) Select A Register |
||
1465 | AT91C_PIOD_PPUSR EQU (0xFFFFFA68) ;- (PIOD) Pad Pull-up Status Register |
||
1466 | AT91C_PIOD_PPUDR EQU (0xFFFFFA60) ;- (PIOD) Pull-up Disable Register |
||
1467 | AT91C_PIOD_MDSR EQU (0xFFFFFA58) ;- (PIOD) Multi-driver Status Register |
||
1468 | AT91C_PIOD_PSR EQU (0xFFFFFA08) ;- (PIOD) PIO Status Register |
||
1469 | AT91C_PIOD_OER EQU (0xFFFFFA10) ;- (PIOD) Output Enable Register |
||
1470 | AT91C_PIOD_OSR EQU (0xFFFFFA18) ;- (PIOD) Output Status Register |
||
1471 | AT91C_PIOD_IFER EQU (0xFFFFFA20) ;- (PIOD) Input Filter Enable Register |
||
1472 | AT91C_PIOD_BSR EQU (0xFFFFFA74) ;- (PIOD) Select B Register |
||
1473 | AT91C_PIOD_IFDR EQU (0xFFFFFA24) ;- (PIOD) Input Filter Disable Register |
||
1474 | AT91C_PIOD_IFSR EQU (0xFFFFFA28) ;- (PIOD) Input Filter Status Register |
||
1475 | ;- ========== Register definition for PIOC peripheral ========== |
||
1476 | AT91C_PIOC_IFDR EQU (0xFFFFF824) ;- (PIOC) Input Filter Disable Register |
||
1477 | AT91C_PIOC_ODR EQU (0xFFFFF814) ;- (PIOC) Output Disable Registerr |
||
1478 | AT91C_PIOC_ABSR EQU (0xFFFFF878) ;- (PIOC) AB Select Status Register |
||
1479 | AT91C_PIOC_SODR EQU (0xFFFFF830) ;- (PIOC) Set Output Data Register |
||
1480 | AT91C_PIOC_IFSR EQU (0xFFFFF828) ;- (PIOC) Input Filter Status Register |
||
1481 | AT91C_PIOC_CODR EQU (0xFFFFF834) ;- (PIOC) Clear Output Data Register |
||
1482 | AT91C_PIOC_ODSR EQU (0xFFFFF838) ;- (PIOC) Output Data Status Register |
||
1483 | AT91C_PIOC_IER EQU (0xFFFFF840) ;- (PIOC) Interrupt Enable Register |
||
1484 | AT91C_PIOC_IMR EQU (0xFFFFF848) ;- (PIOC) Interrupt Mask Register |
||
1485 | AT91C_PIOC_OWDR EQU (0xFFFFF8A4) ;- (PIOC) Output Write Disable Register |
||
1486 | AT91C_PIOC_MDDR EQU (0xFFFFF854) ;- (PIOC) Multi-driver Disable Register |
||
1487 | AT91C_PIOC_PDSR EQU (0xFFFFF83C) ;- (PIOC) Pin Data Status Register |
||
1488 | AT91C_PIOC_IDR EQU (0xFFFFF844) ;- (PIOC) Interrupt Disable Register |
||
1489 | AT91C_PIOC_ISR EQU (0xFFFFF84C) ;- (PIOC) Interrupt Status Register |
||
1490 | AT91C_PIOC_PDR EQU (0xFFFFF804) ;- (PIOC) PIO Disable Register |
||
1491 | AT91C_PIOC_OWSR EQU (0xFFFFF8A8) ;- (PIOC) Output Write Status Register |
||
1492 | AT91C_PIOC_OWER EQU (0xFFFFF8A0) ;- (PIOC) Output Write Enable Register |
||
1493 | AT91C_PIOC_ASR EQU (0xFFFFF870) ;- (PIOC) Select A Register |
||
1494 | AT91C_PIOC_PPUSR EQU (0xFFFFF868) ;- (PIOC) Pad Pull-up Status Register |
||
1495 | AT91C_PIOC_PPUDR EQU (0xFFFFF860) ;- (PIOC) Pull-up Disable Register |
||
1496 | AT91C_PIOC_MDSR EQU (0xFFFFF858) ;- (PIOC) Multi-driver Status Register |
||
1497 | AT91C_PIOC_MDER EQU (0xFFFFF850) ;- (PIOC) Multi-driver Enable Register |
||
1498 | AT91C_PIOC_IFER EQU (0xFFFFF820) ;- (PIOC) Input Filter Enable Register |
||
1499 | AT91C_PIOC_OSR EQU (0xFFFFF818) ;- (PIOC) Output Status Register |
||
1500 | AT91C_PIOC_OER EQU (0xFFFFF810) ;- (PIOC) Output Enable Register |
||
1501 | AT91C_PIOC_PSR EQU (0xFFFFF808) ;- (PIOC) PIO Status Register |
||
1502 | AT91C_PIOC_PER EQU (0xFFFFF800) ;- (PIOC) PIO Enable Register |
||
1503 | AT91C_PIOC_BSR EQU (0xFFFFF874) ;- (PIOC) Select B Register |
||
1504 | AT91C_PIOC_PPUER EQU (0xFFFFF864) ;- (PIOC) Pull-up Enable Register |
||
1505 | ;- ========== Register definition for PIOB peripheral ========== |
||
1506 | AT91C_PIOB_OWSR EQU (0xFFFFF6A8) ;- (PIOB) Output Write Status Register |
||
1507 | AT91C_PIOB_PPUSR EQU (0xFFFFF668) ;- (PIOB) Pad Pull-up Status Register |
||
1508 | AT91C_PIOB_PPUDR EQU (0xFFFFF660) ;- (PIOB) Pull-up Disable Register |
||
1509 | AT91C_PIOB_MDSR EQU (0xFFFFF658) ;- (PIOB) Multi-driver Status Register |
||
1510 | AT91C_PIOB_MDER EQU (0xFFFFF650) ;- (PIOB) Multi-driver Enable Register |
||
1511 | AT91C_PIOB_IMR EQU (0xFFFFF648) ;- (PIOB) Interrupt Mask Register |
||
1512 | AT91C_PIOB_OSR EQU (0xFFFFF618) ;- (PIOB) Output Status Register |
||
1513 | AT91C_PIOB_OER EQU (0xFFFFF610) ;- (PIOB) Output Enable Register |
||
1514 | AT91C_PIOB_PSR EQU (0xFFFFF608) ;- (PIOB) PIO Status Register |
||
1515 | AT91C_PIOB_PER EQU (0xFFFFF600) ;- (PIOB) PIO Enable Register |
||
1516 | AT91C_PIOB_BSR EQU (0xFFFFF674) ;- (PIOB) Select B Register |
||
1517 | AT91C_PIOB_PPUER EQU (0xFFFFF664) ;- (PIOB) Pull-up Enable Register |
||
1518 | AT91C_PIOB_IFDR EQU (0xFFFFF624) ;- (PIOB) Input Filter Disable Register |
||
1519 | AT91C_PIOB_ODR EQU (0xFFFFF614) ;- (PIOB) Output Disable Registerr |
||
1520 | AT91C_PIOB_ABSR EQU (0xFFFFF678) ;- (PIOB) AB Select Status Register |
||
1521 | AT91C_PIOB_ASR EQU (0xFFFFF670) ;- (PIOB) Select A Register |
||
1522 | AT91C_PIOB_IFER EQU (0xFFFFF620) ;- (PIOB) Input Filter Enable Register |
||
1523 | AT91C_PIOB_IFSR EQU (0xFFFFF628) ;- (PIOB) Input Filter Status Register |
||
1524 | AT91C_PIOB_SODR EQU (0xFFFFF630) ;- (PIOB) Set Output Data Register |
||
1525 | AT91C_PIOB_ODSR EQU (0xFFFFF638) ;- (PIOB) Output Data Status Register |
||
1526 | AT91C_PIOB_CODR EQU (0xFFFFF634) ;- (PIOB) Clear Output Data Register |
||
1527 | AT91C_PIOB_PDSR EQU (0xFFFFF63C) ;- (PIOB) Pin Data Status Register |
||
1528 | AT91C_PIOB_OWER EQU (0xFFFFF6A0) ;- (PIOB) Output Write Enable Register |
||
1529 | AT91C_PIOB_IER EQU (0xFFFFF640) ;- (PIOB) Interrupt Enable Register |
||
1530 | AT91C_PIOB_OWDR EQU (0xFFFFF6A4) ;- (PIOB) Output Write Disable Register |
||
1531 | AT91C_PIOB_MDDR EQU (0xFFFFF654) ;- (PIOB) Multi-driver Disable Register |
||
1532 | AT91C_PIOB_ISR EQU (0xFFFFF64C) ;- (PIOB) Interrupt Status Register |
||
1533 | AT91C_PIOB_IDR EQU (0xFFFFF644) ;- (PIOB) Interrupt Disable Register |
||
1534 | AT91C_PIOB_PDR EQU (0xFFFFF604) ;- (PIOB) PIO Disable Register |
||
1535 | ;- ========== Register definition for PIOA peripheral ========== |
||
1536 | AT91C_PIOA_IMR EQU (0xFFFFF448) ;- (PIOA) Interrupt Mask Register |
||
1537 | AT91C_PIOA_IER EQU (0xFFFFF440) ;- (PIOA) Interrupt Enable Register |
||
1538 | AT91C_PIOA_OWDR EQU (0xFFFFF4A4) ;- (PIOA) Output Write Disable Register |
||
1539 | AT91C_PIOA_ISR EQU (0xFFFFF44C) ;- (PIOA) Interrupt Status Register |
||
1540 | AT91C_PIOA_PPUDR EQU (0xFFFFF460) ;- (PIOA) Pull-up Disable Register |
||
1541 | AT91C_PIOA_MDSR EQU (0xFFFFF458) ;- (PIOA) Multi-driver Status Register |
||
1542 | AT91C_PIOA_MDER EQU (0xFFFFF450) ;- (PIOA) Multi-driver Enable Register |
||
1543 | AT91C_PIOA_PER EQU (0xFFFFF400) ;- (PIOA) PIO Enable Register |
||
1544 | AT91C_PIOA_PSR EQU (0xFFFFF408) ;- (PIOA) PIO Status Register |
||
1545 | AT91C_PIOA_OER EQU (0xFFFFF410) ;- (PIOA) Output Enable Register |
||
1546 | AT91C_PIOA_BSR EQU (0xFFFFF474) ;- (PIOA) Select B Register |
||
1547 | AT91C_PIOA_PPUER EQU (0xFFFFF464) ;- (PIOA) Pull-up Enable Register |
||
1548 | AT91C_PIOA_MDDR EQU (0xFFFFF454) ;- (PIOA) Multi-driver Disable Register |
||
1549 | AT91C_PIOA_PDR EQU (0xFFFFF404) ;- (PIOA) PIO Disable Register |
||
1550 | AT91C_PIOA_ODR EQU (0xFFFFF414) ;- (PIOA) Output Disable Registerr |
||
1551 | AT91C_PIOA_IFDR EQU (0xFFFFF424) ;- (PIOA) Input Filter Disable Register |
||
1552 | AT91C_PIOA_ABSR EQU (0xFFFFF478) ;- (PIOA) AB Select Status Register |
||
1553 | AT91C_PIOA_ASR EQU (0xFFFFF470) ;- (PIOA) Select A Register |
||
1554 | AT91C_PIOA_PPUSR EQU (0xFFFFF468) ;- (PIOA) Pad Pull-up Status Register |
||
1555 | AT91C_PIOA_ODSR EQU (0xFFFFF438) ;- (PIOA) Output Data Status Register |
||
1556 | AT91C_PIOA_SODR EQU (0xFFFFF430) ;- (PIOA) Set Output Data Register |
||
1557 | AT91C_PIOA_IFSR EQU (0xFFFFF428) ;- (PIOA) Input Filter Status Register |
||
1558 | AT91C_PIOA_IFER EQU (0xFFFFF420) ;- (PIOA) Input Filter Enable Register |
||
1559 | AT91C_PIOA_OSR EQU (0xFFFFF418) ;- (PIOA) Output Status Register |
||
1560 | AT91C_PIOA_IDR EQU (0xFFFFF444) ;- (PIOA) Interrupt Disable Register |
||
1561 | AT91C_PIOA_PDSR EQU (0xFFFFF43C) ;- (PIOA) Pin Data Status Register |
||
1562 | AT91C_PIOA_CODR EQU (0xFFFFF434) ;- (PIOA) Clear Output Data Register |
||
1563 | AT91C_PIOA_OWSR EQU (0xFFFFF4A8) ;- (PIOA) Output Write Status Register |
||
1564 | AT91C_PIOA_OWER EQU (0xFFFFF4A0) ;- (PIOA) Output Write Enable Register |
||
1565 | ;- ========== Register definition for DBGU peripheral ========== |
||
1566 | AT91C_DBGU_C2R EQU (0xFFFFF244) ;- (DBGU) Chip ID2 Register |
||
1567 | AT91C_DBGU_THR EQU (0xFFFFF21C) ;- (DBGU) Transmitter Holding Register |
||
1568 | AT91C_DBGU_CSR EQU (0xFFFFF214) ;- (DBGU) Channel Status Register |
||
1569 | AT91C_DBGU_IDR EQU (0xFFFFF20C) ;- (DBGU) Interrupt Disable Register |
||
1570 | AT91C_DBGU_MR EQU (0xFFFFF204) ;- (DBGU) Mode Register |
||
1571 | AT91C_DBGU_FNTR EQU (0xFFFFF248) ;- (DBGU) Force NTRST Register |
||
1572 | AT91C_DBGU_C1R EQU (0xFFFFF240) ;- (DBGU) Chip ID1 Register |
||
1573 | AT91C_DBGU_BRGR EQU (0xFFFFF220) ;- (DBGU) Baud Rate Generator Register |
||
1574 | AT91C_DBGU_RHR EQU (0xFFFFF218) ;- (DBGU) Receiver Holding Register |
||
1575 | AT91C_DBGU_IMR EQU (0xFFFFF210) ;- (DBGU) Interrupt Mask Register |
||
1576 | AT91C_DBGU_IER EQU (0xFFFFF208) ;- (DBGU) Interrupt Enable Register |
||
1577 | AT91C_DBGU_CR EQU (0xFFFFF200) ;- (DBGU) Control Register |
||
1578 | ;- ========== Register definition for PDC_DBGU peripheral ========== |
||
1579 | AT91C_DBGU_TNCR EQU (0xFFFFF31C) ;- (PDC_DBGU) Transmit Next Counter Register |
||
1580 | AT91C_DBGU_RNCR EQU (0xFFFFF314) ;- (PDC_DBGU) Receive Next Counter Register |
||
1581 | AT91C_DBGU_PTCR EQU (0xFFFFF320) ;- (PDC_DBGU) PDC Transfer Control Register |
||
1582 | AT91C_DBGU_PTSR EQU (0xFFFFF324) ;- (PDC_DBGU) PDC Transfer Status Register |
||
1583 | AT91C_DBGU_RCR EQU (0xFFFFF304) ;- (PDC_DBGU) Receive Counter Register |
||
1584 | AT91C_DBGU_TCR EQU (0xFFFFF30C) ;- (PDC_DBGU) Transmit Counter Register |
||
1585 | AT91C_DBGU_RPR EQU (0xFFFFF300) ;- (PDC_DBGU) Receive Pointer Register |
||
1586 | AT91C_DBGU_TPR EQU (0xFFFFF308) ;- (PDC_DBGU) Transmit Pointer Register |
||
1587 | AT91C_DBGU_RNPR EQU (0xFFFFF310) ;- (PDC_DBGU) Receive Next Pointer Register |
||
1588 | AT91C_DBGU_TNPR EQU (0xFFFFF318) ;- (PDC_DBGU) Transmit Next Pointer Register |
||
1589 | ;- ========== Register definition for AIC peripheral ========== |
||
1590 | AT91C_AIC_ICCR EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register |
||
1591 | AT91C_AIC_IECR EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register |
||
1592 | AT91C_AIC_SMR EQU (0xFFFFF000) ;- (AIC) Source Mode Register |
||
1593 | AT91C_AIC_ISCR EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register |
||
1594 | AT91C_AIC_EOICR EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register |
||
1595 | AT91C_AIC_DCR EQU (0xFFFFF138) ;- (AIC) Debug Control Register (Protect) |
||
1596 | AT91C_AIC_FFER EQU (0xFFFFF140) ;- (AIC) Fast Forcing Enable Register |
||
1597 | AT91C_AIC_SVR EQU (0xFFFFF080) ;- (AIC) Source Vector Register |
||
1598 | AT91C_AIC_SPU EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register |
||
1599 | AT91C_AIC_FFDR EQU (0xFFFFF144) ;- (AIC) Fast Forcing Disable Register |
||
1600 | AT91C_AIC_FVR EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register |
||
1601 | AT91C_AIC_FFSR EQU (0xFFFFF148) ;- (AIC) Fast Forcing Status Register |
||
1602 | AT91C_AIC_IMR EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register |
||
1603 | AT91C_AIC_ISR EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register |
||
1604 | AT91C_AIC_IVR EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register |
||
1605 | AT91C_AIC_IDCR EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command Register |
||
1606 | AT91C_AIC_CISR EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register |
||
1607 | AT91C_AIC_IPR EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register |
||
1608 | ;- ========== Register definition for PDC_SPI peripheral ========== |
||
1609 | AT91C_SPI_PTCR EQU (0xFFFE0120) ;- (PDC_SPI) PDC Transfer Control Register |
||
1610 | AT91C_SPI_TNPR EQU (0xFFFE0118) ;- (PDC_SPI) Transmit Next Pointer Register |
||
1611 | AT91C_SPI_RNPR EQU (0xFFFE0110) ;- (PDC_SPI) Receive Next Pointer Register |
||
1612 | AT91C_SPI_TPR EQU (0xFFFE0108) ;- (PDC_SPI) Transmit Pointer Register |
||
1613 | AT91C_SPI_RPR EQU (0xFFFE0100) ;- (PDC_SPI) Receive Pointer Register |
||
1614 | AT91C_SPI_PTSR EQU (0xFFFE0124) ;- (PDC_SPI) PDC Transfer Status Register |
||
1615 | AT91C_SPI_TNCR EQU (0xFFFE011C) ;- (PDC_SPI) Transmit Next Counter Register |
||
1616 | AT91C_SPI_RNCR EQU (0xFFFE0114) ;- (PDC_SPI) Receive Next Counter Register |
||
1617 | AT91C_SPI_TCR EQU (0xFFFE010C) ;- (PDC_SPI) Transmit Counter Register |
||
1618 | AT91C_SPI_RCR EQU (0xFFFE0104) ;- (PDC_SPI) Receive Counter Register |
||
1619 | ;- ========== Register definition for SPI peripheral ========== |
||
1620 | AT91C_SPI_CSR EQU (0xFFFE0030) ;- (SPI) Chip Select Register |
||
1621 | AT91C_SPI_IDR EQU (0xFFFE0018) ;- (SPI) Interrupt Disable Register |
||
1622 | AT91C_SPI_SR EQU (0xFFFE0010) ;- (SPI) Status Register |
||
1623 | AT91C_SPI_RDR EQU (0xFFFE0008) ;- (SPI) Receive Data Register |
||
1624 | AT91C_SPI_CR EQU (0xFFFE0000) ;- (SPI) Control Register |
||
1625 | AT91C_SPI_IMR EQU (0xFFFE001C) ;- (SPI) Interrupt Mask Register |
||
1626 | AT91C_SPI_IER EQU (0xFFFE0014) ;- (SPI) Interrupt Enable Register |
||
1627 | AT91C_SPI_TDR EQU (0xFFFE000C) ;- (SPI) Transmit Data Register |
||
1628 | AT91C_SPI_MR EQU (0xFFFE0004) ;- (SPI) Mode Register |
||
1629 | ;- ========== Register definition for PDC_SSC2 peripheral ========== |
||
1630 | AT91C_SSC2_PTCR EQU (0xFFFD8120) ;- (PDC_SSC2) PDC Transfer Control Register |
||
1631 | AT91C_SSC2_TNPR EQU (0xFFFD8118) ;- (PDC_SSC2) Transmit Next Pointer Register |
||
1632 | AT91C_SSC2_RNPR EQU (0xFFFD8110) ;- (PDC_SSC2) Receive Next Pointer Register |
||
1633 | AT91C_SSC2_TPR EQU (0xFFFD8108) ;- (PDC_SSC2) Transmit Pointer Register |
||
1634 | AT91C_SSC2_RPR EQU (0xFFFD8100) ;- (PDC_SSC2) Receive Pointer Register |
||
1635 | AT91C_SSC2_PTSR EQU (0xFFFD8124) ;- (PDC_SSC2) PDC Transfer Status Register |
||
1636 | AT91C_SSC2_TNCR EQU (0xFFFD811C) ;- (PDC_SSC2) Transmit Next Counter Register |
||
1637 | AT91C_SSC2_RNCR EQU (0xFFFD8114) ;- (PDC_SSC2) Receive Next Counter Register |
||
1638 | AT91C_SSC2_TCR EQU (0xFFFD810C) ;- (PDC_SSC2) Transmit Counter Register |
||
1639 | AT91C_SSC2_RCR EQU (0xFFFD8104) ;- (PDC_SSC2) Receive Counter Register |
||
1640 | ;- ========== Register definition for SSC2 peripheral ========== |
||
1641 | AT91C_SSC2_IMR EQU (0xFFFD804C) ;- (SSC2) Interrupt Mask Register |
||
1642 | AT91C_SSC2_IER EQU (0xFFFD8044) ;- (SSC2) Interrupt Enable Register |
||
1643 | AT91C_SSC2_RC1R EQU (0xFFFD803C) ;- (SSC2) Receive Compare 1 Register |
||
1644 | AT91C_SSC2_TSHR EQU (0xFFFD8034) ;- (SSC2) Transmit Sync Holding Register |
||
1645 | AT91C_SSC2_CMR EQU (0xFFFD8004) ;- (SSC2) Clock Mode Register |
||
1646 | AT91C_SSC2_IDR EQU (0xFFFD8048) ;- (SSC2) Interrupt Disable Register |
||
1647 | AT91C_SSC2_TCMR EQU (0xFFFD8018) ;- (SSC2) Transmit Clock Mode Register |
||
1648 | AT91C_SSC2_RCMR EQU (0xFFFD8010) ;- (SSC2) Receive Clock ModeRegister |
||
1649 | AT91C_SSC2_CR EQU (0xFFFD8000) ;- (SSC2) Control Register |
||
1650 | AT91C_SSC2_RFMR EQU (0xFFFD8014) ;- (SSC2) Receive Frame Mode Register |
||
1651 | AT91C_SSC2_TFMR EQU (0xFFFD801C) ;- (SSC2) Transmit Frame Mode Register |
||
1652 | AT91C_SSC2_THR EQU (0xFFFD8024) ;- (SSC2) Transmit Holding Register |
||
1653 | AT91C_SSC2_SR EQU (0xFFFD8040) ;- (SSC2) Status Register |
||
1654 | AT91C_SSC2_RC0R EQU (0xFFFD8038) ;- (SSC2) Receive Compare 0 Register |
||
1655 | AT91C_SSC2_RSHR EQU (0xFFFD8030) ;- (SSC2) Receive Sync Holding Register |
||
1656 | AT91C_SSC2_RHR EQU (0xFFFD8020) ;- (SSC2) Receive Holding Register |
||
1657 | ;- ========== Register definition for PDC_SSC1 peripheral ========== |
||
1658 | AT91C_SSC1_PTCR EQU (0xFFFD4120) ;- (PDC_SSC1) PDC Transfer Control Register |
||
1659 | AT91C_SSC1_TNPR EQU (0xFFFD4118) ;- (PDC_SSC1) Transmit Next Pointer Register |
||
1660 | AT91C_SSC1_RNPR EQU (0xFFFD4110) ;- (PDC_SSC1) Receive Next Pointer Register |
||
1661 | AT91C_SSC1_TPR EQU (0xFFFD4108) ;- (PDC_SSC1) Transmit Pointer Register |
||
1662 | AT91C_SSC1_RPR EQU (0xFFFD4100) ;- (PDC_SSC1) Receive Pointer Register |
||
1663 | AT91C_SSC1_PTSR EQU (0xFFFD4124) ;- (PDC_SSC1) PDC Transfer Status Register |
||
1664 | AT91C_SSC1_TNCR EQU (0xFFFD411C) ;- (PDC_SSC1) Transmit Next Counter Register |
||
1665 | AT91C_SSC1_RNCR EQU (0xFFFD4114) ;- (PDC_SSC1) Receive Next Counter Register |
||
1666 | AT91C_SSC1_TCR EQU (0xFFFD410C) ;- (PDC_SSC1) Transmit Counter Register |
||
1667 | AT91C_SSC1_RCR EQU (0xFFFD4104) ;- (PDC_SSC1) Receive Counter Register |
||
1668 | ;- ========== Register definition for SSC1 peripheral ========== |
||
1669 | AT91C_SSC1_RFMR EQU (0xFFFD4014) ;- (SSC1) Receive Frame Mode Register |
||
1670 | AT91C_SSC1_CMR EQU (0xFFFD4004) ;- (SSC1) Clock Mode Register |
||
1671 | AT91C_SSC1_IDR EQU (0xFFFD4048) ;- (SSC1) Interrupt Disable Register |
||
1672 | AT91C_SSC1_SR EQU (0xFFFD4040) ;- (SSC1) Status Register |
||
1673 | AT91C_SSC1_RC0R EQU (0xFFFD4038) ;- (SSC1) Receive Compare 0 Register |
||
1674 | AT91C_SSC1_RSHR EQU (0xFFFD4030) ;- (SSC1) Receive Sync Holding Register |
||
1675 | AT91C_SSC1_RHR EQU (0xFFFD4020) ;- (SSC1) Receive Holding Register |
||
1676 | AT91C_SSC1_TCMR EQU (0xFFFD4018) ;- (SSC1) Transmit Clock Mode Register |
||
1677 | AT91C_SSC1_RCMR EQU (0xFFFD4010) ;- (SSC1) Receive Clock ModeRegister |
||
1678 | AT91C_SSC1_CR EQU (0xFFFD4000) ;- (SSC1) Control Register |
||
1679 | AT91C_SSC1_IMR EQU (0xFFFD404C) ;- (SSC1) Interrupt Mask Register |
||
1680 | AT91C_SSC1_IER EQU (0xFFFD4044) ;- (SSC1) Interrupt Enable Register |
||
1681 | AT91C_SSC1_RC1R EQU (0xFFFD403C) ;- (SSC1) Receive Compare 1 Register |
||
1682 | AT91C_SSC1_TSHR EQU (0xFFFD4034) ;- (SSC1) Transmit Sync Holding Register |
||
1683 | AT91C_SSC1_THR EQU (0xFFFD4024) ;- (SSC1) Transmit Holding Register |
||
1684 | AT91C_SSC1_TFMR EQU (0xFFFD401C) ;- (SSC1) Transmit Frame Mode Register |
||
1685 | ;- ========== Register definition for PDC_SSC0 peripheral ========== |
||
1686 | AT91C_SSC0_PTCR EQU (0xFFFD0120) ;- (PDC_SSC0) PDC Transfer Control Register |
||
1687 | AT91C_SSC0_TNPR EQU (0xFFFD0118) ;- (PDC_SSC0) Transmit Next Pointer Register |
||
1688 | AT91C_SSC0_RNPR EQU (0xFFFD0110) ;- (PDC_SSC0) Receive Next Pointer Register |
||
1689 | AT91C_SSC0_TPR EQU (0xFFFD0108) ;- (PDC_SSC0) Transmit Pointer Register |
||
1690 | AT91C_SSC0_RPR EQU (0xFFFD0100) ;- (PDC_SSC0) Receive Pointer Register |
||
1691 | AT91C_SSC0_PTSR EQU (0xFFFD0124) ;- (PDC_SSC0) PDC Transfer Status Register |
||
1692 | AT91C_SSC0_TNCR EQU (0xFFFD011C) ;- (PDC_SSC0) Transmit Next Counter Register |
||
1693 | AT91C_SSC0_RNCR EQU (0xFFFD0114) ;- (PDC_SSC0) Receive Next Counter Register |
||
1694 | AT91C_SSC0_TCR EQU (0xFFFD010C) ;- (PDC_SSC0) Transmit Counter Register |
||
1695 | AT91C_SSC0_RCR EQU (0xFFFD0104) ;- (PDC_SSC0) Receive Counter Register |
||
1696 | ;- ========== Register definition for SSC0 peripheral ========== |
||
1697 | AT91C_SSC0_IMR EQU (0xFFFD004C) ;- (SSC0) Interrupt Mask Register |
||
1698 | AT91C_SSC0_IER EQU (0xFFFD0044) ;- (SSC0) Interrupt Enable Register |
||
1699 | AT91C_SSC0_RC1R EQU (0xFFFD003C) ;- (SSC0) Receive Compare 1 Register |
||
1700 | AT91C_SSC0_TSHR EQU (0xFFFD0034) ;- (SSC0) Transmit Sync Holding Register |
||
1701 | AT91C_SSC0_THR EQU (0xFFFD0024) ;- (SSC0) Transmit Holding Register |
||
1702 | AT91C_SSC0_TFMR EQU (0xFFFD001C) ;- (SSC0) Transmit Frame Mode Register |
||
1703 | AT91C_SSC0_RFMR EQU (0xFFFD0014) ;- (SSC0) Receive Frame Mode Register |
||
1704 | AT91C_SSC0_CMR EQU (0xFFFD0004) ;- (SSC0) Clock Mode Register |
||
1705 | AT91C_SSC0_IDR EQU (0xFFFD0048) ;- (SSC0) Interrupt Disable Register |
||
1706 | AT91C_SSC0_SR EQU (0xFFFD0040) ;- (SSC0) Status Register |
||
1707 | AT91C_SSC0_RC0R EQU (0xFFFD0038) ;- (SSC0) Receive Compare 0 Register |
||
1708 | AT91C_SSC0_RSHR EQU (0xFFFD0030) ;- (SSC0) Receive Sync Holding Register |
||
1709 | AT91C_SSC0_RHR EQU (0xFFFD0020) ;- (SSC0) Receive Holding Register |
||
1710 | AT91C_SSC0_TCMR EQU (0xFFFD0018) ;- (SSC0) Transmit Clock Mode Register |
||
1711 | AT91C_SSC0_RCMR EQU (0xFFFD0010) ;- (SSC0) Receive Clock ModeRegister |
||
1712 | AT91C_SSC0_CR EQU (0xFFFD0000) ;- (SSC0) Control Register |
||
1713 | ;- ========== Register definition for PDC_US3 peripheral ========== |
||
1714 | AT91C_US3_PTSR EQU (0xFFFCC124) ;- (PDC_US3) PDC Transfer Status Register |
||
1715 | AT91C_US3_TNCR EQU (0xFFFCC11C) ;- (PDC_US3) Transmit Next Counter Register |
||
1716 | AT91C_US3_RNCR EQU (0xFFFCC114) ;- (PDC_US3) Receive Next Counter Register |
||
1717 | AT91C_US3_TCR EQU (0xFFFCC10C) ;- (PDC_US3) Transmit Counter Register |
||
1718 | AT91C_US3_RCR EQU (0xFFFCC104) ;- (PDC_US3) Receive Counter Register |
||
1719 | AT91C_US3_PTCR EQU (0xFFFCC120) ;- (PDC_US3) PDC Transfer Control Register |
||
1720 | AT91C_US3_TNPR EQU (0xFFFCC118) ;- (PDC_US3) Transmit Next Pointer Register |
||
1721 | AT91C_US3_RNPR EQU (0xFFFCC110) ;- (PDC_US3) Receive Next Pointer Register |
||
1722 | AT91C_US3_TPR EQU (0xFFFCC108) ;- (PDC_US3) Transmit Pointer Register |
||
1723 | AT91C_US3_RPR EQU (0xFFFCC100) ;- (PDC_US3) Receive Pointer Register |
||
1724 | ;- ========== Register definition for US3 peripheral ========== |
||
1725 | AT91C_US3_IF EQU (0xFFFCC04C) ;- (US3) IRDA_FILTER Register |
||
1726 | AT91C_US3_NER EQU (0xFFFCC044) ;- (US3) Nb Errors Register |
||
1727 | AT91C_US3_RTOR EQU (0xFFFCC024) ;- (US3) Receiver Time-out Register |
||
1728 | AT91C_US3_THR EQU (0xFFFCC01C) ;- (US3) Transmitter Holding Register |
||
1729 | AT91C_US3_CSR EQU (0xFFFCC014) ;- (US3) Channel Status Register |
||
1730 | AT91C_US3_IDR EQU (0xFFFCC00C) ;- (US3) Interrupt Disable Register |
||
1731 | AT91C_US3_MR EQU (0xFFFCC004) ;- (US3) Mode Register |
||
1732 | AT91C_US3_XXR EQU (0xFFFCC048) ;- (US3) XON_XOFF Register |
||
1733 | AT91C_US3_FIDI EQU (0xFFFCC040) ;- (US3) FI_DI_Ratio Register |
||
1734 | AT91C_US3_TTGR EQU (0xFFFCC028) ;- (US3) Transmitter Time-guard Register |
||
1735 | AT91C_US3_BRGR EQU (0xFFFCC020) ;- (US3) Baud Rate Generator Register |
||
1736 | AT91C_US3_RHR EQU (0xFFFCC018) ;- (US3) Receiver Holding Register |
||
1737 | AT91C_US3_IMR EQU (0xFFFCC010) ;- (US3) Interrupt Mask Register |
||
1738 | AT91C_US3_IER EQU (0xFFFCC008) ;- (US3) Interrupt Enable Register |
||
1739 | AT91C_US3_CR EQU (0xFFFCC000) ;- (US3) Control Register |
||
1740 | ;- ========== Register definition for PDC_US2 peripheral ========== |
||
1741 | AT91C_US2_PTSR EQU (0xFFFC8124) ;- (PDC_US2) PDC Transfer Status Register |
||
1742 | AT91C_US2_TNCR EQU (0xFFFC811C) ;- (PDC_US2) Transmit Next Counter Register |
||
1743 | AT91C_US2_RNCR EQU (0xFFFC8114) ;- (PDC_US2) Receive Next Counter Register |
||
1744 | AT91C_US2_TCR EQU (0xFFFC810C) ;- (PDC_US2) Transmit Counter Register |
||
1745 | AT91C_US2_PTCR EQU (0xFFFC8120) ;- (PDC_US2) PDC Transfer Control Register |
||
1746 | AT91C_US2_RCR EQU (0xFFFC8104) ;- (PDC_US2) Receive Counter Register |
||
1747 | AT91C_US2_TNPR EQU (0xFFFC8118) ;- (PDC_US2) Transmit Next Pointer Register |
||
1748 | AT91C_US2_RPR EQU (0xFFFC8100) ;- (PDC_US2) Receive Pointer Register |
||
1749 | AT91C_US2_TPR EQU (0xFFFC8108) ;- (PDC_US2) Transmit Pointer Register |
||
1750 | AT91C_US2_RNPR EQU (0xFFFC8110) ;- (PDC_US2) Receive Next Pointer Register |
||
1751 | ;- ========== Register definition for US2 peripheral ========== |
||
1752 | AT91C_US2_XXR EQU (0xFFFC8048) ;- (US2) XON_XOFF Register |
||
1753 | AT91C_US2_FIDI EQU (0xFFFC8040) ;- (US2) FI_DI_Ratio Register |
||
1754 | AT91C_US2_TTGR EQU (0xFFFC8028) ;- (US2) Transmitter Time-guard Register |
||
1755 | AT91C_US2_BRGR EQU (0xFFFC8020) ;- (US2) Baud Rate Generator Register |
||
1756 | AT91C_US2_RHR EQU (0xFFFC8018) ;- (US2) Receiver Holding Register |
||
1757 | AT91C_US2_IMR EQU (0xFFFC8010) ;- (US2) Interrupt Mask Register |
||
1758 | AT91C_US2_IER EQU (0xFFFC8008) ;- (US2) Interrupt Enable Register |
||
1759 | AT91C_US2_CR EQU (0xFFFC8000) ;- (US2) Control Register |
||
1760 | AT91C_US2_IF EQU (0xFFFC804C) ;- (US2) IRDA_FILTER Register |
||
1761 | AT91C_US2_NER EQU (0xFFFC8044) ;- (US2) Nb Errors Register |
||
1762 | AT91C_US2_RTOR EQU (0xFFFC8024) ;- (US2) Receiver Time-out Register |
||
1763 | AT91C_US2_THR EQU (0xFFFC801C) ;- (US2) Transmitter Holding Register |
||
1764 | AT91C_US2_CSR EQU (0xFFFC8014) ;- (US2) Channel Status Register |
||
1765 | AT91C_US2_IDR EQU (0xFFFC800C) ;- (US2) Interrupt Disable Register |
||
1766 | AT91C_US2_MR EQU (0xFFFC8004) ;- (US2) Mode Register |
||
1767 | ;- ========== Register definition for PDC_US1 peripheral ========== |
||
1768 | AT91C_US1_PTSR EQU (0xFFFC4124) ;- (PDC_US1) PDC Transfer Status Register |
||
1769 | AT91C_US1_TNCR EQU (0xFFFC411C) ;- (PDC_US1) Transmit Next Counter Register |
||
1770 | AT91C_US1_RNCR EQU (0xFFFC4114) ;- (PDC_US1) Receive Next Counter Register |
||
1771 | AT91C_US1_TCR EQU (0xFFFC410C) ;- (PDC_US1) Transmit Counter Register |
||
1772 | AT91C_US1_RCR EQU (0xFFFC4104) ;- (PDC_US1) Receive Counter Register |
||
1773 | AT91C_US1_PTCR EQU (0xFFFC4120) ;- (PDC_US1) PDC Transfer Control Register |
||
1774 | AT91C_US1_TNPR EQU (0xFFFC4118) ;- (PDC_US1) Transmit Next Pointer Register |
||
1775 | AT91C_US1_RNPR EQU (0xFFFC4110) ;- (PDC_US1) Receive Next Pointer Register |
||
1776 | AT91C_US1_TPR EQU (0xFFFC4108) ;- (PDC_US1) Transmit Pointer Register |
||
1777 | AT91C_US1_RPR EQU (0xFFFC4100) ;- (PDC_US1) Receive Pointer Register |
||
1778 | ;- ========== Register definition for US1 peripheral ========== |
||
1779 | AT91C_US1_XXR EQU (0xFFFC4048) ;- (US1) XON_XOFF Register |
||
1780 | AT91C_US1_RHR EQU (0xFFFC4018) ;- (US1) Receiver Holding Register |
||
1781 | AT91C_US1_IMR EQU (0xFFFC4010) ;- (US1) Interrupt Mask Register |
||
1782 | AT91C_US1_IER EQU (0xFFFC4008) ;- (US1) Interrupt Enable Register |
||
1783 | AT91C_US1_CR EQU (0xFFFC4000) ;- (US1) Control Register |
||
1784 | AT91C_US1_RTOR EQU (0xFFFC4024) ;- (US1) Receiver Time-out Register |
||
1785 | AT91C_US1_THR EQU (0xFFFC401C) ;- (US1) Transmitter Holding Register |
||
1786 | AT91C_US1_CSR EQU (0xFFFC4014) ;- (US1) Channel Status Register |
||
1787 | AT91C_US1_IDR EQU (0xFFFC400C) ;- (US1) Interrupt Disable Register |
||
1788 | AT91C_US1_FIDI EQU (0xFFFC4040) ;- (US1) FI_DI_Ratio Register |
||
1789 | AT91C_US1_BRGR EQU (0xFFFC4020) ;- (US1) Baud Rate Generator Register |
||
1790 | AT91C_US1_TTGR EQU (0xFFFC4028) ;- (US1) Transmitter Time-guard Register |
||
1791 | AT91C_US1_IF EQU (0xFFFC404C) ;- (US1) IRDA_FILTER Register |
||
1792 | AT91C_US1_NER EQU (0xFFFC4044) ;- (US1) Nb Errors Register |
||
1793 | AT91C_US1_MR EQU (0xFFFC4004) ;- (US1) Mode Register |
||
1794 | ;- ========== Register definition for PDC_US0 peripheral ========== |
||
1795 | AT91C_US0_PTCR EQU (0xFFFC0120) ;- (PDC_US0) PDC Transfer Control Register |
||
1796 | AT91C_US0_TNPR EQU (0xFFFC0118) ;- (PDC_US0) Transmit Next Pointer Register |
||
1797 | AT91C_US0_RNPR EQU (0xFFFC0110) ;- (PDC_US0) Receive Next Pointer Register |
||
1798 | AT91C_US0_TPR EQU (0xFFFC0108) ;- (PDC_US0) Transmit Pointer Register |
||
1799 | AT91C_US0_RPR EQU (0xFFFC0100) ;- (PDC_US0) Receive Pointer Register |
||
1800 | AT91C_US0_PTSR EQU (0xFFFC0124) ;- (PDC_US0) PDC Transfer Status Register |
||
1801 | AT91C_US0_TNCR EQU (0xFFFC011C) ;- (PDC_US0) Transmit Next Counter Register |
||
1802 | AT91C_US0_RNCR EQU (0xFFFC0114) ;- (PDC_US0) Receive Next Counter Register |
||
1803 | AT91C_US0_TCR EQU (0xFFFC010C) ;- (PDC_US0) Transmit Counter Register |
||
1804 | AT91C_US0_RCR EQU (0xFFFC0104) ;- (PDC_US0) Receive Counter Register |
||
1805 | ;- ========== Register definition for US0 peripheral ========== |
||
1806 | AT91C_US0_TTGR EQU (0xFFFC0028) ;- (US0) Transmitter Time-guard Register |
||
1807 | AT91C_US0_BRGR EQU (0xFFFC0020) ;- (US0) Baud Rate Generator Register |
||
1808 | AT91C_US0_RHR EQU (0xFFFC0018) ;- (US0) Receiver Holding Register |
||
1809 | AT91C_US0_IMR EQU (0xFFFC0010) ;- (US0) Interrupt Mask Register |
||
1810 | AT91C_US0_NER EQU (0xFFFC0044) ;- (US0) Nb Errors Register |
||
1811 | AT91C_US0_RTOR EQU (0xFFFC0024) ;- (US0) Receiver Time-out Register |
||
1812 | AT91C_US0_XXR EQU (0xFFFC0048) ;- (US0) XON_XOFF Register |
||
1813 | AT91C_US0_FIDI EQU (0xFFFC0040) ;- (US0) FI_DI_Ratio Register |
||
1814 | AT91C_US0_CR EQU (0xFFFC0000) ;- (US0) Control Register |
||
1815 | AT91C_US0_IER EQU (0xFFFC0008) ;- (US0) Interrupt Enable Register |
||
1816 | AT91C_US0_IF EQU (0xFFFC004C) ;- (US0) IRDA_FILTER Register |
||
1817 | AT91C_US0_MR EQU (0xFFFC0004) ;- (US0) Mode Register |
||
1818 | AT91C_US0_IDR EQU (0xFFFC000C) ;- (US0) Interrupt Disable Register |
||
1819 | AT91C_US0_CSR EQU (0xFFFC0014) ;- (US0) Channel Status Register |
||
1820 | AT91C_US0_THR EQU (0xFFFC001C) ;- (US0) Transmitter Holding Register |
||
1821 | ;- ========== Register definition for TWI peripheral ========== |
||
1822 | AT91C_TWI_RHR EQU (0xFFFB8030) ;- (TWI) Receive Holding Register |
||
1823 | AT91C_TWI_IDR EQU (0xFFFB8028) ;- (TWI) Interrupt Disable Register |
||
1824 | AT91C_TWI_SR EQU (0xFFFB8020) ;- (TWI) Status Register |
||
1825 | AT91C_TWI_CWGR EQU (0xFFFB8010) ;- (TWI) Clock Waveform Generator Register |
||
1826 | AT91C_TWI_SMR EQU (0xFFFB8008) ;- (TWI) Slave Mode Register |
||
1827 | AT91C_TWI_CR EQU (0xFFFB8000) ;- (TWI) Control Register |
||
1828 | AT91C_TWI_THR EQU (0xFFFB8034) ;- (TWI) Transmit Holding Register |
||
1829 | AT91C_TWI_IMR EQU (0xFFFB802C) ;- (TWI) Interrupt Mask Register |
||
1830 | AT91C_TWI_IER EQU (0xFFFB8024) ;- (TWI) Interrupt Enable Register |
||
1831 | AT91C_TWI_IADR EQU (0xFFFB800C) ;- (TWI) Internal Address Register |
||
1832 | AT91C_TWI_MMR EQU (0xFFFB8004) ;- (TWI) Master Mode Register |
||
1833 | ;- ========== Register definition for PDC_MCI peripheral ========== |
||
1834 | AT91C_MCI_PTCR EQU (0xFFFB4120) ;- (PDC_MCI) PDC Transfer Control Register |
||
1835 | AT91C_MCI_TNPR EQU (0xFFFB4118) ;- (PDC_MCI) Transmit Next Pointer Register |
||
1836 | AT91C_MCI_RNPR EQU (0xFFFB4110) ;- (PDC_MCI) Receive Next Pointer Register |
||
1837 | AT91C_MCI_TPR EQU (0xFFFB4108) ;- (PDC_MCI) Transmit Pointer Register |
||
1838 | AT91C_MCI_RPR EQU (0xFFFB4100) ;- (PDC_MCI) Receive Pointer Register |
||
1839 | AT91C_MCI_PTSR EQU (0xFFFB4124) ;- (PDC_MCI) PDC Transfer Status Register |
||
1840 | AT91C_MCI_TNCR EQU (0xFFFB411C) ;- (PDC_MCI) Transmit Next Counter Register |
||
1841 | AT91C_MCI_RNCR EQU (0xFFFB4114) ;- (PDC_MCI) Receive Next Counter Register |
||
1842 | AT91C_MCI_TCR EQU (0xFFFB410C) ;- (PDC_MCI) Transmit Counter Register |
||
1843 | AT91C_MCI_RCR EQU (0xFFFB4104) ;- (PDC_MCI) Receive Counter Register |
||
1844 | ;- ========== Register definition for MCI peripheral ========== |
||
1845 | AT91C_MCI_IDR EQU (0xFFFB4048) ;- (MCI) MCI Interrupt Disable Register |
||
1846 | AT91C_MCI_SR EQU (0xFFFB4040) ;- (MCI) MCI Status Register |
||
1847 | AT91C_MCI_RDR EQU (0xFFFB4030) ;- (MCI) MCI Receive Data Register |
||
1848 | AT91C_MCI_RSPR EQU (0xFFFB4020) ;- (MCI) MCI Response Register |
||
1849 | AT91C_MCI_ARGR EQU (0xFFFB4010) ;- (MCI) MCI Argument Register |
||
1850 | AT91C_MCI_DTOR EQU (0xFFFB4008) ;- (MCI) MCI Data Timeout Register |
||
1851 | AT91C_MCI_CR EQU (0xFFFB4000) ;- (MCI) MCI Control Register |
||
1852 | AT91C_MCI_IMR EQU (0xFFFB404C) ;- (MCI) MCI Interrupt Mask Register |
||
1853 | AT91C_MCI_IER EQU (0xFFFB4044) ;- (MCI) MCI Interrupt Enable Register |
||
1854 | AT91C_MCI_TDR EQU (0xFFFB4034) ;- (MCI) MCI Transmit Data Register |
||
1855 | AT91C_MCI_CMDR EQU (0xFFFB4014) ;- (MCI) MCI Command Register |
||
1856 | AT91C_MCI_SDCR EQU (0xFFFB400C) ;- (MCI) MCI SD Card Register |
||
1857 | AT91C_MCI_MR EQU (0xFFFB4004) ;- (MCI) MCI Mode Register |
||
1858 | ;- ========== Register definition for UDP peripheral ========== |
||
1859 | AT91C_UDP_ISR EQU (0xFFFB001C) ;- (UDP) Interrupt Status Register |
||
1860 | AT91C_UDP_IDR EQU (0xFFFB0014) ;- (UDP) Interrupt Disable Register |
||
1861 | AT91C_UDP_GLBSTATE EQU (0xFFFB0004) ;- (UDP) Global State Register |
||
1862 | AT91C_UDP_FDR EQU (0xFFFB0050) ;- (UDP) Endpoint FIFO Data Register |
||
1863 | AT91C_UDP_CSR EQU (0xFFFB0030) ;- (UDP) Endpoint Control and Status Register |
||
1864 | AT91C_UDP_RSTEP EQU (0xFFFB0028) ;- (UDP) Reset Endpoint Register |
||
1865 | AT91C_UDP_ICR EQU (0xFFFB0020) ;- (UDP) Interrupt Clear Register |
||
1866 | AT91C_UDP_IMR EQU (0xFFFB0018) ;- (UDP) Interrupt Mask Register |
||
1867 | AT91C_UDP_IER EQU (0xFFFB0010) ;- (UDP) Interrupt Enable Register |
||
1868 | AT91C_UDP_FADDR EQU (0xFFFB0008) ;- (UDP) Function Address Register |
||
1869 | AT91C_UDP_NUM EQU (0xFFFB0000) ;- (UDP) Frame Number Register |
||
1870 | ;- ========== Register definition for TC5 peripheral ========== |
||
1871 | AT91C_TC5_CMR EQU (0xFFFA4084) ;- (TC5) Channel Mode Register |
||
1872 | AT91C_TC5_IDR EQU (0xFFFA40A8) ;- (TC5) Interrupt Disable Register |
||
1873 | AT91C_TC5_SR EQU (0xFFFA40A0) ;- (TC5) Status Register |
||
1874 | AT91C_TC5_RB EQU (0xFFFA4098) ;- (TC5) Register B |
||
1875 | AT91C_TC5_CV EQU (0xFFFA4090) ;- (TC5) Counter Value |
||
1876 | AT91C_TC5_CCR EQU (0xFFFA4080) ;- (TC5) Channel Control Register |
||
1877 | AT91C_TC5_IMR EQU (0xFFFA40AC) ;- (TC5) Interrupt Mask Register |
||
1878 | AT91C_TC5_IER EQU (0xFFFA40A4) ;- (TC5) Interrupt Enable Register |
||
1879 | AT91C_TC5_RC EQU (0xFFFA409C) ;- (TC5) Register C |
||
1880 | AT91C_TC5_RA EQU (0xFFFA4094) ;- (TC5) Register A |
||
1881 | ;- ========== Register definition for TC4 peripheral ========== |
||
1882 | AT91C_TC4_IMR EQU (0xFFFA406C) ;- (TC4) Interrupt Mask Register |
||
1883 | AT91C_TC4_IER EQU (0xFFFA4064) ;- (TC4) Interrupt Enable Register |
||
1884 | AT91C_TC4_RC EQU (0xFFFA405C) ;- (TC4) Register C |
||
1885 | AT91C_TC4_RA EQU (0xFFFA4054) ;- (TC4) Register A |
||
1886 | AT91C_TC4_CMR EQU (0xFFFA4044) ;- (TC4) Channel Mode Register |
||
1887 | AT91C_TC4_IDR EQU (0xFFFA4068) ;- (TC4) Interrupt Disable Register |
||
1888 | AT91C_TC4_SR EQU (0xFFFA4060) ;- (TC4) Status Register |
||
1889 | AT91C_TC4_RB EQU (0xFFFA4058) ;- (TC4) Register B |
||
1890 | AT91C_TC4_CV EQU (0xFFFA4050) ;- (TC4) Counter Value |
||
1891 | AT91C_TC4_CCR EQU (0xFFFA4040) ;- (TC4) Channel Control Register |
||
1892 | ;- ========== Register definition for TC3 peripheral ========== |
||
1893 | AT91C_TC3_IMR EQU (0xFFFA402C) ;- (TC3) Interrupt Mask Register |
||
1894 | AT91C_TC3_CV EQU (0xFFFA4010) ;- (TC3) Counter Value |
||
1895 | AT91C_TC3_CCR EQU (0xFFFA4000) ;- (TC3) Channel Control Register |
||
1896 | AT91C_TC3_IER EQU (0xFFFA4024) ;- (TC3) Interrupt Enable Register |
||
1897 | AT91C_TC3_CMR EQU (0xFFFA4004) ;- (TC3) Channel Mode Register |
||
1898 | AT91C_TC3_RA EQU (0xFFFA4014) ;- (TC3) Register A |
||
1899 | AT91C_TC3_RC EQU (0xFFFA401C) ;- (TC3) Register C |
||
1900 | AT91C_TC3_IDR EQU (0xFFFA4028) ;- (TC3) Interrupt Disable Register |
||
1901 | AT91C_TC3_RB EQU (0xFFFA4018) ;- (TC3) Register B |
||
1902 | AT91C_TC3_SR EQU (0xFFFA4020) ;- (TC3) Status Register |
||
1903 | ;- ========== Register definition for TCB1 peripheral ========== |
||
1904 | AT91C_TCB1_BCR EQU (0xFFFA4140) ;- (TCB1) TC Block Control Register |
||
1905 | AT91C_TCB1_BMR EQU (0xFFFA4144) ;- (TCB1) TC Block Mode Register |
||
1906 | ;- ========== Register definition for TC2 peripheral ========== |
||
1907 | AT91C_TC2_IMR EQU (0xFFFA00AC) ;- (TC2) Interrupt Mask Register |
||
1908 | AT91C_TC2_IER EQU (0xFFFA00A4) ;- (TC2) Interrupt Enable Register |
||
1909 | AT91C_TC2_RC EQU (0xFFFA009C) ;- (TC2) Register C |
||
1910 | AT91C_TC2_RA EQU (0xFFFA0094) ;- (TC2) Register A |
||
1911 | AT91C_TC2_CMR EQU (0xFFFA0084) ;- (TC2) Channel Mode Register |
||
1912 | AT91C_TC2_IDR EQU (0xFFFA00A8) ;- (TC2) Interrupt Disable Register |
||
1913 | AT91C_TC2_SR EQU (0xFFFA00A0) ;- (TC2) Status Register |
||
1914 | AT91C_TC2_RB EQU (0xFFFA0098) ;- (TC2) Register B |
||
1915 | AT91C_TC2_CV EQU (0xFFFA0090) ;- (TC2) Counter Value |
||
1916 | AT91C_TC2_CCR EQU (0xFFFA0080) ;- (TC2) Channel Control Register |
||
1917 | ;- ========== Register definition for TC1 peripheral ========== |
||
1918 | AT91C_TC1_IMR EQU (0xFFFA006C) ;- (TC1) Interrupt Mask Register |
||
1919 | AT91C_TC1_IER EQU (0xFFFA0064) ;- (TC1) Interrupt Enable Register |
||
1920 | AT91C_TC1_RC EQU (0xFFFA005C) ;- (TC1) Register C |
||
1921 | AT91C_TC1_RA EQU (0xFFFA0054) ;- (TC1) Register A |
||
1922 | AT91C_TC1_CMR EQU (0xFFFA0044) ;- (TC1) Channel Mode Register |
||
1923 | AT91C_TC1_IDR EQU (0xFFFA0068) ;- (TC1) Interrupt Disable Register |
||
1924 | AT91C_TC1_SR EQU (0xFFFA0060) ;- (TC1) Status Register |
||
1925 | AT91C_TC1_RB EQU (0xFFFA0058) ;- (TC1) Register B |
||
1926 | AT91C_TC1_CV EQU (0xFFFA0050) ;- (TC1) Counter Value |
||
1927 | AT91C_TC1_CCR EQU (0xFFFA0040) ;- (TC1) Channel Control Register |
||
1928 | ;- ========== Register definition for TC0 peripheral ========== |
||
1929 | AT91C_TC0_IMR EQU (0xFFFA002C) ;- (TC0) Interrupt Mask Register |
||
1930 | AT91C_TC0_IER EQU (0xFFFA0024) ;- (TC0) Interrupt Enable Register |
||
1931 | AT91C_TC0_RC EQU (0xFFFA001C) ;- (TC0) Register C |
||
1932 | AT91C_TC0_RA EQU (0xFFFA0014) ;- (TC0) Register A |
||
1933 | AT91C_TC0_CMR EQU (0xFFFA0004) ;- (TC0) Channel Mode Register |
||
1934 | AT91C_TC0_IDR EQU (0xFFFA0028) ;- (TC0) Interrupt Disable Register |
||
1935 | AT91C_TC0_SR EQU (0xFFFA0020) ;- (TC0) Status Register |
||
1936 | AT91C_TC0_RB EQU (0xFFFA0018) ;- (TC0) Register B |
||
1937 | AT91C_TC0_CV EQU (0xFFFA0010) ;- (TC0) Counter Value |
||
1938 | AT91C_TC0_CCR EQU (0xFFFA0000) ;- (TC0) Channel Control Register |
||
1939 | ;- ========== Register definition for TCB0 peripheral ========== |
||
1940 | AT91C_TCB0_BMR EQU (0xFFFA00C4) ;- (TCB0) TC Block Mode Register |
||
1941 | AT91C_TCB0_BCR EQU (0xFFFA00C0) ;- (TCB0) TC Block Control Register |
||
1942 | ;- ========== Register definition for UHP peripheral ========== |
||
1943 | AT91C_UHP_HcRhDescriptorA EQU (0x00300048) ;- (UHP) Root Hub characteristics A |
||
1944 | AT91C_UHP_HcRhPortStatus EQU (0x00300054) ;- (UHP) Root Hub Port Status Register |
||
1945 | AT91C_UHP_HcRhDescriptorB EQU (0x0030004C) ;- (UHP) Root Hub characteristics B |
||
1946 | AT91C_UHP_HcControl EQU (0x00300004) ;- (UHP) Operating modes for the Host Controller |
||
1947 | AT91C_UHP_HcInterruptStatus EQU (0x0030000C) ;- (UHP) Interrupt Status Register |
||
1948 | AT91C_UHP_HcRhStatus EQU (0x00300050) ;- (UHP) Root Hub Status register |
||
1949 | AT91C_UHP_HcRevision EQU (0x00300000) ;- (UHP) Revision |
||
1950 | AT91C_UHP_HcCommandStatus EQU (0x00300008) ;- (UHP) Command & status Register |
||
1951 | AT91C_UHP_HcInterruptEnable EQU (0x00300010) ;- (UHP) Interrupt Enable Register |
||
1952 | AT91C_UHP_HcHCCA EQU (0x00300018) ;- (UHP) Pointer to the Host Controller Communication Area |
||
1953 | AT91C_UHP_HcControlHeadED EQU (0x00300020) ;- (UHP) First Endpoint Descriptor of the Control list |
||
1954 | AT91C_UHP_HcInterruptDisable EQU (0x00300014) ;- (UHP) Interrupt Disable Register |
||
1955 | AT91C_UHP_HcPeriodCurrentED EQU (0x0030001C) ;- (UHP) Current Isochronous or Interrupt Endpoint Descriptor |
||
1956 | AT91C_UHP_HcControlCurrentED EQU (0x00300024) ;- (UHP) Endpoint Control and Status Register |
||
1957 | AT91C_UHP_HcBulkCurrentED EQU (0x0030002C) ;- (UHP) Current endpoint of the Bulk list |
||
1958 | AT91C_UHP_HcFmInterval EQU (0x00300034) ;- (UHP) Bit time between 2 consecutive SOFs |
||
1959 | AT91C_UHP_HcBulkHeadED EQU (0x00300028) ;- (UHP) First endpoint register of the Bulk list |
||
1960 | AT91C_UHP_HcBulkDoneHead EQU (0x00300030) ;- (UHP) Last completed transfer descriptor |
||
1961 | AT91C_UHP_HcFmRemaining EQU (0x00300038) ;- (UHP) Bit time remaining in the current Frame |
||
1962 | AT91C_UHP_HcPeriodicStart EQU (0x00300040) ;- (UHP) Periodic Start |
||
1963 | AT91C_UHP_HcLSThreshold EQU (0x00300044) ;- (UHP) LS Threshold |
||
1964 | AT91C_UHP_HcFmNumber EQU (0x0030003C) ;- (UHP) Frame number |
||
1965 | ;- ========== Register definition for EMAC peripheral ========== |
||
1966 | AT91C_EMAC_RSR EQU (0xFFFBC020) ;- (EMAC) Receive Status Register |
||
1967 | AT91C_EMAC_MAN EQU (0xFFFBC034) ;- (EMAC) PHY Maintenance Register |
||
1968 | AT91C_EMAC_HSH EQU (0xFFFBC090) ;- (EMAC) Hash Address High[63:32] |
||
1969 | AT91C_EMAC_MCOL EQU (0xFFFBC048) ;- (EMAC) Multiple Collision Frame Register |
||
1970 | AT91C_EMAC_IER EQU (0xFFFBC028) ;- (EMAC) Interrupt Enable Register |
||
1971 | AT91C_EMAC_SA2H EQU (0xFFFBC0A4) ;- (EMAC) Specific Address 2 High, Last 2 bytes |
||
1972 | AT91C_EMAC_HSL EQU (0xFFFBC094) ;- (EMAC) Hash Address Low[31:0] |
||
1973 | AT91C_EMAC_LCOL EQU (0xFFFBC05C) ;- (EMAC) Late Collision Register |
||
1974 | AT91C_EMAC_OK EQU (0xFFFBC04C) ;- (EMAC) Frames Received OK Register |
||
1975 | AT91C_EMAC_CFG EQU (0xFFFBC004) ;- (EMAC) Network Configuration Register |
||
1976 | AT91C_EMAC_SA3L EQU (0xFFFBC0A8) ;- (EMAC) Specific Address 3 Low, First 4 bytes |
||
1977 | AT91C_EMAC_SEQE EQU (0xFFFBC050) ;- (EMAC) Frame Check Sequence Error Register |
||
1978 | AT91C_EMAC_ECOL EQU (0xFFFBC060) ;- (EMAC) Excessive Collision Register |
||
1979 | AT91C_EMAC_ELR EQU (0xFFFBC070) ;- (EMAC) Excessive Length Error Register |
||
1980 | AT91C_EMAC_SR EQU (0xFFFBC008) ;- (EMAC) Network Status Register |
||
1981 | AT91C_EMAC_RBQP EQU (0xFFFBC018) ;- (EMAC) Receive Buffer Queue Pointer |
||
1982 | AT91C_EMAC_CSE EQU (0xFFFBC064) ;- (EMAC) Carrier Sense Error Register |
||
1983 | AT91C_EMAC_RJB EQU (0xFFFBC074) ;- (EMAC) Receive Jabber Register |
||
1984 | AT91C_EMAC_USF EQU (0xFFFBC078) ;- (EMAC) Undersize Frame Register |
||
1985 | AT91C_EMAC_IDR EQU (0xFFFBC02C) ;- (EMAC) Interrupt Disable Register |
||
1986 | AT91C_EMAC_SA1L EQU (0xFFFBC098) ;- (EMAC) Specific Address 1 Low, First 4 bytes |
||
1987 | AT91C_EMAC_IMR EQU (0xFFFBC030) ;- (EMAC) Interrupt Mask Register |
||
1988 | AT91C_EMAC_FRA EQU (0xFFFBC040) ;- (EMAC) Frames Transmitted OK Register |
||
1989 | AT91C_EMAC_SA3H EQU (0xFFFBC0AC) ;- (EMAC) Specific Address 3 High, Last 2 bytes |
||
1990 | AT91C_EMAC_SA1H EQU (0xFFFBC09C) ;- (EMAC) Specific Address 1 High, Last 2 bytes |
||
1991 | AT91C_EMAC_SCOL EQU (0xFFFBC044) ;- (EMAC) Single Collision Frame Register |
||
1992 | AT91C_EMAC_ALE EQU (0xFFFBC054) ;- (EMAC) Alignment Error Register |
||
1993 | AT91C_EMAC_TAR EQU (0xFFFBC00C) ;- (EMAC) Transmit Address Register |
||
1994 | AT91C_EMAC_SA4L EQU (0xFFFBC0B0) ;- (EMAC) Specific Address 4 Low, First 4 bytes |
||
1995 | AT91C_EMAC_SA2L EQU (0xFFFBC0A0) ;- (EMAC) Specific Address 2 Low, First 4 bytes |
||
1996 | AT91C_EMAC_TUE EQU (0xFFFBC068) ;- (EMAC) Transmit Underrun Error Register |
||
1997 | AT91C_EMAC_DTE EQU (0xFFFBC058) ;- (EMAC) Deferred Transmission Frame Register |
||
1998 | AT91C_EMAC_TCR EQU (0xFFFBC010) ;- (EMAC) Transmit Control Register |
||
1999 | AT91C_EMAC_CTL EQU (0xFFFBC000) ;- (EMAC) Network Control Register |
||
2000 | AT91C_EMAC_SA4H EQU (0xFFFBC0B4) ;- (EMAC) Specific Address 4 High, Last 2 bytesr |
||
2001 | AT91C_EMAC_CDE EQU (0xFFFBC06C) ;- (EMAC) Code Error Register |
||
2002 | AT91C_EMAC_SQEE EQU (0xFFFBC07C) ;- (EMAC) SQE Test Error Register |
||
2003 | AT91C_EMAC_TSR EQU (0xFFFBC014) ;- (EMAC) Transmit Status Register |
||
2004 | AT91C_EMAC_DRFC EQU (0xFFFBC080) ;- (EMAC) Discarded RX Frame Register |
||
2005 | ;- ========== Register definition for EBI peripheral ========== |
||
2006 | AT91C_EBI_CFGR EQU (0xFFFFFF64) ;- (EBI) Configuration Register |
||
2007 | AT91C_EBI_CSA EQU (0xFFFFFF60) ;- (EBI) Chip Select Assignment Register |
||
2008 | ;- ========== Register definition for SMC2 peripheral ========== |
||
2009 | AT91C_SMC2_CSR EQU (0xFFFFFF70) ;- (SMC2) SMC2 Chip Select Register |
||
2010 | ;- ========== Register definition for SDRC peripheral ========== |
||
2011 | AT91C_SDRC_IMR EQU (0xFFFFFFAC) ;- (SDRC) SDRAM Controller Interrupt Mask Register |
||
2012 | AT91C_SDRC_IER EQU (0xFFFFFFA4) ;- (SDRC) SDRAM Controller Interrupt Enable Register |
||
2013 | AT91C_SDRC_SRR EQU (0xFFFFFF9C) ;- (SDRC) SDRAM Controller Self Refresh Register |
||
2014 | AT91C_SDRC_TR EQU (0xFFFFFF94) ;- (SDRC) SDRAM Controller Refresh Timer Register |
||
2015 | AT91C_SDRC_ISR EQU (0xFFFFFFB0) ;- (SDRC) SDRAM Controller Interrupt Mask Register |
||
2016 | AT91C_SDRC_IDR EQU (0xFFFFFFA8) ;- (SDRC) SDRAM Controller Interrupt Disable Register |
||
2017 | AT91C_SDRC_LPR EQU (0xFFFFFFA0) ;- (SDRC) SDRAM Controller Low Power Register |
||
2018 | AT91C_SDRC_CR EQU (0xFFFFFF98) ;- (SDRC) SDRAM Controller Configuration Register |
||
2019 | AT91C_SDRC_MR EQU (0xFFFFFF90) ;- (SDRC) SDRAM Controller Mode Register |
||
2020 | ;- ========== Register definition for BFC peripheral ========== |
||
2021 | AT91C_BFC_MR EQU (0xFFFFFFC0) ;- (BFC) BFC Mode Register |
||
2022 | |||
2023 | ;- ***************************************************************************** |
||
2024 | ;- PIO DEFINITIONS FOR AT91RM9200 |
||
2025 | ;- ***************************************************************************** |
||
2026 | AT91C_PIO_PA0 EQU (1:SHL:0) ;- Pin Controlled by PA0 |
||
2027 | AT91C_PA0_MISO EQU (AT91C_PIO_PA0) ;- SPI Master In Slave |
||
2028 | AT91C_PA0_PCK3 EQU (AT91C_PIO_PA0) ;- PMC Programmable Clock Output 3 |
||
2029 | AT91C_PIO_PA1 EQU (1:SHL:1) ;- Pin Controlled by PA1 |
||
2030 | AT91C_PA1_MOSI EQU (AT91C_PIO_PA1) ;- SPI Master Out Slave |
||
2031 | AT91C_PA1_PCK0 EQU (AT91C_PIO_PA1) ;- PMC Programmable Clock Output 0 |
||
2032 | AT91C_PIO_PA10 EQU (1:SHL:10) ;- Pin Controlled by PA10 |
||
2033 | AT91C_PA10_ETX1 EQU (AT91C_PIO_PA10) ;- Ethernet MAC Transmit Data 1 |
||
2034 | AT91C_PA10_MCDB1 EQU (AT91C_PIO_PA10) ;- Multimedia Card B Data 1 |
||
2035 | AT91C_PIO_PA11 EQU (1:SHL:11) ;- Pin Controlled by PA11 |
||
2036 | AT91C_PA11_ECRS_ECRSDV EQU (AT91C_PIO_PA11) ;- Ethernet MAC Carrier Sense/Carrier Sense and Data Valid |
||
2037 | AT91C_PA11_MCDB2 EQU (AT91C_PIO_PA11) ;- Multimedia Card B Data 2 |
||
2038 | AT91C_PIO_PA12 EQU (1:SHL:12) ;- Pin Controlled by PA12 |
||
2039 | AT91C_PA12_ERX0 EQU (AT91C_PIO_PA12) ;- Ethernet MAC Receive Data 0 |
||
2040 | AT91C_PA12_MCDB3 EQU (AT91C_PIO_PA12) ;- Multimedia Card B Data 3 |
||
2041 | AT91C_PIO_PA13 EQU (1:SHL:13) ;- Pin Controlled by PA13 |
||
2042 | AT91C_PA13_ERX1 EQU (AT91C_PIO_PA13) ;- Ethernet MAC Receive Data 1 |
||
2043 | AT91C_PA13_TCLK0 EQU (AT91C_PIO_PA13) ;- Timer Counter 0 external clock input |
||
2044 | AT91C_PIO_PA14 EQU (1:SHL:14) ;- Pin Controlled by PA14 |
||
2045 | AT91C_PA14_ERXER EQU (AT91C_PIO_PA14) ;- Ethernet MAC Receive Error |
||
2046 | AT91C_PA14_TCLK1 EQU (AT91C_PIO_PA14) ;- Timer Counter 1 external clock input |
||
2047 | AT91C_PIO_PA15 EQU (1:SHL:15) ;- Pin Controlled by PA15 |
||
2048 | AT91C_PA15_EMDC EQU (AT91C_PIO_PA15) ;- Ethernet MAC Management Data Clock |
||
2049 | AT91C_PA15_TCLK2 EQU (AT91C_PIO_PA15) ;- Timer Counter 2 external clock input |
||
2050 | AT91C_PIO_PA16 EQU (1:SHL:16) ;- Pin Controlled by PA16 |
||
2051 | AT91C_PA16_EMDIO EQU (AT91C_PIO_PA16) ;- Ethernet MAC Management Data Input/Output |
||
2052 | AT91C_PA16_IRQ6 EQU (AT91C_PIO_PA16) ;- AIC Interrupt input 6 |
||
2053 | AT91C_PIO_PA17 EQU (1:SHL:17) ;- Pin Controlled by PA17 |
||
2054 | AT91C_PA17_TXD0 EQU (AT91C_PIO_PA17) ;- USART 0 Transmit Data |
||
2055 | AT91C_PA17_TIOA0 EQU (AT91C_PIO_PA17) ;- Timer Counter 0 Multipurpose Timer I/O Pin A |
||
2056 | AT91C_PIO_PA18 EQU (1:SHL:18) ;- Pin Controlled by PA18 |
||
2057 | AT91C_PA18_RXD0 EQU (AT91C_PIO_PA18) ;- USART 0 Receive Data |
||
2058 | AT91C_PA18_TIOB0 EQU (AT91C_PIO_PA18) ;- Timer Counter 0 Multipurpose Timer I/O Pin B |
||
2059 | AT91C_PIO_PA19 EQU (1:SHL:19) ;- Pin Controlled by PA19 |
||
2060 | AT91C_PA19_SCK0 EQU (AT91C_PIO_PA19) ;- USART 0 Serial Clock |
||
2061 | AT91C_PA19_TIOA1 EQU (AT91C_PIO_PA19) ;- Timer Counter 1 Multipurpose Timer I/O Pin A |
||
2062 | AT91C_PIO_PA2 EQU (1:SHL:2) ;- Pin Controlled by PA2 |
||
2063 | AT91C_PA2_SPCK EQU (AT91C_PIO_PA2) ;- SPI Serial Clock |
||
2064 | AT91C_PA2_IRQ4 EQU (AT91C_PIO_PA2) ;- AIC Interrupt Input 4 |
||
2065 | AT91C_PIO_PA20 EQU (1:SHL:20) ;- Pin Controlled by PA20 |
||
2066 | AT91C_PA20_CTS0 EQU (AT91C_PIO_PA20) ;- USART 0 Clear To Send |
||
2067 | AT91C_PA20_TIOB1 EQU (AT91C_PIO_PA20) ;- Timer Counter 1 Multipurpose Timer I/O Pin B |
||
2068 | AT91C_PIO_PA21 EQU (1:SHL:21) ;- Pin Controlled by PA21 |
||
2069 | AT91C_PA21_RTS0 EQU (AT91C_PIO_PA21) ;- Usart 0 Ready To Send |
||
2070 | AT91C_PA21_TIOA2 EQU (AT91C_PIO_PA21) ;- Timer Counter 2 Multipurpose Timer I/O Pin A |
||
2071 | AT91C_PIO_PA22 EQU (1:SHL:22) ;- Pin Controlled by PA22 |
||
2072 | AT91C_PA22_RXD2 EQU (AT91C_PIO_PA22) ;- USART 2 Receive Data |
||
2073 | AT91C_PA22_TIOB2 EQU (AT91C_PIO_PA22) ;- Timer Counter 2 Multipurpose Timer I/O Pin B |
||
2074 | AT91C_PIO_PA23 EQU (1:SHL:23) ;- Pin Controlled by PA23 |
||
2075 | AT91C_PA23_TXD2 EQU (AT91C_PIO_PA23) ;- USART 2 Transmit Data |
||
2076 | AT91C_PA23_IRQ3 EQU (AT91C_PIO_PA23) ;- Interrupt input 3 |
||
2077 | AT91C_PIO_PA24 EQU (1:SHL:24) ;- Pin Controlled by PA24 |
||
2078 | AT91C_PA24_SCK2 EQU (AT91C_PIO_PA24) ;- USART2 Serial Clock |
||
2079 | AT91C_PA24_PCK1 EQU (AT91C_PIO_PA24) ;- PMC Programmable Clock Output 1 |
||
2080 | AT91C_PIO_PA25 EQU (1:SHL:25) ;- Pin Controlled by PA25 |
||
2081 | AT91C_PA25_TWD EQU (AT91C_PIO_PA25) ;- TWI Two-wire Serial Data |
||
2082 | AT91C_PA25_IRQ2 EQU (AT91C_PIO_PA25) ;- Interrupt input 2 |
||
2083 | AT91C_PIO_PA26 EQU (1:SHL:26) ;- Pin Controlled by PA26 |
||
2084 | AT91C_PA26_TWCK EQU (AT91C_PIO_PA26) ;- TWI Two-wire Serial Clock |
||
2085 | AT91C_PA26_IRQ1 EQU (AT91C_PIO_PA26) ;- Interrupt input 1 |
||
2086 | AT91C_PIO_PA27 EQU (1:SHL:27) ;- Pin Controlled by PA27 |
||
2087 | AT91C_PA27_MCCK EQU (AT91C_PIO_PA27) ;- Multimedia Card Clock |
||
2088 | AT91C_PA27_TCLK3 EQU (AT91C_PIO_PA27) ;- Timer Counter 3 External Clock Input |
||
2089 | AT91C_PIO_PA28 EQU (1:SHL:28) ;- Pin Controlled by PA28 |
||
2090 | AT91C_PA28_MCCDA EQU (AT91C_PIO_PA28) ;- Multimedia Card A Command |
||
2091 | AT91C_PA28_TCLK4 EQU (AT91C_PIO_PA28) ;- Timer Counter 4 external Clock Input |
||
2092 | AT91C_PIO_PA29 EQU (1:SHL:29) ;- Pin Controlled by PA29 |
||
2093 | AT91C_PA29_MCDA0 EQU (AT91C_PIO_PA29) ;- Multimedia Card A Data 0 |
||
2094 | AT91C_PA29_TCLK5 EQU (AT91C_PIO_PA29) ;- Timer Counter 5 external clock input |
||
2095 | AT91C_PIO_PA3 EQU (1:SHL:3) ;- Pin Controlled by PA3 |
||
2096 | AT91C_PA3_NPCS0 EQU (AT91C_PIO_PA3) ;- SPI Peripheral Chip Select 0 |
||
2097 | AT91C_PA3_IRQ5 EQU (AT91C_PIO_PA3) ;- AIC Interrupt Input 5 |
||
2098 | AT91C_PIO_PA30 EQU (1:SHL:30) ;- Pin Controlled by PA30 |
||
2099 | AT91C_PA30_DRXD EQU (AT91C_PIO_PA30) ;- DBGU Debug Receive Data |
||
2100 | AT91C_PA30_CTS2 EQU (AT91C_PIO_PA30) ;- Usart 2 Clear To Send |
||
2101 | AT91C_PIO_PA31 EQU (1:SHL:31) ;- Pin Controlled by PA31 |
||
2102 | AT91C_PA31_DTXD EQU (AT91C_PIO_PA31) ;- DBGU Debug Transmit Data |
||
2103 | AT91C_PA31_RTS2 EQU (AT91C_PIO_PA31) ;- USART 2 Ready To Send |
||
2104 | AT91C_PIO_PA4 EQU (1:SHL:4) ;- Pin Controlled by PA4 |
||
2105 | AT91C_PA4_NPCS1 EQU (AT91C_PIO_PA4) ;- SPI Peripheral Chip Select 1 |
||
2106 | AT91C_PA4_PCK1 EQU (AT91C_PIO_PA4) ;- PMC Programmable Clock Output 1 |
||
2107 | AT91C_PIO_PA5 EQU (1:SHL:5) ;- Pin Controlled by PA5 |
||
2108 | AT91C_PA5_NPCS2 EQU (AT91C_PIO_PA5) ;- SPI Peripheral Chip Select 2 |
||
2109 | AT91C_PA5_TXD3 EQU (AT91C_PIO_PA5) ;- USART 3 Transmit Data |
||
2110 | AT91C_PIO_PA6 EQU (1:SHL:6) ;- Pin Controlled by PA6 |
||
2111 | AT91C_PA6_NPCS3 EQU (AT91C_PIO_PA6) ;- SPI Peripheral Chip Select 3 |
||
2112 | AT91C_PA6_RXD3 EQU (AT91C_PIO_PA6) ;- USART 3 Receive Data |
||
2113 | AT91C_PIO_PA7 EQU (1:SHL:7) ;- Pin Controlled by PA7 |
||
2114 | AT91C_PA7_ETXCK_EREFCK EQU (AT91C_PIO_PA7) ;- Ethernet MAC Transmit Clock/Reference Clock |
||
2115 | AT91C_PA7_PCK2 EQU (AT91C_PIO_PA7) ;- PMC Programmable Clock 2 |
||
2116 | AT91C_PIO_PA8 EQU (1:SHL:8) ;- Pin Controlled by PA8 |
||
2117 | AT91C_PA8_ETXEN EQU (AT91C_PIO_PA8) ;- Ethernet MAC Transmit Enable |
||
2118 | AT91C_PA8_MCCDB EQU (AT91C_PIO_PA8) ;- Multimedia Card B Command |
||
2119 | AT91C_PIO_PA9 EQU (1:SHL:9) ;- Pin Controlled by PA9 |
||
2120 | AT91C_PA9_ETX0 EQU (AT91C_PIO_PA9) ;- Ethernet MAC Transmit Data 0 |
||
2121 | AT91C_PA9_MCDB0 EQU (AT91C_PIO_PA9) ;- Multimedia Card B Data 0 |
||
2122 | AT91C_PIO_PB0 EQU (1:SHL:0) ;- Pin Controlled by PB0 |
||
2123 | AT91C_PB0_TF0 EQU (AT91C_PIO_PB0) ;- SSC Transmit Frame Sync 0 |
||
2124 | AT91C_PB0_TIOB3 EQU (AT91C_PIO_PB0) ;- Timer Counter 3 Multipurpose Timer I/O Pin B |
||
2125 | AT91C_PIO_PB1 EQU (1:SHL:1) ;- Pin Controlled by PB1 |
||
2126 | AT91C_PB1_TK0 EQU (AT91C_PIO_PB1) ;- SSC Transmit Clock 0 |
||
2127 | AT91C_PB1_CTS3 EQU (AT91C_PIO_PB1) ;- USART 3 Clear To Send |
||
2128 | AT91C_PIO_PB10 EQU (1:SHL:10) ;- Pin Controlled by PB10 |
||
2129 | AT91C_PB10_RK1 EQU (AT91C_PIO_PB10) ;- SSC Receive Clock 1 |
||
2130 | AT91C_PB10_TIOA5 EQU (AT91C_PIO_PB10) ;- Timer Counter 5 Multipurpose Timer I/O Pin A |
||
2131 | AT91C_PIO_PB11 EQU (1:SHL:11) ;- Pin Controlled by PB11 |
||
2132 | AT91C_PB11_RF1 EQU (AT91C_PIO_PB11) ;- SSC Receive Frame Sync 1 |
||
2133 | AT91C_PB11_TIOB5 EQU (AT91C_PIO_PB11) ;- Timer Counter 5 Multipurpose Timer I/O Pin B |
||
2134 | AT91C_PIO_PB12 EQU (1:SHL:12) ;- Pin Controlled by PB12 |
||
2135 | AT91C_PB12_TF2 EQU (AT91C_PIO_PB12) ;- SSC Transmit Frame Sync 2 |
||
2136 | AT91C_PB12_ETX2 EQU (AT91C_PIO_PB12) ;- Ethernet MAC Transmit Data 2 |
||
2137 | AT91C_PIO_PB13 EQU (1:SHL:13) ;- Pin Controlled by PB13 |
||
2138 | AT91C_PB13_TK2 EQU (AT91C_PIO_PB13) ;- SSC Transmit Clock 2 |
||
2139 | AT91C_PB13_ETX3 EQU (AT91C_PIO_PB13) ;- Ethernet MAC Transmit Data 3 |
||
2140 | AT91C_PIO_PB14 EQU (1:SHL:14) ;- Pin Controlled by PB14 |
||
2141 | AT91C_PB14_TD2 EQU (AT91C_PIO_PB14) ;- SSC Transmit Data 2 |
||
2142 | AT91C_PB14_ETXER EQU (AT91C_PIO_PB14) ;- Ethernet MAC Transmikt Coding Error |
||
2143 | AT91C_PIO_PB15 EQU (1:SHL:15) ;- Pin Controlled by PB15 |
||
2144 | AT91C_PB15_RD2 EQU (AT91C_PIO_PB15) ;- SSC Receive Data 2 |
||
2145 | AT91C_PB15_ERX2 EQU (AT91C_PIO_PB15) ;- Ethernet MAC Receive Data 2 |
||
2146 | AT91C_PIO_PB16 EQU (1:SHL:16) ;- Pin Controlled by PB16 |
||
2147 | AT91C_PB16_RK2 EQU (AT91C_PIO_PB16) ;- SSC Receive Clock 2 |
||
2148 | AT91C_PB16_ERX3 EQU (AT91C_PIO_PB16) ;- Ethernet MAC Receive Data 3 |
||
2149 | AT91C_PIO_PB17 EQU (1:SHL:17) ;- Pin Controlled by PB17 |
||
2150 | AT91C_PB17_RF2 EQU (AT91C_PIO_PB17) ;- SSC Receive Frame Sync 2 |
||
2151 | AT91C_PB17_ERXDV EQU (AT91C_PIO_PB17) ;- Ethernet MAC Receive Data Valid |
||
2152 | AT91C_PIO_PB18 EQU (1:SHL:18) ;- Pin Controlled by PB18 |
||
2153 | AT91C_PB18_RI1 EQU (AT91C_PIO_PB18) ;- USART 1 Ring Indicator |
||
2154 | AT91C_PB18_ECOL EQU (AT91C_PIO_PB18) ;- Ethernet MAC Collision Detected |
||
2155 | AT91C_PIO_PB19 EQU (1:SHL:19) ;- Pin Controlled by PB19 |
||
2156 | AT91C_PB19_DTR1 EQU (AT91C_PIO_PB19) ;- USART 1 Data Terminal ready |
||
2157 | AT91C_PB19_ERXCK EQU (AT91C_PIO_PB19) ;- Ethernet MAC Receive Clock |
||
2158 | AT91C_PIO_PB2 EQU (1:SHL:2) ;- Pin Controlled by PB2 |
||
2159 | AT91C_PB2_TD0 EQU (AT91C_PIO_PB2) ;- SSC Transmit data |
||
2160 | AT91C_PB2_SCK3 EQU (AT91C_PIO_PB2) ;- USART 3 Serial Clock |
||
2161 | AT91C_PIO_PB20 EQU (1:SHL:20) ;- Pin Controlled by PB20 |
||
2162 | AT91C_PB20_TXD1 EQU (AT91C_PIO_PB20) ;- USART 1 Transmit Data |
||
2163 | AT91C_PIO_PB21 EQU (1:SHL:21) ;- Pin Controlled by PB21 |
||
2164 | AT91C_PB21_RXD1 EQU (AT91C_PIO_PB21) ;- USART 1 Receive Data |
||
2165 | AT91C_PIO_PB22 EQU (1:SHL:22) ;- Pin Controlled by PB22 |
||
2166 | AT91C_PB22_SCK1 EQU (AT91C_PIO_PB22) ;- USART1 Serial Clock |
||
2167 | AT91C_PIO_PB23 EQU (1:SHL:23) ;- Pin Controlled by PB23 |
||
2168 | AT91C_PB23_DCD1 EQU (AT91C_PIO_PB23) ;- USART 1 Data Carrier Detect |
||
2169 | AT91C_PIO_PB24 EQU (1:SHL:24) ;- Pin Controlled by PB24 |
||
2170 | AT91C_PB24_CTS1 EQU (AT91C_PIO_PB24) ;- USART 1 Clear To Send |
||
2171 | AT91C_PIO_PB25 EQU (1:SHL:25) ;- Pin Controlled by PB25 |
||
2172 | AT91C_PB25_DSR1 EQU (AT91C_PIO_PB25) ;- USART 1 Data Set ready |
||
2173 | AT91C_PB25_EF100 EQU (AT91C_PIO_PB25) ;- Ethernet MAC Force 100 Mbits/sec |
||
2174 | AT91C_PIO_PB26 EQU (1:SHL:26) ;- Pin Controlled by PB26 |
||
2175 | AT91C_PB26_RTS1 EQU (AT91C_PIO_PB26) ;- Usart 0 Ready To Send |
||
2176 | AT91C_PIO_PB27 EQU (1:SHL:27) ;- Pin Controlled by PB27 |
||
2177 | AT91C_PB27_PCK0 EQU (AT91C_PIO_PB27) ;- PMC Programmable Clock Output 0 |
||
2178 | AT91C_PIO_PB28 EQU (1:SHL:28) ;- Pin Controlled by PB28 |
||
2179 | AT91C_PB28_FIQ EQU (AT91C_PIO_PB28) ;- AIC Fast Interrupt Input |
||
2180 | AT91C_PIO_PB29 EQU (1:SHL:29) ;- Pin Controlled by PB29 |
||
2181 | AT91C_PB29_IRQ0 EQU (AT91C_PIO_PB29) ;- Interrupt input 0 |
||
2182 | AT91C_PIO_PB3 EQU (1:SHL:3) ;- Pin Controlled by PB3 |
||
2183 | AT91C_PB3_RD0 EQU (AT91C_PIO_PB3) ;- SSC Receive Data |
||
2184 | AT91C_PB3_MCDA1 EQU (AT91C_PIO_PB3) ;- Multimedia Card A Data 1 |
||
2185 | AT91C_PIO_PB4 EQU (1:SHL:4) ;- Pin Controlled by PB4 |
||
2186 | AT91C_PB4_RK0 EQU (AT91C_PIO_PB4) ;- SSC Receive Clock |
||
2187 | AT91C_PB4_MCDA2 EQU (AT91C_PIO_PB4) ;- Multimedia Card A Data 2 |
||
2188 | AT91C_PIO_PB5 EQU (1:SHL:5) ;- Pin Controlled by PB5 |
||
2189 | AT91C_PB5_RF0 EQU (AT91C_PIO_PB5) ;- SSC Receive Frame Sync 0 |
||
2190 | AT91C_PB5_MCDA3 EQU (AT91C_PIO_PB5) ;- Multimedia Card A Data 3 |
||
2191 | AT91C_PIO_PB6 EQU (1:SHL:6) ;- Pin Controlled by PB6 |
||
2192 | AT91C_PB6_TF1 EQU (AT91C_PIO_PB6) ;- SSC Transmit Frame Sync 1 |
||
2193 | AT91C_PB6_TIOA3 EQU (AT91C_PIO_PB6) ;- Timer Counter 4 Multipurpose Timer I/O Pin A |
||
2194 | AT91C_PIO_PB7 EQU (1:SHL:7) ;- Pin Controlled by PB7 |
||
2195 | AT91C_PB7_TK1 EQU (AT91C_PIO_PB7) ;- SSC Transmit Clock 1 |
||
2196 | AT91C_PB7_TIOB3 EQU (AT91C_PIO_PB7) ;- Timer Counter 3 Multipurpose Timer I/O Pin B |
||
2197 | AT91C_PIO_PB8 EQU (1:SHL:8) ;- Pin Controlled by PB8 |
||
2198 | AT91C_PB8_TD1 EQU (AT91C_PIO_PB8) ;- SSC Transmit Data 1 |
||
2199 | AT91C_PB8_TIOA4 EQU (AT91C_PIO_PB8) ;- Timer Counter 4 Multipurpose Timer I/O Pin A |
||
2200 | AT91C_PIO_PB9 EQU (1:SHL:9) ;- Pin Controlled by PB9 |
||
2201 | AT91C_PB9_RD1 EQU (AT91C_PIO_PB9) ;- SSC Receive Data 1 |
||
2202 | AT91C_PB9_TIOB4 EQU (AT91C_PIO_PB9) ;- Timer Counter 4 Multipurpose Timer I/O Pin B |
||
2203 | AT91C_PIO_PC0 EQU (1:SHL:0) ;- Pin Controlled by PC0 |
||
2204 | AT91C_PC0_BFCK EQU (AT91C_PIO_PC0) ;- Burst Flash Clock |
||
2205 | AT91C_PIO_PC1 EQU (1:SHL:1) ;- Pin Controlled by PC1 |
||
2206 | AT91C_PC1_BFRDY_SMOE EQU (AT91C_PIO_PC1) ;- Burst Flash Ready |
||
2207 | AT91C_PIO_PC10 EQU (1:SHL:10) ;- Pin Controlled by PC10 |
||
2208 | AT91C_PC10_NCS4_CFCS EQU (AT91C_PIO_PC10) ;- Compact Flash Chip Select |
||
2209 | AT91C_PIO_PC11 EQU (1:SHL:11) ;- Pin Controlled by PC11 |
||
2210 | AT91C_PC11_NCS5_CFCE1 EQU (AT91C_PIO_PC11) ;- Chip Select 5 / Compact Flash Chip Enable 1 |
||
2211 | AT91C_PIO_PC12 EQU (1:SHL:12) ;- Pin Controlled by PC12 |
||
2212 | AT91C_PC12_NCS6_CFCE2 EQU (AT91C_PIO_PC12) ;- Chip Select 6 / Compact Flash Chip Enable 2 |
||
2213 | AT91C_PIO_PC13 EQU (1:SHL:13) ;- Pin Controlled by PC13 |
||
2214 | AT91C_PC13_NCS7 EQU (AT91C_PIO_PC13) ;- Chip Select 7 |
||
2215 | AT91C_PIO_PC14 EQU (1:SHL:14) ;- Pin Controlled by PC14 |
||
2216 | AT91C_PIO_PC15 EQU (1:SHL:15) ;- Pin Controlled by PC15 |
||
2217 | AT91C_PIO_PC16 EQU (1:SHL:16) ;- Pin Controlled by PC16 |
||
2218 | AT91C_PC16_D16 EQU (AT91C_PIO_PC16) ;- Data Bus [16] |
||
2219 | AT91C_PIO_PC17 EQU (1:SHL:17) ;- Pin Controlled by PC17 |
||
2220 | AT91C_PC17_D17 EQU (AT91C_PIO_PC17) ;- Data Bus [17] |
||
2221 | AT91C_PIO_PC18 EQU (1:SHL:18) ;- Pin Controlled by PC18 |
||
2222 | AT91C_PC18_D18 EQU (AT91C_PIO_PC18) ;- Data Bus [18] |
||
2223 | AT91C_PIO_PC19 EQU (1:SHL:19) ;- Pin Controlled by PC19 |
||
2224 | AT91C_PC19_D19 EQU (AT91C_PIO_PC19) ;- Data Bus [19] |
||
2225 | AT91C_PIO_PC2 EQU (1:SHL:2) ;- Pin Controlled by PC2 |
||
2226 | AT91C_PC2_BFAVD EQU (AT91C_PIO_PC2) ;- Burst Flash Address Valid |
||
2227 | AT91C_PIO_PC20 EQU (1:SHL:20) ;- Pin Controlled by PC20 |
||
2228 | AT91C_PC20_D20 EQU (AT91C_PIO_PC20) ;- Data Bus [20] |
||
2229 | AT91C_PIO_PC21 EQU (1:SHL:21) ;- Pin Controlled by PC21 |
||
2230 | AT91C_PC21_D21 EQU (AT91C_PIO_PC21) ;- Data Bus [21] |
||
2231 | AT91C_PIO_PC22 EQU (1:SHL:22) ;- Pin Controlled by PC22 |
||
2232 | AT91C_PC22_D22 EQU (AT91C_PIO_PC22) ;- Data Bus [22] |
||
2233 | AT91C_PIO_PC23 EQU (1:SHL:23) ;- Pin Controlled by PC23 |
||
2234 | AT91C_PC23_D23 EQU (AT91C_PIO_PC23) ;- Data Bus [23] |
||
2235 | AT91C_PIO_PC24 EQU (1:SHL:24) ;- Pin Controlled by PC24 |
||
2236 | AT91C_PC24_D24 EQU (AT91C_PIO_PC24) ;- Data Bus [24] |
||
2237 | AT91C_PIO_PC25 EQU (1:SHL:25) ;- Pin Controlled by PC25 |
||
2238 | AT91C_PC25_D25 EQU (AT91C_PIO_PC25) ;- Data Bus [25] |
||
2239 | AT91C_PIO_PC26 EQU (1:SHL:26) ;- Pin Controlled by PC26 |
||
2240 | AT91C_PC26_D26 EQU (AT91C_PIO_PC26) ;- Data Bus [26] |
||
2241 | AT91C_PIO_PC27 EQU (1:SHL:27) ;- Pin Controlled by PC27 |
||
2242 | AT91C_PC27_D27 EQU (AT91C_PIO_PC27) ;- Data Bus [27] |
||
2243 | AT91C_PIO_PC28 EQU (1:SHL:28) ;- Pin Controlled by PC28 |
||
2244 | AT91C_PC28_D28 EQU (AT91C_PIO_PC28) ;- Data Bus [28] |
||
2245 | AT91C_PIO_PC29 EQU (1:SHL:29) ;- Pin Controlled by PC29 |
||
2246 | AT91C_PC29_D29 EQU (AT91C_PIO_PC29) ;- Data Bus [29] |
||
2247 | AT91C_PIO_PC3 EQU (1:SHL:3) ;- Pin Controlled by PC3 |
||
2248 | AT91C_PC3_BFBAA_SMWE EQU (AT91C_PIO_PC3) ;- Burst Flash Address Advance / SmartMedia Write Enable |
||
2249 | AT91C_PIO_PC30 EQU (1:SHL:30) ;- Pin Controlled by PC30 |
||
2250 | AT91C_PC30_D30 EQU (AT91C_PIO_PC30) ;- Data Bus [30] |
||
2251 | AT91C_PIO_PC31 EQU (1:SHL:31) ;- Pin Controlled by PC31 |
||
2252 | AT91C_PC31_D31 EQU (AT91C_PIO_PC31) ;- Data Bus [31] |
||
2253 | AT91C_PIO_PC4 EQU (1:SHL:4) ;- Pin Controlled by PC4 |
||
2254 | AT91C_PC4_BFOE EQU (AT91C_PIO_PC4) ;- Burst Flash Output Enable |
||
2255 | AT91C_PIO_PC5 EQU (1:SHL:5) ;- Pin Controlled by PC5 |
||
2256 | AT91C_PC5_BFWE EQU (AT91C_PIO_PC5) ;- Burst Flash Write Enable |
||
2257 | AT91C_PIO_PC6 EQU (1:SHL:6) ;- Pin Controlled by PC6 |
||
2258 | AT91C_PC6_NWAIT EQU (AT91C_PIO_PC6) ;- NWAIT |
||
2259 | AT91C_PIO_PC7 EQU (1:SHL:7) ;- Pin Controlled by PC7 |
||
2260 | AT91C_PC7_A23 EQU (AT91C_PIO_PC7) ;- Address Bus[23] |
||
2261 | AT91C_PIO_PC8 EQU (1:SHL:8) ;- Pin Controlled by PC8 |
||
2262 | AT91C_PC8_A24 EQU (AT91C_PIO_PC8) ;- Address Bus[24] |
||
2263 | AT91C_PIO_PC9 EQU (1:SHL:9) ;- Pin Controlled by PC9 |
||
2264 | AT91C_PC9_A25_CFRNW EQU (AT91C_PIO_PC9) ;- Address Bus[25] / Compact Flash Read Not Write |
||
2265 | AT91C_PIO_PD0 EQU (1:SHL:0) ;- Pin Controlled by PD0 |
||
2266 | AT91C_PD0_ETX0 EQU (AT91C_PIO_PD0) ;- Ethernet MAC Transmit Data 0 |
||
2267 | AT91C_PIO_PD1 EQU (1:SHL:1) ;- Pin Controlled by PD1 |
||
2268 | AT91C_PD1_ETX1 EQU (AT91C_PIO_PD1) ;- Ethernet MAC Transmit Data 1 |
||
2269 | AT91C_PIO_PD10 EQU (1:SHL:10) ;- Pin Controlled by PD10 |
||
2270 | AT91C_PD10_PCK3 EQU (AT91C_PIO_PD10) ;- PMC Programmable Clock Output 3 |
||
2271 | AT91C_PD10_TPS1 EQU (AT91C_PIO_PD10) ;- ETM ARM9 pipeline status 1 |
||
2272 | AT91C_PIO_PD11 EQU (1:SHL:11) ;- Pin Controlled by PD11 |
||
2273 | AT91C_PD11_ EQU (AT91C_PIO_PD11) ;- |
||
2274 | AT91C_PD11_TPS2 EQU (AT91C_PIO_PD11) ;- ETM ARM9 pipeline status 2 |
||
2275 | AT91C_PIO_PD12 EQU (1:SHL:12) ;- Pin Controlled by PD12 |
||
2276 | AT91C_PD12_ EQU (AT91C_PIO_PD12) ;- |
||
2277 | AT91C_PD12_TPK0 EQU (AT91C_PIO_PD12) ;- ETM Trace Packet 0 |
||
2278 | AT91C_PIO_PD13 EQU (1:SHL:13) ;- Pin Controlled by PD13 |
||
2279 | AT91C_PD13_ EQU (AT91C_PIO_PD13) ;- |
||
2280 | AT91C_PD13_TPK1 EQU (AT91C_PIO_PD13) ;- ETM Trace Packet 1 |
||
2281 | AT91C_PIO_PD14 EQU (1:SHL:14) ;- Pin Controlled by PD14 |
||
2282 | AT91C_PD14_ EQU (AT91C_PIO_PD14) ;- |
||
2283 | AT91C_PD14_TPK2 EQU (AT91C_PIO_PD14) ;- ETM Trace Packet 2 |
||
2284 | AT91C_PIO_PD15 EQU (1:SHL:15) ;- Pin Controlled by PD15 |
||
2285 | AT91C_PD15_TD0 EQU (AT91C_PIO_PD15) ;- SSC Transmit data |
||
2286 | AT91C_PD15_TPK3 EQU (AT91C_PIO_PD15) ;- ETM Trace Packet 3 |
||
2287 | AT91C_PIO_PD16 EQU (1:SHL:16) ;- Pin Controlled by PD16 |
||
2288 | AT91C_PD16_TD1 EQU (AT91C_PIO_PD16) ;- SSC Transmit Data 1 |
||
2289 | AT91C_PD16_TPK4 EQU (AT91C_PIO_PD16) ;- ETM Trace Packet 4 |
||
2290 | AT91C_PIO_PD17 EQU (1:SHL:17) ;- Pin Controlled by PD17 |
||
2291 | AT91C_PD17_TD2 EQU (AT91C_PIO_PD17) ;- SSC Transmit Data 2 |
||
2292 | AT91C_PD17_TPK5 EQU (AT91C_PIO_PD17) ;- ETM Trace Packet 5 |
||
2293 | AT91C_PIO_PD18 EQU (1:SHL:18) ;- Pin Controlled by PD18 |
||
2294 | AT91C_PD18_NPCS1 EQU (AT91C_PIO_PD18) ;- SPI Peripheral Chip Select 1 |
||
2295 | AT91C_PD18_TPK6 EQU (AT91C_PIO_PD18) ;- ETM Trace Packet 6 |
||
2296 | AT91C_PIO_PD19 EQU (1:SHL:19) ;- Pin Controlled by PD19 |
||
2297 | AT91C_PD19_NPCS2 EQU (AT91C_PIO_PD19) ;- SPI Peripheral Chip Select 2 |
||
2298 | AT91C_PD19_TPK7 EQU (AT91C_PIO_PD19) ;- ETM Trace Packet 7 |
||
2299 | AT91C_PIO_PD2 EQU (1:SHL:2) ;- Pin Controlled by PD2 |
||
2300 | AT91C_PD2_ETX2 EQU (AT91C_PIO_PD2) ;- Ethernet MAC Transmit Data 2 |
||
2301 | AT91C_PIO_PD20 EQU (1:SHL:20) ;- Pin Controlled by PD20 |
||
2302 | AT91C_PD20_NPCS3 EQU (AT91C_PIO_PD20) ;- SPI Peripheral Chip Select 3 |
||
2303 | AT91C_PD20_TPK8 EQU (AT91C_PIO_PD20) ;- ETM Trace Packet 8 |
||
2304 | AT91C_PIO_PD21 EQU (1:SHL:21) ;- Pin Controlled by PD21 |
||
2305 | AT91C_PD21_RTS0 EQU (AT91C_PIO_PD21) ;- Usart 0 Ready To Send |
||
2306 | AT91C_PD21_TPK9 EQU (AT91C_PIO_PD21) ;- ETM Trace Packet 9 |
||
2307 | AT91C_PIO_PD22 EQU (1:SHL:22) ;- Pin Controlled by PD22 |
||
2308 | AT91C_PD22_RTS1 EQU (AT91C_PIO_PD22) ;- Usart 0 Ready To Send |
||
2309 | AT91C_PD22_TPK10 EQU (AT91C_PIO_PD22) ;- ETM Trace Packet 10 |
||
2310 | AT91C_PIO_PD23 EQU (1:SHL:23) ;- Pin Controlled by PD23 |
||
2311 | AT91C_PD23_RTS2 EQU (AT91C_PIO_PD23) ;- USART 2 Ready To Send |
||
2312 | AT91C_PD23_TPK11 EQU (AT91C_PIO_PD23) ;- ETM Trace Packet 11 |
||
2313 | AT91C_PIO_PD24 EQU (1:SHL:24) ;- Pin Controlled by PD24 |
||
2314 | AT91C_PD24_RTS3 EQU (AT91C_PIO_PD24) ;- USART 3 Ready To Send |
||
2315 | AT91C_PD24_TPK12 EQU (AT91C_PIO_PD24) ;- ETM Trace Packet 12 |
||
2316 | AT91C_PIO_PD25 EQU (1:SHL:25) ;- Pin Controlled by PD25 |
||
2317 | AT91C_PD25_DTR1 EQU (AT91C_PIO_PD25) ;- USART 1 Data Terminal ready |
||
2318 | AT91C_PD25_TPK13 EQU (AT91C_PIO_PD25) ;- ETM Trace Packet 13 |
||
2319 | AT91C_PIO_PD26 EQU (1:SHL:26) ;- Pin Controlled by PD26 |
||
2320 | AT91C_PD26_TPK14 EQU (AT91C_PIO_PD26) ;- ETM Trace Packet 14 |
||
2321 | AT91C_PIO_PD27 EQU (1:SHL:27) ;- Pin Controlled by PD27 |
||
2322 | AT91C_PD27_TPK15 EQU (AT91C_PIO_PD27) ;- ETM Trace Packet 15 |
||
2323 | AT91C_PIO_PD3 EQU (1:SHL:3) ;- Pin Controlled by PD3 |
||
2324 | AT91C_PD3_ETX3 EQU (AT91C_PIO_PD3) ;- Ethernet MAC Transmit Data 3 |
||
2325 | AT91C_PIO_PD4 EQU (1:SHL:4) ;- Pin Controlled by PD4 |
||
2326 | AT91C_PD4_ETXEN EQU (AT91C_PIO_PD4) ;- Ethernet MAC Transmit Enable |
||
2327 | AT91C_PIO_PD5 EQU (1:SHL:5) ;- Pin Controlled by PD5 |
||
2328 | AT91C_PD5_ETXER EQU (AT91C_PIO_PD5) ;- Ethernet MAC Transmikt Coding Error |
||
2329 | AT91C_PIO_PD6 EQU (1:SHL:6) ;- Pin Controlled by PD6 |
||
2330 | AT91C_PD6_DTXD EQU (AT91C_PIO_PD6) ;- DBGU Debug Transmit Data |
||
2331 | AT91C_PIO_PD7 EQU (1:SHL:7) ;- Pin Controlled by PD7 |
||
2332 | AT91C_PD7_PCK0 EQU (AT91C_PIO_PD7) ;- PMC Programmable Clock Output 0 |
||
2333 | AT91C_PD7_TSYNC EQU (AT91C_PIO_PD7) ;- ETM Synchronization signal |
||
2334 | AT91C_PIO_PD8 EQU (1:SHL:8) ;- Pin Controlled by PD8 |
||
2335 | AT91C_PD8_PCK1 EQU (AT91C_PIO_PD8) ;- PMC Programmable Clock Output 1 |
||
2336 | AT91C_PD8_TCLK EQU (AT91C_PIO_PD8) ;- ETM Trace Clock signal |
||
2337 | AT91C_PIO_PD9 EQU (1:SHL:9) ;- Pin Controlled by PD9 |
||
2338 | AT91C_PD9_PCK2 EQU (AT91C_PIO_PD9) ;- PMC Programmable Clock 2 |
||
2339 | AT91C_PD9_TPS0 EQU (AT91C_PIO_PD9) ;- ETM ARM9 pipeline status 0 |
||
2340 | |||
2341 | ;- ***************************************************************************** |
||
2342 | ;- PERIPHERAL ID DEFINITIONS FOR AT91RM9200 |
||
2343 | ;- ***************************************************************************** |
||
2344 | AT91C_ID_FIQ EQU ( 0) ;- Advanced Interrupt Controller (FIQ) |
||
2345 | AT91C_ID_SYS EQU ( 1) ;- System Peripheral |
||
2346 | AT91C_ID_PIOA EQU ( 2) ;- Parallel IO Controller A |
||
2347 | AT91C_ID_PIOB EQU ( 3) ;- Parallel IO Controller B |
||
2348 | AT91C_ID_PIOC EQU ( 4) ;- Parallel IO Controller C |
||
2349 | AT91C_ID_PIOD EQU ( 5) ;- Parallel IO Controller D |
||
2350 | AT91C_ID_US0 EQU ( 6) ;- USART 0 |
||
2351 | AT91C_ID_US1 EQU ( 7) ;- USART 1 |
||
2352 | AT91C_ID_US2 EQU ( 8) ;- USART 2 |
||
2353 | AT91C_ID_US3 EQU ( 9) ;- USART 3 |
||
2354 | AT91C_ID_MCI EQU (10) ;- Multimedia Card Interface |
||
2355 | AT91C_ID_UDP EQU (11) ;- USB Device Port |
||
2356 | AT91C_ID_TWI EQU (12) ;- Two-Wire Interface |
||
2357 | AT91C_ID_SPI EQU (13) ;- Serial Peripheral Interface |
||
2358 | AT91C_ID_SSC0 EQU (14) ;- Serial Synchronous Controller 0 |
||
2359 | AT91C_ID_SSC1 EQU (15) ;- Serial Synchronous Controller 1 |
||
2360 | AT91C_ID_SSC2 EQU (16) ;- Serial Synchronous Controller 2 |
||
2361 | AT91C_ID_TC0 EQU (17) ;- Timer Counter 0 |
||
2362 | AT91C_ID_TC1 EQU (18) ;- Timer Counter 1 |
||
2363 | AT91C_ID_TC2 EQU (19) ;- Timer Counter 2 |
||
2364 | AT91C_ID_TC3 EQU (20) ;- Timer Counter 3 |
||
2365 | AT91C_ID_TC4 EQU (21) ;- Timer Counter 4 |
||
2366 | AT91C_ID_TC5 EQU (22) ;- Timer Counter 5 |
||
2367 | AT91C_ID_UHP EQU (23) ;- USB Host port |
||
2368 | AT91C_ID_EMAC EQU (24) ;- Ethernet MAC |
||
2369 | AT91C_ID_IRQ0 EQU (25) ;- Advanced Interrupt Controller (IRQ0) |
||
2370 | AT91C_ID_IRQ1 EQU (26) ;- Advanced Interrupt Controller (IRQ1) |
||
2371 | AT91C_ID_IRQ2 EQU (27) ;- Advanced Interrupt Controller (IRQ2) |
||
2372 | AT91C_ID_IRQ3 EQU (28) ;- Advanced Interrupt Controller (IRQ3) |
||
2373 | AT91C_ID_IRQ4 EQU (29) ;- Advanced Interrupt Controller (IRQ4) |
||
2374 | AT91C_ID_IRQ5 EQU (30) ;- Advanced Interrupt Controller (IRQ5) |
||
2375 | AT91C_ID_IRQ6 EQU (31) ;- Advanced Interrupt Controller (IRQ6) |
||
2376 | |||
2377 | ;- ***************************************************************************** |
||
2378 | ;- BASE ADDRESS DEFINITIONS FOR AT91RM9200 |
||
2379 | ;- ***************************************************************************** |
||
2380 | AT91C_BASE_SYS EQU (0xFFFFF000) ;- (SYS) Base Address |
||
2381 | AT91C_BASE_MC EQU (0xFFFFFF00) ;- (MC) Base Address |
||
2382 | AT91C_BASE_RTC EQU (0xFFFFFE00) ;- (RTC) Base Address |
||
2383 | AT91C_BASE_ST EQU (0xFFFFFD00) ;- (ST) Base Address |
||
2384 | AT91C_BASE_PMC EQU (0xFFFFFC00) ;- (PMC) Base Address |
||
2385 | AT91C_BASE_CKGR EQU (0xFFFFFC20) ;- (CKGR) Base Address |
||
2386 | AT91C_BASE_PIOD EQU (0xFFFFFA00) ;- (PIOD) Base Address |
||
2387 | AT91C_BASE_PIOC EQU (0xFFFFF800) ;- (PIOC) Base Address |
||
2388 | AT91C_BASE_PIOB EQU (0xFFFFF600) ;- (PIOB) Base Address |
||
2389 | AT91C_BASE_PIOA EQU (0xFFFFF400) ;- (PIOA) Base Address |
||
2390 | AT91C_BASE_DBGU EQU (0xFFFFF200) ;- (DBGU) Base Address |
||
2391 | AT91C_BASE_PDC_DBGU EQU (0xFFFFF300) ;- (PDC_DBGU) Base Address |
||
2392 | AT91C_BASE_AIC EQU (0xFFFFF000) ;- (AIC) Base Address |
||
2393 | AT91C_BASE_PDC_SPI EQU (0xFFFE0100) ;- (PDC_SPI) Base Address |
||
2394 | AT91C_BASE_SPI EQU (0xFFFE0000) ;- (SPI) Base Address |
||
2395 | AT91C_BASE_PDC_SSC2 EQU (0xFFFD8100) ;- (PDC_SSC2) Base Address |
||
2396 | AT91C_BASE_SSC2 EQU (0xFFFD8000) ;- (SSC2) Base Address |
||
2397 | AT91C_BASE_PDC_SSC1 EQU (0xFFFD4100) ;- (PDC_SSC1) Base Address |
||
2398 | AT91C_BASE_SSC1 EQU (0xFFFD4000) ;- (SSC1) Base Address |
||
2399 | AT91C_BASE_PDC_SSC0 EQU (0xFFFD0100) ;- (PDC_SSC0) Base Address |
||
2400 | AT91C_BASE_SSC0 EQU (0xFFFD0000) ;- (SSC0) Base Address |
||
2401 | AT91C_BASE_PDC_US3 EQU (0xFFFCC100) ;- (PDC_US3) Base Address |
||
2402 | AT91C_BASE_US3 EQU (0xFFFCC000) ;- (US3) Base Address |
||
2403 | AT91C_BASE_PDC_US2 EQU (0xFFFC8100) ;- (PDC_US2) Base Address |
||
2404 | AT91C_BASE_US2 EQU (0xFFFC8000) ;- (US2) Base Address |
||
2405 | AT91C_BASE_PDC_US1 EQU (0xFFFC4100) ;- (PDC_US1) Base Address |
||
2406 | AT91C_BASE_US1 EQU (0xFFFC4000) ;- (US1) Base Address |
||
2407 | AT91C_BASE_PDC_US0 EQU (0xFFFC0100) ;- (PDC_US0) Base Address |
||
2408 | AT91C_BASE_US0 EQU (0xFFFC0000) ;- (US0) Base Address |
||
2409 | AT91C_BASE_TWI EQU (0xFFFB8000) ;- (TWI) Base Address |
||
2410 | AT91C_BASE_PDC_MCI EQU (0xFFFB4100) ;- (PDC_MCI) Base Address |
||
2411 | AT91C_BASE_MCI EQU (0xFFFB4000) ;- (MCI) Base Address |
||
2412 | AT91C_BASE_UDP EQU (0xFFFB0000) ;- (UDP) Base Address |
||
2413 | AT91C_BASE_TC5 EQU (0xFFFA4080) ;- (TC5) Base Address |
||
2414 | AT91C_BASE_TC4 EQU (0xFFFA4040) ;- (TC4) Base Address |
||
2415 | AT91C_BASE_TC3 EQU (0xFFFA4000) ;- (TC3) Base Address |
||
2416 | AT91C_BASE_TCB1 EQU (0xFFFA4080) ;- (TCB1) Base Address |
||
2417 | AT91C_BASE_TC2 EQU (0xFFFA0080) ;- (TC2) Base Address |
||
2418 | AT91C_BASE_TC1 EQU (0xFFFA0040) ;- (TC1) Base Address |
||
2419 | AT91C_BASE_TC0 EQU (0xFFFA0000) ;- (TC0) Base Address |
||
2420 | AT91C_BASE_TCB0 EQU (0xFFFA0000) ;- (TCB0) Base Address |
||
2421 | AT91C_BASE_UHP EQU (0x00300000) ;- (UHP) Base Address |
||
2422 | AT91C_BASE_EMAC EQU (0xFFFBC000) ;- (EMAC) Base Address |
||
2423 | AT91C_BASE_EBI EQU (0xFFFFFF60) ;- (EBI) Base Address |
||
2424 | AT91C_BASE_SMC2 EQU (0xFFFFFF70) ;- (SMC2) Base Address |
||
2425 | AT91C_BASE_SDRC EQU (0xFFFFFF90) ;- (SDRC) Base Address |
||
2426 | AT91C_BASE_BFC EQU (0xFFFFFFC0) ;- (BFC) Base Address |
||
2427 | |||
2428 | ;- ***************************************************************************** |
||
2429 | ;- MEMORY MAPPING DEFINITIONS FOR AT91RM9200 |
||
2430 | ;- ***************************************************************************** |
||
2431 | AT91C_ISRAM EQU (0x00200000) ;- Internal SRAM base address |
||
2432 | AT91C_ISRAM_SIZE EQU (0x00004000) ;- Internal SRAM size in byte (16 Kbyte) |
||
2433 | AT91C_IROM EQU (0x00100000) ;- Internal ROM base address |
||
2434 | AT91C_IROM_SIZE EQU (0x00020000) ;- Internal ROM size in byte (128 Kbyte) |
||
2435 | |||
2436 | |||
2437 | END |