OpenWrt – Blame information for rev 4
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Rev | Author | Line No. | Line |
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4 | office | 1 | /* |
2 | * Atheros AR71xx SoC specific platform data definitions |
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3 | * |
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4 | * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org> |
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5 | * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> |
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6 | * |
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7 | * This program is free software; you can redistribute it and/or modify it |
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8 | * under the terms of the GNU General Public License version 2 as published |
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9 | * by the Free Software Foundation. |
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10 | */ |
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11 | |||
12 | #ifndef __ASM_MACH_ATH79_PLATFORM_H |
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13 | #define __ASM_MACH_ATH79_PLATFORM_H |
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14 | |||
15 | #include <linux/if_ether.h> |
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16 | #include <linux/skbuff.h> |
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17 | #include <linux/phy.h> |
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18 | #include <linux/spi/spi.h> |
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19 | |||
20 | struct ag71xx_switch_platform_data { |
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21 | u8 phy4_mii_en:1; |
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22 | u8 phy_poll_mask; |
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23 | }; |
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24 | |||
25 | struct ag71xx_platform_data { |
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26 | phy_interface_t phy_if_mode; |
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27 | u32 phy_mask; |
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28 | int speed; |
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29 | int duplex; |
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30 | u32 reset_bit; |
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31 | u8 mac_addr[ETH_ALEN]; |
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32 | struct device *mii_bus_dev; |
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33 | |||
34 | u8 has_gbit:1; |
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35 | u8 is_ar91xx:1; |
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36 | u8 is_ar7240:1; |
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37 | u8 is_ar724x:1; |
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38 | u8 has_ar8216:1; |
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39 | u8 use_flow_control:1; |
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40 | u8 disable_inline_checksum_engine:1; |
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41 | |||
42 | struct ag71xx_switch_platform_data *switch_data; |
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43 | |||
44 | void (*ddr_flush)(void); |
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45 | void (*set_speed)(int speed); |
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46 | void (*update_pll)(u32 pll_10, u32 pll_100, u32 pll_1000); |
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47 | |||
48 | unsigned int max_frame_len; |
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49 | unsigned int desc_pktlen_mask; |
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50 | }; |
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51 | |||
52 | struct ag71xx_mdio_platform_data { |
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53 | u32 phy_mask; |
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54 | u8 builtin_switch:1; |
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55 | u8 is_ar7240:1; |
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56 | u8 is_ar9330:1; |
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57 | u8 is_ar934x:1; |
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58 | unsigned long mdio_clock; |
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59 | unsigned long ref_clock; |
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60 | |||
61 | void (*reset)(struct mii_bus *bus); |
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62 | }; |
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63 | |||
64 | #endif /* __ASM_MACH_ATH79_PLATFORM_H */ |