OpenWrt – Blame information for rev 4
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4 | office | 1 | /****************************************************************************** |
2 | ** |
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3 | ** FILE NAME : ifxmips_ptm_amazon_se.c |
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4 | ** PROJECT : UEIP |
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5 | ** MODULES : PTM |
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6 | ** |
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7 | ** DATE : 7 Jul 2009 |
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8 | ** AUTHOR : Xu Liang |
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9 | ** DESCRIPTION : PTM driver common source file (core functions) |
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10 | ** COPYRIGHT : Copyright (c) 2006 |
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11 | ** Infineon Technologies AG |
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12 | ** Am Campeon 1-12, 85579 Neubiberg, Germany |
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13 | ** |
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14 | ** This program is free software; you can redistribute it and/or modify |
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15 | ** it under the terms of the GNU General Public License as published by |
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16 | ** the Free Software Foundation; either version 2 of the License, or |
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17 | ** (at your option) any later version. |
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18 | ** |
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19 | ** HISTORY |
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20 | ** $Date $Author $Comment |
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21 | ** 07 JUL 2009 Xu Liang Init Version |
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22 | *******************************************************************************/ |
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23 | |||
24 | |||
25 | |||
26 | /* |
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27 | * #################################### |
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28 | * Head File |
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29 | * #################################### |
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30 | */ |
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31 | |||
32 | /* |
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33 | * Common Head File |
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34 | */ |
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35 | #include <linux/kernel.h> |
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36 | #include <linux/module.h> |
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37 | #include <linux/version.h> |
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38 | #include <linux/types.h> |
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39 | #include <linux/errno.h> |
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40 | #include <linux/proc_fs.h> |
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41 | #include <linux/init.h> |
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42 | #include <linux/ioctl.h> |
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43 | #include <asm/delay.h> |
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44 | |||
45 | /* |
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46 | * Chip Specific Head File |
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47 | */ |
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48 | #include <asm/ifx/ifx_types.h> |
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49 | #include <asm/ifx/ifx_regs.h> |
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50 | #include <asm/ifx/common_routines.h> |
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51 | #include <asm/ifx/ifx_pmu.h> |
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52 | #include <asm/ifx/ifx_rcu.h> |
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53 | #include "ifxmips_ptm_adsl.h" |
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54 | #include "ifxmips_ptm_fw_amazon_se.h" |
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55 | |||
56 | |||
57 | |||
58 | /* |
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59 | * #################################### |
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60 | * Definition |
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61 | * #################################### |
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62 | */ |
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63 | |||
64 | /* |
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65 | * EMA Settings |
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66 | */ |
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67 | #define EMA_CMD_BUF_LEN 0x0040 |
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68 | #define EMA_CMD_BASE_ADDR (0x00001580 << 2) |
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69 | #define EMA_DATA_BUF_LEN 0x0100 |
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70 | #define EMA_DATA_BASE_ADDR (0x00000B00 << 2) |
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71 | #define EMA_WRITE_BURST 0x2 |
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72 | #define EMA_READ_BURST 0x2 |
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73 | |||
74 | |||
75 | |||
76 | /* |
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77 | * #################################### |
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78 | * Declaration |
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79 | * #################################### |
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80 | */ |
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81 | |||
82 | /* |
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83 | * Hardware Init/Uninit Functions |
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84 | */ |
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85 | static inline void init_pmu(void); |
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86 | static inline void uninit_pmu(void); |
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87 | static inline void reset_ppe(void); |
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88 | static inline void init_ema(void); |
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89 | static inline void init_mailbox(void); |
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90 | static inline void init_atm_tc(void); |
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91 | static inline void clear_share_buffer(void); |
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92 | |||
93 | |||
94 | |||
95 | /* |
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96 | * #################################### |
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97 | * Local Variable |
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98 | * #################################### |
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99 | */ |
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100 | |||
101 | |||
102 | |||
103 | /* |
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104 | * #################################### |
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105 | * Local Function |
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106 | * #################################### |
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107 | */ |
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108 | |||
109 | static inline void init_pmu(void) |
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110 | { |
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111 | //*(unsigned long *)0xBF10201C &= ~((1 << 15) | (1 << 13) | (1 << 9)); |
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112 | //PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE); |
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113 | PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE); |
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114 | PPE_TC_PMU_SETUP(IFX_PMU_ENABLE); |
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115 | PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE); |
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116 | //PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE); |
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117 | PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE); |
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118 | DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE); |
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119 | } |
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120 | |||
121 | static inline void uninit_pmu(void) |
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122 | { |
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123 | PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE); |
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124 | PPE_TC_PMU_SETUP(IFX_PMU_DISABLE); |
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125 | PPE_EMA_PMU_SETUP(IFX_PMU_DISABLE); |
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126 | //PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE); |
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127 | PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE); |
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128 | DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE); |
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129 | //PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE); |
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130 | } |
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131 | |||
132 | static inline void reset_ppe(void) |
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133 | { |
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134 | #ifdef MODULE |
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135 | unsigned int etop_cfg; |
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136 | unsigned int etop_mdio_cfg; |
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137 | unsigned int etop_ig_plen_ctrl; |
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138 | unsigned int enet_mac_cfg; |
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139 | |||
140 | etop_cfg = *IFX_PP32_ETOP_CFG; |
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141 | etop_mdio_cfg = *IFX_PP32_ETOP_MDIO_CFG; |
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142 | etop_ig_plen_ctrl = *IFX_PP32_ETOP_IG_PLEN_CTRL; |
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143 | enet_mac_cfg = *IFX_PP32_ENET_MAC_CFG; |
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144 | |||
145 | *IFX_PP32_ETOP_CFG = (*IFX_PP32_ETOP_CFG & ~0x03C0) | 0x0001; |
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146 | |||
147 | // reset PPE |
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148 | ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_PTM); |
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149 | |||
150 | *IFX_PP32_ETOP_MDIO_CFG = etop_mdio_cfg; |
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151 | *IFX_PP32_ETOP_IG_PLEN_CTRL = etop_ig_plen_ctrl; |
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152 | *IFX_PP32_ENET_MAC_CFG = enet_mac_cfg; |
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153 | *IFX_PP32_ETOP_CFG = etop_cfg; |
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154 | #endif |
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155 | } |
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156 | |||
157 | static inline void init_ema(void) |
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158 | { |
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159 | // Configure share buffer master selection |
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160 | *SB_MST_PRI0 = 1; |
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161 | *SB_MST_PRI1 = 1; |
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162 | |||
163 | // EMA Settings |
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164 | IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG); |
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165 | IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG); |
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166 | IFX_REG_W32(0x000000FF, EMA_IER); |
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167 | IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG); |
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168 | } |
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169 | |||
170 | static inline void init_mailbox(void) |
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171 | { |
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172 | IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC); |
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173 | IFX_REG_W32(0x00000000, MBOX_IGU1_IER); |
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174 | IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC); |
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175 | IFX_REG_W32(0x00000000, MBOX_IGU3_IER); |
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176 | } |
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177 | |||
178 | static inline void init_atm_tc(void) |
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179 | { |
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180 | IFX_REG_W32(0x0F00, DREG_AT_CTRL); |
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181 | IFX_REG_W32(0x3C00, DREG_AR_CTRL); |
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182 | IFX_REG_W32(0x0, DREG_AT_IDLE0); |
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183 | IFX_REG_W32(0x0, DREG_AT_IDLE1); |
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184 | IFX_REG_W32(0x0, DREG_AR_IDLE0); |
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185 | IFX_REG_W32(0x0, DREG_AR_IDLE1); |
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186 | IFX_REG_W32(0x0, RFBI_CFG); |
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187 | IFX_REG_W32(0x0200, SFSM_DBA0); |
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188 | IFX_REG_W32(0x0800, SFSM_DBA1); |
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189 | IFX_REG_W32(0x0321, SFSM_CBA0); |
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190 | IFX_REG_W32(0x0921, SFSM_CBA1); |
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191 | IFX_REG_W32(0x14011, SFSM_CFG0); |
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192 | IFX_REG_W32(0x14011, SFSM_CFG1); |
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193 | IFX_REG_W32(0x0332, FFSM_DBA0); |
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194 | IFX_REG_W32(0x0932, FFSM_DBA1); |
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195 | IFX_REG_W32(0x3000C, FFSM_CFG0); |
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196 | IFX_REG_W32(0x3000C, FFSM_CFG1); |
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197 | IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC0); |
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198 | IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC1); |
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199 | } |
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200 | |||
201 | static inline void clear_share_buffer(void) |
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202 | { |
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203 | volatile u32 *p = SB_RAM0_ADDR(0); |
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204 | unsigned int i; |
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205 | |||
206 | for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN; i++ ) |
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207 | IFX_REG_W32(0, p++); |
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208 | } |
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209 | |||
210 | /* |
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211 | * Description: |
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212 | * Download PPE firmware binary code. |
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213 | * Input: |
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214 | * src --- u32 *, binary code buffer |
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215 | * dword_len --- unsigned int, binary code length in DWORD (32-bit) |
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216 | * Output: |
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217 | * int --- 0: Success |
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218 | * else: Error Code |
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219 | */ |
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220 | static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len) |
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221 | { |
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222 | volatile u32 *dest; |
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223 | |||
224 | if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0 |
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225 | || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 ) |
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226 | return -1; |
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227 | |||
228 | if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) ) |
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229 | IFX_REG_W32(0x00, CDM_CFG); |
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230 | else |
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231 | IFX_REG_W32(0x04, CDM_CFG); |
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232 | |||
233 | /* copy code */ |
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234 | dest = CDM_CODE_MEMORY(0, 0); |
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235 | while ( code_dword_len-- > 0 ) |
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236 | IFX_REG_W32(*code_src++, dest++); |
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237 | |||
238 | /* copy data */ |
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239 | dest = CDM_DATA_MEMORY(0, 0); |
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240 | while ( data_dword_len-- > 0 ) |
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241 | IFX_REG_W32(*data_src++, dest++); |
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242 | |||
243 | return 0; |
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244 | } |
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245 | |||
246 | |||
247 | |||
248 | /* |
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249 | * #################################### |
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250 | * Global Function |
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251 | * #################################### |
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252 | */ |
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253 | |||
254 | extern void ifx_ptm_get_fw_ver(unsigned int *major, unsigned int *minor) |
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255 | { |
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256 | ASSERT(major != NULL, "pointer is NULL"); |
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257 | ASSERT(minor != NULL, "pointer is NULL"); |
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258 | |||
259 | *major = FW_VER_ID->major; |
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260 | *minor = FW_VER_ID->minor; |
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261 | } |
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262 | |||
263 | void ifx_ptm_init_chip(void) |
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264 | { |
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265 | init_pmu(); |
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266 | |||
267 | reset_ppe(); |
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268 | |||
269 | init_ema(); |
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270 | |||
271 | init_mailbox(); |
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272 | |||
273 | init_atm_tc(); |
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274 | |||
275 | clear_share_buffer(); |
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276 | } |
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277 | |||
278 | void ifx_ptm_uninit_chip(void) |
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279 | { |
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280 | uninit_pmu(); |
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281 | } |
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282 | |||
283 | /* |
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284 | * Description: |
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285 | * Initialize and start up PP32. |
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286 | * Input: |
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287 | * none |
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288 | * Output: |
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289 | * int --- 0: Success |
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290 | * else: Error Code |
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291 | */ |
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292 | int ifx_pp32_start(int pp32) |
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293 | { |
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294 | int ret; |
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295 | |||
296 | /* download firmware */ |
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297 | ret = pp32_download_code(firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data)); |
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298 | if ( ret != 0 ) |
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299 | return ret; |
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300 | |||
301 | /* run PP32 */ |
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302 | IFX_REG_W32(DBG_CTRL_RESTART, PP32_DBG_CTRL(pp32)); |
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303 | |||
304 | /* idle for a while to let PP32 init itself */ |
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305 | udelay(10); |
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306 | |||
307 | return 0; |
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308 | } |
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309 | |||
310 | /* |
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311 | * Description: |
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312 | * Halt PP32. |
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313 | * Input: |
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314 | * none |
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315 | * Output: |
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316 | * none |
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317 | */ |
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318 | void ifx_pp32_stop(int pp32) |
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319 | { |
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320 | /* halt PP32 */ |
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321 | IFX_REG_W32(DBG_CTRL_STOP, PP32_DBG_CTRL(pp32)); |
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322 | } |