OpenWrt – Blame information for rev 4
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4 | office | 1 | /****************************************************************************** |
2 | ** |
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3 | ** FILE NAME : ifxmips_deu_vr9.h |
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4 | ** PROJECT : IFX UEIP |
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5 | ** MODULES : DEU Module for VR9 |
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6 | ** |
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7 | ** DATE : September 8, 2009 |
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8 | ** AUTHOR : Mohammad Firdaus |
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9 | ** DESCRIPTION : Data Encryption Unit Driver |
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10 | ** COPYRIGHT : Copyright (c) 2009 |
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11 | ** Infineon Technologies AG |
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12 | ** Am Campeon 1-12, 85579 Neubiberg, Germany |
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13 | ** |
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14 | ** This program is free software; you can redistribute it and/or modify |
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15 | ** it under the terms of the GNU General Public License as published by |
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16 | ** the Free Software Foundation; either version 2 of the License, or |
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17 | ** (at your option) any later version. |
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18 | ** |
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19 | ** HISTORY |
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20 | ** $Date $Author $Comment |
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21 | ** 08,Sept 2009 Mohammad Firdaus Initial UEIP release |
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22 | *******************************************************************************/ |
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23 | /*! |
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24 | \defgroup IFX_DEU IFX_DEU_DRIVERS |
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25 | \ingroup API |
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26 | \brief deu driver module |
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27 | */ |
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28 | |||
29 | /*! |
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30 | \file ifxmips_deu_vr9.h |
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31 | \ingroup IFX_DEU |
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32 | \brief board specific deu driver header file for vr9 |
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33 | */ |
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34 | |||
35 | /*! |
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36 | \defgroup IFX_DEU_DEFINITIONS IFX_DEU_DEFINITIONS |
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37 | \brief deu driver header file |
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38 | */ |
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39 | |||
40 | |||
41 | #ifndef IFXMIPS_DEU_VR9_H |
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42 | #define IFXMIPS_DEU_VR9_H |
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43 | |||
44 | /* Project Header Files */ |
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45 | #include <linux/version.h> |
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46 | #include <linux/module.h> |
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47 | #include <linux/init.h> |
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48 | #include <linux/types.h> |
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49 | #include <linux/errno.h> |
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50 | #include <linux/crypto.h> |
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51 | #include <linux/interrupt.h> |
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52 | #include <linux/delay.h> |
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53 | #include <asm/byteorder.h> |
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54 | #include <crypto/algapi.h> |
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55 | #include <linux/module.h> |
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56 | #include <linux/mm.h> |
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57 | #include <linux/scatterlist.h> |
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58 | #include <linux/skbuff.h> |
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59 | #include <linux/netdevice.h> |
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60 | #include "ifxmips_deu.h" |
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61 | |||
62 | |||
63 | #define AES_INIT 1 |
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64 | #define DES_INIT 2 |
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65 | #define ARC4_INIT 3 |
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66 | #define SHA1_INIT 4 |
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67 | #define MD5_INIT 5 |
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68 | #define SHA1_HMAC_INIT 6 |
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69 | #define MD5_HMAC_INIT 7 |
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70 | |||
71 | #define AES_START IFX_AES_CON |
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72 | #define DES_3DES_START IFX_DES_CON |
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73 | |||
74 | #if 0 |
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75 | #define AES_IDLE 0 |
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76 | #define AES_BUSY 1 |
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77 | #define AES_STARTED 2 |
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78 | #define AES_COMPLETED 3 |
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79 | #define DES_IDLE 0 |
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80 | #define DES_BUSY 1 |
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81 | #define DES_STARTED 2 |
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82 | #define DES_COMPLETED 3 |
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83 | #endif |
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84 | |||
85 | /* SHA1 CONSTANT */ |
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86 | #define HASH_CON_VALUE 0x0701002C |
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87 | |||
88 | #define INPUT_ENDIAN_SWAP(input) input_swap(input) |
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89 | #define DEU_ENDIAN_SWAP(input) endian_swap(input) |
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90 | #define FIND_DEU_CHIP_VERSION chip_version() |
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91 | |||
92 | #if defined (CONFIG_AR10) |
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93 | #define DELAY_PERIOD 30 |
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94 | #else |
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95 | #define DELAY_PERIOD 10 |
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96 | #endif |
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97 | |||
98 | #define WAIT_AES_DMA_READY() \ |
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99 | do { \ |
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100 | int i; \ |
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101 | volatile struct deu_dma_t *dma = (struct deu_dma_t *) IFX_DEU_DMA_CON; \ |
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102 | volatile struct aes_t *aes = (volatile struct aes_t *) AES_START; \ |
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103 | for (i = 0; i < 10; i++) \ |
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104 | udelay(DELAY_PERIOD); \ |
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105 | while (dma->controlr.BSY) {}; \ |
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106 | while (aes->controlr.BUS) {}; \ |
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107 | } while (0) |
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108 | |||
109 | #define WAIT_DES_DMA_READY() \ |
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110 | do { \ |
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111 | int i; \ |
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112 | volatile struct deu_dma_t *dma = (struct deu_dma_t *) IFX_DEU_DMA_CON; \ |
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113 | volatile struct des_t *des = (struct des_t *) DES_3DES_START; \ |
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114 | for (i = 0; i < 10; i++) \ |
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115 | udelay(DELAY_PERIOD); \ |
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116 | while (dma->controlr.BSY) {}; \ |
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117 | while (des->controlr.BUS) {}; \ |
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118 | } while (0) |
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119 | |||
120 | #define AES_DMA_MISC_CONFIG() \ |
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121 | do { \ |
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122 | volatile struct aes_t *aes = (volatile struct aes_t *) AES_START; \ |
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123 | aes->controlr.KRE = 1; \ |
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124 | aes->controlr.GO = 1; \ |
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125 | } while(0) |
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126 | |||
127 | #define SHA_HASH_INIT \ |
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128 | do { \ |
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129 | volatile struct deu_hash_t *hash = (struct deu_hash_t *) HASH_START; \ |
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130 | hash->controlr.ENDI = 1; \ |
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131 | hash->controlr.SM = 1; \ |
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132 | hash->controlr.ALGO = 0; \ |
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133 | hash->controlr.INIT = 1; \ |
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134 | } while(0) |
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135 | |||
136 | #define MD5_HASH_INIT \ |
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137 | do { \ |
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138 | volatile struct deu_hash_t *hash = (struct deu_hash_t *) HASH_START; \ |
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139 | hash->controlr.ENDI = 1; \ |
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140 | hash->controlr.SM = 1; \ |
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141 | hash->controlr.ALGO = 1; \ |
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142 | hash->controlr.INIT = 1; \ |
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143 | } while(0) |
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144 | |||
145 | /* DEU Common Structures for AR9*/ |
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146 | |||
147 | struct clc_controlr_t { |
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148 | u32 Res:26; |
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149 | u32 FSOE:1; |
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150 | u32 SBWE:1; |
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151 | u32 EDIS:1; |
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152 | u32 SPEN:1; |
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153 | u32 DISS:1; |
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154 | u32 DISR:1; |
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155 | |||
156 | }; |
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157 | |||
158 | struct des_t { |
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159 | struct des_controlr { //10h |
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160 | u32 KRE:1; |
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161 | u32 reserved1:5; |
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162 | u32 GO:1; |
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163 | u32 STP:1; |
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164 | u32 Res2:6; |
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165 | u32 NDC:1; |
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166 | u32 ENDI:1; |
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167 | u32 Res3:2; |
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168 | u32 F:3; |
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169 | u32 O:3; |
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170 | u32 BUS:1; |
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171 | u32 DAU:1; |
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172 | u32 ARS:1; |
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173 | u32 SM:1; |
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174 | u32 E_D:1; |
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175 | u32 M:3; |
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176 | |||
177 | } controlr; |
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178 | u32 IHR; //14h |
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179 | u32 ILR; //18h |
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180 | u32 K1HR; //1c |
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181 | u32 K1LR; // |
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182 | u32 K2HR; |
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183 | u32 K2LR; |
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184 | u32 K3HR; |
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185 | u32 K3LR; //30h |
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186 | u32 IVHR; //34h |
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187 | u32 IVLR; //38 |
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188 | u32 OHR; //3c |
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189 | u32 OLR; //40 |
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190 | }; |
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191 | |||
192 | struct aes_t { |
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193 | struct aes_controlr { |
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194 | |||
195 | u32 KRE:1; |
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196 | u32 reserved1:4; |
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197 | u32 PNK:1; |
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198 | u32 GO:1; |
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199 | u32 STP:1; |
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200 | u32 reserved2:6; |
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201 | u32 NDC:1; |
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202 | u32 ENDI:1; |
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203 | u32 reserved3:2; |
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204 | u32 F:3; //fbs |
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205 | u32 O:3; //om |
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206 | u32 BUS:1; //bsy |
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207 | u32 DAU:1; |
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208 | u32 ARS:1; |
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209 | u32 SM:1; |
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210 | u32 E_D:1; |
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211 | u32 KV:1; |
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212 | u32 K:2; //KL |
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213 | |||
214 | } controlr; |
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215 | u32 ID3R; //80h |
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216 | u32 ID2R; //84h |
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217 | u32 ID1R; //88h |
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218 | u32 ID0R; //8Ch |
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219 | u32 K7R; //90h |
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220 | u32 K6R; //94h |
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221 | u32 K5R; //98h |
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222 | u32 K4R; //9Ch |
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223 | u32 K3R; //A0h |
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224 | u32 K2R; //A4h |
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225 | u32 K1R; //A8h |
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226 | u32 K0R; //ACh |
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227 | u32 IV3R; //B0h |
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228 | u32 IV2R; //B4h |
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229 | u32 IV1R; //B8h |
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230 | u32 IV0R; //BCh |
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231 | u32 OD3R; //D4h |
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232 | u32 OD2R; //D8h |
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233 | u32 OD1R; //DCh |
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234 | u32 OD0R; //E0h |
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235 | }; |
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236 | |||
237 | struct arc4_t { |
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238 | struct arc4_controlr { |
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239 | |||
240 | u32 KRE:1; |
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241 | u32 KLEN:4; |
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242 | u32 KSAE:1; |
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243 | u32 GO:1; |
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244 | u32 STP:1; |
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245 | u32 reserved1:6; |
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246 | u32 NDC:1; |
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247 | u32 ENDI:1; |
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248 | u32 reserved2:8; |
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249 | u32 BUS:1; //bsy |
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250 | u32 reserved3:1; |
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251 | u32 ARS:1; |
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252 | u32 SM:1; |
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253 | u32 reserved4:4; |
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254 | |||
255 | } controlr; |
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256 | u32 K3R; //104h |
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257 | u32 K2R; //108h |
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258 | u32 K1R; //10Ch |
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259 | u32 K0R; //110h |
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260 | |||
261 | u32 IDLEN; //114h |
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262 | |||
263 | u32 ID3R; //118h |
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264 | u32 ID2R; //11Ch |
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265 | u32 ID1R; //120h |
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266 | u32 ID0R; //124h |
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267 | |||
268 | u32 OD3R; //128h |
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269 | u32 OD2R; //12Ch |
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270 | u32 OD1R; //130h |
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271 | u32 OD0R; //134h |
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272 | }; |
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273 | |||
274 | struct deu_hash_t { |
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275 | struct hash_controlr { |
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276 | u32 reserved1:5; |
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277 | u32 KHS:1; |
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278 | u32 GO:1; |
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279 | u32 INIT:1; |
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280 | u32 reserved2:6; |
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281 | u32 NDC:1; |
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282 | u32 ENDI:1; |
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283 | u32 reserved3:7; |
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284 | u32 DGRY:1; |
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285 | u32 BSY:1; |
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286 | u32 reserved4:1; |
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287 | u32 IRCL:1; |
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288 | u32 SM:1; |
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289 | u32 KYUE:1; |
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290 | u32 HMEN:1; |
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291 | u32 SSEN:1; |
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292 | u32 ALGO:1; |
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293 | |||
294 | } controlr; |
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295 | u32 MR; //B4h |
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296 | u32 D1R; //B8h |
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297 | u32 D2R; //BCh |
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298 | u32 D3R; //C0h |
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299 | u32 D4R; //C4h |
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300 | u32 D5R; //C8h |
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301 | |||
302 | u32 dummy; //CCh |
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303 | |||
304 | u32 KIDX; //D0h |
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305 | u32 KEY; //D4h |
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306 | u32 DBN; //D8h |
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307 | }; |
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308 | |||
309 | |||
310 | struct deu_dma_t { |
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311 | struct dma_controlr { |
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312 | u32 reserved1:22; |
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313 | u32 BS:2; |
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314 | u32 BSY:1; |
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315 | u32 reserved2:1; |
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316 | u32 ALGO:2; |
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317 | u32 RXCLS:2; |
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318 | u32 reserved3:1; |
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319 | u32 EN:1; |
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320 | |||
321 | } controlr; |
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322 | }; |
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323 | |||
324 | #endif /* IFXMIPS_DEU_VR9_H */ |