OpenWrt – Blame information for rev 4
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4 | office | 1 | /****************************************************************************** |
2 | ** |
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3 | ** FILE NAME : ifxmips_atm_danube.c |
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4 | ** PROJECT : UEIP |
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5 | ** MODULES : ATM |
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6 | ** |
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7 | ** DATE : 7 Jul 2009 |
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8 | ** AUTHOR : Xu Liang |
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9 | ** DESCRIPTION : ATM driver common source file (core functions) |
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10 | ** COPYRIGHT : Copyright (c) 2006 |
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11 | ** Infineon Technologies AG |
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12 | ** Am Campeon 1-12, 85579 Neubiberg, Germany |
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13 | ** |
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14 | ** This program is free software; you can redistribute it and/or modify |
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15 | ** it under the terms of the GNU General Public License as published by |
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16 | ** the Free Software Foundation; either version 2 of the License, or |
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17 | ** (at your option) any later version. |
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18 | ** |
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19 | ** HISTORY |
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20 | ** $Date $Author $Comment |
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21 | ** 07 JUL 2009 Xu Liang Init Version |
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22 | *******************************************************************************/ |
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23 | |||
24 | |||
25 | |||
26 | /* |
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27 | * #################################### |
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28 | * Head File |
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29 | * #################################### |
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30 | */ |
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31 | |||
32 | /* |
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33 | * Common Head File |
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34 | */ |
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35 | #include <linux/kernel.h> |
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36 | #include <linux/module.h> |
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37 | #include <linux/version.h> |
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38 | #include <linux/types.h> |
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39 | #include <linux/errno.h> |
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40 | #include <linux/proc_fs.h> |
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41 | #include <linux/init.h> |
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42 | #include <linux/ioctl.h> |
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43 | #include <linux/delay.h> |
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44 | |||
45 | /* |
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46 | * Chip Specific Head File |
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47 | */ |
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48 | #include "ifxmips_atm_core.h" |
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49 | |||
50 | #ifdef CONFIG_DANUBE |
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51 | |||
52 | #include "ifxmips_atm_fw_danube.h" |
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53 | #include "ifxmips_atm_fw_regs_danube.h" |
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54 | |||
55 | #include <lantiq_soc.h> |
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56 | |||
57 | #define EMA_CMD_BUF_LEN 0x0040 |
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58 | #define EMA_CMD_BASE_ADDR (0x00001580 << 2) |
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59 | #define EMA_DATA_BUF_LEN 0x0100 |
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60 | #define EMA_DATA_BASE_ADDR (0x00001900 << 2) |
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61 | #define EMA_WRITE_BURST 0x2 |
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62 | #define EMA_READ_BURST 0x2 |
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63 | |||
64 | static inline void reset_ppe(void); |
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65 | |||
66 | #define IFX_PMU_MODULE_PPE_SLL01 BIT(19) |
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67 | #define IFX_PMU_MODULE_PPE_TC BIT(21) |
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68 | #define IFX_PMU_MODULE_PPE_EMA BIT(22) |
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69 | #define IFX_PMU_MODULE_PPE_QSB BIT(18) |
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70 | #define IFX_PMU_MODULE_TPE BIT(13) |
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71 | #define IFX_PMU_MODULE_DSL_DFE BIT(9) |
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72 | |||
73 | static inline void reset_ppe(void) |
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74 | { |
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75 | /*#ifdef MODULE |
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76 | unsigned int etop_cfg; |
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77 | unsigned int etop_mdio_cfg; |
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78 | unsigned int etop_ig_plen_ctrl; |
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79 | unsigned int enet_mac_cfg; |
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80 | |||
81 | etop_cfg = *IFX_PP32_ETOP_CFG; |
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82 | etop_mdio_cfg = *IFX_PP32_ETOP_MDIO_CFG; |
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83 | etop_ig_plen_ctrl = *IFX_PP32_ETOP_IG_PLEN_CTRL; |
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84 | enet_mac_cfg = *IFX_PP32_ENET_MAC_CFG; |
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85 | |||
86 | *IFX_PP32_ETOP_CFG &= ~0x03C0; |
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87 | |||
88 | // reset PPE |
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89 | ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_ATM); |
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90 | |||
91 | *IFX_PP32_ETOP_MDIO_CFG = etop_mdio_cfg; |
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92 | *IFX_PP32_ETOP_IG_PLEN_CTRL = etop_ig_plen_ctrl; |
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93 | *IFX_PP32_ENET_MAC_CFG = enet_mac_cfg; |
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94 | *IFX_PP32_ETOP_CFG = etop_cfg; |
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95 | #endif*/ |
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96 | } |
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97 | |||
98 | /* |
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99 | * Description: |
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100 | * Download PPE firmware binary code. |
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101 | * Input: |
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102 | * src --- u32 *, binary code buffer |
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103 | * dword_len --- unsigned int, binary code length in DWORD (32-bit) |
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104 | * Output: |
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105 | * int --- 0: Success |
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106 | * else: Error Code |
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107 | */ |
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108 | static inline int danube_pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len) |
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109 | { |
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110 | volatile u32 *dest; |
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111 | |||
112 | if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0 |
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113 | || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 ) |
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114 | return -1; |
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115 | |||
116 | if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) ) |
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117 | IFX_REG_W32(0x00, CDM_CFG); |
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118 | else |
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119 | IFX_REG_W32(0x04, CDM_CFG); |
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120 | |||
121 | /* copy code */ |
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122 | dest = CDM_CODE_MEMORY(0, 0); |
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123 | while ( code_dword_len-- > 0 ) |
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124 | IFX_REG_W32(*code_src++, dest++); |
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125 | |||
126 | /* copy data */ |
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127 | dest = CDM_DATA_MEMORY(0, 0); |
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128 | while ( data_dword_len-- > 0 ) |
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129 | IFX_REG_W32(*data_src++, dest++); |
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130 | |||
131 | return 0; |
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132 | } |
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133 | |||
134 | static void danube_fw_ver(unsigned int *major, unsigned int *minor) |
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135 | { |
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136 | ASSERT(major != NULL, "pointer is NULL"); |
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137 | ASSERT(minor != NULL, "pointer is NULL"); |
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138 | |||
139 | *major = FW_VER_ID->major; |
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140 | *minor = FW_VER_ID->minor; |
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141 | } |
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142 | |||
143 | static void danube_init(void) |
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144 | { |
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145 | volatile u32 *p = SB_RAM0_ADDR(0); |
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146 | unsigned int i; |
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147 | |||
148 | ltq_pmu_enable(IFX_PMU_MODULE_PPE_SLL01 | |
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149 | IFX_PMU_MODULE_PPE_TC | |
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150 | IFX_PMU_MODULE_PPE_EMA | |
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151 | IFX_PMU_MODULE_PPE_QSB | |
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152 | IFX_PMU_MODULE_TPE | |
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153 | IFX_PMU_MODULE_DSL_DFE); |
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154 | |||
155 | reset_ppe(); |
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156 | |||
157 | /* init ema */ |
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158 | IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG); |
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159 | IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG); |
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160 | IFX_REG_W32(0x000000FF, EMA_IER); |
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161 | IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG); |
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162 | |||
163 | /* init mailbox */ |
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164 | IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC); |
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165 | IFX_REG_W32(0x00000000, MBOX_IGU1_IER); |
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166 | IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC); |
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167 | IFX_REG_W32(0x00000000, MBOX_IGU3_IER); |
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168 | |||
169 | /* init atm tc */ |
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170 | IFX_REG_W32(0x0000, DREG_AT_CTRL); |
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171 | IFX_REG_W32(0x0000, DREG_AR_CTRL); |
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172 | IFX_REG_W32(0x0, DREG_AT_IDLE0); |
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173 | IFX_REG_W32(0x0, DREG_AT_IDLE1); |
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174 | IFX_REG_W32(0x0, DREG_AR_IDLE0); |
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175 | IFX_REG_W32(0x0, DREG_AR_IDLE1); |
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176 | IFX_REG_W32(0x40, RFBI_CFG); |
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177 | IFX_REG_W32(0x1600, SFSM_DBA0); |
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178 | IFX_REG_W32(0x1718, SFSM_DBA1); |
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179 | IFX_REG_W32(0x1830, SFSM_CBA0); |
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180 | IFX_REG_W32(0x1844, SFSM_CBA1); |
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181 | IFX_REG_W32(0x14014, SFSM_CFG0); |
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182 | IFX_REG_W32(0x14014, SFSM_CFG1); |
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183 | IFX_REG_W32(0x1858, FFSM_DBA0); |
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184 | IFX_REG_W32(0x18AC, FFSM_DBA1); |
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185 | IFX_REG_W32(0x10006, FFSM_CFG0); |
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186 | IFX_REG_W32(0x10006, FFSM_CFG1); |
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187 | IFX_REG_W32(0x00000001, FFSM_IDLE_HEAD_BC0); |
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188 | IFX_REG_W32(0x00000001, FFSM_IDLE_HEAD_BC1); |
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189 | |||
190 | for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN; i++ ) |
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191 | IFX_REG_W32(0, p++); |
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192 | } |
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193 | |||
194 | static void danube_shutdown(void) |
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195 | { |
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196 | } |
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197 | |||
198 | int danube_start(int pp32) |
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199 | { |
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200 | int ret; |
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201 | |||
202 | /* download firmware */ |
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203 | ret = danube_pp32_download_code( |
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204 | danube_fw_bin, sizeof(danube_fw_bin) / sizeof(*danube_fw_bin), |
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205 | danube_fw_data, sizeof(danube_fw_data) / sizeof(*danube_fw_data)); |
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206 | if ( ret != 0 ) |
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207 | return ret; |
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208 | |||
209 | /* run PP32 */ |
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210 | IFX_REG_W32(DBG_CTRL_START_SET(1), PP32_DBG_CTRL); |
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211 | |||
212 | /* idle for a while to let PP32 init itself */ |
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213 | udelay(10); |
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214 | |||
215 | return 0; |
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216 | } |
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217 | |||
218 | void danube_stop(int pp32) |
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219 | { |
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220 | IFX_REG_W32(DBG_CTRL_STOP_SET(1), PP32_DBG_CTRL); |
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221 | } |
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222 | |||
223 | struct ltq_atm_ops danube_ops = { |
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224 | .init = danube_init, |
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225 | .shutdown = danube_shutdown, |
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226 | .start = danube_start, |
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227 | .stop = danube_stop, |
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228 | .fw_ver = danube_fw_ver, |
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229 | }; |
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230 | |||
231 | #endif |