OpenWrt – Blame information for rev 4
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Rev | Author | Line No. | Line |
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4 | office | 1 | From e17398316e82d8b28217232b4fd6030c65138e74 Mon Sep 17 00:00:00 2001 |
2 | From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> |
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3 | Date: Mon, 12 Aug 2013 01:18:00 +0200 |
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4 | Subject: MIPS: lantiq: add NAND SPL support |
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5 | |||
6 | Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> |
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7 | |||
8 | --- a/arch/mips/cpu/mips32/lantiq-common/spl.c |
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9 | +++ b/arch/mips/cpu/mips32/lantiq-common/spl.c |
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10 | @@ -8,6 +8,7 @@ |
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11 | #include <image.h> |
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12 | #include <version.h> |
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13 | #include <spi_flash.h> |
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14 | +#include <nand.h> |
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15 | #include <linux/compiler.h> |
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16 | #include <lzma/LzmaDec.h> |
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17 | #include <linux/lzo.h> |
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18 | @@ -63,6 +64,18 @@ |
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19 | #define spl_boot_nor_flash 0 |
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20 | #endif |
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21 | |||
22 | +#if defined(CONFIG_LTQ_SUPPORT_SPL_NAND_FLASH) && defined(CONFIG_SYS_BOOT_NANDSPL) |
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23 | +#define spl_boot_nand_flash 1 |
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24 | +#else |
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25 | +#define spl_boot_nand_flash 0 |
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26 | +#ifndef CONFIG_SYS_NAND_U_BOOT_OFFS |
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27 | +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0 |
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28 | +#endif |
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29 | +#ifndef CONFIG_SYS_NAND_PAGE_SIZE |
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30 | +#define CONFIG_SYS_NAND_PAGE_SIZE 0 |
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31 | +#endif |
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32 | +#endif |
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33 | + |
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34 | #define spl_sync() __asm__ __volatile__("sync"); |
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35 | |||
36 | struct spl_image { |
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37 | @@ -337,6 +350,58 @@ static int spl_load_nor_flash(struct spl |
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38 | return ret; |
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39 | } |
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40 | |||
41 | +static int spl_load_nand_flash(struct spl_image *spl) |
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42 | +{ |
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43 | + image_header_t *hdr; |
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44 | + int ret; |
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45 | + unsigned long loadaddr; |
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46 | + |
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47 | + /* |
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48 | + * Image format: |
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49 | + * |
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50 | + * - 12 byte non-volatile bootstrap header |
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51 | + * - SPL binary |
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52 | + * - 12 byte non-volatile bootstrap header |
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53 | + * - padding bytes up to CONFIG_SYS_NAND_U_BOOT_OFFS |
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54 | + * - 64 byte U-Boot mkimage header |
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55 | + * - U-Boot binary |
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56 | + */ |
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57 | + spl->data_addr = CONFIG_SYS_NAND_U_BOOT_OFFS; |
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58 | + |
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59 | + spl_puts("SPL: initializing NAND flash\n"); |
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60 | + nand_init(); |
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61 | + |
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62 | + spl_debug("SPL: reading image header at page offset %lx\n", |
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63 | + spl->data_addr); |
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64 | + |
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65 | + hdr = (image_header_t *) CONFIG_LOADADDR; |
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66 | + ret = nand_spl_load_image(spl->data_addr, |
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67 | + CONFIG_SYS_NAND_PAGE_SIZE, hdr); |
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68 | + if (ret) |
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69 | + return ret; |
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70 | + |
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71 | + spl_debug("SPL: checking image header at address %p\n", hdr); |
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72 | + |
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73 | + ret = spl_parse_image(hdr, spl); |
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74 | + if (ret) |
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75 | + return ret; |
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76 | + |
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77 | + if (spl_is_compressed(spl)) |
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78 | + loadaddr = CONFIG_LOADADDR; |
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79 | + else |
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80 | + loadaddr = spl->entry_addr; |
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81 | + |
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82 | + spl_puts("SPL: loading U-Boot to RAM\n"); |
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83 | + |
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84 | + ret = nand_spl_load_image(spl->data_addr, spl->data_size, |
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85 | + (void *) loadaddr); |
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86 | + |
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87 | + if (spl_is_compressed(spl)) |
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88 | + ret = spl_uncompress(spl, loadaddr); |
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89 | + |
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90 | + return ret; |
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91 | +} |
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92 | + |
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93 | static int spl_load(struct spl_image *spl) |
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94 | { |
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95 | int ret; |
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96 | @@ -345,6 +410,8 @@ static int spl_load(struct spl_image *sp |
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97 | ret = spl_load_spi_flash(spl); |
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98 | else if (spl_boot_nor_flash) |
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99 | ret = spl_load_nor_flash(spl); |
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100 | + else if (spl_boot_nand_flash) |
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101 | + ret = spl_load_nand_flash(spl); |
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102 | else |
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103 | ret = 1; |
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104 | |||
105 | --- a/arch/mips/include/asm/lantiq/config.h |
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106 | +++ b/arch/mips/include/asm/lantiq/config.h |
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107 | @@ -40,6 +40,26 @@ |
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108 | #define CONFIG_SPI_SPL_SIMPLE |
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109 | #endif |
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110 | |||
111 | +/* |
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112 | + * NAND flash SPL |
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113 | + * BOOT CFG 06 only (address cycle based probing, 2KB or 512B page size) |
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114 | + */ |
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115 | +#if defined(CONFIG_LTQ_SUPPORT_SPL_NAND_FLASH) && defined(CONFIG_SYS_BOOT_NANDSPL) |
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116 | +#define CONFIG_SPL |
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117 | +#define CONFIG_SPL_NAND_SUPPORT |
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118 | +#define CONFIG_SPL_NAND_DRIVERS |
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119 | +#define CONFIG_SPL_NAND_SIMPLE |
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120 | +#define CONFIG_SPL_NAND_ECC |
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121 | + |
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122 | +/* use software ECC until driver supports HW ECC */ |
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123 | +#define CONFIG_SPL_NAND_SOFTECC |
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124 | +#define CONFIG_SYS_NAND_ECCSIZE 256 |
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125 | +#define CONFIG_SYS_NAND_ECCBYTES 3 |
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126 | +#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47, \ |
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127 | + 48, 49, 50, 51, 52, 53, 54, 55, \ |
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128 | + 56, 57, 58, 59, 60, 61, 62, 63} |
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129 | +#endif |
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130 | + |
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131 | #if defined(CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH) && defined(CONFIG_SYS_BOOT_NORSPL) |
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132 | #define CONFIG_SPL |
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133 | #endif |
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134 | @@ -148,6 +168,21 @@ |
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135 | #define CONFIG_ENV_LOAD_UBOOT_SF |
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136 | #endif |
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137 | |||
138 | +#if defined(CONFIG_LTQ_SUPPORT_NAND_FLASH) |
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139 | +#define CONFIG_ENV_WRITE_UBOOT_NAND \ |
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140 | + "write-uboot-nand=" \ |
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141 | + "nand erase 0 $filesize && " \ |
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142 | + "nand write $fileaddr 0 $filesize\0" |
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143 | + |
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144 | +#define CONFIG_ENV_LOAD_UBOOT_NAND \ |
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145 | + "load-uboot-nandspl=tftpboot u-boot.ltq.nandspl\0" \ |
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146 | + "load-uboot-nandspl-lzo=tftpboot u-boot.ltq.lzo.nandspl\0" \ |
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147 | + "load-uboot-nandspl-lzma=tftpboot u-boot.ltq.lzma.nandspl\0" |
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148 | +#else |
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149 | +#define CONFIG_ENV_WRITE_UBOOT_NAND |
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150 | +#define CONFIG_ENV_LOAD_UBOOT_NAND |
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151 | +#endif |
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152 | + |
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153 | #define CONFIG_ENV_LANTIQ_DEFAULTS \ |
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154 | CONFIG_ENV_CONSOLEDEV \ |
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155 | CONFIG_ENV_ADDCONSOLE \ |
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156 | @@ -159,6 +194,8 @@ |
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157 | CONFIG_ENV_LOAD_UBOOT_NOR \ |
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158 | CONFIG_ENV_SF_PROBE \ |
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159 | CONFIG_ENV_WRITE_UBOOT_SF \ |
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160 | - CONFIG_ENV_LOAD_UBOOT_SF |
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161 | + CONFIG_ENV_LOAD_UBOOT_SF \ |
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162 | + CONFIG_ENV_WRITE_UBOOT_NAND \ |
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163 | + CONFIG_ENV_LOAD_UBOOT_NAND |
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164 | |||
165 | #endif /* __LANTIQ_CONFIG_H__ */ |