OpenWrt – Blame information for rev 3
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Rev | Author | Line No. | Line |
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1 | office | 1 | From 69fdd2c4f937796b934e89c33acde9d082e27bfd Mon Sep 17 00:00:00 2001 |
2 | From: John Crispin <blogic@openwrt.org> |
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3 | Date: Mon, 4 Aug 2014 20:36:29 +0200 |
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4 | Subject: [PATCH 27/53] GPIO: MIPS: ralink: add gpio driver for ralink SoC |
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5 | |||
6 | Add gpio driver for Ralink SoC. This driver makes the gpio core on |
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7 | RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work. |
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8 | |||
9 | Signed-off-by: John Crispin <blogic@openwrt.org> |
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10 | Cc: linux-mips@linux-mips.org |
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11 | Cc: linux-gpio@vger.kernel.org |
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12 | --- |
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13 | arch/mips/include/asm/mach-ralink/gpio.h | 24 ++ |
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14 | drivers/gpio/Kconfig | 6 + |
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15 | drivers/gpio/Makefile | 1 + |
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16 | drivers/gpio/gpio-ralink.c | 355 ++++++++++++++++++++++++++++++ |
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17 | 4 files changed, 386 insertions(+) |
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18 | create mode 100644 arch/mips/include/asm/mach-ralink/gpio.h |
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19 | create mode 100644 drivers/gpio/gpio-ralink.c |
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20 | |||
21 | --- /dev/null |
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22 | +++ b/arch/mips/include/asm/mach-ralink/gpio.h |
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23 | @@ -0,0 +1,24 @@ |
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24 | +/* |
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25 | + * Ralink SoC GPIO API support |
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26 | + * |
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27 | + * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org> |
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28 | + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> |
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29 | + * |
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30 | + * This program is free software; you can redistribute it and/or modify it |
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31 | + * under the terms of the GNU General Public License version 2 as published |
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32 | + * by the Free Software Foundation. |
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33 | + * |
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34 | + */ |
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35 | + |
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36 | +#ifndef __ASM_MACH_RALINK_GPIO_H |
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37 | +#define __ASM_MACH_RALINK_GPIO_H |
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38 | + |
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39 | +#define ARCH_NR_GPIOS 128 |
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40 | +#include <asm-generic/gpio.h> |
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41 | + |
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42 | +#define gpio_get_value __gpio_get_value |
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43 | +#define gpio_set_value __gpio_set_value |
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44 | +#define gpio_cansleep __gpio_cansleep |
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45 | +#define gpio_to_irq __gpio_to_irq |
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46 | + |
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47 | +#endif /* __ASM_MACH_RALINK_GPIO_H */ |
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48 | --- a/drivers/gpio/Kconfig |
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49 | +++ b/drivers/gpio/Kconfig |
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50 | @@ -398,6 +398,12 @@ config GPIO_REG |
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51 | A 32-bit single register GPIO fixed in/out implementation. This |
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52 | can be used to represent any register as a set of GPIO signals. |
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53 | |||
54 | +config GPIO_RALINK |
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55 | + bool "Ralink GPIO Support" |
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56 | + depends on RALINK |
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57 | + help |
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58 | + Say yes here to support the Ralink SoC GPIO device |
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59 | + |
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60 | config GPIO_SPEAR_SPICS |
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61 | bool "ST SPEAr13xx SPI Chip Select as GPIO support" |
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62 | depends on PLAT_SPEAR |
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63 | --- a/drivers/gpio/Makefile |
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64 | +++ b/drivers/gpio/Makefile |
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65 | @@ -98,6 +98,7 @@ obj-$(CONFIG_GPIO_PCI_IDIO_16) += gpio-p |
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66 | obj-$(CONFIG_GPIO_PISOSR) += gpio-pisosr.o |
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67 | obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o |
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68 | obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o |
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69 | +obj-$(CONFIG_GPIO_RALINK) += gpio-ralink.o |
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70 | obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o |
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71 | obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o |
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72 | obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o |
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73 | --- /dev/null |
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74 | +++ b/drivers/gpio/gpio-ralink.c |
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75 | @@ -0,0 +1,355 @@ |
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76 | +/* |
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77 | + * This program is free software; you can redistribute it and/or modify it |
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78 | + * under the terms of the GNU General Public License version 2 as published |
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79 | + * by the Free Software Foundation. |
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80 | + * |
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81 | + * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org> |
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82 | + * Copyright (C) 2013 John Crispin <blogic@openwrt.org> |
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83 | + */ |
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84 | + |
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85 | +#include <linux/module.h> |
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86 | +#include <linux/io.h> |
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87 | +#include <linux/gpio.h> |
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88 | +#include <linux/spinlock.h> |
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89 | +#include <linux/platform_device.h> |
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90 | +#include <linux/of_irq.h> |
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91 | +#include <linux/irqdomain.h> |
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92 | +#include <linux/interrupt.h> |
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93 | + |
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94 | +enum ralink_gpio_reg { |
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95 | + GPIO_REG_INT = 0, |
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96 | + GPIO_REG_EDGE, |
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97 | + GPIO_REG_RENA, |
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98 | + GPIO_REG_FENA, |
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99 | + GPIO_REG_DATA, |
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100 | + GPIO_REG_DIR, |
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101 | + GPIO_REG_POL, |
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102 | + GPIO_REG_SET, |
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103 | + GPIO_REG_RESET, |
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104 | + GPIO_REG_TOGGLE, |
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105 | + GPIO_REG_MAX |
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106 | +}; |
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107 | + |
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108 | +struct ralink_gpio_chip { |
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109 | + struct gpio_chip chip; |
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110 | + u8 regs[GPIO_REG_MAX]; |
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111 | + |
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112 | + spinlock_t lock; |
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113 | + void __iomem *membase; |
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114 | + struct irq_domain *domain; |
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115 | + int irq; |
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116 | + |
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117 | + u32 rising; |
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118 | + u32 falling; |
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119 | +}; |
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120 | + |
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121 | +#define MAP_MAX 4 |
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122 | +static struct irq_domain *irq_map[MAP_MAX]; |
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123 | +static int irq_map_count; |
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124 | +static atomic_t irq_refcount = ATOMIC_INIT(0); |
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125 | + |
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126 | +static inline struct ralink_gpio_chip *to_ralink_gpio(struct gpio_chip *chip) |
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127 | +{ |
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128 | + struct ralink_gpio_chip *rg; |
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129 | + |
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130 | + rg = container_of(chip, struct ralink_gpio_chip, chip); |
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131 | + |
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132 | + return rg; |
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133 | +} |
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134 | + |
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135 | +static inline void rt_gpio_w32(struct ralink_gpio_chip *rg, u8 reg, u32 val) |
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136 | +{ |
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137 | + iowrite32(val, rg->membase + rg->regs[reg]); |
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138 | +} |
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139 | + |
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140 | +static inline u32 rt_gpio_r32(struct ralink_gpio_chip *rg, u8 reg) |
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141 | +{ |
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142 | + return ioread32(rg->membase + rg->regs[reg]); |
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143 | +} |
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144 | + |
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145 | +static void ralink_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
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146 | +{ |
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147 | + struct ralink_gpio_chip *rg = to_ralink_gpio(chip); |
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148 | + |
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149 | + rt_gpio_w32(rg, (value) ? GPIO_REG_SET : GPIO_REG_RESET, BIT(offset)); |
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150 | +} |
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151 | + |
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152 | +static int ralink_gpio_get(struct gpio_chip *chip, unsigned offset) |
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153 | +{ |
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154 | + struct ralink_gpio_chip *rg = to_ralink_gpio(chip); |
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155 | + |
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156 | + return !!(rt_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset)); |
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157 | +} |
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158 | + |
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159 | +static int ralink_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
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160 | +{ |
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161 | + struct ralink_gpio_chip *rg = to_ralink_gpio(chip); |
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162 | + unsigned long flags; |
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163 | + u32 t; |
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164 | + |
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165 | + spin_lock_irqsave(&rg->lock, flags); |
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166 | + t = rt_gpio_r32(rg, GPIO_REG_DIR); |
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167 | + t &= ~BIT(offset); |
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168 | + rt_gpio_w32(rg, GPIO_REG_DIR, t); |
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169 | + spin_unlock_irqrestore(&rg->lock, flags); |
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170 | + |
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171 | + return 0; |
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172 | +} |
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173 | + |
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174 | +static int ralink_gpio_direction_output(struct gpio_chip *chip, |
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175 | + unsigned offset, int value) |
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176 | +{ |
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177 | + struct ralink_gpio_chip *rg = to_ralink_gpio(chip); |
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178 | + unsigned long flags; |
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179 | + u32 t; |
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180 | + |
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181 | + spin_lock_irqsave(&rg->lock, flags); |
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182 | + ralink_gpio_set(chip, offset, value); |
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183 | + t = rt_gpio_r32(rg, GPIO_REG_DIR); |
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184 | + t |= BIT(offset); |
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185 | + rt_gpio_w32(rg, GPIO_REG_DIR, t); |
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186 | + spin_unlock_irqrestore(&rg->lock, flags); |
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187 | + |
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188 | + return 0; |
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189 | +} |
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190 | + |
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191 | +static int ralink_gpio_to_irq(struct gpio_chip *chip, unsigned pin) |
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192 | +{ |
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193 | + struct ralink_gpio_chip *rg = to_ralink_gpio(chip); |
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194 | + |
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195 | + if (rg->irq < 1) |
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196 | + return -1; |
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197 | + |
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198 | + return irq_create_mapping(rg->domain, pin); |
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199 | +} |
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200 | + |
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201 | +static void ralink_gpio_irq_handler(struct irq_desc *desc) |
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202 | +{ |
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203 | + int i; |
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204 | + |
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205 | + for (i = 0; i < irq_map_count; i++) { |
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206 | + struct irq_domain *domain = irq_map[i]; |
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207 | + struct ralink_gpio_chip *rg; |
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208 | + unsigned long pending; |
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209 | + int bit; |
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210 | + |
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211 | + rg = (struct ralink_gpio_chip *) domain->host_data; |
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212 | + pending = rt_gpio_r32(rg, GPIO_REG_INT); |
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213 | + |
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214 | + for_each_set_bit(bit, &pending, rg->chip.ngpio) { |
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215 | + u32 map = irq_find_mapping(domain, bit); |
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216 | + generic_handle_irq(map); |
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217 | + rt_gpio_w32(rg, GPIO_REG_INT, BIT(bit)); |
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218 | + } |
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219 | + } |
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220 | +} |
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221 | + |
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222 | +static void ralink_gpio_irq_unmask(struct irq_data *d) |
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223 | +{ |
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224 | + struct ralink_gpio_chip *rg; |
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225 | + unsigned long flags; |
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226 | + u32 rise, fall; |
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227 | + |
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228 | + rg = (struct ralink_gpio_chip *) d->domain->host_data; |
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229 | + rise = rt_gpio_r32(rg, GPIO_REG_RENA); |
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230 | + fall = rt_gpio_r32(rg, GPIO_REG_FENA); |
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231 | + |
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232 | + spin_lock_irqsave(&rg->lock, flags); |
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233 | + rt_gpio_w32(rg, GPIO_REG_RENA, rise | (BIT(d->hwirq) & rg->rising)); |
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234 | + rt_gpio_w32(rg, GPIO_REG_FENA, fall | (BIT(d->hwirq) & rg->falling)); |
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235 | + spin_unlock_irqrestore(&rg->lock, flags); |
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236 | +} |
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237 | + |
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238 | +static void ralink_gpio_irq_mask(struct irq_data *d) |
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239 | +{ |
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240 | + struct ralink_gpio_chip *rg; |
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241 | + unsigned long flags; |
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242 | + u32 rise, fall; |
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243 | + |
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244 | + rg = (struct ralink_gpio_chip *) d->domain->host_data; |
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245 | + rise = rt_gpio_r32(rg, GPIO_REG_RENA); |
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246 | + fall = rt_gpio_r32(rg, GPIO_REG_FENA); |
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247 | + |
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248 | + spin_lock_irqsave(&rg->lock, flags); |
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249 | + rt_gpio_w32(rg, GPIO_REG_FENA, fall & ~BIT(d->hwirq)); |
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250 | + rt_gpio_w32(rg, GPIO_REG_RENA, rise & ~BIT(d->hwirq)); |
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251 | + spin_unlock_irqrestore(&rg->lock, flags); |
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252 | +} |
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253 | + |
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254 | +static int ralink_gpio_irq_type(struct irq_data *d, unsigned int type) |
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255 | +{ |
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256 | + struct ralink_gpio_chip *rg; |
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257 | + u32 mask = BIT(d->hwirq); |
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258 | + |
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259 | + rg = (struct ralink_gpio_chip *) d->domain->host_data; |
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260 | + |
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261 | + if (type == IRQ_TYPE_PROBE) { |
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262 | + if ((rg->rising | rg->falling) & mask) |
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263 | + return 0; |
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264 | + |
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265 | + type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
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266 | + } |
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267 | + |
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268 | + if (type & IRQ_TYPE_EDGE_RISING) |
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269 | + rg->rising |= mask; |
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270 | + else |
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271 | + rg->rising &= ~mask; |
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272 | + |
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273 | + if (type & IRQ_TYPE_EDGE_FALLING) |
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274 | + rg->falling |= mask; |
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275 | + else |
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276 | + rg->falling &= ~mask; |
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277 | + |
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278 | + return 0; |
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279 | +} |
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280 | + |
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281 | +static struct irq_chip ralink_gpio_irq_chip = { |
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282 | + .name = "GPIO", |
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283 | + .irq_unmask = ralink_gpio_irq_unmask, |
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284 | + .irq_mask = ralink_gpio_irq_mask, |
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285 | + .irq_mask_ack = ralink_gpio_irq_mask, |
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286 | + .irq_set_type = ralink_gpio_irq_type, |
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287 | +}; |
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288 | + |
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289 | +static int gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) |
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290 | +{ |
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291 | + irq_set_chip_and_handler(irq, &ralink_gpio_irq_chip, handle_level_irq); |
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292 | + irq_set_handler_data(irq, d); |
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293 | + |
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294 | + return 0; |
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295 | +} |
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296 | + |
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297 | +static const struct irq_domain_ops irq_domain_ops = { |
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298 | + .xlate = irq_domain_xlate_onecell, |
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299 | + .map = gpio_map, |
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300 | +}; |
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301 | + |
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302 | +static void ralink_gpio_irq_init(struct device_node *np, |
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303 | + struct ralink_gpio_chip *rg) |
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304 | +{ |
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305 | + if (irq_map_count >= MAP_MAX) |
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306 | + return; |
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307 | + |
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308 | + rg->irq = irq_of_parse_and_map(np, 0); |
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309 | + if (!rg->irq) |
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310 | + return; |
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311 | + |
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312 | + rg->domain = irq_domain_add_linear(np, rg->chip.ngpio, |
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313 | + &irq_domain_ops, rg); |
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314 | + if (!rg->domain) { |
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315 | + dev_err(rg->chip.parent, "irq_domain_add_linear failed\n"); |
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316 | + return; |
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317 | + } |
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318 | + |
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319 | + irq_map[irq_map_count++] = rg->domain; |
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320 | + |
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321 | + rt_gpio_w32(rg, GPIO_REG_RENA, 0x0); |
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322 | + rt_gpio_w32(rg, GPIO_REG_FENA, 0x0); |
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323 | + |
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324 | + if (!atomic_read(&irq_refcount)) |
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325 | + irq_set_chained_handler(rg->irq, ralink_gpio_irq_handler); |
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326 | + atomic_inc(&irq_refcount); |
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327 | + |
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328 | + dev_info(rg->chip.parent, "registering %d irq handlers\n", rg->chip.ngpio); |
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329 | +} |
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330 | + |
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331 | +static int ralink_gpio_request(struct gpio_chip *chip, unsigned offset) |
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332 | +{ |
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333 | + int gpio = chip->base + offset; |
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334 | + |
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335 | + return pinctrl_request_gpio(gpio); |
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336 | +} |
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337 | + |
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338 | +static void ralink_gpio_free(struct gpio_chip *chip, unsigned offset) |
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339 | +{ |
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340 | + int gpio = chip->base + offset; |
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341 | + |
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342 | + pinctrl_free_gpio(gpio); |
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343 | +} |
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344 | + |
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345 | +static int ralink_gpio_probe(struct platform_device *pdev) |
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346 | +{ |
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347 | + struct device_node *np = pdev->dev.of_node; |
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348 | + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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349 | + struct ralink_gpio_chip *rg; |
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350 | + const __be32 *ngpio, *gpiobase; |
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351 | + |
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352 | + if (!res) { |
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353 | + dev_err(&pdev->dev, "failed to find resource\n"); |
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354 | + return -ENOMEM; |
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355 | + } |
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356 | + |
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357 | + rg = devm_kzalloc(&pdev->dev, |
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358 | + sizeof(struct ralink_gpio_chip), GFP_KERNEL); |
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359 | + if (!rg) |
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360 | + return -ENOMEM; |
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361 | + |
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362 | + rg->membase = devm_ioremap_resource(&pdev->dev, res); |
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363 | + if (!rg->membase) { |
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364 | + dev_err(&pdev->dev, "cannot remap I/O memory region\n"); |
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365 | + return -ENOMEM; |
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366 | + } |
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367 | + |
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368 | + if (of_property_read_u8_array(np, "ralink,register-map", |
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369 | + rg->regs, GPIO_REG_MAX)) { |
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370 | + dev_err(&pdev->dev, "failed to read register definition\n"); |
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371 | + return -EINVAL; |
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372 | + } |
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373 | + |
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3 | office | 374 | + ngpio = of_get_property(np, "ralink,num-gpios", NULL); |
1 | office | 375 | + if (!ngpio) { |
376 | + dev_err(&pdev->dev, "failed to read number of pins\n"); |
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377 | + return -EINVAL; |
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378 | + } |
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379 | + |
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380 | + gpiobase = of_get_property(np, "ralink,gpio-base", NULL); |
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381 | + if (gpiobase) |
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382 | + rg->chip.base = be32_to_cpu(*gpiobase); |
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383 | + else |
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384 | + rg->chip.base = -1; |
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385 | + |
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386 | + spin_lock_init(&rg->lock); |
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387 | + |
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388 | + rg->chip.parent = &pdev->dev; |
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389 | + rg->chip.label = dev_name(&pdev->dev); |
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390 | + rg->chip.of_node = np; |
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391 | + rg->chip.ngpio = be32_to_cpu(*ngpio); |
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392 | + rg->chip.direction_input = ralink_gpio_direction_input; |
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393 | + rg->chip.direction_output = ralink_gpio_direction_output; |
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394 | + rg->chip.get = ralink_gpio_get; |
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395 | + rg->chip.set = ralink_gpio_set; |
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396 | + rg->chip.request = ralink_gpio_request; |
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397 | + rg->chip.to_irq = ralink_gpio_to_irq; |
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398 | + rg->chip.free = ralink_gpio_free; |
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399 | + |
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400 | + /* set polarity to low for all lines */ |
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401 | + rt_gpio_w32(rg, GPIO_REG_POL, 0); |
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402 | + |
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403 | + dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio); |
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404 | + |
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405 | + ralink_gpio_irq_init(np, rg); |
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406 | + |
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407 | + return gpiochip_add(&rg->chip); |
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408 | +} |
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409 | + |
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410 | +static const struct of_device_id ralink_gpio_match[] = { |
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411 | + { .compatible = "ralink,rt2880-gpio" }, |
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412 | + {}, |
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413 | +}; |
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414 | +MODULE_DEVICE_TABLE(of, ralink_gpio_match); |
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415 | + |
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416 | +static struct platform_driver ralink_gpio_driver = { |
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417 | + .probe = ralink_gpio_probe, |
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418 | + .driver = { |
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419 | + .name = "rt2880_gpio", |
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420 | + .owner = THIS_MODULE, |
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421 | + .of_match_table = ralink_gpio_match, |
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422 | + }, |
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423 | +}; |
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424 | + |
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425 | +static int __init ralink_gpio_init(void) |
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426 | +{ |
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427 | + return platform_driver_register(&ralink_gpio_driver); |
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428 | +} |
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429 | + |
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430 | +subsys_initcall(ralink_gpio_init); |