OpenWrt – Blame information for rev 3

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1 office 1 #include <dt-bindings/interrupt-controller/mips-gic.h>
2  
3 / {
4 #address-cells = <1>;
5 #size-cells = <1>;
6 compatible = "mediatek,mt7621-soc";
7  
8 cpus {
9 cpu@0 {
10 compatible = "mips,mips1004Kc";
11 };
12  
13 cpu@1 {
14 compatible = "mips,mips1004Kc";
15 };
16 };
17  
3 office 18 cpuintc: cpuintc@0 {
1 office 19 #address-cells = <0>;
20 #interrupt-cells = <1>;
21 interrupt-controller;
22 compatible = "mti,cpu-interrupt-controller";
23 };
24  
25 aliases {
26 serial0 = &uartlite;
27 };
28  
3 office 29 cpuclock: cpuclock@0 {
30 #clock-cells = <0>;
31 compatible = "fixed-clock";
1 office 32  
3 office 33 /* FIXME: there should be way to detect this */
34 clock-frequency = <880000000>;
1 office 35 };
36  
3 office 37 sysclock: sysclock@0 {
1 office 38 #clock-cells = <0>;
39 compatible = "fixed-clock";
40  
41 /* FIXME: there should be way to detect this */
42 clock-frequency = <50000000>;
43 };
44  
45  
46  
47 palmbus: palmbus@1E000000 {
48 compatible = "palmbus";
49 reg = <0x1E000000 0x100000>;
50 ranges = <0x0 0x1E000000 0x0FFFFF>;
51  
52 #address-cells = <1>;
53 #size-cells = <1>;
54  
55 sysc: sysc@0 {
56 compatible = "mtk,mt7621-sysc";
57 reg = <0x0 0x100>;
58 };
59  
60 wdt: wdt@100 {
61 compatible = "mediatek,mt7621-wdt";
62 reg = <0x100 0x100>;
63 };
64  
65 gpio@600 {
66 #address-cells = <1>;
67 #size-cells = <0>;
68  
69 compatible = "mtk,mt7621-gpio";
70 reg = <0x600 0x100>;
71  
72 gpio0: bank@0 {
73 reg = <0>;
74 compatible = "mtk,mt7621-gpio-bank";
75 gpio-controller;
76 #gpio-cells = <2>;
77 };
78  
79 gpio1: bank@1 {
80 reg = <1>;
81 compatible = "mtk,mt7621-gpio-bank";
82 gpio-controller;
83 #gpio-cells = <2>;
84 };
85  
86 gpio2: bank@2 {
87 reg = <2>;
88 compatible = "mtk,mt7621-gpio-bank";
89 gpio-controller;
90 #gpio-cells = <2>;
91 };
92 };
93  
94 i2c: i2c@900 {
95 compatible = "mediatek,mt7621-i2c";
96 reg = <0x900 0x100>;
97  
98 clocks = <&sysclock>;
99  
100 resets = <&rstctrl 16>;
101 reset-names = "i2c";
102  
103 #address-cells = <1>;
104 #size-cells = <0>;
105  
106 status = "disabled";
107  
108 pinctrl-names = "default";
109 pinctrl-0 = <&i2c_pins>;
110 };
111  
112 i2s: i2s@a00 {
113 compatible = "mediatek,mt7621-i2s";
114 reg = <0xa00 0x100>;
115  
116 clocks = <&sysclock>;
117  
118 resets = <&rstctrl 17>;
119 reset-names = "i2s";
120  
121 interrupt-parent = <&gic>;
122 interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
123  
124 txdma-req = <2>;
125 rxdma-req = <3>;
126  
127 dmas = <&gdma 4>,
128 <&gdma 6>;
129 dma-names = "tx", "rx";
130  
131 status = "disabled";
132 };
133  
3 office 134 systick: systick@d00 {
1 office 135 compatible = "ralink,mt7621-systick", "ralink,cevt-systick";
3 office 136 reg = <0xd00 0x10>;
1 office 137  
138 resets = <&rstctrl 28>;
139 reset-names = "intc";
140  
141 interrupt-parent = <&gic>;
142 interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
143 };
144  
145 memc: memc@5000 {
146 compatible = "mtk,mt7621-memc";
3 office 147 reg = <0x300 0x100>;
1 office 148 };
149  
150 cpc: cpc@1fbf0000 {
3 office 151 compatible = "mtk,mt7621-cpc";
152 reg = <0x1fbf0000 0x8000>;
1 office 153 };
154  
155 mc: mc@1fbf8000 {
3 office 156 compatible = "mtk,mt7621-mc";
157 reg = <0x1fbf8000 0x8000>;
158 };
1 office 159  
160 uartlite: uartlite@c00 {
161 compatible = "ns16550a";
162 reg = <0xc00 0x100>;
163  
3 office 164 clocks = <&sysclock>;
1 office 165 clock-frequency = <50000000>;
166  
167 interrupt-parent = <&gic>;
168 interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
169  
170 reg-shift = <2>;
171 reg-io-width = <4>;
172 no-loopback-test;
173 };
174  
175 spi0: spi@b00 {
176 status = "disabled";
177  
178 compatible = "ralink,mt7621-spi";
179 reg = <0xb00 0x100>;
180  
3 office 181 clocks = <&sysclock>;
1 office 182  
183 resets = <&rstctrl 18>;
184 reset-names = "spi";
185  
186 #address-cells = <1>;
187 #size-cells = <0>;
188  
189 pinctrl-names = "default";
190 pinctrl-0 = <&spi_pins>;
191 };
192  
193 gdma: gdma@2800 {
194 compatible = "ralink,rt3883-gdma";
195 reg = <0x2800 0x800>;
196  
197 resets = <&rstctrl 14>;
198 reset-names = "dma";
199  
200 interrupt-parent = <&gic>;
201 interrupts = <0 13 4>;
202  
203 #dma-cells = <1>;
204 #dma-channels = <16>;
205 #dma-requests = <16>;
206  
207 status = "disabled";
208 };
209  
210 hsdma: hsdma@7000 {
211 compatible = "mediatek,mt7621-hsdma";
212 reg = <0x7000 0x1000>;
213  
214 resets = <&rstctrl 5>;
215 reset-names = "hsdma";
216  
217 interrupt-parent = <&gic>;
218 interrupts = <0 11 4>;
219  
220 #dma-cells = <1>;
221 #dma-channels = <1>;
222 #dma-requests = <1>;
223  
224 status = "disabled";
225 };
226 };
227  
228 pinctrl: pinctrl {
229 compatible = "ralink,rt2880-pinmux";
230 pinctrl-names = "default";
231 pinctrl-0 = <&state_default>;
232  
233 state_default: pinctrl0 {
234 };
235  
3 office 236 i2c_pins: i2c {
237 i2c {
1 office 238 ralink,group = "i2c";
239 ralink,function = "i2c";
240 };
241 };
242  
3 office 243 spi_pins: spi {
244 spi {
1 office 245 ralink,group = "spi";
246 ralink,function = "spi";
247 };
248 };
249  
250 uart1_pins: uart1 {
251 uart1 {
252 ralink,group = "uart1";
253 ralink,function = "uart1";
254 };
255 };
256  
257 uart2_pins: uart2 {
258 uart2 {
259 ralink,group = "uart2";
260 ralink,function = "uart2";
261 };
262 };
263  
264 uart3_pins: uart3 {
265 uart3 {
266 ralink,group = "uart3";
267 ralink,function = "uart3";
268 };
269 };
270  
271 rgmii1_pins: rgmii1 {
272 rgmii1 {
273 ralink,group = "rgmii1";
274 ralink,function = "rgmii1";
275 };
276 };
277  
278 rgmii2_pins: rgmii2 {
279 rgmii2 {
280 ralink,group = "rgmii2";
281 ralink,function = "rgmii2";
282 };
283 };
284  
285 mdio_pins: mdio {
286 mdio {
287 ralink,group = "mdio";
288 ralink,function = "mdio";
289 };
290 };
291  
292 pcie_pins: pcie {
293 pcie {
294 ralink,group = "pcie";
295 ralink,function = "pcie rst";
296 };
297 };
298  
299 nand_pins: nand {
300 spi-nand {
301 ralink,group = "spi";
302 ralink,function = "nand1";
303 };
304  
305 sdhci-nand {
306 ralink,group = "sdhci";
307 ralink,function = "nand2";
308 };
309 };
310  
311 sdhci_pins: sdhci {
312 sdhci {
313 ralink,group = "sdhci";
314 ralink,function = "sdhci";
315 };
316 };
317 };
318  
319 rstctrl: rstctrl {
320 compatible = "ralink,rt2880-reset";
321 #reset-cells = <1>;
322 };
323  
324 clkctrl: clkctrl {
325 compatible = "ralink,rt2880-clock";
326 #clock-cells = <1>;
327 };
328  
329 sdhci: sdhci@1E130000 {
330 status = "disabled";
331  
332 compatible = "ralink,mt7620-sdhci";
333 reg = <0x1E130000 0x4000>;
334  
335 interrupt-parent = <&gic>;
336 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
337 };
338  
339 xhci: xhci@1E1C0000 {
340 status = "okay";
341  
342 compatible = "mediatek,mt8173-xhci";
343 reg = <0x1e1c0000 0x1000
344 0x1e1d0700 0x0100>;
345 reg-names = "mac", "ippc";
346  
347 clocks = <&sysclock>;
348 clock-names = "sys_ck";
349  
350 interrupt-parent = <&gic>;
351 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
352 };
353  
354 gic: interrupt-controller@1fbc0000 {
355 compatible = "mti,gic";
356 reg = <0x1fbc0000 0x2000>;
357  
358 interrupt-controller;
359 #interrupt-cells = <3>;
360  
361 mti,reserved-cpu-vectors = <7>;
362  
363 timer {
364 compatible = "mti,gic-timer";
365 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
3 office 366 clocks = <&cpuclock>;
1 office 367 };
368 };
369  
370 nand: nand@1e003000 {
371 status = "disabled";
372  
373 compatible = "mtk,mt7621-nand";
374 bank-width = <2>;
375 reg = <0x1e003000 0x800
376 0x1e003800 0x800>;
3 office 377 #address-cells = <1>;
378 #size-cells = <1>;
1 office 379 };
380  
3 office 381 hnat: hnat@1e100000 {
382 compatible = "mediatek,mt7623-hnat";
383 reg = <0x1e100000 0x10000>;
384 mtketh-ppd = "eth0";
385 mtketh-lan = "eth0";
386 mtketh-wan = "eth0";
387 resets = <&rstctrl 0>;
388 reset-names = "mtketh";
389 };
390  
1 office 391 ethernet: ethernet@1e100000 {
392 compatible = "mediatek,mt7621-eth";
393 reg = <0x1e100000 0x10000>;
394  
395 #address-cells = <1>;
3 office 396 #size-cells = <0>;
1 office 397  
398 resets = <&rstctrl 6 &rstctrl 23>;
399 reset-names = "fe", "eth";
400  
401 interrupt-parent = <&gic>;
402 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
403  
404 mediatek,switch = <&gsw>;
405  
406 mdio-bus {
407 #address-cells = <1>;
408 #size-cells = <0>;
409  
410 phy1f: ethernet-phy@1f {
411 reg = <0x1f>;
412 phy-mode = "rgmii";
413 };
414 };
415 };
416  
417 gsw: gsw@1e110000 {
418 compatible = "mediatek,mt7621-gsw";
419 reg = <0x1e110000 0x8000>;
420 interrupt-parent = <&gic>;
421 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
422 };
423  
424 pcie: pcie@1e140000 {
425 compatible = "mediatek,mt7621-pci";
426 reg = <0x1e140000 0x100
427 0x1e142000 0x100>;
428  
429 #address-cells = <3>;
430 #size-cells = <2>;
431  
432 pinctrl-names = "default";
433 pinctrl-0 = <&pcie_pins>;
434  
435 device_type = "pci";
436  
437 bus-range = <0 255>;
438 ranges = <
439 0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
440 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
441 >;
442  
443 interrupt-parent = <&gic>;
444 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
445 GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
446 GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
447  
448 status = "disabled";
449  
450 resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
451 reset-names = "pcie0", "pcie1", "pcie2";
452 clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
453 clock-names = "pcie0", "pcie1", "pcie2";
454  
3 office 455 pcie0 {
1 office 456 reg = <0x0000 0 0 0 0>;
457  
458 #address-cells = <3>;
459 #size-cells = <2>;
460  
3 office 461 device_type = "pci";
1 office 462 };
463  
3 office 464 pcie1 {
1 office 465 reg = <0x0800 0 0 0 0>;
466  
467 #address-cells = <3>;
468 #size-cells = <2>;
469  
3 office 470 device_type = "pci";
1 office 471 };
472  
3 office 473 pcie2 {
1 office 474 reg = <0x1000 0 0 0 0>;
475  
476 #address-cells = <3>;
477 #size-cells = <2>;
478  
3 office 479 device_type = "pci";
1 office 480 };
481 };
482 };