OpenWrt – Blame information for rev 3

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Rev Author Line No. Line
1 office 1 /dts-v1/;
2  
3 #include "mt7620a.dtsi"
4  
5 / {
6 compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc";
7 model = "Ralink MT7620a + MT7530 evaluation board";
8 };
9  
10 &spi0 {
11 status = "okay";
12  
13 m25p80@0 {
3 office 14 #address-cells = <1>;
15 #size-cells = <1>;
1 office 16 compatible = "jedec,spi-nor";
17 reg = <0>;
18 spi-max-frequency = <10000000>;
19  
3 office 20 partition@0 {
21 label = "u-boot";
22 reg = <0x0 0x30000>;
23 read-only;
24 };
1 office 25  
3 office 26 partition@30000 {
27 label = "u-boot-env";
28 reg = <0x30000 0x10000>;
29 read-only;
30 };
1 office 31  
3 office 32 factory: partition@40000 {
33 label = "factory";
34 reg = <0x40000 0x10000>;
35 read-only;
36 };
1 office 37  
3 office 38 partition@50000 {
39 label = "firmware";
40 reg = <0x50000 0x7b0000>;
1 office 41 };
42 };
43 };
44  
45 &pinctrl {
46 state_default: pinctrl0 {
47 gpio {
48 ralink,group = "i2c", "uartf";
49 ralink,function = "gpio";
50 };
51 };
52 };
53  
54 &ethernet {
55 status = "okay";
56 pinctrl-names = "default";
57 pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
58 mediatek,portmap = "llllw";
59  
60 port@5 {
61 status = "okay";
62 mediatek,fixed-link = <1000 1 1 1>;
63 phy-mode = "rgmii";
64 };
65  
66 mdio-bus {
67 status = "okay";
68  
69 phy0: ethernet-phy@0 {
70 reg = <0>;
71 phy-mode = "rgmii";
72 };
73  
74 phy1: ethernet-phy@1 {
75 reg = <1>;
76 phy-mode = "rgmii";
77 };
78  
79 phy2: ethernet-phy@2 {
80 reg = <2>;
81 phy-mode = "rgmii";
82 };
83  
84 phy3: ethernet-phy@3 {
85 reg = <3>;
86 phy-mode = "rgmii";
87 };
88  
89 phy4: ethernet-phy@4 {
90 reg = <4>;
91 phy-mode = "rgmii";
92 };
93  
94 phy1f: ethernet-phy@1f {
95 reg = <0x1f>;
96 phy-mode = "rgmii";
97 };
98 };
99 };
100  
101 &gsw {
102 mediatek,port4 = "gmac";
3 office 103 mediatek,mt7530 = <1>;
1 office 104 };
105  
106 &pcie {
107 status = "okay";
108 };
109  
110 &ehci {
111 status = "okay";
112 };
113  
114 &ohci {
115 status = "okay";
116 };