OpenWrt – Blame information for rev 3
?pathlinks?
Rev | Author | Line No. | Line |
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1 | office | 1 | From 082a89a78e29b15008284df90441747cb742f149 Mon Sep 17 00:00:00 2001 |
2 | From: Ezequiel Garcia <ezequiel.garcia@imgtec.com> |
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3 | Date: Tue, 2 Dec 2014 09:58:52 -0300 |
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4 | Subject: mtd: Introduce SPI NAND framework |
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5 | |||
6 | Add a new framework, to support SPI NAND devices. The framework registers |
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7 | a NAND chip and handles the generic SPI NAND protocol, calling device-specific |
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8 | hooks for each SPI NAND command. |
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9 | |||
10 | The following is the stack design, from userspace to hardware. This commit |
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11 | adds the "SPI NAND core" layer. |
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12 | |||
13 | Userspace |
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14 | ------------------ |
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15 | MTD |
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16 | ------------------ |
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17 | NAND core |
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18 | ------------------ |
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19 | SPI NAND core |
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20 | ------------------ |
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21 | SPI NAND device |
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22 | ------------------ |
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23 | SPI core |
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24 | ------------------ |
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25 | SPI master |
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26 | ------------------ |
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27 | Hardware |
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28 | |||
29 | (based on http://lists.infradead.org/pipermail/linux-mtd/2014-December/056763.html) |
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30 | |||
31 | Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> |
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32 | Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com> |
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33 | Signed-off-by: Ian Pozella <Ian.Pozella@imgtec.com> |
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34 | --- |
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35 | drivers/mtd/Kconfig | 2 + |
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36 | drivers/mtd/Makefile | 1 + |
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37 | drivers/mtd/spi-nand/Kconfig | 7 + |
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38 | drivers/mtd/spi-nand/Makefile | 1 + |
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39 | drivers/mtd/spi-nand/spi-nand-base.c | 566 +++++++++++++++++++++++++++++++++++ |
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40 | include/linux/mtd/spi-nand.h | 54 ++++ |
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41 | 6 files changed, 631 insertions(+) |
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42 | create mode 100644 drivers/mtd/spi-nand/Kconfig |
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43 | create mode 100644 drivers/mtd/spi-nand/Makefile |
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44 | create mode 100644 drivers/mtd/spi-nand/spi-nand-base.c |
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45 | create mode 100644 include/linux/mtd/spi-nand.h |
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46 | |||
47 | --- a/drivers/mtd/Kconfig |
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48 | +++ b/drivers/mtd/Kconfig |
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49 | @@ -373,6 +373,8 @@ source "drivers/mtd/onenand/Kconfig" |
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50 | |||
51 | source "drivers/mtd/lpddr/Kconfig" |
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52 | |||
53 | +source "drivers/mtd/spi-nand/Kconfig" |
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54 | + |
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55 | source "drivers/mtd/spi-nor/Kconfig" |
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56 | |||
57 | source "drivers/mtd/ubi/Kconfig" |
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58 | --- a/drivers/mtd/Makefile |
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59 | +++ b/drivers/mtd/Makefile |
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3 | office | 60 | @@ -37,5 +37,6 @@ inftl-objs := inftlcore.o inftlmount.o |
1 | office | 61 | |
62 | obj-y += chips/ lpddr/ maps/ devices/ nand/ onenand/ tests/ |
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63 | |||
64 | +obj-$(CONFIG_MTD_SPI_NAND) += spi-nand/ |
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65 | obj-$(CONFIG_MTD_SPI_NOR) += spi-nor/ |
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66 | obj-$(CONFIG_MTD_UBI) += ubi/ |
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67 | --- /dev/null |
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68 | +++ b/drivers/mtd/spi-nand/Kconfig |
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69 | @@ -0,0 +1,7 @@ |
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70 | +menuconfig MTD_SPI_NAND |
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71 | + tristate "SPI NAND device support" |
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72 | + depends on MTD |
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73 | + select MTD_NAND |
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74 | + help |
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75 | + This is the framework for the SPI NAND. |
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76 | + |
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77 | --- /dev/null |
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78 | +++ b/drivers/mtd/spi-nand/Makefile |
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79 | @@ -0,0 +1 @@ |
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80 | +obj-$(CONFIG_MTD_SPI_NAND) += spi-nand-base.o |
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81 | --- /dev/null |
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82 | +++ b/drivers/mtd/spi-nand/spi-nand-base.c |
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83 | @@ -0,0 +1,566 @@ |
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84 | +/* |
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85 | + * Copyright (C) 2014 Imagination Technologies Ltd. |
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86 | + * |
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87 | + * This program is free software; you can redistribute it and/or modify |
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88 | + * it under the terms of the GNU General Public License as published by |
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89 | + * the Free Software Foundation; version 2 of the License. |
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90 | + * |
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91 | + * Notes: |
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92 | + * 1. Erase and program operations need to call write_enable() first, |
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93 | + * to clear the enable bit. This bit is cleared automatically after |
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94 | + * the erase or program operation. |
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95 | + * |
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96 | + */ |
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97 | + |
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98 | +#include <linux/device.h> |
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99 | +#include <linux/err.h> |
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100 | +#include <linux/errno.h> |
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101 | +#include <linux/kernel.h> |
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102 | +#include <linux/module.h> |
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103 | +#include <linux/mtd/rawnand.h> |
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104 | +#include <linux/mtd/mtd.h> |
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105 | +#include <linux/mtd/partitions.h> |
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106 | +#include <linux/mtd/spi-nand.h> |
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107 | +#include <linux/of.h> |
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108 | +#include <linux/slab.h> |
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109 | + |
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110 | +/* Registers common to all devices */ |
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111 | +#define SPI_NAND_LOCK_REG 0xa0 |
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112 | +#define SPI_NAND_PROT_UNLOCK_ALL 0x0 |
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113 | + |
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114 | +#define SPI_NAND_FEATURE_REG 0xb0 |
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115 | +#define SPI_NAND_ECC_EN BIT(4) |
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116 | +#define SPI_NAND_QUAD_EN BIT(0) |
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117 | + |
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118 | +#define SPI_NAND_STATUS_REG 0xc0 |
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119 | +#define SPI_NAND_STATUS_REG_ECC_MASK 0x3 |
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120 | +#define SPI_NAND_STATUS_REG_ECC_SHIFT 4 |
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121 | +#define SPI_NAND_STATUS_REG_PROG_FAIL BIT(3) |
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122 | +#define SPI_NAND_STATUS_REG_ERASE_FAIL BIT(2) |
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123 | +#define SPI_NAND_STATUS_REG_WREN BIT(1) |
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124 | +#define SPI_NAND_STATUS_REG_BUSY BIT(0) |
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125 | + |
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126 | +#define SPI_NAND_CMD_BUF_LEN 8 |
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127 | + |
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128 | +/* Rewind and fill the buffer with 0xff */ |
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129 | +static void spi_nand_clear_buffer(struct spi_nand *snand) |
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130 | +{ |
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131 | + snand->buf_start = 0; |
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132 | + memset(snand->data_buf, 0xff, snand->buf_size); |
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133 | +} |
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134 | + |
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135 | +static int spi_nand_enable_ecc(struct spi_nand *snand) |
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136 | +{ |
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137 | + int ret; |
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138 | + |
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139 | + ret = snand->read_reg(snand, SPI_NAND_FEATURE_REG, snand->buf); |
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140 | + if (ret) |
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141 | + return ret; |
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142 | + |
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143 | + snand->buf[0] |= SPI_NAND_ECC_EN; |
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144 | + ret = snand->write_reg(snand, SPI_NAND_FEATURE_REG, snand->buf); |
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145 | + if (ret) |
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146 | + return ret; |
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147 | + snand->ecc = true; |
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148 | + |
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149 | + return 0; |
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150 | +} |
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151 | + |
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152 | +static int spi_nand_disable_ecc(struct spi_nand *snand) |
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153 | +{ |
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154 | + int ret; |
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155 | + |
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156 | + ret = snand->read_reg(snand, SPI_NAND_FEATURE_REG, snand->buf); |
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157 | + if (ret) |
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158 | + return ret; |
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159 | + |
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160 | + snand->buf[0] &= ~SPI_NAND_ECC_EN; |
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161 | + ret = snand->write_reg(snand, SPI_NAND_FEATURE_REG, snand->buf); |
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162 | + if (ret) |
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163 | + return ret; |
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164 | + snand->ecc = false; |
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165 | + |
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166 | + return 0; |
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167 | +} |
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168 | + |
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169 | +static int spi_nand_enable_quad(struct spi_nand *snand) |
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170 | +{ |
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171 | + int ret; |
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172 | + |
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173 | + ret = snand->read_reg(snand, SPI_NAND_FEATURE_REG, snand->buf); |
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174 | + if (ret) |
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175 | + return ret; |
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176 | + |
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177 | + snand->buf[0] |= SPI_NAND_QUAD_EN; |
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178 | + ret = snand->write_reg(snand, SPI_NAND_FEATURE_REG, snand->buf); |
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179 | + if (ret) |
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180 | + return ret; |
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181 | + |
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182 | + return 0; |
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183 | +} |
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184 | +/* |
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185 | + * Wait until the status register busy bit is cleared. |
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186 | + * Returns a negatie errno on error or time out, and a non-negative status |
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187 | + * value if the device is ready. |
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188 | + */ |
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189 | +static int spi_nand_wait_till_ready(struct spi_nand *snand) |
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190 | +{ |
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191 | + unsigned long deadline = jiffies + msecs_to_jiffies(100); |
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192 | + bool timeout = false; |
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193 | + int ret; |
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194 | + |
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195 | + /* |
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196 | + * Perhaps we should set a different timeout for each |
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197 | + * operation (reset, read, write, erase). |
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198 | + */ |
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199 | + while (!timeout) { |
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200 | + if (time_after_eq(jiffies, deadline)) |
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201 | + timeout = true; |
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202 | + |
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203 | + ret = snand->read_reg(snand, SPI_NAND_STATUS_REG, snand->buf); |
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204 | + if (ret < 0) { |
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205 | + dev_err(snand->dev, "error reading status register\n"); |
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206 | + return ret; |
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207 | + } else if (!(snand->buf[0] & SPI_NAND_STATUS_REG_BUSY)) { |
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208 | + return snand->buf[0]; |
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209 | + } |
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210 | + |
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211 | + cond_resched(); |
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212 | + } |
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213 | + |
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214 | + dev_err(snand->dev, "operation timed out\n"); |
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215 | + |
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216 | + return -ETIMEDOUT; |
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217 | +} |
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218 | + |
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219 | +static int spi_nand_reset(struct spi_nand *snand) |
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220 | +{ |
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221 | + int ret; |
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222 | + |
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223 | + ret = snand->reset(snand); |
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224 | + if (ret < 0) { |
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225 | + dev_err(snand->dev, "reset command failed\n"); |
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226 | + return ret; |
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227 | + } |
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228 | + |
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229 | + /* |
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230 | + * The NAND core won't wait after a device reset, so we need |
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231 | + * to do that here. |
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232 | + */ |
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233 | + ret = spi_nand_wait_till_ready(snand); |
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234 | + if (ret < 0) |
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235 | + return ret; |
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236 | + return 0; |
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237 | +} |
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238 | + |
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239 | +static int spi_nand_status(struct spi_nand *snand) |
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240 | +{ |
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241 | + int ret, status; |
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242 | + |
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243 | + ret = snand->read_reg(snand, SPI_NAND_STATUS_REG, snand->buf); |
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244 | + if (ret < 0) { |
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245 | + dev_err(snand->dev, "error reading status register\n"); |
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246 | + return ret; |
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247 | + } |
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248 | + status = snand->buf[0]; |
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249 | + |
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250 | + /* Convert this into standard NAND_STATUS values */ |
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251 | + if (status & SPI_NAND_STATUS_REG_BUSY) |
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252 | + snand->buf[0] = 0; |
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253 | + else |
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254 | + snand->buf[0] = NAND_STATUS_READY; |
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255 | + |
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256 | + if (status & SPI_NAND_STATUS_REG_PROG_FAIL || |
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257 | + status & SPI_NAND_STATUS_REG_ERASE_FAIL) |
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258 | + snand->buf[0] |= NAND_STATUS_FAIL; |
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259 | + |
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260 | + /* |
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261 | + * Since we unlock the entire device at initialization, unconditionally |
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262 | + * set the WP bit to indicate it's not protected. |
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263 | + */ |
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264 | + snand->buf[0] |= NAND_STATUS_WP; |
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265 | + return 0; |
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266 | +} |
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267 | + |
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268 | +static int spi_nand_erase(struct spi_nand *snand, int page_addr) |
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269 | +{ |
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270 | + int ret; |
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271 | + |
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272 | + ret = snand->write_enable(snand); |
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273 | + if (ret < 0) { |
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274 | + dev_err(snand->dev, "write enable command failed\n"); |
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275 | + return ret; |
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276 | + } |
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277 | + |
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278 | + ret = snand->block_erase(snand, page_addr); |
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279 | + if (ret < 0) { |
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280 | + dev_err(snand->dev, "block erase command failed\n"); |
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281 | + return ret; |
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282 | + } |
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283 | + |
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284 | + return 0; |
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285 | +} |
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286 | + |
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287 | +static int spi_nand_write(struct spi_nand *snand) |
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288 | +{ |
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289 | + int ret; |
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290 | + |
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291 | + /* Enable quad mode */ |
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292 | + ret = spi_nand_enable_quad(snand); |
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293 | + if (ret) { |
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294 | + dev_err(snand->dev, "error %d enabling quad mode\n", ret); |
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295 | + return ret; |
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296 | + } |
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297 | + /* Store the page to cache */ |
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298 | + ret = snand->store_cache(snand, 0, snand->buf_size, snand->data_buf); |
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299 | + if (ret < 0) { |
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300 | + dev_err(snand->dev, "error %d storing page 0x%x to cache\n", |
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301 | + ret, snand->page_addr); |
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302 | + return ret; |
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303 | + } |
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304 | + |
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305 | + ret = snand->write_enable(snand); |
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306 | + if (ret < 0) { |
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307 | + dev_err(snand->dev, "write enable command failed\n"); |
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308 | + return ret; |
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309 | + } |
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310 | + |
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311 | + /* Get page from the device cache into our internal buffer */ |
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312 | + ret = snand->write_page(snand, snand->page_addr); |
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313 | + if (ret < 0) { |
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314 | + dev_err(snand->dev, "error %d reading page 0x%x from cache\n", |
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315 | + ret, snand->page_addr); |
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316 | + return ret; |
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317 | + } |
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318 | + |
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319 | + return 0; |
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320 | +} |
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321 | + |
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322 | +static int spi_nand_read_id(struct spi_nand *snand) |
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323 | +{ |
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324 | + int ret; |
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325 | + |
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326 | + ret = snand->read_id(snand, snand->data_buf); |
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327 | + if (ret < 0) { |
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328 | + dev_err(snand->dev, "error %d reading ID\n", ret); |
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329 | + return ret; |
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330 | + } |
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331 | + return 0; |
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332 | +} |
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333 | + |
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334 | +static int spi_nand_read_page(struct spi_nand *snand, unsigned int page_addr, |
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335 | + unsigned int page_offset, size_t length) |
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336 | +{ |
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337 | + unsigned int corrected = 0, ecc_error = 0; |
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338 | + int ret; |
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339 | + |
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340 | + /* Load a page into the cache register */ |
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341 | + ret = snand->load_page(snand, page_addr); |
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342 | + if (ret < 0) { |
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343 | + dev_err(snand->dev, "error %d loading page 0x%x to cache\n", |
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344 | + ret, page_addr); |
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345 | + return ret; |
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346 | + } |
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347 | + |
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348 | + ret = spi_nand_wait_till_ready(snand); |
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349 | + if (ret < 0) |
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350 | + return ret; |
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351 | + |
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352 | + if (snand->ecc) { |
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353 | + snand->get_ecc_status(ret, &corrected, &ecc_error); |
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354 | + snand->bitflips = corrected; |
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355 | + |
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356 | + /* |
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357 | + * If there's an ECC error, print a message and notify MTD |
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358 | + * about it. Then complete the read, to load actual data on |
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359 | + * the buffer (instead of the status result). |
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360 | + */ |
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361 | + if (ecc_error) { |
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362 | + dev_err(snand->dev, |
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363 | + "internal ECC error reading page 0x%x\n", |
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364 | + page_addr); |
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365 | + snand->nand_chip.mtd.ecc_stats.failed++; |
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366 | + } else { |
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367 | + snand->nand_chip.mtd.ecc_stats.corrected += corrected; |
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368 | + } |
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369 | + } |
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370 | + |
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371 | + /* Enable quad mode */ |
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372 | + ret = spi_nand_enable_quad(snand); |
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373 | + if (ret) { |
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374 | + dev_err(snand->dev, "error %d enabling quad mode\n", ret); |
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375 | + return ret; |
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376 | + } |
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377 | + /* Get page from the device cache into our internal buffer */ |
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378 | + ret = snand->read_cache(snand, page_offset, length, snand->data_buf); |
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379 | + if (ret < 0) { |
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380 | + dev_err(snand->dev, "error %d reading page 0x%x from cache\n", |
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381 | + ret, page_addr); |
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382 | + return ret; |
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383 | + } |
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384 | + return 0; |
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385 | +} |
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386 | + |
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387 | +static u8 spi_nand_read_byte(struct mtd_info *mtd) |
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388 | +{ |
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389 | + struct nand_chip *chip = mtd_to_nand(mtd); |
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390 | + struct spi_nand *snand = nand_get_controller_data(chip); |
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391 | + char val = 0xff; |
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392 | + |
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393 | + if (snand->buf_start < snand->buf_size) |
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394 | + val = snand->data_buf[snand->buf_start++]; |
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395 | + return val; |
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396 | +} |
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397 | + |
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398 | +static void spi_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len) |
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399 | +{ |
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400 | + struct nand_chip *chip = mtd_to_nand(mtd); |
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401 | + struct spi_nand *snand = nand_get_controller_data(chip); |
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402 | + size_t n = min_t(size_t, len, snand->buf_size - snand->buf_start); |
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403 | + |
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404 | + memcpy(snand->data_buf + snand->buf_start, buf, n); |
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405 | + snand->buf_start += n; |
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406 | +} |
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407 | + |
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408 | +static void spi_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len) |
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409 | +{ |
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410 | + struct nand_chip *chip = mtd_to_nand(mtd); |
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411 | + struct spi_nand *snand = nand_get_controller_data(chip); |
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412 | + size_t n = min_t(size_t, len, snand->buf_size - snand->buf_start); |
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413 | + |
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414 | + memcpy(buf, snand->data_buf + snand->buf_start, n); |
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415 | + snand->buf_start += n; |
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416 | +} |
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417 | + |
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418 | +static int spi_nand_write_page_hwecc(struct mtd_info *mtd, |
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419 | + struct nand_chip *chip, const uint8_t *buf, int oob_required, |
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420 | + int page) |
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421 | +{ |
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422 | + chip->write_buf(mtd, buf, mtd->writesize); |
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423 | + chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); |
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424 | + |
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425 | + return 0; |
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426 | +} |
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427 | + |
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428 | +static int spi_nand_read_page_hwecc(struct mtd_info *mtd, |
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429 | + struct nand_chip *chip, uint8_t *buf, int oob_required, |
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430 | + int page) |
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431 | +{ |
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432 | + struct spi_nand *snand = nand_get_controller_data(chip); |
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433 | + |
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434 | + chip->read_buf(mtd, buf, mtd->writesize); |
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435 | + chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
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436 | + |
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437 | + return snand->bitflips; |
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438 | +} |
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439 | + |
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440 | +static int spi_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *chip) |
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441 | +{ |
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442 | + struct spi_nand *snand = nand_get_controller_data(chip); |
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443 | + int ret; |
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444 | + |
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445 | + ret = spi_nand_wait_till_ready(snand); |
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446 | + |
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447 | + if (ret < 0) { |
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448 | + return NAND_STATUS_FAIL; |
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449 | + } else if (ret & SPI_NAND_STATUS_REG_PROG_FAIL) { |
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450 | + dev_err(snand->dev, "page program failed\n"); |
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451 | + return NAND_STATUS_FAIL; |
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452 | + } else if (ret & SPI_NAND_STATUS_REG_ERASE_FAIL) { |
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453 | + dev_err(snand->dev, "block erase failed\n"); |
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454 | + return NAND_STATUS_FAIL; |
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455 | + } |
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456 | + |
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457 | + return NAND_STATUS_READY; |
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458 | +} |
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459 | + |
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460 | +static void spi_nand_cmdfunc(struct mtd_info *mtd, unsigned int command, |
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461 | + int column, int page_addr) |
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462 | +{ |
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463 | + struct nand_chip *chip = mtd_to_nand(mtd); |
||
464 | + struct spi_nand *snand = nand_get_controller_data(chip); |
||
465 | + |
||
466 | + /* |
||
467 | + * In case there's any unsupported command, let's make sure |
||
468 | + * we don't keep garbage around in the buffer. |
||
469 | + */ |
||
470 | + if (command != NAND_CMD_PAGEPROG) { |
||
471 | + spi_nand_clear_buffer(snand); |
||
472 | + snand->page_addr = 0; |
||
473 | + } |
||
474 | + |
||
475 | + switch (command) { |
||
476 | + case NAND_CMD_READ0: |
||
477 | + spi_nand_read_page(snand, page_addr, 0, mtd->writesize); |
||
478 | + break; |
||
479 | + case NAND_CMD_READOOB: |
||
480 | + spi_nand_disable_ecc(snand); |
||
481 | + spi_nand_read_page(snand, page_addr, mtd->writesize, |
||
482 | + mtd->oobsize); |
||
483 | + spi_nand_enable_ecc(snand); |
||
484 | + break; |
||
485 | + case NAND_CMD_READID: |
||
486 | + spi_nand_read_id(snand); |
||
487 | + break; |
||
488 | + case NAND_CMD_ERASE1: |
||
489 | + spi_nand_erase(snand, page_addr); |
||
490 | + break; |
||
491 | + case NAND_CMD_ERASE2: |
||
492 | + /* There's nothing to do here, as the erase is one-step */ |
||
493 | + break; |
||
494 | + case NAND_CMD_SEQIN: |
||
495 | + snand->buf_start = column; |
||
496 | + snand->page_addr = page_addr; |
||
497 | + break; |
||
498 | + case NAND_CMD_PAGEPROG: |
||
499 | + spi_nand_write(snand); |
||
500 | + break; |
||
501 | + case NAND_CMD_STATUS: |
||
502 | + spi_nand_status(snand); |
||
503 | + break; |
||
504 | + case NAND_CMD_RESET: |
||
505 | + spi_nand_reset(snand); |
||
506 | + break; |
||
507 | + default: |
||
508 | + dev_err(&mtd->dev, "unknown command 0x%x\n", command); |
||
509 | + } |
||
510 | +} |
||
511 | + |
||
512 | +static void spi_nand_select_chip(struct mtd_info *mtd, int chip) |
||
513 | +{ |
||
514 | + /* We need this to override the default */ |
||
515 | +} |
||
516 | + |
||
517 | +int spi_nand_check(struct spi_nand *snand) |
||
518 | +{ |
||
519 | + if (!snand->dev) |
||
520 | + return -ENODEV; |
||
521 | + if (!snand->read_cache) |
||
522 | + return -ENODEV; |
||
523 | + if (!snand->load_page) |
||
524 | + return -ENODEV; |
||
525 | + if (!snand->store_cache) |
||
526 | + return -ENODEV; |
||
527 | + if (!snand->write_page) |
||
528 | + return -ENODEV; |
||
529 | + if (!snand->write_reg) |
||
530 | + return -ENODEV; |
||
531 | + if (!snand->read_reg) |
||
532 | + return -ENODEV; |
||
533 | + if (!snand->block_erase) |
||
534 | + return -ENODEV; |
||
535 | + if (!snand->reset) |
||
536 | + return -ENODEV; |
||
537 | + if (!snand->write_enable) |
||
538 | + return -ENODEV; |
||
539 | + if (!snand->write_disable) |
||
540 | + return -ENODEV; |
||
541 | + if (!snand->get_ecc_status) |
||
542 | + return -ENODEV; |
||
543 | + return 0; |
||
544 | +} |
||
545 | + |
||
546 | +int spi_nand_register(struct spi_nand *snand, struct nand_flash_dev *flash_ids) |
||
547 | +{ |
||
548 | + struct nand_chip *chip = &snand->nand_chip; |
||
549 | + struct mtd_info *mtd = nand_to_mtd(chip); |
||
550 | + struct device_node *np = snand->dev->of_node; |
||
551 | + const char __maybe_unused *of_mtd_name = NULL; |
||
552 | + int ret; |
||
553 | + |
||
554 | + /* Let's check all the hooks are in-place so we don't panic later */ |
||
555 | + ret = spi_nand_check(snand); |
||
556 | + if (ret) |
||
557 | + return ret; |
||
558 | + |
||
559 | + nand_set_controller_data(chip, snand); |
||
560 | + nand_set_flash_node(chip, np); |
||
561 | + chip->read_buf = spi_nand_read_buf; |
||
562 | + chip->write_buf = spi_nand_write_buf; |
||
563 | + chip->read_byte = spi_nand_read_byte; |
||
564 | + chip->cmdfunc = spi_nand_cmdfunc; |
||
565 | + chip->waitfunc = spi_nand_waitfunc; |
||
566 | + chip->select_chip = spi_nand_select_chip; |
||
567 | + chip->options |= NAND_NO_SUBPAGE_WRITE; |
||
568 | + chip->bits_per_cell = 1; |
||
569 | + |
||
570 | + mtd_set_ooblayout(mtd, snand->ooblayout); |
||
571 | + chip->ecc.read_page = spi_nand_read_page_hwecc; |
||
572 | + chip->ecc.write_page = spi_nand_write_page_hwecc; |
||
573 | + chip->ecc.mode = NAND_ECC_HW; |
||
574 | + |
||
575 | + if (of_property_read_bool(np, "nand-on-flash-bbt")) |
||
576 | + chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB; |
||
577 | + |
||
578 | +#ifdef CONFIG_MTD_OF_PARTS |
||
579 | + of_property_read_string(np, "linux,mtd-name", &of_mtd_name); |
||
580 | +#endif |
||
581 | + if (of_mtd_name) |
||
582 | + mtd->name = of_mtd_name; |
||
583 | + else |
||
584 | + mtd->name = snand->name; |
||
585 | + mtd->owner = THIS_MODULE; |
||
586 | + |
||
587 | + /* Allocate buffer to be used to read/write the internal registers */ |
||
588 | + snand->buf = kmalloc(SPI_NAND_CMD_BUF_LEN, GFP_KERNEL); |
||
589 | + if (!snand->buf) |
||
590 | + return -ENOMEM; |
||
591 | + |
||
592 | + /* This is enabled at device power up but we'd better make sure */ |
||
593 | + ret = spi_nand_enable_ecc(snand); |
||
594 | + if (ret) |
||
595 | + return ret; |
||
596 | + |
||
597 | + /* Preallocate buffer for flash identification (NAND_CMD_READID) */ |
||
598 | + snand->buf_size = SPI_NAND_CMD_BUF_LEN; |
||
599 | + snand->data_buf = kmalloc(snand->buf_size, GFP_KERNEL); |
||
600 | + |
||
601 | + ret = nand_scan_ident(mtd, 1, flash_ids); |
||
602 | + if (ret) |
||
603 | + return ret; |
||
604 | + |
||
605 | + /* |
||
606 | + * SPI NAND has on-die ECC, which means we can correct as much as |
||
607 | + * we are required to. This must be done after identification of |
||
608 | + * the device. |
||
609 | + */ |
||
610 | + chip->ecc.strength = chip->ecc_strength_ds; |
||
611 | + chip->ecc.size = chip->ecc_step_ds; |
||
612 | + |
||
613 | + /* |
||
614 | + * Unlock all the device before calling nand_scan_tail. This is needed |
||
615 | + * in case the in-flash bad block table needs to be created. |
||
616 | + * We could override __nand_unlock(), but since it's not currently used |
||
617 | + * by the NAND core we call this explicitly. |
||
618 | + */ |
||
619 | + snand->buf[0] = SPI_NAND_PROT_UNLOCK_ALL; |
||
620 | + ret = snand->write_reg(snand, SPI_NAND_LOCK_REG, snand->buf); |
||
621 | + if (ret) |
||
622 | + return ret; |
||
623 | + |
||
624 | + /* Free the buffer and allocate a good one, to fit a page plus OOB */ |
||
625 | + kfree(snand->data_buf); |
||
626 | + |
||
627 | + snand->buf_size = mtd->writesize + mtd->oobsize; |
||
628 | + snand->data_buf = kmalloc(snand->buf_size, GFP_KERNEL); |
||
629 | + if (!snand->data_buf) |
||
630 | + return -ENOMEM; |
||
631 | + |
||
632 | + ret = nand_scan_tail(mtd); |
||
633 | + if (ret) |
||
634 | + return ret; |
||
635 | + |
||
636 | + return mtd_device_register(mtd, NULL, 0); |
||
637 | +} |
||
638 | +EXPORT_SYMBOL_GPL(spi_nand_register); |
||
639 | + |
||
640 | +void spi_nand_unregister(struct spi_nand *snand) |
||
641 | +{ |
||
642 | + kfree(snand->buf); |
||
643 | + kfree(snand->data_buf); |
||
644 | +} |
||
645 | +EXPORT_SYMBOL_GPL(spi_nand_unregister); |
||
646 | + |
||
647 | +MODULE_AUTHOR("Ezequiel Garcia <ezequiel.garcia@imgtec.com>"); |
||
648 | +MODULE_DESCRIPTION("Framework for SPI NAND"); |
||
649 | +MODULE_LICENSE("GPL v2"); |
||
650 | --- /dev/null |
||
651 | +++ b/include/linux/mtd/spi-nand.h |
||
652 | @@ -0,0 +1,54 @@ |
||
653 | +/* |
||
654 | + * Copyright (C) 2014 Imagination Technologies Ltd. |
||
655 | + * |
||
656 | + * This program is free software; you can redistribute it and/or modify |
||
657 | + * it under the terms of the GNU General Public License as published by |
||
658 | + * the Free Software Foundation; version 2 of the License. |
||
659 | + */ |
||
660 | + |
||
661 | +#ifndef __LINUX_MTD_SPI_NAND_H |
||
662 | +#define __LINUX_MTD_SPI_NAND_H |
||
663 | + |
||
664 | +#include <linux/mtd/mtd.h> |
||
665 | +#include <linux/mtd/rawnand.h> |
||
666 | + |
||
667 | +struct spi_nand { |
||
668 | + struct nand_chip nand_chip; |
||
669 | + struct device *dev; |
||
670 | + const char *name; |
||
671 | + |
||
672 | + u8 *buf, *data_buf; |
||
673 | + size_t buf_size; |
||
674 | + off_t buf_start; |
||
675 | + unsigned int page_addr; |
||
676 | + unsigned int bitflips; |
||
677 | + bool ecc; |
||
678 | + struct mtd_ooblayout_ops *ooblayout; |
||
679 | + |
||
680 | + int (*reset)(struct spi_nand *snand); |
||
681 | + int (*read_id)(struct spi_nand *snand, u8 *buf); |
||
682 | + |
||
683 | + int (*write_disable)(struct spi_nand *snand); |
||
684 | + int (*write_enable)(struct spi_nand *snand); |
||
685 | + |
||
686 | + int (*read_reg)(struct spi_nand *snand, u8 opcode, u8 *buf); |
||
687 | + int (*write_reg)(struct spi_nand *snand, u8 opcode, u8 *buf); |
||
688 | + void (*get_ecc_status)(unsigned int status, |
||
689 | + unsigned int *corrected, |
||
690 | + unsigned int *ecc_errors); |
||
691 | + |
||
692 | + int (*store_cache)(struct spi_nand *snand, unsigned int page_offset, |
||
693 | + size_t length, u8 *write_buf); |
||
694 | + int (*write_page)(struct spi_nand *snand, unsigned int page_addr); |
||
695 | + int (*load_page)(struct spi_nand *snand, unsigned int page_addr); |
||
696 | + int (*read_cache)(struct spi_nand *snand, unsigned int page_offset, |
||
697 | + size_t length, u8 *read_buf); |
||
698 | + int (*block_erase)(struct spi_nand *snand, unsigned int page_addr); |
||
699 | + |
||
700 | + void *priv; |
||
701 | +}; |
||
702 | + |
||
703 | +int spi_nand_register(struct spi_nand *snand, struct nand_flash_dev *flash_ids); |
||
704 | +void spi_nand_unregister(struct spi_nand *snand); |
||
705 | + |
||
706 | +#endif |