OpenWrt – Blame information for rev 3
?pathlinks?
Rev | Author | Line No. | Line |
---|---|---|---|
1 | office | 1 | --- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts |
2 | +++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts |
||
3 | @@ -21,6 +21,10 @@ |
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4 | stdout-path = "serial2:115200n8"; |
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5 | }; |
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6 | |||
7 | + memory { |
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8 | + reg = <0 0x80000000 0 0x20000000>; |
||
9 | + }; |
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10 | + |
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11 | cpus { |
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12 | cpu@0 { |
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13 | proc-supply = <&mt6323_vproc_reg>; |
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14 | @@ -103,6 +107,10 @@ |
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15 | device_type = "memory"; |
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16 | reg = <0 0x80000000 0 0x40000000>; |
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17 | }; |
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18 | + |
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19 | + mt7530: switch@0 { |
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20 | + compatible = "mediatek,mt7530"; |
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21 | + }; |
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22 | }; |
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23 | |||
24 | &cir { |
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25 | @@ -130,11 +138,24 @@ |
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26 | }; |
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27 | }; |
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28 | |||
29 | + gmac1: mac@1 { |
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30 | + compatible = "mediatek,eth-mac"; |
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31 | + reg = <1>; |
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32 | + phy-mode = "rgmii"; |
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33 | + |
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34 | + fixed-link { |
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35 | + speed = <1000>; |
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36 | + full-duplex; |
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37 | + pause; |
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38 | + }; |
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39 | + }; |
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40 | + |
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41 | mdio: mdio-bus { |
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42 | #address-cells = <1>; |
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43 | #size-cells = <0>; |
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44 | - |
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45 | - switch@0 { |
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46 | + }; |
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47 | +}; |
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48 | + &mt7530 { |
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49 | compatible = "mediatek,mt7530"; |
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50 | #address-cells = <1>; |
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51 | #size-cells = <0>; |
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52 | @@ -144,6 +165,8 @@ |
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53 | core-supply = <&mt6323_vpa_reg>; |
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54 | io-supply = <&mt6323_vemc3v3_reg>; |
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55 | |||
56 | + dsa,mii-bus = <&mdio>; |
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57 | + |
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58 | ports { |
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59 | #address-cells = <1>; |
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60 | #size-cells = <0>; |
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61 | @@ -152,29 +175,46 @@ |
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62 | port@0 { |
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63 | reg = <0>; |
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64 | label = "wan"; |
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65 | + cpu = <&cpu_port1>; |
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66 | }; |
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67 | |||
68 | port@1 { |
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69 | reg = <1>; |
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70 | label = "lan0"; |
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71 | + cpu = <&cpu_port0>; |
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72 | }; |
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73 | |||
74 | port@2 { |
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75 | reg = <2>; |
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76 | label = "lan1"; |
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77 | + cpu = <&cpu_port0>; |
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78 | }; |
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79 | |||
80 | port@3 { |
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81 | reg = <3>; |
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82 | label = "lan2"; |
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83 | + cpu = <&cpu_port0>; |
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84 | }; |
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85 | |||
86 | port@4 { |
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87 | reg = <4>; |
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88 | label = "lan3"; |
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89 | + cpu = <&cpu_port0>; |
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90 | }; |
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91 | |||
92 | - port@6 { |
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93 | + cpu_port1: port@5 { |
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94 | + reg = <5>; |
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95 | + label = "cpu"; |
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96 | + ethernet = <&gmac1>; |
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97 | + phy-mode = "rgmii"; |
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98 | + |
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99 | + fixed-link { |
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100 | + speed = <1000>; |
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101 | + full-duplex; |
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102 | + }; |
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103 | + }; |
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104 | + |
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105 | + cpu_port0: port@6 { |
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106 | reg = <6>; |
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107 | label = "cpu"; |
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108 | ethernet = <&gmac0>; |
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109 | @@ -187,8 +227,6 @@ |
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110 | }; |
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111 | }; |
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112 | }; |
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113 | - }; |
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114 | -}; |
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115 | |||
116 | &i2c0 { |
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117 | pinctrl-names = "default"; |
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118 | --- a/arch/arm/boot/dts/Makefile |
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119 | +++ b/arch/arm/boot/dts/Makefile |
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120 | @@ -1061,6 +1061,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ |
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121 | mt6580-evbp1.dtb \ |
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122 | mt6589-aquaris5.dtb \ |
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123 | mt6592-evb.dtb \ |
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124 | + mt7623a-rfb-emmc.dtb \ |
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125 | mt7623n-rfb-nand.dtb \ |
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126 | mt7623n-bananapi-bpi-r2.dtb \ |
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127 | mt8127-moose.dtb \ |
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128 | --- /dev/null |
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129 | +++ b/arch/arm/boot/dts/mt7623a-rfb-emmc.dts |
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130 | @@ -0,0 +1,449 @@ |
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131 | +/* |
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132 | + * Copyright 2017 Sean Wang <sean.wang@mediatek.com> |
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133 | + * |
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134 | + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
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135 | + */ |
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136 | + |
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137 | +/dts-v1/; |
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138 | +#include <dt-bindings/input/input.h> |
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139 | +#include "mt7623.dtsi" |
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140 | +#include "mt6323.dtsi" |
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141 | + |
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142 | +/ { |
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143 | + model = "MediaTek MT7623N NAND reference board"; |
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144 | + compatible = "mediatek,mt7623a-rfb-emmc", "mediatek,mt7623"; |
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145 | + |
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146 | + aliases { |
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147 | + serial2 = &uart2; |
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148 | + }; |
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149 | + |
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150 | + chosen { |
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151 | + bootargs = "earlyprintk block2mtd.block2mtd=/dev/mmcblk0,65536,eMMC,5 mtdparts=eMMC:256k(mbr)ro,512k(uboot)ro,256k(config)ro,256k(factory)ro,32M(kernel),32M(recovery),1024M(rootfs),2048M(usrdata),-(bmtpool) rootfstype=squashfs,jffs2"; |
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152 | + |
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153 | + stdout-path = "serial2:115200n8"; |
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154 | + }; |
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155 | + |
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156 | + memory { |
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157 | + reg = <0 0x80000000 0 0x20000000>; |
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158 | + }; |
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159 | + |
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160 | + cpus { |
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161 | + cpu@0 { |
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162 | + proc-supply = <&mt6323_vproc_reg>; |
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163 | + }; |
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164 | + |
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165 | + cpu@1 { |
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166 | + proc-supply = <&mt6323_vproc_reg>; |
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167 | + }; |
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168 | + |
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169 | + cpu@2 { |
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170 | + proc-supply = <&mt6323_vproc_reg>; |
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171 | + }; |
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172 | + |
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173 | + cpu@3 { |
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174 | + proc-supply = <&mt6323_vproc_reg>; |
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175 | + }; |
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176 | + }; |
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177 | + |
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178 | + memory@80000000 { |
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179 | + reg = <0 0x80000000 0 0x40000000>; |
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180 | + }; |
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181 | + |
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182 | + mt7530: switch@0 { |
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183 | + compatible = "mediatek,mt7530"; |
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184 | + #address-cells = <1>; |
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185 | + #size-cells = <0>; |
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186 | + }; |
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187 | +}; |
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188 | + |
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189 | +&crypto { |
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190 | + status = "okay"; |
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191 | +}; |
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192 | + |
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193 | +ð { |
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194 | + status = "okay"; |
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195 | + |
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196 | + gmac0: mac@0 { |
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197 | + compatible = "mediatek,eth-mac"; |
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198 | + reg = <0>; |
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199 | + phy-mode = "trgmii"; |
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200 | + |
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201 | + fixed-link { |
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202 | + speed = <1000>; |
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203 | + full-duplex; |
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204 | + pause; |
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205 | + }; |
||
206 | + }; |
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207 | + |
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208 | + gmac1: mac@1 { |
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209 | + compatible = "mediatek,eth-mac"; |
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210 | + reg = <1>; |
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211 | + phy-mode = "rgmiii-rxid"; |
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212 | + phy-handle = <&phy5>; |
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213 | + }; |
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214 | + |
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215 | + mdio: mdio-bus { |
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216 | + #address-cells = <1>; |
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217 | + #size-cells = <0>; |
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218 | + phy5: ethernet-phy@5 { |
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219 | + reg = <5>; |
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220 | + phy-mode = "rgmii-rxid"; |
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221 | + }; |
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222 | + }; |
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223 | +}; |
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224 | + |
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225 | +&mt7530 { |
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226 | + compatible = "mediatek,mt7530"; |
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227 | + #address-cells = <1>; |
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228 | + #size-cells = <0>; |
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229 | + reg = <0>; |
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230 | + pinctrl-names = "default"; |
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231 | + mediatek,mcm; |
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232 | + resets = <ðsys 2>; |
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233 | + reset-names = "mcm"; |
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234 | + core-supply = <&mt6323_vpa_reg>; |
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235 | + io-supply = <&mt6323_vemc3v3_reg>; |
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236 | + |
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237 | + dsa,mii-bus = <&mdio>; |
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238 | + |
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239 | + ports { |
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240 | + #address-cells = <1>; |
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241 | + #size-cells = <0>; |
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242 | + reg = <0>; |
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243 | + |
||
244 | + port@0 { |
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245 | + reg = <0>; |
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246 | + label = "lan0"; |
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247 | + cpu = <&cpu_port0>; |
||
248 | + }; |
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249 | + |
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250 | + port@1 { |
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251 | + reg = <1>; |
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252 | + label = "lan1"; |
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253 | + cpu = <&cpu_port0>; |
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254 | + }; |
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255 | + |
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256 | + port@2 { |
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257 | + reg = <2>; |
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258 | + label = "lan2"; |
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259 | + cpu = <&cpu_port0>; |
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260 | + }; |
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261 | + |
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262 | + port@3 { |
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263 | + reg = <3>; |
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264 | + label = "lan3"; |
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265 | + cpu = <&cpu_port0>; |
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266 | + }; |
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267 | + |
||
268 | + cpu_port0: port@6 { |
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269 | + reg = <6>; |
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270 | + label = "cpu"; |
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271 | + ethernet = <&gmac0>; |
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272 | + phy-mode = "trgmii"; |
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273 | + |
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274 | + fixed-link { |
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275 | + speed = <1000>; |
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276 | + full-duplex; |
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277 | + }; |
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278 | + }; |
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279 | + }; |
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280 | +}; |
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281 | + |
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282 | +&i2c0 { |
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283 | + pinctrl-names = "default"; |
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284 | + pinctrl-0 = <&i2c0_pins_a>; |
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285 | + status = "okay"; |
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286 | +}; |
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287 | + |
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288 | +&i2c1 { |
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289 | + pinctrl-names = "default"; |
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290 | + pinctrl-0 = <&i2c1_pins_a>; |
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291 | + status = "okay"; |
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292 | +}; |
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293 | + |
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294 | +&mmc0 { |
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295 | + pinctrl-names = "default", "state_uhs"; |
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296 | + pinctrl-0 = <&mmc0_pins_default>; |
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297 | + pinctrl-1 = <&mmc0_pins_uhs>; |
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298 | + status = "okay"; |
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299 | + bus-width = <8>; |
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300 | + max-frequency = <50000000>; |
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301 | + cap-mmc-highspeed; |
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302 | + vmmc-supply = <&mt6323_vemc3v3_reg>; |
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303 | + vqmmc-supply = <&mt6323_vio18_reg>; |
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304 | + non-removable; |
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305 | +}; |
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306 | + |
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307 | +&mmc1 { |
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308 | + pinctrl-names = "default", "state_uhs"; |
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309 | + pinctrl-0 = <&mmc1_pins_default>; |
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310 | + pinctrl-1 = <&mmc1_pins_uhs>; |
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311 | + status = "okay"; |
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312 | + bus-width = <4>; |
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313 | + max-frequency = <50000000>; |
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314 | + cap-sd-highspeed; |
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315 | + cd-gpios = <&pio 261 0>; |
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316 | + vmmc-supply = <&mt6323_vmch_reg>; |
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317 | + vqmmc-supply = <&mt6323_vio18_reg>; |
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318 | +}; |
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319 | + |
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320 | +&pio { |
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321 | + cir_pins_a:cir@0 { |
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322 | + pins_cir { |
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323 | + pinmux = <MT7623_PIN_46_IR_FUNC_IR>; |
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324 | + bias-disable; |
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325 | + }; |
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326 | + }; |
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327 | + |
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328 | + i2c0_pins_a: i2c@0 { |
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329 | + pins_i2c0 { |
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330 | + pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>, |
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331 | + <MT7623_PIN_76_SCL0_FUNC_SCL0>; |
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332 | + bias-disable; |
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333 | + }; |
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334 | + }; |
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335 | + |
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336 | + i2c1_pins_a: i2c@1 { |
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337 | + pin_i2c1 { |
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338 | + pinmux = <MT7623_PIN_57_SDA1_FUNC_SDA1>, |
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339 | + <MT7623_PIN_58_SCL1_FUNC_SCL1>; |
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340 | + bias-disable; |
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341 | + }; |
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342 | + }; |
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343 | + |
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344 | + i2s0_pins_a: i2s@0 { |
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345 | + pin_i2s0 { |
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346 | + pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>, |
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347 | + <MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>, |
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348 | + <MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>, |
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349 | + <MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK>, |
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350 | + <MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK>; |
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351 | + drive-strength = <MTK_DRIVE_12mA>; |
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352 | + bias-pull-down; |
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353 | + }; |
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354 | + }; |
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355 | + |
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356 | + i2s1_pins_a: i2s@1 { |
||
357 | + pin_i2s1 { |
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358 | + pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>, |
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359 | + <MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>, |
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360 | + <MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>, |
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361 | + <MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK>, |
||
362 | + <MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK>; |
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363 | + drive-strength = <MTK_DRIVE_12mA>; |
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364 | + bias-pull-down; |
||
365 | + }; |
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366 | + }; |
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367 | + |
||
368 | + mmc0_pins_default: mmc0default { |
||
369 | + pins_cmd_dat { |
||
370 | + pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>, |
||
371 | + <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>, |
||
372 | + <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>, |
||
373 | + <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>, |
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374 | + <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>, |
||
375 | + <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>, |
||
376 | + <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>, |
||
377 | + <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>, |
||
378 | + <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>; |
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379 | + input-enable; |
||
380 | + bias-pull-up; |
||
381 | + }; |
||
382 | + |
||
383 | + pins_clk { |
||
384 | + pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>; |
||
385 | + bias-pull-down; |
||
386 | + }; |
||
387 | + |
||
388 | + pins_rst { |
||
389 | + pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>; |
||
390 | + bias-pull-up; |
||
391 | + }; |
||
392 | + }; |
||
393 | + |
||
394 | + mmc0_pins_uhs: mmc0 { |
||
395 | + pins_cmd_dat { |
||
396 | + pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>, |
||
397 | + <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>, |
||
398 | + <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>, |
||
399 | + <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>, |
||
400 | + <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>, |
||
401 | + <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>, |
||
402 | + <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>, |
||
403 | + <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>, |
||
404 | + <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>; |
||
405 | + input-enable; |
||
406 | + drive-strength = <MTK_DRIVE_2mA>; |
||
407 | + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; |
||
408 | + }; |
||
409 | + |
||
410 | + pins_clk { |
||
411 | + pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>; |
||
412 | + drive-strength = <MTK_DRIVE_2mA>; |
||
413 | + bias-pull-down = <MTK_PUPD_SET_R1R0_01>; |
||
414 | + }; |
||
415 | + |
||
416 | + pins_rst { |
||
417 | + pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>; |
||
418 | + bias-pull-up; |
||
419 | + }; |
||
420 | + }; |
||
421 | + |
||
422 | + mmc1_pins_default: mmc1default { |
||
423 | + pins_cmd_dat { |
||
424 | + pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>, |
||
425 | + <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>, |
||
426 | + <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>, |
||
427 | + <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>, |
||
428 | + <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>; |
||
429 | + input-enable; |
||
430 | + drive-strength = <MTK_DRIVE_4mA>; |
||
431 | + bias-pull-up = <MTK_PUPD_SET_R1R0_10>; |
||
432 | + }; |
||
433 | + |
||
434 | + pins_clk { |
||
435 | + pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>; |
||
436 | + bias-pull-down; |
||
437 | + drive-strength = <MTK_DRIVE_4mA>; |
||
438 | + }; |
||
439 | + |
||
440 | + pins_wp { |
||
441 | + pinmux = <MT7623_PIN_29_EINT7_FUNC_MSDC1_WP>; |
||
442 | + input-enable; |
||
443 | + bias-pull-up; |
||
444 | + }; |
||
445 | + |
||
446 | + pins_insert { |
||
447 | + pinmux = <MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261>; |
||
448 | + bias-pull-up; |
||
449 | + }; |
||
450 | + }; |
||
451 | + |
||
452 | + mmc1_pins_uhs: mmc1 { |
||
453 | + pins_cmd_dat { |
||
454 | + pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>, |
||
455 | + <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>, |
||
456 | + <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>, |
||
457 | + <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>, |
||
458 | + <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>; |
||
459 | + input-enable; |
||
460 | + drive-strength = <MTK_DRIVE_4mA>; |
||
461 | + bias-pull-up = <MTK_PUPD_SET_R1R0_10>; |
||
462 | + }; |
||
463 | + |
||
464 | + pins_clk { |
||
465 | + pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>; |
||
466 | + drive-strength = <MTK_DRIVE_4mA>; |
||
467 | + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; |
||
468 | + }; |
||
469 | + }; |
||
470 | + |
||
471 | + pwm_pins_a: pwm@0 { |
||
472 | + pins_pwm { |
||
473 | + pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>, |
||
474 | + <MT7623_PIN_204_PWM1_FUNC_PWM1>, |
||
475 | + <MT7623_PIN_205_PWM2_FUNC_PWM2>, |
||
476 | + <MT7623_PIN_206_PWM3_FUNC_PWM3>, |
||
477 | + <MT7623_PIN_207_PWM4_FUNC_PWM4>; |
||
478 | + }; |
||
479 | + }; |
||
480 | + |
||
481 | + spi0_pins_a: spi@0 { |
||
482 | + pins_spi { |
||
483 | + pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>, |
||
484 | + <MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>, |
||
485 | + <MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI>, |
||
486 | + <MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO>; |
||
487 | + bias-disable; |
||
488 | + }; |
||
489 | + }; |
||
490 | + |
||
491 | + uart0_pins_a: uart@0 { |
||
492 | + pins_dat { |
||
493 | + pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>, |
||
494 | + <MT7623_PIN_80_UTXD0_FUNC_UTXD0>; |
||
495 | + }; |
||
496 | + }; |
||
497 | + |
||
498 | + uart1_pins_a: uart@1 { |
||
499 | + pins_dat { |
||
500 | + pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>, |
||
501 | + <MT7623_PIN_82_UTXD1_FUNC_UTXD1>; |
||
502 | + }; |
||
503 | + }; |
||
504 | +}; |
||
505 | + |
||
506 | +&pwm { |
||
507 | + pinctrl-names = "default"; |
||
508 | + pinctrl-0 = <&pwm_pins_a>; |
||
509 | + status = "okay"; |
||
510 | +}; |
||
511 | + |
||
512 | +&pwrap { |
||
513 | + mt6323 { |
||
514 | + mt6323led: led { |
||
515 | + compatible = "mediatek,mt6323-led"; |
||
516 | + #address-cells = <1>; |
||
517 | + #size-cells = <0>; |
||
518 | + |
||
519 | + led@0 { |
||
520 | + reg = <0>; |
||
521 | + label = "bpi-r2:isink:green"; |
||
522 | + default-state = "off"; |
||
523 | + }; |
||
524 | + |
||
525 | + led@1 { |
||
526 | + reg = <1>; |
||
527 | + label = "bpi-r2:isink:red"; |
||
528 | + default-state = "off"; |
||
529 | + }; |
||
530 | + |
||
531 | + led@2 { |
||
532 | + reg = <2>; |
||
533 | + label = "bpi-r2:isink:blue"; |
||
534 | + default-state = "off"; |
||
535 | + }; |
||
536 | + }; |
||
537 | + }; |
||
538 | +}; |
||
539 | + |
||
540 | +&spi0 { |
||
541 | + pinctrl-names = "default"; |
||
542 | + pinctrl-0 = <&spi0_pins_a>; |
||
543 | + status = "okay"; |
||
544 | +}; |
||
545 | + |
||
546 | +&uart0 { |
||
547 | + pinctrl-names = "default"; |
||
548 | + pinctrl-0 = <&uart0_pins_a>; |
||
549 | + status = "disabled"; |
||
550 | +}; |
||
551 | + |
||
552 | +&uart1 { |
||
553 | + pinctrl-names = "default"; |
||
554 | + pinctrl-0 = <&uart1_pins_a>; |
||
555 | + status = "disabled"; |
||
556 | +}; |
||
557 | + |
||
558 | +&uart2 { |
||
559 | + status = "okay"; |
||
560 | +}; |
||
561 | + |
||
562 | +&usb1 { |
||
563 | + vusb33-supply = <&mt6323_vusb_reg>; |
||
564 | + status = "okay"; |
||
565 | +}; |
||
566 | + |
||
567 | +&usb2 { |
||
568 | + vusb33-supply = <&mt6323_vusb_reg>; |
||
569 | + status = "okay"; |
||
570 | +}; |
||
571 | + |
||
572 | +&u3phy1 { |
||
573 | + status = "okay"; |
||
574 | +}; |
||
575 | + |
||
576 | +&u3phy2 { |
||
577 | + status = "okay"; |
||
578 | +}; |
||
579 | + |
||
580 | --- a/arch/arm/boot/dts/mt7623.dtsi |
||
581 | +++ b/arch/arm/boot/dts/mt7623.dtsi |
||
3 | office | 582 | @@ -323,6 +323,7 @@ |
1 | office | 583 | "syscon"; |
584 | reg = <0 0x10209000 0 0x1000>; |
||
585 | #clock-cells = <1>; |
||
586 | + #reset-cells = <1>; |
||
587 | }; |
||
588 | |||
589 | rng: rng@1020f000 { |