OpenWrt – Blame information for rev 3
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Rev | Author | Line No. | Line |
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1 | office | 1 | From 9afadf01b1be371ee88491819aa67364684461f9 Mon Sep 17 00:00:00 2001 |
2 | From: John Crispin <blogic@openwrt.org> |
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3 | Date: Fri, 3 Aug 2012 10:27:25 +0200 |
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4 | Subject: [PATCH 04/36] MIPS: lantiq: add atm hack |
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5 | |||
6 | Signed-off-by: John Crispin <blogic@openwrt.org> |
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7 | --- |
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8 | arch/mips/include/asm/mach-lantiq/lantiq_atm.h | 196 +++++++++++++++++++++++ |
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9 | arch/mips/include/asm/mach-lantiq/lantiq_ptm.h | 203 ++++++++++++++++++++++++ |
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10 | arch/mips/lantiq/irq.c | 2 + |
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11 | arch/mips/mm/cache.c | 2 + |
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12 | include/uapi/linux/atm.h | 6 + |
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13 | net/atm/common.c | 6 + |
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14 | net/atm/proc.c | 2 +- |
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15 | 7 files changed, 416 insertions(+), 1 deletion(-) |
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16 | create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_atm.h |
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17 | create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_ptm.h |
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18 | |||
19 | --- /dev/null |
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20 | +++ b/arch/mips/include/asm/mach-lantiq/lantiq_atm.h |
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21 | @@ -0,0 +1,196 @@ |
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22 | +/****************************************************************************** |
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23 | +** |
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24 | +** FILE NAME : ifx_atm.h |
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25 | +** PROJECT : UEIP |
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26 | +** MODULES : ATM |
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27 | +** |
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28 | +** DATE : 17 Jun 2009 |
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29 | +** AUTHOR : Xu Liang |
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30 | +** DESCRIPTION : Global ATM driver header file |
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31 | +** COPYRIGHT : Copyright (c) 2006 |
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32 | +** Infineon Technologies AG |
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33 | +** Am Campeon 1-12, 85579 Neubiberg, Germany |
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34 | +** |
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35 | +** This program is free software; you can redistribute it and/or modify |
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36 | +** it under the terms of the GNU General Public License as published by |
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37 | +** the Free Software Foundation; either version 2 of the License, or |
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38 | +** (at your option) any later version. |
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39 | +** |
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40 | +** HISTORY |
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41 | +** $Date $Author $Comment |
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42 | +** 07 JUL 2009 Xu Liang Init Version |
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43 | +*******************************************************************************/ |
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44 | + |
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45 | +#ifndef IFX_ATM_H |
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46 | +#define IFX_ATM_H |
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47 | + |
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48 | + |
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49 | + |
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50 | +/*! |
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51 | + \defgroup IFX_ATM UEIP Project - ATM driver module |
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52 | + \brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9. |
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53 | + */ |
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54 | + |
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55 | +/*! |
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56 | + \defgroup IFX_ATM_IOCTL IOCTL Commands |
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57 | + \ingroup IFX_ATM |
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58 | + \brief IOCTL Commands used by user application. |
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59 | + */ |
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60 | + |
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61 | +/*! |
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62 | + \defgroup IFX_ATM_STRUCT Structures |
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63 | + \ingroup IFX_ATM |
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64 | + \brief Structures used by user application. |
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65 | + */ |
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66 | + |
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67 | +/*! |
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68 | + \file ifx_atm.h |
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69 | + \ingroup IFX_ATM |
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70 | + \brief ATM driver header file |
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71 | + */ |
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72 | + |
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73 | + |
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74 | + |
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75 | +/* |
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76 | + * #################################### |
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77 | + * Definition |
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78 | + * #################################### |
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79 | + */ |
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80 | + |
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81 | +/*! |
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82 | + \addtogroup IFX_ATM_STRUCT |
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83 | + */ |
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84 | +/*@{*/ |
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85 | + |
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86 | +/* |
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87 | + * ATM MIB |
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88 | + */ |
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89 | + |
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90 | +/*! |
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91 | + \struct atm_cell_ifEntry_t |
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92 | + \brief Structure used for Cell Level MIB Counters. |
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93 | + |
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94 | + User application use this structure to call IOCTL command "PPE_ATM_MIB_CELL". |
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95 | + */ |
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96 | +typedef struct { |
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97 | + __u32 ifHCInOctets_h; /*!< byte counter of ingress cells (upper 32 bits, total 64 bits) */ |
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98 | + __u32 ifHCInOctets_l; /*!< byte counter of ingress cells (lower 32 bits, total 64 bits) */ |
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99 | + __u32 ifHCOutOctets_h; /*!< byte counter of egress cells (upper 32 bits, total 64 bits) */ |
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100 | + __u32 ifHCOutOctets_l; /*!< byte counter of egress cells (lower 32 bits, total 64 bits) */ |
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101 | + __u32 ifInErrors; /*!< counter of error ingress cells */ |
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102 | + __u32 ifInUnknownProtos; /*!< counter of unknown ingress cells */ |
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103 | + __u32 ifOutErrors; /*!< counter of error egress cells */ |
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104 | +} atm_cell_ifEntry_t; |
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105 | + |
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106 | +/*! |
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107 | + \struct atm_aal5_ifEntry_t |
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108 | + \brief Structure used for AAL5 Frame Level MIB Counters. |
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109 | + |
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110 | + User application use this structure to call IOCTL command "PPE_ATM_MIB_AAL5". |
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111 | + */ |
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112 | +typedef struct { |
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113 | + __u32 ifHCInOctets_h; /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */ |
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114 | + __u32 ifHCInOctets_l; /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */ |
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115 | + __u32 ifHCOutOctets_h; /*!< byte counter of egress packets (upper 32 bits, total 64 bits) */ |
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116 | + __u32 ifHCOutOctets_l; /*!< byte counter of egress packets (lower 32 bits, total 64 bits) */ |
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117 | + __u32 ifInUcastPkts; /*!< counter of ingress packets */ |
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118 | + __u32 ifOutUcastPkts; /*!< counter of egress packets */ |
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119 | + __u32 ifInErrors; /*!< counter of error ingress packets */ |
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120 | + __u32 ifInDiscards; /*!< counter of dropped ingress packets */ |
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121 | + __u32 ifOutErros; /*!< counter of error egress packets */ |
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122 | + __u32 ifOutDiscards; /*!< counter of dropped egress packets */ |
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123 | +} atm_aal5_ifEntry_t; |
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124 | + |
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125 | +/*! |
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126 | + \struct atm_aal5_vcc_t |
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127 | + \brief Structure used for per PVC AAL5 Frame Level MIB Counters. |
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128 | + |
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129 | + This structure is a part of structure "atm_aal5_vcc_x_t". |
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130 | + */ |
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131 | +typedef struct { |
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132 | + __u32 aal5VccCrcErrors; /*!< counter of ingress packets with CRC error */ |
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133 | + __u32 aal5VccSarTimeOuts; /*!< counter of ingress packets with Re-assemble timeout */ //no timer support yet |
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134 | + __u32 aal5VccOverSizedSDUs; /*!< counter of oversized ingress packets */ |
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135 | +} atm_aal5_vcc_t; |
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136 | + |
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137 | +/*! |
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138 | + \struct atm_aal5_vcc_x_t |
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139 | + \brief Structure used for per PVC AAL5 Frame Level MIB Counters. |
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140 | + |
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141 | + User application use this structure to call IOCTL command "PPE_ATM_MIB_VCC". |
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142 | + */ |
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143 | +typedef struct { |
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144 | + int vpi; /*!< VPI of the VCC to get MIB counters */ |
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145 | + int vci; /*!< VCI of the VCC to get MIB counters */ |
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146 | + atm_aal5_vcc_t mib_vcc; /*!< structure to get MIB counters */ |
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147 | +} atm_aal5_vcc_x_t; |
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148 | + |
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149 | +/*@}*/ |
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150 | + |
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151 | + |
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152 | + |
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153 | +/* |
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154 | + * #################################### |
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155 | + * IOCTL |
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156 | + * #################################### |
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157 | + */ |
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158 | + |
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159 | +/*! |
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160 | + \addtogroup IFX_ATM_IOCTL |
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161 | + */ |
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162 | +/*@{*/ |
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163 | + |
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164 | +/* |
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165 | + * ioctl Command |
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166 | + */ |
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167 | +/*! |
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168 | + \brief ATM IOCTL Magic Number |
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169 | + */ |
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170 | +#define PPE_ATM_IOC_MAGIC 'o' |
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171 | +/*! |
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172 | + \brief ATM IOCTL Command - Get Cell Level MIB Counters |
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173 | + |
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174 | + This command is obsolete. User can get cell level MIB from DSL API. |
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175 | + This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters. |
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176 | + */ |
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177 | +#define PPE_ATM_MIB_CELL _IOW(PPE_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t) |
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178 | +/*! |
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179 | + \brief ATM IOCTL Command - Get AAL5 Level MIB Counters |
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180 | + |
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181 | + Get AAL5 packet counters. |
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182 | + This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters. |
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183 | + */ |
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184 | +#define PPE_ATM_MIB_AAL5 _IOW(PPE_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t) |
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185 | +/*! |
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186 | + \brief ATM IOCTL Command - Get Per PVC MIB Counters |
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187 | + |
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188 | + Get AAL5 packet counters for each PVC. |
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189 | + This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters. |
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190 | + */ |
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191 | +#define PPE_ATM_MIB_VCC _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t) |
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192 | +/*! |
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193 | + \brief Total Number of ATM IOCTL Commands |
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194 | + */ |
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195 | +#define PPE_ATM_IOC_MAXNR 3 |
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196 | + |
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197 | +/*@}*/ |
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198 | + |
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199 | + |
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200 | + |
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201 | +/* |
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202 | + * #################################### |
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203 | + * API |
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204 | + * #################################### |
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205 | + */ |
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206 | + |
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207 | +#ifdef __KERNEL__ |
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208 | +struct port_cell_info { |
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209 | + unsigned int port_num; |
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210 | + unsigned int tx_link_rate[2]; |
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211 | +}; |
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212 | +#endif |
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213 | + |
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214 | + |
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215 | + |
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216 | +#endif // IFX_ATM_H |
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217 | + |
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218 | --- /dev/null |
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219 | +++ b/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h |
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220 | @@ -0,0 +1,203 @@ |
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221 | +/****************************************************************************** |
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222 | +** |
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223 | +** FILE NAME : ifx_ptm.h |
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224 | +** PROJECT : UEIP |
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225 | +** MODULES : PTM |
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226 | +** |
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227 | +** DATE : 17 Jun 2009 |
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228 | +** AUTHOR : Xu Liang |
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229 | +** DESCRIPTION : Global PTM driver header file |
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230 | +** COPYRIGHT : Copyright (c) 2006 |
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231 | +** Infineon Technologies AG |
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232 | +** Am Campeon 1-12, 85579 Neubiberg, Germany |
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233 | +** |
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234 | +** This program is free software; you can redistribute it and/or modify |
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235 | +** it under the terms of the GNU General Public License as published by |
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236 | +** the Free Software Foundation; either version 2 of the License, or |
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237 | +** (at your option) any later version. |
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238 | +** |
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239 | +** HISTORY |
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240 | +** $Date $Author $Comment |
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241 | +** 07 JUL 2009 Xu Liang Init Version |
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242 | +*******************************************************************************/ |
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243 | + |
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244 | +#ifndef IFX_PTM_H |
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245 | +#define IFX_PTM_H |
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246 | + |
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247 | + |
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248 | + |
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249 | +/*! |
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250 | + \defgroup IFX_PTM UEIP Project - PTM driver module |
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251 | + \brief UEIP Project - PTM driver module, support Danube, Amazon-SE, AR9, VR9. |
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252 | + */ |
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253 | + |
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254 | +/*! |
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255 | + \defgroup IFX_PTM_IOCTL IOCTL Commands |
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256 | + \ingroup IFX_PTM |
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257 | + \brief IOCTL Commands used by user application. |
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258 | + */ |
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259 | + |
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260 | +/*! |
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261 | + \defgroup IFX_PTM_STRUCT Structures |
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262 | + \ingroup IFX_PTM |
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263 | + \brief Structures used by user application. |
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264 | + */ |
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265 | + |
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266 | +/*! |
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267 | + \file ifx_ptm.h |
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268 | + \ingroup IFX_PTM |
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269 | + \brief PTM driver header file |
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270 | + */ |
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271 | + |
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272 | + |
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273 | + |
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274 | +/* |
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275 | + * #################################### |
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276 | + * Definition |
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277 | + * #################################### |
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278 | + */ |
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279 | + |
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280 | + |
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281 | + |
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282 | +/* |
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283 | + * #################################### |
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284 | + * IOCTL |
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285 | + * #################################### |
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286 | + */ |
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287 | + |
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288 | +/*! |
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289 | + \addtogroup IFX_PTM_IOCTL |
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290 | + */ |
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291 | +/*@{*/ |
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292 | + |
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293 | +/* |
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294 | + * ioctl Command |
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295 | + */ |
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296 | +/*! |
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297 | + \brief PTM IOCTL Command - Get codeword MIB counters. |
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298 | + |
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299 | + This command uses structure "PTM_CW_IF_ENTRY_T" to get codeword level MIB counters. |
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300 | + */ |
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301 | +#define IFX_PTM_MIB_CW_GET SIOCDEVPRIVATE + 1 |
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302 | +/*! |
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303 | + \brief PTM IOCTL Command - Get packet MIB counters. |
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304 | + |
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305 | + This command uses structure "PTM_FRAME_MIB_T" to get packet level MIB counters. |
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306 | + */ |
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307 | +#define IFX_PTM_MIB_FRAME_GET SIOCDEVPRIVATE + 2 |
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308 | +/*! |
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309 | + \brief PTM IOCTL Command - Get firmware configuration (CRC). |
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310 | + |
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311 | + This command uses structure "IFX_PTM_CFG_T" to get firmware configuration (CRC). |
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312 | + */ |
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313 | +#define IFX_PTM_CFG_GET SIOCDEVPRIVATE + 3 |
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314 | +/*! |
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315 | + \brief PTM IOCTL Command - Set firmware configuration (CRC). |
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316 | + |
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317 | + This command uses structure "IFX_PTM_CFG_T" to set firmware configuration (CRC). |
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318 | + */ |
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319 | +#define IFX_PTM_CFG_SET SIOCDEVPRIVATE + 4 |
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320 | +/*! |
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321 | + \brief PTM IOCTL Command - Program priority value to TX queue mapping. |
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322 | + |
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323 | + This command uses structure "IFX_PTM_PRIO_Q_MAP_T" to program priority value to TX queue mapping. |
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324 | + */ |
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325 | +#define IFX_PTM_MAP_PKT_PRIO_TO_Q SIOCDEVPRIVATE + 14 |
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326 | + |
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327 | +/*@}*/ |
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328 | + |
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329 | + |
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330 | +/*! |
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331 | + \addtogroup IFX_PTM_STRUCT |
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332 | + */ |
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333 | +/*@{*/ |
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334 | + |
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335 | +/* |
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336 | + * ioctl Data Type |
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337 | + */ |
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338 | + |
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339 | +/*! |
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340 | + \typedef PTM_CW_IF_ENTRY_T |
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341 | + \brief Wrapping of structure "ptm_cw_ifEntry_t". |
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342 | + */ |
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343 | +/*! |
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344 | + \struct ptm_cw_ifEntry_t |
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345 | + \brief Structure used for CodeWord level MIB counters. |
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346 | + */ |
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347 | +typedef struct ptm_cw_ifEntry_t { |
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348 | + uint32_t ifRxNoIdleCodewords; /*!< output, number of ingress user codeword */ |
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349 | + uint32_t ifRxIdleCodewords; /*!< output, number of ingress idle codeword */ |
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350 | + uint32_t ifRxCodingViolation; /*!< output, number of error ingress codeword */ |
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351 | + uint32_t ifTxNoIdleCodewords; /*!< output, number of egress user codeword */ |
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352 | + uint32_t ifTxIdleCodewords; /*!< output, number of egress idle codeword */ |
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353 | +} PTM_CW_IF_ENTRY_T; |
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354 | + |
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355 | +/*! |
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356 | + \typedef PTM_FRAME_MIB_T |
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357 | + \brief Wrapping of structure "ptm_frame_mib_t". |
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358 | + */ |
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359 | +/*! |
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360 | + \struct ptm_frame_mib_t |
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361 | + \brief Structure used for packet level MIB counters. |
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362 | + */ |
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363 | +typedef struct ptm_frame_mib_t { |
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364 | + uint32_t RxCorrect; /*!< output, number of ingress packet */ |
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365 | + uint32_t TC_CrcError; /*!< output, number of egress packet with CRC error */ |
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366 | + uint32_t RxDropped; /*!< output, number of dropped ingress packet */ |
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367 | + uint32_t TxSend; /*!< output, number of egress packet */ |
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368 | +} PTM_FRAME_MIB_T; |
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369 | + |
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370 | +/*! |
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371 | + \typedef IFX_PTM_CFG_T |
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372 | + \brief Wrapping of structure "ptm_cfg_t". |
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373 | + */ |
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374 | +/*! |
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375 | + \struct ptm_cfg_t |
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376 | + \brief Structure used for ETH/TC CRC configuration. |
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377 | + */ |
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378 | +typedef struct ptm_cfg_t { |
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379 | + uint32_t RxEthCrcPresent; /*!< input/output, ingress packet has ETH CRC */ |
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380 | + uint32_t RxEthCrcCheck; /*!< input/output, check ETH CRC of ingress packet */ |
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381 | + uint32_t RxTcCrcCheck; /*!< input/output, check TC CRC of ingress codeword */ |
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382 | + uint32_t RxTcCrcLen; /*!< input/output, length of TC CRC of ingress codeword */ |
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383 | + uint32_t TxEthCrcGen; /*!< input/output, generate ETH CRC for egress packet */ |
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384 | + uint32_t TxTcCrcGen; /*!< input/output, generate TC CRC for egress codeword */ |
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385 | + uint32_t TxTcCrcLen; /*!< input/output, length of TC CRC of egress codeword */ |
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386 | +} IFX_PTM_CFG_T; |
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387 | + |
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388 | +/*! |
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389 | + \typedef IFX_PTM_PRIO_Q_MAP_T |
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390 | + \brief Wrapping of structure "ppe_prio_q_map". |
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391 | + */ |
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392 | +/*! |
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393 | + \struct ppe_prio_q_map |
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394 | + \brief Structure used for Priority Value to TX Queue mapping. |
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395 | + */ |
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396 | +typedef struct ppe_prio_q_map { |
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397 | + int pkt_prio; |
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398 | + int qid; |
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399 | + int vpi; // ignored in eth interface |
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400 | + int vci; // ignored in eth interface |
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401 | +} IFX_PTM_PRIO_Q_MAP_T; |
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402 | + |
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403 | +/*@}*/ |
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404 | + |
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405 | + |
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406 | + |
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407 | +/* |
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408 | + * #################################### |
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409 | + * API |
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410 | + * #################################### |
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411 | + */ |
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412 | + |
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413 | +#ifdef __KERNEL__ |
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414 | +struct port_cell_info { |
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415 | + unsigned int port_num; |
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416 | + unsigned int tx_link_rate[2]; |
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417 | +}; |
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418 | +#endif |
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419 | + |
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420 | + |
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421 | + |
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422 | +#endif // IFX_PTM_H |
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423 | + |
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424 | --- a/arch/mips/lantiq/irq.c |
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425 | +++ b/arch/mips/lantiq/irq.c |
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426 | @@ -14,6 +14,7 @@ |
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427 | #include <linux/of_platform.h> |
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428 | #include <linux/of_address.h> |
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429 | #include <linux/of_irq.h> |
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430 | +#include <linux/module.h> |
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431 | |||
432 | #include <asm/bootinfo.h> |
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433 | #include <asm/irq_cpu.h> |
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434 | @@ -96,6 +97,7 @@ void ltq_mask_and_ack_irq(struct irq_dat |
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435 | ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier); |
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436 | ltq_icu_w32(im, BIT(offset), isr); |
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437 | } |
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438 | +EXPORT_SYMBOL(ltq_mask_and_ack_irq); |
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439 | |||
440 | static void ltq_ack_irq(struct irq_data *d) |
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441 | { |
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442 | --- a/arch/mips/mm/cache.c |
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443 | +++ b/arch/mips/mm/cache.c |
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444 | @@ -64,6 +64,8 @@ void (*_dma_cache_wback)(unsigned long s |
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445 | void (*_dma_cache_inv)(unsigned long start, unsigned long size); |
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446 | |||
447 | EXPORT_SYMBOL(_dma_cache_wback_inv); |
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448 | +EXPORT_SYMBOL(_dma_cache_wback); |
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449 | +EXPORT_SYMBOL(_dma_cache_inv); |
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450 | |||
451 | #endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */ |
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452 | |||
453 | --- a/include/uapi/linux/atm.h |
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454 | +++ b/include/uapi/linux/atm.h |
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455 | @@ -131,8 +131,14 @@ |
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456 | #define ATM_ABR 4 |
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457 | #define ATM_ANYCLASS 5 /* compatible with everything */ |
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458 | |||
459 | +#define ATM_VBR_NRT ATM_VBR |
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460 | +#define ATM_VBR_RT 6 |
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461 | +#define ATM_UBR_PLUS 7 |
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462 | +#define ATM_GFR 8 |
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463 | + |
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464 | #define ATM_MAX_PCR -1 /* maximum available PCR */ |
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465 | |||
466 | + |
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467 | struct atm_trafprm { |
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468 | unsigned char traffic_class; /* traffic class (ATM_UBR, ...) */ |
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469 | int max_pcr; /* maximum PCR in cells per second */ |
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3 | office | 470 | --- a/net/atm/common.c |
471 | +++ b/net/atm/common.c |
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472 | @@ -62,10 +62,16 @@ static void vcc_remove_socket(struct soc |
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473 | write_unlock_irq(&vcc_sklist_lock); |
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474 | } |
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475 | |||
476 | +struct sk_buff* (*ifx_atm_alloc_tx)(struct atm_vcc *, unsigned int) = NULL; |
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477 | +EXPORT_SYMBOL(ifx_atm_alloc_tx); |
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478 | + |
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479 | static bool vcc_tx_ready(struct atm_vcc *vcc, unsigned int size) |
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480 | { |
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481 | struct sock *sk = sk_atm(vcc); |
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482 | |||
483 | + if (ifx_atm_alloc_tx != NULL) |
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484 | + return ifx_atm_alloc_tx(vcc, size); |
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485 | + |
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486 | if (sk_wmem_alloc_get(sk) && !atm_may_send(vcc, size)) { |
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487 | pr_debug("Sorry: wmem_alloc = %d, size = %d, sndbuf = %d\n", |
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488 | sk_wmem_alloc_get(sk), size, sk->sk_sndbuf); |
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1 | office | 489 | --- a/net/atm/proc.c |
490 | +++ b/net/atm/proc.c |
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491 | @@ -155,7 +155,7 @@ static void *vcc_seq_next(struct seq_fil |
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492 | static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc) |
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493 | { |
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494 | static const char *const class_name[] = { |
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495 | - "off", "UBR", "CBR", "VBR", "ABR"}; |
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496 | + "off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"}; |
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497 | static const char *const aal_name[] = { |
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498 | "---", "1", "2", "3/4", /* 0- 3 */ |
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499 | "???", "5", "???", "???", /* 4- 7 */ |