OpenWrt – Blame information for rev 3
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Rev | Author | Line No. | Line |
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1 | office | 1 | From 6f933347d0b4ed02d9534f5fa07f7b99f13eeaa1 Mon Sep 17 00:00:00 2001 |
2 | From: John Crispin <blogic@openwrt.org> |
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3 | Date: Thu, 7 Aug 2014 18:12:28 +0200 |
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4 | Subject: [PATCH 01/36] MIPS: lantiq: add pcie driver |
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5 | |||
6 | Signed-off-by: John Crispin <blogic@openwrt.org> |
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7 | --- |
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8 | arch/mips/lantiq/Kconfig | 10 + |
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9 | arch/mips/lantiq/xway/sysctrl.c | 2 + |
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10 | arch/mips/pci/Makefile | 2 + |
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11 | arch/mips/pci/fixup-lantiq-pcie.c | 82 +++ |
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12 | arch/mips/pci/fixup-lantiq.c | 5 +- |
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13 | arch/mips/pci/ifxmips_pci_common.h | 57 ++ |
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14 | arch/mips/pci/ifxmips_pcie.c | 1099 ++++++++++++++++++++++++++++++ |
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15 | arch/mips/pci/ifxmips_pcie.h | 135 ++++ |
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16 | arch/mips/pci/ifxmips_pcie_ar10.h | 290 ++++++++ |
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17 | arch/mips/pci/ifxmips_pcie_msi.c | 392 +++++++++++ |
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18 | arch/mips/pci/ifxmips_pcie_phy.c | 478 +++++++++++++ |
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19 | arch/mips/pci/ifxmips_pcie_pm.c | 176 +++++ |
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20 | arch/mips/pci/ifxmips_pcie_pm.h | 36 + |
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21 | arch/mips/pci/ifxmips_pcie_reg.h | 1001 +++++++++++++++++++++++++++ |
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22 | arch/mips/pci/ifxmips_pcie_vr9.h | 271 ++++++++ |
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23 | arch/mips/pci/pci.c | 25 + |
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24 | arch/mips/pci/pcie-lantiq.h | 1305 ++++++++++++++++++++++++++++++++++++ |
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25 | drivers/pci/pcie/aer/Kconfig | 2 +- |
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26 | include/linux/pci.h | 2 + |
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27 | include/linux/pci_ids.h | 6 + |
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28 | 20 files changed, 5374 insertions(+), 2 deletions(-) |
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29 | create mode 100644 arch/mips/pci/fixup-lantiq-pcie.c |
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30 | create mode 100644 arch/mips/pci/ifxmips_pci_common.h |
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31 | create mode 100644 arch/mips/pci/ifxmips_pcie.c |
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32 | create mode 100644 arch/mips/pci/ifxmips_pcie.h |
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33 | create mode 100644 arch/mips/pci/ifxmips_pcie_ar10.h |
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34 | create mode 100644 arch/mips/pci/ifxmips_pcie_msi.c |
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35 | create mode 100644 arch/mips/pci/ifxmips_pcie_phy.c |
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36 | create mode 100644 arch/mips/pci/ifxmips_pcie_pm.c |
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37 | create mode 100644 arch/mips/pci/ifxmips_pcie_pm.h |
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38 | create mode 100644 arch/mips/pci/ifxmips_pcie_reg.h |
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39 | create mode 100644 arch/mips/pci/ifxmips_pcie_vr9.h |
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40 | create mode 100644 arch/mips/pci/pcie-lantiq.h |
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41 | |||
42 | --- a/arch/mips/lantiq/Kconfig |
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43 | +++ b/arch/mips/lantiq/Kconfig |
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44 | @@ -20,6 +20,7 @@ config SOC_XWAY |
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45 | bool "XWAY" |
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46 | select SOC_TYPE_XWAY |
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47 | select HW_HAS_PCI |
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48 | + select ARCH_SUPPORTS_MSI |
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49 | select MFD_SYSCON |
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50 | select MFD_CORE |
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51 | |||
52 | @@ -52,6 +53,15 @@ config PCI_LANTIQ |
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53 | bool "PCI Support" |
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54 | depends on SOC_XWAY && PCI |
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55 | |||
56 | +config PCIE_LANTIQ |
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57 | + bool "PCIE Support" |
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58 | + depends on SOC_XWAY && PCI |
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59 | + |
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60 | +config PCIE_LANTIQ_MSI |
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61 | + bool |
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62 | + depends on PCIE_LANTIQ && PCI_MSI |
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63 | + default y |
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64 | + |
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65 | config XRX200_PHY_FW |
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66 | bool "XRX200 PHY firmware loader" |
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67 | depends on SOC_XWAY |
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68 | --- a/arch/mips/pci/Makefile |
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69 | +++ b/arch/mips/pci/Makefile |
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70 | @@ -49,6 +49,8 @@ obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o |
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71 | obj-$(CONFIG_SOC_MT7620) += pci-mt7620.o |
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72 | obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o |
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73 | obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o |
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74 | +obj-$(CONFIG_PCIE_LANTIQ) += ifxmips_pcie_phy.o ifxmips_pcie.o fixup-lantiq-pcie.o |
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75 | +obj-$(CONFIG_PCIE_LANTIQ_MSI) += pcie-lantiq-msi.o |
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76 | obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o |
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77 | obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o |
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78 | obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o |
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79 | --- /dev/null |
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80 | +++ b/arch/mips/pci/fixup-lantiq-pcie.c |
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81 | @@ -0,0 +1,74 @@ |
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82 | +/****************************************************************************** |
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83 | +** |
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84 | +** FILE NAME : ifxmips_fixup_pcie.c |
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85 | +** PROJECT : IFX UEIP for VRX200 |
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86 | +** MODULES : PCIe |
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87 | +** |
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88 | +** DATE : 02 Mar 2009 |
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89 | +** AUTHOR : Lei Chuanhua |
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90 | +** DESCRIPTION : PCIe Root Complex Driver |
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91 | +** COPYRIGHT : Copyright (c) 2009 |
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92 | +** Infineon Technologies AG |
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93 | +** Am Campeon 1-12, 85579 Neubiberg, Germany |
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94 | +** |
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95 | +** This program is free software; you can redistribute it and/or modify |
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96 | +** it under the terms of the GNU General Public License as published by |
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97 | +** the Free Software Foundation; either version 2 of the License, or |
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98 | +** (at your option) any later version. |
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99 | +** HISTORY |
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100 | +** $Version $Date $Author $Comment |
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101 | +** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version |
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102 | +*******************************************************************************/ |
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103 | +/*! |
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104 | + \file ifxmips_fixup_pcie.c |
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105 | + \ingroup IFX_PCIE |
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106 | + \brief PCIe Fixup functions source file |
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107 | +*/ |
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108 | +#include <linux/pci.h> |
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109 | +#include <linux/pci_regs.h> |
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110 | +#include <linux/pci_ids.h> |
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111 | + |
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112 | +#include <lantiq_soc.h> |
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113 | + |
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114 | +#include "pcie-lantiq.h" |
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115 | + |
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116 | +static void |
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117 | +ifx_pcie_fixup_resource(struct pci_dev *dev) |
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118 | +{ |
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119 | + u32 reg; |
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120 | + |
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121 | + IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: enter\n", __func__, pci_name(dev)); |
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122 | + |
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123 | + printk("%s: fixup host controller %s (%04x:%04x)\n", |
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124 | + __func__, pci_name(dev), dev->vendor, dev->device); |
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125 | + |
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126 | + /* Setup COMMAND register */ |
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127 | + reg = PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER /* | |
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128 | + PCI_COMMAND_INTX_DISABLE */| PCI_COMMAND_SERR; |
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129 | + pci_write_config_word(dev, PCI_COMMAND, reg); |
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130 | + IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: exit\n", __func__, pci_name(dev)); |
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131 | +} |
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132 | +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INFINEON, PCI_DEVICE_ID_INFINEON_PCIE, ifx_pcie_fixup_resource); |
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133 | +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LANTIQ, PCI_VENDOR_ID_LANTIQ, ifx_pcie_fixup_resource); |
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134 | + |
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135 | +static void |
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136 | +ifx_pcie_rc_class_early_fixup(struct pci_dev *dev) |
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137 | +{ |
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138 | + IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: enter\n", __func__, pci_name(dev)); |
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139 | + |
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140 | + if (dev->devfn == PCI_DEVFN(0, 0) && |
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141 | + (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { |
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142 | + |
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143 | + dev->class = (PCI_CLASS_BRIDGE_PCI << 8) | (dev->class & 0xff); |
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144 | + |
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145 | + printk(KERN_INFO "%s: fixed pcie host bridge to pci-pci bridge\n", __func__); |
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146 | + } |
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147 | + IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: exit\n", __func__, pci_name(dev)); |
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148 | + mdelay(10); |
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149 | +} |
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150 | + |
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151 | +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INFINEON, PCI_DEVICE_ID_INFINEON_PCIE, |
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152 | + ifx_pcie_rc_class_early_fixup); |
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153 | + |
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154 | +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LANTIQ, PCI_DEVICE_ID_LANTIQ_PCIE, |
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155 | + ifx_pcie_rc_class_early_fixup); |
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156 | --- a/arch/mips/pci/fixup-lantiq.c |
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157 | +++ b/arch/mips/pci/fixup-lantiq.c |
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158 | @@ -8,12 +8,18 @@ |
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159 | |||
160 | #include <linux/of_irq.h> |
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161 | #include <linux/of_pci.h> |
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162 | +#include "ifxmips_pci_common.h" |
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163 | |||
164 | int (*ltq_pci_plat_arch_init)(struct pci_dev *dev) = NULL; |
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165 | int (*ltq_pci_plat_dev_init)(struct pci_dev *dev) = NULL; |
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166 | |||
167 | int pcibios_plat_dev_init(struct pci_dev *dev) |
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168 | { |
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169 | +#ifdef CONFIG_PCIE_LANTIQ |
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170 | + if (pci_find_capability(dev, PCI_CAP_ID_EXP)) |
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171 | + ifx_pcie_bios_plat_dev_init(dev); |
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172 | +#endif |
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173 | + |
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174 | if (ltq_pci_plat_arch_init) |
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175 | return ltq_pci_plat_arch_init(dev); |
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176 | |||
177 | @@ -25,5 +31,10 @@ int pcibios_plat_dev_init(struct pci_dev |
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178 | |||
179 | int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
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180 | { |
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181 | +#ifdef CONFIG_PCIE_LANTIQ |
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182 | + if (pci_find_capability(dev, PCI_CAP_ID_EXP)) |
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183 | + return ifx_pcie_bios_map_irq(dev, slot, pin); |
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184 | +#endif |
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185 | + |
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186 | return of_irq_parse_and_map_pci(dev, slot, pin); |
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187 | } |
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188 | --- /dev/null |
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189 | +++ b/arch/mips/pci/ifxmips_pci_common.h |
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190 | @@ -0,0 +1,57 @@ |
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191 | +/****************************************************************************** |
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192 | +** |
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193 | +** FILE NAME : ifxmips_pci_common.h |
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194 | +** PROJECT : IFX UEIP |
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195 | +** MODULES : PCI subsystem |
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196 | +** |
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197 | +** DATE : 30 June 2009 |
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198 | +** AUTHOR : Lei Chuanhua |
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199 | +** DESCRIPTION : PCIe Root Complex Driver |
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200 | +** COPYRIGHT : Copyright (c) 2009 |
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201 | +** Infineon Technologies AG |
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202 | +** Am Campeon 1-12, 85579 Neubiberg, Germany |
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203 | +** |
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204 | +** This program is free software; you can redistribute it and/or modify |
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205 | +** it under the terms of the GNU General Public License as published by |
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206 | +** the Free Software Foundation; either version 2 of the License, or |
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207 | +** (at your option) any later version. |
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208 | +** HISTORY |
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209 | +** $Version $Date $Author $Comment |
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210 | +** 0.0.1 30 June,2009 Lei Chuanhua Initial version |
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211 | +*******************************************************************************/ |
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212 | + |
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213 | +#ifndef IFXMIPS_PCI_COMMON_H |
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214 | +#define IFXMIPS_PCI_COMMON_H |
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215 | +#include <linux/version.h> |
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216 | +/*! |
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217 | + \defgroup IFX_PCI_COM IFX PCI/PCIe common parts for OS integration |
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218 | + \brief PCI/PCIe common parts |
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219 | +*/ |
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220 | + |
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221 | +/*! |
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222 | + \defgroup IFX_PCI_COM_OS OS APIs |
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223 | + \ingroup IFX_PCI_COM |
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224 | + \brief PCI/PCIe bus driver OS interface functions |
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225 | +*/ |
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226 | +/*! |
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227 | + \file ifxmips_pci_common.h |
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228 | + \ingroup IFX_PCI_COM |
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229 | + \brief PCI/PCIe bus driver common OS header file |
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230 | +*/ |
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231 | +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) |
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232 | +#define IFX_PCI_CONST |
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233 | +#else |
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234 | +#define IFX_PCI_CONST const |
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235 | +#endif |
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236 | +#ifdef CONFIG_IFX_PCI |
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237 | +extern int ifx_pci_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin); |
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238 | +extern int ifx_pci_bios_plat_dev_init(struct pci_dev *dev); |
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239 | +#endif /* COFNIG_IFX_PCI */ |
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240 | + |
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241 | +#ifdef CONFIG_PCIE_LANTIQ |
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242 | +extern int ifx_pcie_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin); |
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243 | +extern int ifx_pcie_bios_plat_dev_init(struct pci_dev *dev); |
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244 | +#endif |
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245 | + |
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246 | +#endif /* IFXMIPS_PCI_COMMON_H */ |
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247 | + |
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248 | --- /dev/null |
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249 | +++ b/arch/mips/pci/ifxmips_pcie.c |
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250 | @@ -0,0 +1,1092 @@ |
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251 | +/* |
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252 | + * This program is free software; you can redistribute it and/or modify it |
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253 | + * under the terms of the GNU General Public License version 2 as published |
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254 | + * by the Free Software Foundation. |
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255 | + * |
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256 | + * Copyright (C) 2009 Lei Chuanhua <chuanhua.lei@infineon.com> |
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257 | + * Copyright (C) 2013 John Crispin <blogic@openwrt.org> |
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258 | + */ |
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259 | + |
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260 | +#include <linux/types.h> |
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261 | +#include <linux/pci.h> |
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262 | +#include <linux/kernel.h> |
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263 | +#include <linux/init.h> |
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264 | +#include <linux/delay.h> |
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265 | +#include <linux/mm.h> |
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266 | +#include <asm/paccess.h> |
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267 | +#include <linux/pci.h> |
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268 | +#include <linux/pci_regs.h> |
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269 | +#include <linux/module.h> |
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270 | + |
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271 | +#include "ifxmips_pcie.h" |
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272 | +#include "ifxmips_pcie_reg.h" |
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273 | + |
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274 | +/* Enable 32bit io due to its mem mapped io nature */ |
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275 | +#define IFX_PCIE_ERROR_INT |
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276 | +#define IFX_PCIE_IO_32BIT |
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277 | + |
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278 | +#define IFX_PCIE_IR (INT_NUM_IM4_IRL0 + 25) |
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279 | +#define IFX_PCIE_INTA (INT_NUM_IM4_IRL0 + 8) |
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280 | +#define IFX_PCIE_INTB (INT_NUM_IM4_IRL0 + 9) |
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281 | +#define IFX_PCIE_INTC (INT_NUM_IM4_IRL0 + 10) |
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282 | +#define IFX_PCIE_INTD (INT_NUM_IM4_IRL0 + 11) |
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283 | +#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) |
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284 | +#define SM(_v, _f) (((_v) << _f##_S) & (_f)) |
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285 | +#define IFX_REG_SET_BIT(_f, _r) \ |
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286 | + IFX_REG_W32((IFX_REG_R32((_r)) &~ (_f)) | (_f), (_r)) |
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287 | + |
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288 | +#define IFX_PCIE_LTSSM_ENABLE_TIMEOUT 10 |
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289 | + |
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290 | +static DEFINE_SPINLOCK(ifx_pcie_lock); |
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291 | + |
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292 | +u32 g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG); |
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293 | + |
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294 | +static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = { |
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295 | + { |
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296 | + .ir_irq = { |
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297 | + .irq = IFX_PCIE_IR, |
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298 | + .name = "ifx_pcie_rc0", |
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299 | + }, |
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300 | + |
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301 | + .legacy_irq = { |
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302 | + { |
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303 | + .irq_bit = PCIE_IRN_INTA, |
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304 | + .irq = IFX_PCIE_INTA, |
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305 | + }, |
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306 | + { |
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307 | + .irq_bit = PCIE_IRN_INTB, |
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308 | + .irq = IFX_PCIE_INTB, |
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309 | + }, |
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310 | + { |
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311 | + .irq_bit = PCIE_IRN_INTC, |
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312 | + .irq = IFX_PCIE_INTC, |
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313 | + }, |
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314 | + { |
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315 | + .irq_bit = PCIE_IRN_INTD, |
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316 | + .irq = IFX_PCIE_INTD, |
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317 | + }, |
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318 | + }, |
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319 | + }, |
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320 | + |
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321 | +}; |
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322 | + |
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323 | +void ifx_pcie_debug(const char *fmt, ...) |
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324 | +{ |
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325 | + static char buf[256] = {0}; /* XXX */ |
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326 | + va_list ap; |
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327 | + |
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328 | + va_start(ap, fmt); |
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329 | + vsnprintf(buf, sizeof(buf), fmt, ap); |
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330 | + va_end(ap); |
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331 | + |
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332 | + printk("%s", buf); |
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333 | +} |
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334 | + |
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335 | + |
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336 | +static inline int pcie_ltssm_enable(int pcie_port) |
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337 | +{ |
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338 | + int i; |
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339 | + |
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340 | + /* Enable LTSSM */ |
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341 | + IFX_REG_W32(PCIE_RC_CCR_LTSSM_ENABLE, PCIE_RC_CCR(pcie_port)); |
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342 | + |
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343 | + /* Wait for the link to come up */ |
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344 | + for (i = 0; i < IFX_PCIE_LTSSM_ENABLE_TIMEOUT; i++) { |
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345 | + if (!(IFX_REG_R32(PCIE_LCTLSTS(pcie_port)) & PCIE_LCTLSTS_RETRAIN_PENDING)) |
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346 | + return 0; |
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347 | + udelay(10); |
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348 | + } |
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349 | + |
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350 | + printk("%s link timeout!!!!!\n", __func__); |
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351 | + return -1; |
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352 | +} |
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353 | + |
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354 | +static inline void pcie_status_register_clear(int pcie_port) |
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355 | +{ |
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356 | + IFX_REG_W32(0, PCIE_RC_DR(pcie_port)); |
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357 | + IFX_REG_W32(0, PCIE_PCICMDSTS(pcie_port)); |
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358 | + IFX_REG_W32(0, PCIE_DCTLSTS(pcie_port)); |
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359 | + IFX_REG_W32(0, PCIE_LCTLSTS(pcie_port)); |
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360 | + IFX_REG_W32(0, PCIE_SLCTLSTS(pcie_port)); |
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361 | + IFX_REG_W32(0, PCIE_RSTS(pcie_port)); |
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362 | + IFX_REG_W32(0, PCIE_UES_R(pcie_port)); |
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363 | + IFX_REG_W32(0, PCIE_UEMR(pcie_port)); |
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364 | + IFX_REG_W32(0, PCIE_UESR(pcie_port)); |
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365 | + IFX_REG_W32(0, PCIE_CESR(pcie_port)); |
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366 | + IFX_REG_W32(0, PCIE_CEMR(pcie_port)); |
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367 | + IFX_REG_W32(0, PCIE_RESR(pcie_port)); |
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368 | + IFX_REG_W32(0, PCIE_PVCCRSR(pcie_port)); |
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369 | + IFX_REG_W32(0, PCIE_VC0_RSR0(pcie_port)); |
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370 | + IFX_REG_W32(0, PCIE_TPFCS(pcie_port)); |
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371 | + IFX_REG_W32(0, PCIE_TNPFCS(pcie_port)); |
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372 | + IFX_REG_W32(0, PCIE_TCFCS(pcie_port)); |
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373 | + IFX_REG_W32(0, PCIE_QSR(pcie_port)); |
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374 | + IFX_REG_W32(0, PCIE_IOBLSECS(pcie_port)); |
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375 | +} |
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376 | + |
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377 | +static inline int ifx_pcie_link_up(int pcie_port) |
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378 | +{ |
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379 | + return (IFX_REG_R32(PCIE_PHY_SR(pcie_port)) & PCIE_PHY_SR_PHY_LINK_UP) ? 1 : 0; |
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380 | +} |
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381 | + |
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382 | + |
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383 | +static inline void pcie_mem_io_setup(int pcie_port) |
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384 | +{ |
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385 | + u32 reg; |
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386 | + /* |
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387 | + * BAR[0:1] readonly register |
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388 | + * RC contains only minimal BARs for packets mapped to this device |
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389 | + * Mem/IO filters defines a range of memory occupied by memory mapped IO devices that |
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390 | + * reside on the downstream side fo the bridge. |
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391 | + */ |
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392 | + reg = SM((PCIE_MEM_PHY_PORT_TO_END(pcie_port) >> 20), PCIE_MBML_MEM_LIMIT_ADDR) |
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393 | + | SM((PCIE_MEM_PHY_PORT_TO_BASE(pcie_port) >> 20), PCIE_MBML_MEM_BASE_ADDR); |
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394 | + |
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395 | + IFX_REG_W32(reg, PCIE_MBML(pcie_port)); |
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396 | + |
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397 | + |
||
398 | +#ifdef IFX_PCIE_PREFETCH_MEM_64BIT |
||
399 | + reg = SM((PCIE_MEM_PHY_PORT_TO_END(pcie_port) >> 20), PCIE_PMBL_END_ADDR) |
||
400 | + | SM((PCIE_MEM_PHY_PORT_TO_BASE(pcie_port) >> 20), PCIE_PMBL_UPPER_12BIT) |
||
401 | + | PCIE_PMBL_64BIT_ADDR; |
||
402 | + IFX_REG_W32(reg, PCIE_PMBL(pcie_port)); |
||
403 | + |
||
404 | + /* Must configure upper 32bit */ |
||
405 | + IFX_REG_W32(0, PCIE_PMBU32(pcie_port)); |
||
406 | + IFX_REG_W32(0, PCIE_PMLU32(pcie_port)); |
||
407 | +#else |
||
408 | + /* PCIe_PBML, same as MBML */ |
||
409 | + IFX_REG_W32(IFX_REG_R32(PCIE_MBML(pcie_port)), PCIE_PMBL(pcie_port)); |
||
410 | +#endif |
||
411 | + |
||
412 | + /* IO Address Range */ |
||
413 | + reg = SM((PCIE_IO_PHY_PORT_TO_END(pcie_port) >> 12), PCIE_IOBLSECS_IO_LIMIT_ADDR) |
||
414 | + | SM((PCIE_IO_PHY_PORT_TO_BASE(pcie_port) >> 12), PCIE_IOBLSECS_IO_BASE_ADDR); |
||
415 | +#ifdef IFX_PCIE_IO_32BIT |
||
416 | + reg |= PCIE_IOBLSECS_32BIT_IO_ADDR; |
||
417 | +#endif /* IFX_PCIE_IO_32BIT */ |
||
418 | + IFX_REG_W32(reg, PCIE_IOBLSECS(pcie_port)); |
||
419 | + |
||
420 | +#ifdef IFX_PCIE_IO_32BIT |
||
421 | + reg = SM((PCIE_IO_PHY_PORT_TO_END(pcie_port) >> 16), PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT) |
||
422 | + | SM((PCIE_IO_PHY_PORT_TO_BASE(pcie_port) >> 16), PCIE_IO_BANDL_UPPER_16BIT_IO_BASE); |
||
423 | + IFX_REG_W32(reg, PCIE_IO_BANDL(pcie_port)); |
||
424 | + |
||
425 | +#endif /* IFX_PCIE_IO_32BIT */ |
||
426 | +} |
||
427 | + |
||
428 | +static inline void |
||
429 | +pcie_device_setup(int pcie_port) |
||
430 | +{ |
||
431 | + u32 reg; |
||
432 | + |
||
433 | + /* Device capability register, set up Maximum payload size */ |
||
434 | + reg = IFX_REG_R32(PCIE_DCAP(pcie_port)); |
||
435 | + reg |= PCIE_DCAP_ROLE_BASE_ERR_REPORT; |
||
436 | + reg |= SM(PCIE_MAX_PAYLOAD_128, PCIE_DCAP_MAX_PAYLOAD_SIZE); |
||
437 | + |
||
438 | + /* Only available for EP */ |
||
439 | + reg &= ~(PCIE_DCAP_EP_L0S_LATENCY | PCIE_DCAP_EP_L1_LATENCY); |
||
440 | + IFX_REG_W32(reg, PCIE_DCAP(pcie_port)); |
||
441 | + |
||
442 | + /* Device control and status register */ |
||
443 | + /* Set Maximum Read Request size for the device as a Requestor */ |
||
444 | + reg = IFX_REG_R32(PCIE_DCTLSTS(pcie_port)); |
||
445 | + |
||
446 | + /* |
||
447 | + * Request size can be larger than the MPS used, but the completions returned |
||
448 | + * for the read will be bounded by the MPS size. |
||
449 | + * In our system, Max request size depends on AHB burst size. It is 64 bytes. |
||
450 | + * but we set it as 128 as minimum one. |
||
451 | + */ |
||
452 | + reg |= SM(PCIE_MAX_PAYLOAD_128, PCIE_DCTLSTS_MAX_READ_SIZE) |
||
453 | + | SM(PCIE_MAX_PAYLOAD_128, PCIE_DCTLSTS_MAX_PAYLOAD_SIZE); |
||
454 | + |
||
455 | + /* Enable relaxed ordering, no snoop, and all kinds of errors */ |
||
456 | + reg |= PCIE_DCTLSTS_RELAXED_ORDERING_EN | PCIE_DCTLSTS_ERR_EN | PCIE_DCTLSTS_NO_SNOOP_EN; |
||
457 | + |
||
458 | + IFX_REG_W32(reg, PCIE_DCTLSTS(pcie_port)); |
||
459 | +} |
||
460 | + |
||
461 | +static inline void |
||
462 | +pcie_link_setup(int pcie_port) |
||
463 | +{ |
||
464 | + u32 reg; |
||
465 | + |
||
466 | + /* |
||
467 | + * XXX, Link capability register, bit 18 for EP CLKREQ# dynamic clock management for L1, L2/3 CPM |
||
468 | + * L0s is reported during link training via TS1 order set by N_FTS |
||
469 | + */ |
||
470 | + reg = IFX_REG_R32(PCIE_LCAP(pcie_port)); |
||
471 | + reg &= ~PCIE_LCAP_L0S_EIXT_LATENCY; |
||
472 | + reg |= SM(3, PCIE_LCAP_L0S_EIXT_LATENCY); |
||
473 | + IFX_REG_W32(reg, PCIE_LCAP(pcie_port)); |
||
474 | + |
||
475 | + /* Link control and status register */ |
||
476 | + reg = IFX_REG_R32(PCIE_LCTLSTS(pcie_port)); |
||
477 | + |
||
478 | + /* Link Enable, ASPM enabled */ |
||
479 | + reg &= ~PCIE_LCTLSTS_LINK_DISABLE; |
||
480 | + |
||
481 | +#ifdef CONFIG_PCIEASPM |
||
482 | + /* |
||
483 | + * We use the same physical reference clock that the platform provides on the connector |
||
484 | + * It paved the way for ASPM to calculate the new exit Latency |
||
485 | + */ |
||
486 | + reg |= PCIE_LCTLSTS_SLOT_CLK_CFG; |
||
487 | + reg |= PCIE_LCTLSTS_COM_CLK_CFG; |
||
488 | + /* |
||
489 | + * We should disable ASPM by default except that we have dedicated power management support |
||
490 | + * Enable ASPM will cause the system hangup/instability, performance degration |
||
491 | + */ |
||
492 | + reg |= PCIE_LCTLSTS_ASPM_ENABLE; |
||
493 | +#else |
||
494 | + reg &= ~PCIE_LCTLSTS_ASPM_ENABLE; |
||
495 | +#endif /* CONFIG_PCIEASPM */ |
||
496 | + |
||
497 | + /* |
||
498 | + * The maximum size of any completion with data packet is bounded by the MPS setting |
||
499 | + * in device control register |
||
500 | + */ |
||
501 | + |
||
502 | + /* RCB may cause multiple split transactions, two options available, we use 64 byte RCB */ |
||
503 | + reg &= ~ PCIE_LCTLSTS_RCB128; |
||
504 | + |
||
505 | + IFX_REG_W32(reg, PCIE_LCTLSTS(pcie_port)); |
||
506 | +} |
||
507 | + |
||
508 | +static inline void pcie_error_setup(int pcie_port) |
||
509 | +{ |
||
510 | + u32 reg; |
||
511 | + |
||
512 | + /* |
||
513 | + * Forward ERR_COR, ERR_NONFATAL, ERR_FATAL to the backbone |
||
514 | + * Poisoned write TLPs and completions indicating poisoned TLPs will set the PCIe_PCICMDSTS.MDPE |
||
515 | + */ |
||
516 | + reg = IFX_REG_R32(PCIE_INTRBCTRL(pcie_port)); |
||
517 | + reg |= PCIE_INTRBCTRL_SERR_ENABLE | PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE; |
||
518 | + |
||
519 | + IFX_REG_W32(reg, PCIE_INTRBCTRL(pcie_port)); |
||
520 | + |
||
521 | + /* Uncorrectable Error Mask Register, Unmask <enable> all bits in PCIE_UESR */ |
||
522 | + reg = IFX_REG_R32(PCIE_UEMR(pcie_port)); |
||
523 | + reg &= ~PCIE_ALL_UNCORRECTABLE_ERR; |
||
524 | + IFX_REG_W32(reg, PCIE_UEMR(pcie_port)); |
||
525 | + |
||
526 | + /* Uncorrectable Error Severity Register, ALL errors are FATAL */ |
||
527 | + IFX_REG_W32(PCIE_ALL_UNCORRECTABLE_ERR, PCIE_UESR(pcie_port)); |
||
528 | + |
||
529 | + /* Correctable Error Mask Register, unmask <enable> all bits */ |
||
530 | + reg = IFX_REG_R32(PCIE_CEMR(pcie_port)); |
||
531 | + reg &= ~PCIE_CORRECTABLE_ERR; |
||
532 | + IFX_REG_W32(reg, PCIE_CEMR(pcie_port)); |
||
533 | + |
||
534 | + /* Advanced Error Capabilities and Control Registr */ |
||
535 | + reg = IFX_REG_R32(PCIE_AECCR(pcie_port)); |
||
536 | + reg |= PCIE_AECCR_ECRC_CHECK_EN | PCIE_AECCR_ECRC_GEN_EN; |
||
537 | + IFX_REG_W32(reg, PCIE_AECCR(pcie_port)); |
||
538 | + |
||
539 | + /* Root Error Command Register, Report all types of errors */ |
||
540 | + reg = IFX_REG_R32(PCIE_RECR(pcie_port)); |
||
541 | + reg |= PCIE_RECR_ERR_REPORT_EN; |
||
542 | + IFX_REG_W32(reg, PCIE_RECR(pcie_port)); |
||
543 | + |
||
544 | + /* Clear the Root status register */ |
||
545 | + reg = IFX_REG_R32(PCIE_RESR(pcie_port)); |
||
546 | + IFX_REG_W32(reg, PCIE_RESR(pcie_port)); |
||
547 | +} |
||
548 | + |
||
549 | +static inline void pcie_port_logic_setup(int pcie_port) |
||
550 | +{ |
||
551 | + u32 reg; |
||
552 | + |
||
553 | + /* FTS number, default 12, increase to 63, may increase time from/to L0s to L0 */ |
||
554 | + reg = IFX_REG_R32(PCIE_AFR(pcie_port)); |
||
555 | + reg &= ~(PCIE_AFR_FTS_NUM | PCIE_AFR_COM_FTS_NUM); |
||
556 | + reg |= SM(PCIE_AFR_FTS_NUM_DEFAULT, PCIE_AFR_FTS_NUM) |
||
557 | + | SM(PCIE_AFR_FTS_NUM_DEFAULT, PCIE_AFR_COM_FTS_NUM); |
||
558 | + /* L0s and L1 entry latency */ |
||
559 | + reg &= ~(PCIE_AFR_L0S_ENTRY_LATENCY | PCIE_AFR_L1_ENTRY_LATENCY); |
||
560 | + reg |= SM(PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT, PCIE_AFR_L0S_ENTRY_LATENCY) |
||
561 | + | SM(PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT, PCIE_AFR_L1_ENTRY_LATENCY); |
||
562 | + IFX_REG_W32(reg, PCIE_AFR(pcie_port)); |
||
563 | + |
||
564 | + |
||
565 | + /* Port Link Control Register */ |
||
566 | + reg = IFX_REG_R32(PCIE_PLCR(pcie_port)); |
||
567 | + reg |= PCIE_PLCR_DLL_LINK_EN; /* Enable the DLL link */ |
||
568 | + IFX_REG_W32(reg, PCIE_PLCR(pcie_port)); |
||
569 | + |
||
570 | + /* Lane Skew Register */ |
||
571 | + reg = IFX_REG_R32(PCIE_LSR(pcie_port)); |
||
572 | + /* Enable ACK/NACK and FC */ |
||
573 | + reg &= ~(PCIE_LSR_ACKNAK_DISABLE | PCIE_LSR_FC_DISABLE); |
||
574 | + IFX_REG_W32(reg, PCIE_LSR(pcie_port)); |
||
575 | + |
||
576 | + /* Symbol Timer Register and Filter Mask Register 1 */ |
||
577 | + reg = IFX_REG_R32(PCIE_STRFMR(pcie_port)); |
||
578 | + |
||
579 | + /* Default SKP interval is very accurate already, 5us */ |
||
580 | + /* Enable IO/CFG transaction */ |
||
581 | + reg |= PCIE_STRFMR_RX_CFG_TRANS_ENABLE | PCIE_STRFMR_RX_IO_TRANS_ENABLE; |
||
582 | + /* Disable FC WDT */ |
||
583 | + reg &= ~PCIE_STRFMR_FC_WDT_DISABLE; |
||
584 | + IFX_REG_W32(reg, PCIE_STRFMR(pcie_port)); |
||
585 | + |
||
586 | + /* Filter Masker Register 2 */ |
||
587 | + reg = IFX_REG_R32(PCIE_FMR2(pcie_port)); |
||
588 | + reg |= PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 | PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1; |
||
589 | + IFX_REG_W32(reg, PCIE_FMR2(pcie_port)); |
||
590 | + |
||
591 | + /* VC0 Completion Receive Queue Control Register */ |
||
592 | + reg = IFX_REG_R32(PCIE_VC0_CRQCR(pcie_port)); |
||
593 | + reg &= ~PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE; |
||
594 | + reg |= SM(PCIE_VC0_TLP_QUEUE_MODE_BYPASS, PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE); |
||
595 | + IFX_REG_W32(reg, PCIE_VC0_CRQCR(pcie_port)); |
||
596 | +} |
||
597 | + |
||
598 | +static inline void pcie_rc_cfg_reg_setup(int pcie_port) |
||
599 | +{ |
||
600 | + u32 reg; |
||
601 | + |
||
602 | + /* Disable LTSSM */ |
||
603 | + IFX_REG_W32(0, PCIE_RC_CCR(pcie_port)); /* Disable LTSSM */ |
||
604 | + |
||
605 | + pcie_mem_io_setup(pcie_port); |
||
606 | + |
||
607 | + /* XXX, MSI stuff should only apply to EP */ |
||
608 | + /* MSI Capability: Only enable 32-bit addresses */ |
||
609 | + reg = IFX_REG_R32(PCIE_MCAPR(pcie_port)); |
||
610 | + reg &= ~PCIE_MCAPR_ADDR64_CAP; |
||
611 | + |
||
612 | + reg |= PCIE_MCAPR_MSI_ENABLE; |
||
613 | + |
||
614 | + /* Disable multiple message */ |
||
615 | + reg &= ~(PCIE_MCAPR_MULTI_MSG_CAP | PCIE_MCAPR_MULTI_MSG_ENABLE); |
||
616 | + IFX_REG_W32(reg, PCIE_MCAPR(pcie_port)); |
||
617 | + |
||
618 | + |
||
619 | + /* Enable PME, Soft reset enabled */ |
||
620 | + reg = IFX_REG_R32(PCIE_PM_CSR(pcie_port)); |
||
621 | + reg |= PCIE_PM_CSR_PME_ENABLE | PCIE_PM_CSR_SW_RST; |
||
622 | + IFX_REG_W32(reg, PCIE_PM_CSR(pcie_port)); |
||
623 | + |
||
624 | + /* setup the bus */ |
||
625 | + reg = SM(0, PCIE_BNR_PRIMARY_BUS_NUM) | SM(1, PCIE_PNR_SECONDARY_BUS_NUM) | SM(0xFF, PCIE_PNR_SUB_BUS_NUM); |
||
626 | + IFX_REG_W32(reg, PCIE_BNR(pcie_port)); |
||
627 | + |
||
628 | + |
||
629 | + pcie_device_setup(pcie_port); |
||
630 | + pcie_link_setup(pcie_port); |
||
631 | + pcie_error_setup(pcie_port); |
||
632 | + |
||
633 | + /* Root control and capabilities register */ |
||
634 | + reg = IFX_REG_R32(PCIE_RCTLCAP(pcie_port)); |
||
635 | + reg |= PCIE_RCTLCAP_SERR_ENABLE | PCIE_RCTLCAP_PME_INT_EN; |
||
636 | + IFX_REG_W32(reg, PCIE_RCTLCAP(pcie_port)); |
||
637 | + |
||
638 | + /* Port VC Capability Register 2 */ |
||
639 | + reg = IFX_REG_R32(PCIE_PVC2(pcie_port)); |
||
640 | + reg &= ~PCIE_PVC2_VC_ARB_WRR; |
||
641 | + reg |= PCIE_PVC2_VC_ARB_16P_FIXED_WRR; |
||
642 | + IFX_REG_W32(reg, PCIE_PVC2(pcie_port)); |
||
643 | + |
||
644 | + /* VC0 Resource Capability Register */ |
||
645 | + reg = IFX_REG_R32(PCIE_VC0_RC(pcie_port)); |
||
646 | + reg &= ~PCIE_VC0_RC_REJECT_SNOOP; |
||
647 | + IFX_REG_W32(reg, PCIE_VC0_RC(pcie_port)); |
||
648 | + |
||
649 | + pcie_port_logic_setup(pcie_port); |
||
650 | +} |
||
651 | + |
||
652 | +static int ifx_pcie_wait_phy_link_up(int pcie_port) |
||
653 | +{ |
||
654 | +#define IFX_PCIE_PHY_LINK_UP_TIMEOUT 1000 /* XXX, tunable */ |
||
655 | + int i; |
||
656 | + |
||
657 | + /* Wait for PHY link is up */ |
||
658 | + for (i = 0; i < IFX_PCIE_PHY_LINK_UP_TIMEOUT; i++) { |
||
659 | + if (ifx_pcie_link_up(pcie_port)) { |
||
660 | + break; |
||
661 | + } |
||
662 | + udelay(100); |
||
663 | + } |
||
664 | + if (i >= IFX_PCIE_PHY_LINK_UP_TIMEOUT) { |
||
665 | + printk(KERN_ERR "%s timeout\n", __func__); |
||
666 | + return -1; |
||
667 | + } |
||
668 | + |
||
669 | + /* Check data link up or not */ |
||
670 | + if (!(IFX_REG_R32(PCIE_RC_DR(pcie_port)) & PCIE_RC_DR_DLL_UP)) { |
||
671 | + printk(KERN_ERR "%s DLL link is still down\n", __func__); |
||
672 | + return -1; |
||
673 | + } |
||
674 | + |
||
675 | + /* Check Data link active or not */ |
||
676 | + if (!(IFX_REG_R32(PCIE_LCTLSTS(pcie_port)) & PCIE_LCTLSTS_DLL_ACTIVE)) { |
||
677 | + printk(KERN_ERR "%s DLL is not active\n", __func__); |
||
678 | + return -1; |
||
679 | + } |
||
680 | + return 0; |
||
681 | +} |
||
682 | + |
||
683 | +static inline int pcie_app_loigc_setup(int pcie_port) |
||
684 | +{ |
||
685 | + /* supress ahb bus errrors */ |
||
686 | + IFX_REG_W32(PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS, PCIE_AHB_CTRL(pcie_port)); |
||
687 | + |
||
688 | + /* Pull PCIe EP out of reset */ |
||
689 | + pcie_device_rst_deassert(pcie_port); |
||
690 | + |
||
691 | + /* Start LTSSM training between RC and EP */ |
||
692 | + pcie_ltssm_enable(pcie_port); |
||
693 | + |
||
694 | + /* Check PHY status after enabling LTSSM */ |
||
695 | + if (ifx_pcie_wait_phy_link_up(pcie_port) != 0) |
||
696 | + return -1; |
||
697 | + |
||
698 | + return 0; |
||
699 | +} |
||
700 | + |
||
701 | +/* |
||
702 | + * The numbers below are directly from the PCIe spec table 3-4/5. |
||
703 | + */ |
||
704 | +static inline void pcie_replay_time_update(int pcie_port) |
||
705 | +{ |
||
706 | + u32 reg; |
||
707 | + int nlw; |
||
708 | + int rtl; |
||
709 | + |
||
710 | + reg = IFX_REG_R32(PCIE_LCTLSTS(pcie_port)); |
||
711 | + |
||
712 | + nlw = MS(reg, PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH); |
||
713 | + switch (nlw) { |
||
714 | + case PCIE_MAX_LENGTH_WIDTH_X1: |
||
715 | + rtl = 1677; |
||
716 | + break; |
||
717 | + case PCIE_MAX_LENGTH_WIDTH_X2: |
||
718 | + rtl = 867; |
||
719 | + break; |
||
720 | + case PCIE_MAX_LENGTH_WIDTH_X4: |
||
721 | + rtl = 462; |
||
722 | + break; |
||
723 | + case PCIE_MAX_LENGTH_WIDTH_X8: |
||
724 | + rtl = 258; |
||
725 | + break; |
||
726 | + default: |
||
727 | + rtl = 1677; |
||
728 | + break; |
||
729 | + } |
||
730 | + reg = IFX_REG_R32(PCIE_ALTRT(pcie_port)); |
||
731 | + reg &= ~PCIE_ALTRT_REPLAY_TIME_LIMIT; |
||
732 | + reg |= SM(rtl, PCIE_ALTRT_REPLAY_TIME_LIMIT); |
||
733 | + IFX_REG_W32(reg, PCIE_ALTRT(pcie_port)); |
||
734 | +} |
||
735 | + |
||
736 | +/* |
||
737 | + * Table 359 Enhanced Configuration Address Mapping1) |
||
738 | + * 1) This table is defined in Table 7-1, page 341, PCI Express Base Specification v1.1 |
||
739 | + * Memory Address PCI Express Configuration Space |
||
740 | + * A[(20+n-1):20] Bus Number 1 < n < 8 |
||
741 | + * A[19:15] Device Number |
||
742 | + * A[14:12] Function Number |
||
743 | + * A[11:8] Extended Register Number |
||
744 | + * A[7:2] Register Number |
||
745 | + * A[1:0] Along with size of the access, used to generate Byte Enables |
||
746 | + * For VR9, only the address bits [22:0] are mapped to the configuration space: |
||
747 | + * . Address bits [22:20] select the target bus (1-of-8)1) |
||
748 | + * . Address bits [19:15] select the target device (1-of-32) on the bus |
||
749 | + * . Address bits [14:12] select the target function (1-of-8) within the device. |
||
750 | + * . Address bits [11:2] selects the target dword (1-of-1024) within the selected function.s configuration space |
||
751 | + * . Address bits [1:0] define the start byte location within the selected dword. |
||
752 | + */ |
||
753 | +static inline u32 pcie_bus_addr(u8 bus_num, u16 devfn, int where) |
||
754 | +{ |
||
755 | + u32 addr; |
||
756 | + u8 bus; |
||
757 | + |
||
758 | + if (!bus_num) { |
||
759 | + /* type 0 */ |
||
760 | + addr = ((PCI_SLOT(devfn) & 0x1F) << 15) | ((PCI_FUNC(devfn) & 0x7) << 12) | ((where & 0xFFF)& ~3); |
||
761 | + } else { |
||
762 | + bus = bus_num; |
||
763 | + /* type 1, only support 8 buses */ |
||
764 | + addr = ((bus & 0x7) << 20) | ((PCI_SLOT(devfn) & 0x1F) << 15) | |
||
765 | + ((PCI_FUNC(devfn) & 0x7) << 12) | ((where & 0xFFF) & ~3); |
||
766 | + } |
||
767 | + return addr; |
||
768 | +} |
||
769 | + |
||
770 | +static int pcie_valid_config(int pcie_port, int bus, int dev) |
||
771 | +{ |
||
772 | + /* RC itself */ |
||
773 | + if ((bus == 0) && (dev == 0)) { |
||
774 | + return 1; |
||
775 | + } |
||
776 | + |
||
777 | + /* No physical link */ |
||
778 | + if (!ifx_pcie_link_up(pcie_port)) { |
||
779 | + return 0; |
||
780 | + } |
||
781 | + |
||
782 | + /* Bus zero only has RC itself |
||
783 | + * XXX, check if EP will be integrated |
||
784 | + */ |
||
785 | + if ((bus == 0) && (dev != 0)) { |
||
786 | + return 0; |
||
787 | + } |
||
788 | + |
||
789 | + /* Maximum 8 buses supported for VRX */ |
||
790 | + if (bus > 9) { |
||
791 | + return 0; |
||
792 | + } |
||
793 | + |
||
794 | + /* |
||
795 | + * PCIe is PtP link, one bus only supports only one device |
||
796 | + * except bus zero and PCIe switch which is virtual bus device |
||
797 | + * The following two conditions really depends on the system design |
||
798 | + * and attached the device. |
||
799 | + * XXX, how about more new switch |
||
800 | + */ |
||
801 | + if ((bus == 1) && (dev != 0)) { |
||
802 | + return 0; |
||
803 | + } |
||
804 | + |
||
805 | + if ((bus >= 3) && (dev != 0)) { |
||
806 | + return 0; |
||
807 | + } |
||
808 | + return 1; |
||
809 | +} |
||
810 | + |
||
811 | +static inline u32 ifx_pcie_cfg_rd(int pcie_port, u32 reg) |
||
812 | +{ |
||
813 | + return IFX_REG_R32((volatile u32 *)(PCIE_CFG_PORT_TO_BASE(pcie_port) + reg)); |
||
814 | +} |
||
815 | + |
||
816 | +static inline void ifx_pcie_cfg_wr(int pcie_port, unsigned int reg, u32 val) |
||
817 | +{ |
||
818 | + IFX_REG_W32( val, (volatile u32 *)(PCIE_CFG_PORT_TO_BASE(pcie_port) + reg)); |
||
819 | +} |
||
820 | + |
||
821 | +static inline u32 ifx_pcie_rc_cfg_rd(int pcie_port, u32 reg) |
||
822 | +{ |
||
823 | + return IFX_REG_R32((volatile u32 *)(PCIE_RC_PORT_TO_BASE(pcie_port) + reg)); |
||
824 | +} |
||
825 | + |
||
826 | +static inline void ifx_pcie_rc_cfg_wr(int pcie_port, unsigned int reg, u32 val) |
||
827 | +{ |
||
828 | + IFX_REG_W32(val, (volatile u32 *)(PCIE_RC_PORT_TO_BASE(pcie_port) + reg)); |
||
829 | +} |
||
830 | + |
||
831 | +u32 ifx_pcie_bus_enum_read_hack(int where, u32 value) |
||
832 | +{ |
||
833 | + u32 tvalue = value; |
||
834 | + |
||
835 | + if (where == PCI_PRIMARY_BUS) { |
||
836 | + u8 primary, secondary, subordinate; |
||
837 | + |
||
838 | + primary = tvalue & 0xFF; |
||
839 | + secondary = (tvalue >> 8) & 0xFF; |
||
840 | + subordinate = (tvalue >> 16) & 0xFF; |
||
841 | + primary += pcibios_1st_host_bus_nr(); |
||
842 | + secondary += pcibios_1st_host_bus_nr(); |
||
843 | + subordinate += pcibios_1st_host_bus_nr(); |
||
844 | + tvalue = (tvalue & 0xFF000000) | (u32)primary | (u32)(secondary << 8) | (u32)(subordinate << 16); |
||
845 | + } |
||
846 | + return tvalue; |
||
847 | +} |
||
848 | + |
||
849 | +u32 ifx_pcie_bus_enum_write_hack(int where, u32 value) |
||
850 | +{ |
||
851 | + u32 tvalue = value; |
||
852 | + |
||
853 | + if (where == PCI_PRIMARY_BUS) { |
||
854 | + u8 primary, secondary, subordinate; |
||
855 | + |
||
856 | + primary = tvalue & 0xFF; |
||
857 | + secondary = (tvalue >> 8) & 0xFF; |
||
858 | + subordinate = (tvalue >> 16) & 0xFF; |
||
859 | + if (primary > 0 && primary != 0xFF) { |
||
860 | + primary -= pcibios_1st_host_bus_nr(); |
||
861 | + } |
||
862 | + |
||
863 | + if (secondary > 0 && secondary != 0xFF) { |
||
864 | + secondary -= pcibios_1st_host_bus_nr(); |
||
865 | + } |
||
866 | + if (subordinate > 0 && subordinate != 0xFF) { |
||
867 | + subordinate -= pcibios_1st_host_bus_nr(); |
||
868 | + } |
||
869 | + tvalue = (tvalue & 0xFF000000) | (u32)primary | (u32)(secondary << 8) | (u32)(subordinate << 16); |
||
870 | + } |
||
871 | + else if (where == PCI_SUBORDINATE_BUS) { |
||
872 | + u8 subordinate = tvalue & 0xFF; |
||
873 | + |
||
874 | + subordinate = subordinate > 0 ? subordinate - pcibios_1st_host_bus_nr() : 0; |
||
875 | + tvalue = subordinate; |
||
876 | + } |
||
877 | + return tvalue; |
||
878 | +} |
||
879 | + |
||
880 | +static int ifx_pcie_read_config(struct pci_bus *bus, u32 devfn, |
||
881 | + int where, int size, u32 *value) |
||
882 | +{ |
||
883 | + u32 data = 0; |
||
884 | + int bus_number = bus->number; |
||
885 | + static const u32 mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0}; |
||
886 | + int ret = PCIBIOS_SUCCESSFUL; |
||
887 | + struct ifx_pci_controller *ctrl = bus->sysdata; |
||
888 | + int pcie_port = ctrl->port; |
||
889 | + |
||
890 | + if (unlikely(size != 1 && size != 2 && size != 4)){ |
||
891 | + ret = PCIBIOS_BAD_REGISTER_NUMBER; |
||
892 | + goto out; |
||
893 | + } |
||
894 | + |
||
895 | + /* Make sure the address is aligned to natural boundary */ |
||
896 | + if (unlikely(((size - 1) & where))) { |
||
897 | + ret = PCIBIOS_BAD_REGISTER_NUMBER; |
||
898 | + goto out; |
||
899 | + } |
||
900 | + |
||
901 | + /* |
||
902 | + * If we are second controller, we have to cheat OS so that it assume |
||
903 | + * its bus number starts from 0 in host controller |
||
904 | + */ |
||
905 | + bus_number = ifx_pcie_bus_nr_deduct(bus_number, pcie_port); |
||
906 | + |
||
907 | + /* |
||
908 | + * We need to force the bus number to be zero on the root |
||
909 | + * bus. Linux numbers the 2nd root bus to start after all |
||
910 | + * busses on root 0. |
||
911 | + */ |
||
912 | + if (bus->parent == NULL) { |
||
913 | + bus_number = 0; |
||
914 | + } |
||
915 | + |
||
916 | + /* |
||
917 | + * PCIe only has a single device connected to it. It is |
||
918 | + * always device ID 0. Don't bother doing reads for other |
||
919 | + * device IDs on the first segment. |
||
920 | + */ |
||
921 | + if ((bus_number == 0) && (PCI_SLOT(devfn) != 0)) { |
||
922 | + ret = PCIBIOS_FUNC_NOT_SUPPORTED; |
||
923 | + goto out; |
||
924 | + } |
||
925 | + |
||
926 | + if (pcie_valid_config(pcie_port, bus_number, PCI_SLOT(devfn)) == 0) { |
||
927 | + *value = 0xffffffff; |
||
928 | + ret = PCIBIOS_DEVICE_NOT_FOUND; |
||
929 | + goto out; |
||
930 | + } |
||
931 | + |
||
932 | + PCIE_IRQ_LOCK(ifx_pcie_lock); |
||
933 | + if (bus_number == 0) { /* RC itself */ |
||
934 | + u32 t; |
||
935 | + |
||
936 | + t = (where & ~3); |
||
937 | + data = ifx_pcie_rc_cfg_rd(pcie_port, t); |
||
938 | + } else { |
||
939 | + u32 addr = pcie_bus_addr(bus_number, devfn, where); |
||
940 | + |
||
941 | + data = ifx_pcie_cfg_rd(pcie_port, addr); |
||
942 | + #ifdef CONFIG_IFX_PCIE_HW_SWAP |
||
943 | + data = le32_to_cpu(data); |
||
944 | + #endif /* CONFIG_IFX_PCIE_HW_SWAP */ |
||
945 | + } |
||
946 | + /* To get a correct PCI topology, we have to restore the bus number to OS */ |
||
947 | + data = ifx_pcie_bus_enum_hack(bus, devfn, where, data, pcie_port, 1); |
||
948 | + |
||
949 | + PCIE_IRQ_UNLOCK(ifx_pcie_lock); |
||
950 | + |
||
951 | + *value = (data >> (8 * (where & 3))) & mask[size & 7]; |
||
952 | +out: |
||
953 | + return ret; |
||
954 | +} |
||
955 | + |
||
956 | +static u32 ifx_pcie_size_to_value(int where, int size, u32 data, u32 value) |
||
957 | +{ |
||
958 | + u32 shift; |
||
959 | + u32 tdata = data; |
||
960 | + |
||
961 | + switch (size) { |
||
962 | + case 1: |
||
963 | + shift = (where & 0x3) << 3; |
||
964 | + tdata &= ~(0xffU << shift); |
||
965 | + tdata |= ((value & 0xffU) << shift); |
||
966 | + break; |
||
967 | + case 2: |
||
968 | + shift = (where & 3) << 3; |
||
969 | + tdata &= ~(0xffffU << shift); |
||
970 | + tdata |= ((value & 0xffffU) << shift); |
||
971 | + break; |
||
972 | + case 4: |
||
973 | + tdata = value; |
||
974 | + break; |
||
975 | + } |
||
976 | + return tdata; |
||
977 | +} |
||
978 | + |
||
979 | +static int ifx_pcie_write_config(struct pci_bus *bus, u32 devfn, |
||
980 | + int where, int size, u32 value) |
||
981 | +{ |
||
982 | + int bus_number = bus->number; |
||
983 | + int ret = PCIBIOS_SUCCESSFUL; |
||
984 | + struct ifx_pci_controller *ctrl = bus->sysdata; |
||
985 | + int pcie_port = ctrl->port; |
||
986 | + u32 tvalue = value; |
||
987 | + u32 data; |
||
988 | + |
||
989 | + /* Make sure the address is aligned to natural boundary */ |
||
990 | + if (unlikely(((size - 1) & where))) { |
||
991 | + ret = PCIBIOS_BAD_REGISTER_NUMBER; |
||
992 | + goto out; |
||
993 | + } |
||
994 | + /* |
||
995 | + * If we are second controller, we have to cheat OS so that it assume |
||
996 | + * its bus number starts from 0 in host controller |
||
997 | + */ |
||
998 | + bus_number = ifx_pcie_bus_nr_deduct(bus_number, pcie_port); |
||
999 | + |
||
1000 | + /* |
||
1001 | + * We need to force the bus number to be zero on the root |
||
1002 | + * bus. Linux numbers the 2nd root bus to start after all |
||
1003 | + * busses on root 0. |
||
1004 | + */ |
||
1005 | + if (bus->parent == NULL) { |
||
1006 | + bus_number = 0; |
||
1007 | + } |
||
1008 | + |
||
1009 | + if (pcie_valid_config(pcie_port, bus_number, PCI_SLOT(devfn)) == 0) { |
||
1010 | + ret = PCIBIOS_DEVICE_NOT_FOUND; |
||
1011 | + goto out; |
||
1012 | + } |
||
1013 | + |
||
1014 | + /* XXX, some PCIe device may need some delay */ |
||
1015 | + PCIE_IRQ_LOCK(ifx_pcie_lock); |
||
1016 | + |
||
1017 | + /* |
||
1018 | + * To configure the correct bus topology using native way, we have to cheat Os so that |
||
1019 | + * it can configure the PCIe hardware correctly. |
||
1020 | + */ |
||
1021 | + tvalue = ifx_pcie_bus_enum_hack(bus, devfn, where, value, pcie_port, 0); |
||
1022 | + |
||
1023 | + if (bus_number == 0) { /* RC itself */ |
||
1024 | + u32 t; |
||
1025 | + |
||
1026 | + t = (where & ~3); |
||
1027 | + data = ifx_pcie_rc_cfg_rd(pcie_port, t); |
||
1028 | + |
||
1029 | + data = ifx_pcie_size_to_value(where, size, data, tvalue); |
||
1030 | + |
||
1031 | + ifx_pcie_rc_cfg_wr(pcie_port, t, data); |
||
1032 | + } else { |
||
1033 | + u32 addr = pcie_bus_addr(bus_number, devfn, where); |
||
1034 | + |
||
1035 | + data = ifx_pcie_cfg_rd(pcie_port, addr); |
||
1036 | +#ifdef CONFIG_IFX_PCIE_HW_SWAP |
||
1037 | + data = le32_to_cpu(data); |
||
1038 | +#endif |
||
1039 | + |
||
1040 | + data = ifx_pcie_size_to_value(where, size, data, tvalue); |
||
1041 | +#ifdef CONFIG_IFX_PCIE_HW_SWAP |
||
1042 | + data = cpu_to_le32(data); |
||
1043 | +#endif |
||
1044 | + ifx_pcie_cfg_wr(pcie_port, addr, data); |
||
1045 | + } |
||
1046 | + PCIE_IRQ_UNLOCK(ifx_pcie_lock); |
||
1047 | +out: |
||
1048 | + return ret; |
||
1049 | +} |
||
1050 | + |
||
1051 | +static struct resource ifx_pcie_io_resource = { |
||
1052 | + .name = "PCIe0 I/O space", |
||
1053 | + .start = PCIE_IO_PHY_BASE, |
||
1054 | + .end = PCIE_IO_PHY_END, |
||
1055 | + .flags = IORESOURCE_IO, |
||
1056 | +}; |
||
1057 | + |
||
1058 | +static struct resource ifx_pcie_mem_resource = { |
||
1059 | + .name = "PCIe0 Memory space", |
||
1060 | + .start = PCIE_MEM_PHY_BASE, |
||
1061 | + .end = PCIE_MEM_PHY_END, |
||
1062 | + .flags = IORESOURCE_MEM, |
||
1063 | +}; |
||
1064 | + |
||
1065 | +static struct pci_ops ifx_pcie_ops = { |
||
1066 | + .read = ifx_pcie_read_config, |
||
1067 | + .write = ifx_pcie_write_config, |
||
1068 | +}; |
||
1069 | + |
||
1070 | +static struct ifx_pci_controller ifx_pcie_controller[IFX_PCIE_CORE_NR] = { |
||
1071 | + { |
||
1072 | + .pcic = { |
||
1073 | + .pci_ops = &ifx_pcie_ops, |
||
1074 | + .mem_resource = &ifx_pcie_mem_resource, |
||
1075 | + .io_resource = &ifx_pcie_io_resource, |
||
1076 | + }, |
||
1077 | + .port = IFX_PCIE_PORT0, |
||
1078 | + }, |
||
1079 | +}; |
||
1080 | + |
||
1081 | +#ifdef IFX_PCIE_ERROR_INT |
||
1082 | + |
||
1083 | +static irqreturn_t pcie_rc_core_isr(int irq, void *dev_id) |
||
1084 | +{ |
||
1085 | + struct ifx_pci_controller *ctrl = (struct ifx_pci_controller *)dev_id; |
||
1086 | + int pcie_port = ctrl->port; |
||
1087 | + u32 reg; |
||
1088 | + |
||
1089 | + pr_debug("PCIe RC error intr %d\n", irq); |
||
1090 | + reg = IFX_REG_R32(PCIE_IRNCR(pcie_port)); |
||
1091 | + reg &= PCIE_RC_CORE_COMBINED_INT; |
||
1092 | + IFX_REG_W32(reg, PCIE_IRNCR(pcie_port)); |
||
1093 | + |
||
1094 | + return IRQ_HANDLED; |
||
1095 | +} |
||
1096 | + |
||
1097 | +static int |
||
1098 | +pcie_rc_core_int_init(int pcie_port) |
||
1099 | +{ |
||
1100 | + int ret; |
||
1101 | + |
||
1102 | + /* Enable core interrupt */ |
||
1103 | + IFX_REG_SET_BIT(PCIE_RC_CORE_COMBINED_INT, PCIE_IRNEN(pcie_port)); |
||
1104 | + |
||
1105 | + /* Clear it first */ |
||
1106 | + IFX_REG_SET_BIT(PCIE_RC_CORE_COMBINED_INT, PCIE_IRNCR(pcie_port)); |
||
1107 | + ret = request_irq(pcie_irqs[pcie_port].ir_irq.irq, pcie_rc_core_isr, 0, |
||
1108 | + pcie_irqs[pcie_port].ir_irq.name, &ifx_pcie_controller[pcie_port]); |
||
1109 | + if (ret) |
||
1110 | + printk(KERN_ERR "%s request irq %d failed\n", __func__, IFX_PCIE_IR); |
||
1111 | + |
||
1112 | + return ret; |
||
1113 | +} |
||
1114 | +#endif |
||
1115 | + |
||
1116 | +int ifx_pcie_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin) |
||
1117 | +{ |
||
1118 | + u32 irq_bit = 0; |
||
1119 | + int irq = 0; |
||
1120 | + struct ifx_pci_controller *ctrl = dev->bus->sysdata; |
||
1121 | + int pcie_port = ctrl->port; |
||
1122 | + |
||
1123 | + printk("%s port %d dev %s slot %d pin %d \n", __func__, pcie_port, pci_name(dev), slot, pin); |
||
1124 | + |
||
1125 | + if ((pin == PCIE_LEGACY_DISABLE) || (pin > PCIE_LEGACY_INT_MAX)) { |
||
1126 | + printk(KERN_WARNING "WARNING: dev %s: invalid interrupt pin %d\n", pci_name(dev), pin); |
||
1127 | + return -1; |
||
1128 | + } |
||
1129 | + |
||
1130 | + /* Pin index so minus one */ |
||
1131 | + irq_bit = pcie_irqs[pcie_port].legacy_irq[pin - 1].irq_bit; |
||
1132 | + irq = pcie_irqs[pcie_port].legacy_irq[pin - 1].irq; |
||
1133 | + IFX_REG_SET_BIT(irq_bit, PCIE_IRNEN(pcie_port)); |
||
1134 | + IFX_REG_SET_BIT(irq_bit, PCIE_IRNCR(pcie_port)); |
||
1135 | + printk("%s dev %s irq %d assigned\n", __func__, pci_name(dev), irq); |
||
1136 | + return irq; |
||
1137 | +} |
||
1138 | + |
||
1139 | +int ifx_pcie_bios_plat_dev_init(struct pci_dev *dev) |
||
1140 | +{ |
||
1141 | + u16 config; |
||
1142 | +#ifdef IFX_PCIE_ERROR_INT |
||
1143 | + u32 dconfig; |
||
1144 | + int pos; |
||
1145 | +#endif |
||
1146 | + |
||
1147 | + /* Enable reporting System errors and parity errors on all devices */ |
||
1148 | + /* Enable parity checking and error reporting */ |
||
1149 | + pci_read_config_word(dev, PCI_COMMAND, &config); |
||
1150 | + config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR /*| PCI_COMMAND_INVALIDATE | |
||
1151 | + PCI_COMMAND_FAST_BACK*/; |
||
1152 | + pci_write_config_word(dev, PCI_COMMAND, config); |
||
1153 | + |
||
1154 | + if (dev->subordinate) { |
||
1155 | + /* Set latency timers on sub bridges */ |
||
1156 | + pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 0x40); /* XXX, */ |
||
1157 | + /* More bridge error detection */ |
||
1158 | + pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config); |
||
1159 | + config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR; |
||
1160 | + pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config); |
||
1161 | + } |
||
1162 | +#ifdef IFX_PCIE_ERROR_INT |
||
1163 | + /* Enable the PCIe normal error reporting */ |
||
1164 | + pos = pci_find_capability(dev, PCI_CAP_ID_EXP); |
||
1165 | + if (pos) { |
||
1166 | + |
||
1167 | + /* Disable system error generation in response to error messages */ |
||
1168 | + pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &config); |
||
1169 | + config &= ~(PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | PCI_EXP_RTCTL_SEFEE); |
||
1170 | + pci_write_config_word(dev, pos + PCI_EXP_RTCTL, config); |
||
1171 | + |
||
1172 | + /* Clear PCIE Capability's Device Status */ |
||
1173 | + pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &config); |
||
1174 | + pci_write_config_word(dev, pos + PCI_EXP_DEVSTA, config); |
||
1175 | + |
||
1176 | + /* Update Device Control */ |
||
1177 | + pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config); |
||
1178 | + /* Correctable Error Reporting */ |
||
1179 | + config |= PCI_EXP_DEVCTL_CERE; |
||
1180 | + /* Non-Fatal Error Reporting */ |
||
1181 | + config |= PCI_EXP_DEVCTL_NFERE; |
||
1182 | + /* Fatal Error Reporting */ |
||
1183 | + config |= PCI_EXP_DEVCTL_FERE; |
||
1184 | + /* Unsupported Request */ |
||
1185 | + config |= PCI_EXP_DEVCTL_URRE; |
||
1186 | + pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config); |
||
1187 | + } |
||
1188 | + |
||
1189 | + /* Find the Advanced Error Reporting capability */ |
||
1190 | + pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); |
||
1191 | + if (pos) { |
||
1192 | + /* Clear Uncorrectable Error Status */ |
||
1193 | + pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &dconfig); |
||
1194 | + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, dconfig); |
||
1195 | + /* Enable reporting of all uncorrectable errors */ |
||
1196 | + /* Uncorrectable Error Mask - turned on bits disable errors */ |
||
1197 | + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0); |
||
1198 | + /* |
||
1199 | + * Leave severity at HW default. This only controls if |
||
1200 | + * errors are reported as uncorrectable or |
||
1201 | + * correctable, not if the error is reported. |
||
1202 | + */ |
||
1203 | + /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */ |
||
1204 | + /* Clear Correctable Error Status */ |
||
1205 | + pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig); |
||
1206 | + pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig); |
||
1207 | + /* Enable reporting of all correctable errors */ |
||
1208 | + /* Correctable Error Mask - turned on bits disable errors */ |
||
1209 | + pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0); |
||
1210 | + /* Advanced Error Capabilities */ |
||
1211 | + pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig); |
||
1212 | + /* ECRC Generation Enable */ |
||
1213 | + if (dconfig & PCI_ERR_CAP_ECRC_GENC) { |
||
1214 | + dconfig |= PCI_ERR_CAP_ECRC_GENE; |
||
1215 | + } |
||
1216 | + /* ECRC Check Enable */ |
||
1217 | + if (dconfig & PCI_ERR_CAP_ECRC_CHKC) { |
||
1218 | + dconfig |= PCI_ERR_CAP_ECRC_CHKE; |
||
1219 | + } |
||
1220 | + pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig); |
||
1221 | + |
||
1222 | + /* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */ |
||
1223 | + /* Enable Root Port's interrupt in response to error messages */ |
||
1224 | + pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, |
||
1225 | + PCI_ERR_ROOT_CMD_COR_EN | |
||
1226 | + PCI_ERR_ROOT_CMD_NONFATAL_EN | |
||
1227 | + PCI_ERR_ROOT_CMD_FATAL_EN); |
||
1228 | + /* Clear the Root status register */ |
||
1229 | + pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig); |
||
1230 | + pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig); |
||
1231 | + } |
||
1232 | +#endif /* IFX_PCIE_ERROR_INT */ |
||
1233 | + /* WAR, only 128 MRRS is supported, force all EPs to support this value */ |
||
1234 | + pcie_set_readrq(dev, 128); |
||
1235 | + return 0; |
||
1236 | +} |
||
1237 | + |
||
1238 | +static int |
||
1239 | +pcie_rc_initialize(int pcie_port) |
||
1240 | +{ |
||
1241 | + int i; |
||
1242 | +#define IFX_PCIE_PHY_LOOP_CNT 5 |
||
1243 | + |
||
1244 | + pcie_rcu_endian_setup(pcie_port); |
||
1245 | + |
||
1246 | + pcie_ep_gpio_rst_init(pcie_port); |
||
1247 | + |
||
1248 | + /* |
||
1249 | + * XXX, PCIe elastic buffer bug will cause not to be detected. One more |
||
1250 | + * reset PCIe PHY will solve this issue |
||
1251 | + */ |
||
1252 | + for (i = 0; i < IFX_PCIE_PHY_LOOP_CNT; i++) { |
||
1253 | + /* Disable PCIe PHY Analog part for sanity check */ |
||
1254 | + pcie_phy_pmu_disable(pcie_port); |
||
1255 | + |
||
1256 | + pcie_phy_rst_assert(pcie_port); |
||
1257 | + pcie_phy_rst_deassert(pcie_port); |
||
1258 | + |
||
1259 | + /* Make sure PHY PLL is stable */ |
||
1260 | + udelay(20); |
||
1261 | + |
||
1262 | + /* PCIe Core reset enabled, low active, sw programmed */ |
||
1263 | + pcie_core_rst_assert(pcie_port); |
||
1264 | + |
||
1265 | + /* Put PCIe EP in reset status */ |
||
1266 | + pcie_device_rst_assert(pcie_port); |
||
1267 | + |
||
1268 | + /* PCI PHY & Core reset disabled, high active, sw programmed */ |
||
1269 | + pcie_core_rst_deassert(pcie_port); |
||
1270 | + |
||
1271 | + /* Already in a quiet state, program PLL, enable PHY, check ready bit */ |
||
1272 | + pcie_phy_clock_mode_setup(pcie_port); |
||
1273 | + |
||
1274 | + /* Enable PCIe PHY and Clock */ |
||
1275 | + pcie_core_pmu_setup(pcie_port); |
||
1276 | + |
||
1277 | + /* Clear status registers */ |
||
1278 | + pcie_status_register_clear(pcie_port); |
||
1279 | + |
||
1280 | +#ifdef CONFIG_PCI_MSI |
||
1281 | + pcie_msi_init(pcie_port); |
||
1282 | +#endif /* CONFIG_PCI_MSI */ |
||
1283 | + pcie_rc_cfg_reg_setup(pcie_port); |
||
1284 | + |
||
1285 | + /* Once link is up, break out */ |
||
1286 | + if (pcie_app_loigc_setup(pcie_port) == 0) |
||
1287 | + break; |
||
1288 | + } |
||
1289 | + if (i >= IFX_PCIE_PHY_LOOP_CNT) { |
||
1290 | + printk(KERN_ERR "%s link up failed!!!!!\n", __func__); |
||
1291 | + return -EIO; |
||
1292 | + } |
||
1293 | + /* NB, don't increase ACK/NACK timer timeout value, which will cause a lot of COR errors */ |
||
1294 | + pcie_replay_time_update(pcie_port); |
||
1295 | + return 0; |
||
1296 | +} |
||
1297 | + |
||
1298 | +static int __init ifx_pcie_bios_init(void) |
||
1299 | +{ |
||
1300 | + void __iomem *io_map_base; |
||
1301 | + int pcie_port; |
||
1302 | + int startup_port; |
||
1303 | + |
||
1304 | + /* Enable AHB Master/ Slave */ |
||
1305 | + pcie_ahb_pmu_setup(); |
||
1306 | + |
||
1307 | + startup_port = IFX_PCIE_PORT0; |
||
1308 | + |
||
1309 | + for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){ |
||
1310 | + if (pcie_rc_initialize(pcie_port) == 0) { |
||
1311 | + IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n", |
||
1312 | + __func__, PCIE_CFG_PORT_TO_BASE(pcie_port)); |
||
1313 | + /* Otherwise, warning will pop up */ |
||
1314 | + io_map_base = ioremap(PCIE_IO_PHY_PORT_TO_BASE(pcie_port), PCIE_IO_SIZE); |
||
1315 | + if (io_map_base == NULL) { |
||
1316 | + IFX_PCIE_PRINT(PCIE_MSG_ERR, "%s io space ioremap failed\n", __func__); |
||
1317 | + return -ENOMEM; |
||
1318 | + } |
||
1319 | + ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base; |
||
1320 | + |
||
1321 | + register_pci_controller(&ifx_pcie_controller[pcie_port].pcic); |
||
1322 | + /* XXX, clear error status */ |
||
1323 | + |
||
1324 | + IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: mem_resource 0x%p, io_resource 0x%p\n", |
||
1325 | + __func__, &ifx_pcie_controller[pcie_port].pcic.mem_resource, |
||
1326 | + &ifx_pcie_controller[pcie_port].pcic.io_resource); |
||
1327 | + |
||
1328 | + #ifdef IFX_PCIE_ERROR_INT |
||
1329 | + pcie_rc_core_int_init(pcie_port); |
||
1330 | + #endif /* IFX_PCIE_ERROR_INT */ |
||
1331 | + } |
||
1332 | + } |
||
1333 | + |
||
1334 | + return 0; |
||
1335 | +} |
||
1336 | +arch_initcall(ifx_pcie_bios_init); |
||
1337 | + |
||
1338 | +MODULE_LICENSE("GPL"); |
||
1339 | +MODULE_AUTHOR("Chuanhua.Lei@infineon.com"); |
||
1340 | +MODULE_SUPPORTED_DEVICE("Infineon builtin PCIe RC module"); |
||
1341 | +MODULE_DESCRIPTION("Infineon builtin PCIe RC driver"); |
||
1342 | + |
||
1343 | --- /dev/null |
||
1344 | +++ b/arch/mips/pci/ifxmips_pcie.h |
||
1345 | @@ -0,0 +1,135 @@ |
||
1346 | +/****************************************************************************** |
||
1347 | +** |
||
1348 | +** FILE NAME : ifxmips_pcie.h |
||
1349 | +** PROJECT : IFX UEIP for VRX200 |
||
1350 | +** MODULES : PCIe module |
||
1351 | +** |
||
1352 | +** DATE : 02 Mar 2009 |
||
1353 | +** AUTHOR : Lei Chuanhua |
||
1354 | +** DESCRIPTION : PCIe Root Complex Driver |
||
1355 | +** COPYRIGHT : Copyright (c) 2009 |
||
1356 | +** Infineon Technologies AG |
||
1357 | +** Am Campeon 1-12, 85579 Neubiberg, Germany |
||
1358 | +** |
||
1359 | +** This program is free software; you can redistribute it and/or modify |
||
1360 | +** it under the terms of the GNU General Public License as published by |
||
1361 | +** the Free Software Foundation; either version 2 of the License, or |
||
1362 | +** (at your option) any later version. |
||
1363 | +** HISTORY |
||
1364 | +** $Version $Date $Author $Comment |
||
1365 | +** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version |
||
1366 | +*******************************************************************************/ |
||
1367 | +#ifndef IFXMIPS_PCIE_H |
||
1368 | +#define IFXMIPS_PCIE_H |
||
1369 | +#include <linux/version.h> |
||
1370 | +#include <linux/types.h> |
||
1371 | +#include <linux/pci.h> |
||
1372 | +#include <linux/interrupt.h> |
||
1373 | +#include "ifxmips_pci_common.h" |
||
1374 | +#include "ifxmips_pcie_reg.h" |
||
1375 | + |
||
1376 | +/*! |
||
1377 | + \defgroup IFX_PCIE PCI Express bus driver module |
||
1378 | + \brief PCI Express IP module support VRX200 |
||
1379 | +*/ |
||
1380 | + |
||
1381 | +/*! |
||
1382 | + \defgroup IFX_PCIE_OS OS APIs |
||
1383 | + \ingroup IFX_PCIE |
||
1384 | + \brief PCIe bus driver OS interface functions |
||
1385 | +*/ |
||
1386 | + |
||
1387 | +/*! |
||
1388 | + \file ifxmips_pcie.h |
||
1389 | + \ingroup IFX_PCIE |
||
1390 | + \brief header file for PCIe module common header file |
||
1391 | +*/ |
||
1392 | +#define PCIE_IRQ_LOCK(lock) do { \ |
||
1393 | + unsigned long flags; \ |
||
1394 | + spin_lock_irqsave(&(lock), flags); |
||
1395 | +#define PCIE_IRQ_UNLOCK(lock) \ |
||
1396 | + spin_unlock_irqrestore(&(lock), flags); \ |
||
1397 | +} while (0) |
||
1398 | + |
||
1399 | +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) |
||
1400 | +#define IRQF_SHARED SA_SHIRQ |
||
1401 | +#endif |
||
1402 | + |
||
1403 | +#define PCIE_MSG_MSI 0x00000001 |
||
1404 | +#define PCIE_MSG_ISR 0x00000002 |
||
1405 | +#define PCIE_MSG_FIXUP 0x00000004 |
||
1406 | +#define PCIE_MSG_READ_CFG 0x00000008 |
||
1407 | +#define PCIE_MSG_WRITE_CFG 0x00000010 |
||
1408 | +#define PCIE_MSG_CFG (PCIE_MSG_READ_CFG | PCIE_MSG_WRITE_CFG) |
||
1409 | +#define PCIE_MSG_REG 0x00000020 |
||
1410 | +#define PCIE_MSG_INIT 0x00000040 |
||
1411 | +#define PCIE_MSG_ERR 0x00000080 |
||
1412 | +#define PCIE_MSG_PHY 0x00000100 |
||
1413 | +#define PCIE_MSG_ANY 0x000001ff |
||
1414 | + |
||
1415 | +#define IFX_PCIE_PORT0 0 |
||
1416 | +#define IFX_PCIE_PORT1 1 |
||
1417 | + |
||
1418 | +#ifdef CONFIG_IFX_PCIE_2ND_CORE |
||
1419 | +#define IFX_PCIE_CORE_NR 2 |
||
1420 | +#else |
||
1421 | +#define IFX_PCIE_CORE_NR 1 |
||
1422 | +#endif |
||
1423 | + |
||
1424 | +#define IFX_PCIE_ERROR_INT |
||
1425 | + |
||
1426 | +//#define IFX_PCIE_DBG |
||
1427 | + |
||
1428 | +#if defined(IFX_PCIE_DBG) |
||
1429 | +#define IFX_PCIE_PRINT(_m, _fmt, args...) do { \ |
||
1430 | + ifx_pcie_debug((_fmt), ##args); \ |
||
1431 | +} while (0) |
||
1432 | + |
||
1433 | +#define INLINE |
||
1434 | +#else |
||
1435 | +#define IFX_PCIE_PRINT(_m, _fmt, args...) \ |
||
1436 | + do {} while(0) |
||
1437 | +#define INLINE inline |
||
1438 | +#endif |
||
1439 | + |
||
1440 | +struct ifx_pci_controller { |
||
1441 | + struct pci_controller pcic; |
||
1442 | + |
||
1443 | + /* RC specific, per host bus information */ |
||
1444 | + u32 port; /* Port index, 0 -- 1st core, 1 -- 2nd core */ |
||
1445 | +}; |
||
1446 | + |
||
1447 | +typedef struct ifx_pcie_ir_irq { |
||
1448 | + const unsigned int irq; |
||
1449 | + const char name[16]; |
||
1450 | +}ifx_pcie_ir_irq_t; |
||
1451 | + |
||
1452 | +typedef struct ifx_pcie_legacy_irq{ |
||
1453 | + const u32 irq_bit; |
||
1454 | + const int irq; |
||
1455 | +}ifx_pcie_legacy_irq_t; |
||
1456 | + |
||
1457 | +typedef struct ifx_pcie_irq { |
||
1458 | + ifx_pcie_ir_irq_t ir_irq; |
||
1459 | + ifx_pcie_legacy_irq_t legacy_irq[PCIE_LEGACY_INT_MAX]; |
||
1460 | +}ifx_pcie_irq_t; |
||
1461 | + |
||
1462 | +extern u32 g_pcie_debug_flag; |
||
1463 | +extern void ifx_pcie_debug(const char *fmt, ...); |
||
1464 | +extern void pcie_phy_clock_mode_setup(int pcie_port); |
||
1465 | +extern void pcie_msi_pic_init(int pcie_port); |
||
1466 | +extern u32 ifx_pcie_bus_enum_read_hack(int where, u32 value); |
||
1467 | +extern u32 ifx_pcie_bus_enum_write_hack(int where, u32 value); |
||
1468 | + |
||
1469 | +#define CONFIG_VR9 |
||
1470 | + |
||
1471 | +#ifdef CONFIG_VR9 |
||
1472 | +#include "ifxmips_pcie_vr9.h" |
||
1473 | +#elif defined (CONFIG_AR10) |
||
1474 | +#include "ifxmips_pcie_ar10.h" |
||
1475 | +#else |
||
1476 | +#error "PCIE: platform not defined" |
||
1477 | +#endif /* CONFIG_VR9 */ |
||
1478 | + |
||
1479 | +#endif /* IFXMIPS_PCIE_H */ |
||
1480 | + |
||
1481 | --- /dev/null |
||
1482 | +++ b/arch/mips/pci/ifxmips_pcie_ar10.h |
||
1483 | @@ -0,0 +1,290 @@ |
||
1484 | +/**************************************************************************** |
||
1485 | + Copyright (c) 2010 |
||
1486 | + Lantiq Deutschland GmbH |
||
1487 | + Am Campeon 3; 85579 Neubiberg, Germany |
||
1488 | + |
||
1489 | + For licensing information, see the file 'LICENSE' in the root folder of |
||
1490 | + this software module. |
||
1491 | + |
||
1492 | + *****************************************************************************/ |
||
1493 | +/*! |
||
1494 | + \file ifxmips_pcie_ar10.h |
||
1495 | + \ingroup IFX_PCIE |
||
1496 | + \brief PCIe RC driver ar10 specific file |
||
1497 | +*/ |
||
1498 | + |
||
1499 | +#ifndef IFXMIPS_PCIE_AR10_H |
||
1500 | +#define IFXMIPS_PCIE_AR10_H |
||
1501 | +#ifndef AUTOCONF_INCLUDED |
||
1502 | +#include <linux/config.h> |
||
1503 | +#endif /* AUTOCONF_INCLUDED */ |
||
1504 | +#include <linux/types.h> |
||
1505 | +#include <linux/delay.h> |
||
1506 | + |
||
1507 | +/* Project header file */ |
||
1508 | +#include <asm/ifx/ifx_types.h> |
||
1509 | +#include <asm/ifx/ifx_pmu.h> |
||
1510 | +#include <asm/ifx/ifx_gpio.h> |
||
1511 | +#include <asm/ifx/ifx_ebu_led.h> |
||
1512 | + |
||
1513 | +static inline void pcie_ep_gpio_rst_init(int pcie_port) |
||
1514 | +{ |
||
1515 | + ifx_ebu_led_enable(); |
||
1516 | + if (pcie_port == 0) { |
||
1517 | + ifx_ebu_led_set_data(11, 1); |
||
1518 | + } |
||
1519 | + else { |
||
1520 | + ifx_ebu_led_set_data(12, 1); |
||
1521 | + } |
||
1522 | +} |
||
1523 | + |
||
1524 | +static inline void pcie_ahb_pmu_setup(void) |
||
1525 | +{ |
||
1526 | + /* XXX, moved to CGU to control AHBM */ |
||
1527 | +} |
||
1528 | + |
||
1529 | +static inline void pcie_rcu_endian_setup(int pcie_port) |
||
1530 | +{ |
||
1531 | + u32 reg; |
||
1532 | + |
||
1533 | + reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); |
||
1534 | + /* Inbound, big endian */ |
||
1535 | + reg |= IFX_RCU_BE_AHB4S; |
||
1536 | + if (pcie_port == 0) { |
||
1537 | + reg |= IFX_RCU_BE_PCIE0M; |
||
1538 | + |
||
1539 | + #ifdef CONFIG_IFX_PCIE_HW_SWAP |
||
1540 | + /* Outbound, software swap needed */ |
||
1541 | + reg |= IFX_RCU_BE_AHB3M; |
||
1542 | + reg &= ~IFX_RCU_BE_PCIE0S; |
||
1543 | + #else |
||
1544 | + /* Outbound little endian */ |
||
1545 | + reg &= ~IFX_RCU_BE_AHB3M; |
||
1546 | + reg &= ~IFX_RCU_BE_PCIE0S; |
||
1547 | + #endif |
||
1548 | + } |
||
1549 | + else { |
||
1550 | + reg |= IFX_RCU_BE_PCIE1M; |
||
1551 | + #ifdef CONFIG_IFX_PCIE1_HW_SWAP |
||
1552 | + /* Outbound, software swap needed */ |
||
1553 | + reg |= IFX_RCU_BE_AHB3M; |
||
1554 | + reg &= ~IFX_RCU_BE_PCIE1S; |
||
1555 | + #else |
||
1556 | + /* Outbound little endian */ |
||
1557 | + reg &= ~IFX_RCU_BE_AHB3M; |
||
1558 | + reg &= ~IFX_RCU_BE_PCIE1S; |
||
1559 | + #endif |
||
1560 | + } |
||
1561 | + |
||
1562 | + IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); |
||
1563 | + IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN)); |
||
1564 | +} |
||
1565 | + |
||
1566 | +static inline void pcie_phy_pmu_enable(int pcie_port) |
||
1567 | +{ |
||
1568 | + if (pcie_port == 0) { /* XXX, should use macro*/ |
||
1569 | + PCIE0_PHY_PMU_SETUP(IFX_PMU_ENABLE); |
||
1570 | + } |
||
1571 | + else { |
||
1572 | + PCIE1_PHY_PMU_SETUP(IFX_PMU_ENABLE); |
||
1573 | + } |
||
1574 | +} |
||
1575 | + |
||
1576 | +static inline void pcie_phy_pmu_disable(int pcie_port) |
||
1577 | +{ |
||
1578 | + if (pcie_port == 0) { /* XXX, should use macro*/ |
||
1579 | + PCIE0_PHY_PMU_SETUP(IFX_PMU_DISABLE); |
||
1580 | + } |
||
1581 | + else { |
||
1582 | + PCIE1_PHY_PMU_SETUP(IFX_PMU_DISABLE); |
||
1583 | + } |
||
1584 | +} |
||
1585 | + |
||
1586 | +static inline void pcie_pdi_big_endian(int pcie_port) |
||
1587 | +{ |
||
1588 | + u32 reg; |
||
1589 | + |
||
1590 | + reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); |
||
1591 | + if (pcie_port == 0) { |
||
1592 | + /* Config AHB->PCIe and PDI endianness */ |
||
1593 | + reg |= IFX_RCU_BE_PCIE0_PDI; |
||
1594 | + } |
||
1595 | + else { |
||
1596 | + /* Config AHB->PCIe and PDI endianness */ |
||
1597 | + reg |= IFX_RCU_BE_PCIE1_PDI; |
||
1598 | + } |
||
1599 | + IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); |
||
1600 | +} |
||
1601 | + |
||
1602 | +static inline void pcie_pdi_pmu_enable(int pcie_port) |
||
1603 | +{ |
||
1604 | + if (pcie_port == 0) { |
||
1605 | + /* Enable PDI to access PCIe PHY register */ |
||
1606 | + PDI0_PMU_SETUP(IFX_PMU_ENABLE); |
||
1607 | + } |
||
1608 | + else { |
||
1609 | + PDI1_PMU_SETUP(IFX_PMU_ENABLE); |
||
1610 | + } |
||
1611 | +} |
||
1612 | + |
||
1613 | +static inline void pcie_core_rst_assert(int pcie_port) |
||
1614 | +{ |
||
1615 | + u32 reg; |
||
1616 | + |
||
1617 | + reg = IFX_REG_R32(IFX_RCU_RST_REQ); |
||
1618 | + |
||
1619 | + /* Reset Core, bit 22 */ |
||
1620 | + if (pcie_port == 0) { |
||
1621 | + reg |= 0x00400000; |
||
1622 | + } |
||
1623 | + else { |
||
1624 | + reg |= 0x08000000; /* Bit 27 */ |
||
1625 | + } |
||
1626 | + IFX_REG_W32(reg, IFX_RCU_RST_REQ); |
||
1627 | +} |
||
1628 | + |
||
1629 | +static inline void pcie_core_rst_deassert(int pcie_port) |
||
1630 | +{ |
||
1631 | + u32 reg; |
||
1632 | + |
||
1633 | + /* Make sure one micro-second delay */ |
||
1634 | + udelay(1); |
||
1635 | + |
||
1636 | + reg = IFX_REG_R32(IFX_RCU_RST_REQ); |
||
1637 | + if (pcie_port == 0) { |
||
1638 | + reg &= ~0x00400000; /* bit 22 */ |
||
1639 | + } |
||
1640 | + else { |
||
1641 | + reg &= ~0x08000000; /* Bit 27 */ |
||
1642 | + } |
||
1643 | + IFX_REG_W32(reg, IFX_RCU_RST_REQ); |
||
1644 | +} |
||
1645 | + |
||
1646 | +static inline void pcie_phy_rst_assert(int pcie_port) |
||
1647 | +{ |
||
1648 | + u32 reg; |
||
1649 | + |
||
1650 | + reg = IFX_REG_R32(IFX_RCU_RST_REQ); |
||
1651 | + if (pcie_port == 0) { |
||
1652 | + reg |= 0x00001000; /* Bit 12 */ |
||
1653 | + } |
||
1654 | + else { |
||
1655 | + reg |= 0x00002000; /* Bit 13 */ |
||
1656 | + } |
||
1657 | + IFX_REG_W32(reg, IFX_RCU_RST_REQ); |
||
1658 | +} |
||
1659 | + |
||
1660 | +static inline void pcie_phy_rst_deassert(int pcie_port) |
||
1661 | +{ |
||
1662 | + u32 reg; |
||
1663 | + |
||
1664 | + /* Make sure one micro-second delay */ |
||
1665 | + udelay(1); |
||
1666 | + |
||
1667 | + reg = IFX_REG_R32(IFX_RCU_RST_REQ); |
||
1668 | + if (pcie_port == 0) { |
||
1669 | + reg &= ~0x00001000; /* Bit 12 */ |
||
1670 | + } |
||
1671 | + else { |
||
1672 | + reg &= ~0x00002000; /* Bit 13 */ |
||
1673 | + } |
||
1674 | + IFX_REG_W32(reg, IFX_RCU_RST_REQ); |
||
1675 | +} |
||
1676 | + |
||
1677 | +static inline void pcie_device_rst_assert(int pcie_port) |
||
1678 | +{ |
||
1679 | + if (pcie_port == 0) { |
||
1680 | + ifx_ebu_led_set_data(11, 0); |
||
1681 | + } |
||
1682 | + else { |
||
1683 | + ifx_ebu_led_set_data(12, 0); |
||
1684 | + } |
||
1685 | +} |
||
1686 | + |
||
1687 | +static inline void pcie_device_rst_deassert(int pcie_port) |
||
1688 | +{ |
||
1689 | + mdelay(100); |
||
1690 | + if (pcie_port == 0) { |
||
1691 | + ifx_ebu_led_set_data(11, 1); |
||
1692 | + } |
||
1693 | + else { |
||
1694 | + ifx_ebu_led_set_data(12, 1); |
||
1695 | + } |
||
1696 | + ifx_ebu_led_disable(); |
||
1697 | +} |
||
1698 | + |
||
1699 | +static inline void pcie_core_pmu_setup(int pcie_port) |
||
1700 | +{ |
||
1701 | + if (pcie_port == 0) { |
||
1702 | + PCIE0_CTRL_PMU_SETUP(IFX_PMU_ENABLE); |
||
1703 | + } |
||
1704 | + else { |
||
1705 | + PCIE1_CTRL_PMU_SETUP(IFX_PMU_ENABLE); |
||
1706 | + } |
||
1707 | +} |
||
1708 | + |
||
1709 | +static inline void pcie_msi_init(int pcie_port) |
||
1710 | +{ |
||
1711 | + pcie_msi_pic_init(pcie_port); |
||
1712 | + if (pcie_port == 0) { |
||
1713 | + MSI0_PMU_SETUP(IFX_PMU_ENABLE); |
||
1714 | + } |
||
1715 | + else { |
||
1716 | + MSI1_PMU_SETUP(IFX_PMU_ENABLE); |
||
1717 | + } |
||
1718 | +} |
||
1719 | + |
||
1720 | +static inline u32 |
||
1721 | +ifx_pcie_bus_nr_deduct(u32 bus_number, int pcie_port) |
||
1722 | +{ |
||
1723 | + u32 tbus_number = bus_number; |
||
1724 | + |
||
1725 | +#ifdef CONFIG_IFX_PCIE_2ND_CORE |
||
1726 | + if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */ |
||
1727 | + if (pcibios_host_nr() > 1) { |
||
1728 | + tbus_number -= pcibios_1st_host_bus_nr(); |
||
1729 | + } |
||
1730 | + } |
||
1731 | +#endif /* CONFIG_IFX_PCI */ |
||
1732 | + return tbus_number; |
||
1733 | +} |
||
1734 | + |
||
1735 | +static inline u32 |
||
1736 | +ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read) |
||
1737 | +{ |
||
1738 | + struct pci_dev *pdev; |
||
1739 | + u32 tvalue = value; |
||
1740 | + |
||
1741 | + /* Sanity check */ |
||
1742 | + pdev = pci_get_slot(bus, devfn); |
||
1743 | + if (pdev == NULL) { |
||
1744 | + return tvalue; |
||
1745 | + } |
||
1746 | + |
||
1747 | + /* Only care about PCI bridge */ |
||
1748 | + if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) { |
||
1749 | + return tvalue; |
||
1750 | + } |
||
1751 | + |
||
1752 | + if (read) { /* Read hack */ |
||
1753 | + #ifdef CONFIG_IFX_PCIE_2ND_CORE |
||
1754 | + if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */ |
||
1755 | + if (pcibios_host_nr() > 1) { |
||
1756 | + tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue); |
||
1757 | + } |
||
1758 | + } |
||
1759 | + #endif /* CONFIG_IFX_PCIE_2ND_CORE */ |
||
1760 | + } |
||
1761 | + else { /* Write hack */ |
||
1762 | + #ifdef CONFIG_IFX_PCIE_2ND_CORE |
||
1763 | + if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */ |
||
1764 | + if (pcibios_host_nr() > 1) { |
||
1765 | + tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue); |
||
1766 | + } |
||
1767 | + } |
||
1768 | + #endif |
||
1769 | + } |
||
1770 | + return tvalue; |
||
1771 | +} |
||
1772 | + |
||
1773 | +#endif /* IFXMIPS_PCIE_AR10_H */ |
||
1774 | --- /dev/null |
||
1775 | +++ b/arch/mips/pci/ifxmips_pcie_msi.c |
||
1776 | @@ -0,0 +1,392 @@ |
||
1777 | +/****************************************************************************** |
||
1778 | +** |
||
1779 | +** FILE NAME : ifxmips_pcie_msi.c |
||
1780 | +** PROJECT : IFX UEIP for VRX200 |
||
1781 | +** MODULES : PCI MSI sub module |
||
1782 | +** |
||
1783 | +** DATE : 02 Mar 2009 |
||
1784 | +** AUTHOR : Lei Chuanhua |
||
1785 | +** DESCRIPTION : PCIe MSI Driver |
||
1786 | +** COPYRIGHT : Copyright (c) 2009 |
||
1787 | +** Infineon Technologies AG |
||
1788 | +** Am Campeon 1-12, 85579 Neubiberg, Germany |
||
1789 | +** |
||
1790 | +** This program is free software; you can redistribute it and/or modify |
||
1791 | +** it under the terms of the GNU General Public License as published by |
||
1792 | +** the Free Software Foundation; either version 2 of the License, or |
||
1793 | +** (at your option) any later version. |
||
1794 | +** HISTORY |
||
1795 | +** $Date $Author $Comment |
||
1796 | +** 02 Mar,2009 Lei Chuanhua Initial version |
||
1797 | +*******************************************************************************/ |
||
1798 | +/*! |
||
1799 | + \defgroup IFX_PCIE_MSI MSI OS APIs |
||
1800 | + \ingroup IFX_PCIE |
||
1801 | + \brief PCIe bus driver OS interface functions |
||
1802 | +*/ |
||
1803 | + |
||
1804 | +/*! |
||
1805 | + \file ifxmips_pcie_msi.c |
||
1806 | + \ingroup IFX_PCIE |
||
1807 | + \brief PCIe MSI OS interface file |
||
1808 | +*/ |
||
1809 | + |
||
1810 | +#ifndef AUTOCONF_INCLUDED |
||
1811 | +#include <linux/config.h> |
||
1812 | +#endif /* AUTOCONF_INCLUDED */ |
||
1813 | +#include <linux/init.h> |
||
1814 | +#include <linux/sched.h> |
||
1815 | +#include <linux/slab.h> |
||
1816 | +#include <linux/interrupt.h> |
||
1817 | +#include <linux/kernel_stat.h> |
||
1818 | +#include <linux/pci.h> |
||
1819 | +#include <linux/msi.h> |
||
1820 | +#include <linux/module.h> |
||
1821 | +#include <asm/bootinfo.h> |
||
1822 | +#include <asm/irq.h> |
||
1823 | +#include <asm/traps.h> |
||
1824 | + |
||
1825 | +#include <asm/ifx/ifx_types.h> |
||
1826 | +#include <asm/ifx/ifx_regs.h> |
||
1827 | +#include <asm/ifx/common_routines.h> |
||
1828 | +#include <asm/ifx/irq.h> |
||
1829 | + |
||
1830 | +#include "ifxmips_pcie_reg.h" |
||
1831 | +#include "ifxmips_pcie.h" |
||
1832 | + |
||
1833 | +#define IFX_MSI_IRQ_NUM 16 |
||
1834 | + |
||
1835 | +enum { |
||
1836 | + IFX_PCIE_MSI_IDX0 = 0, |
||
1837 | + IFX_PCIE_MSI_IDX1, |
||
1838 | + IFX_PCIE_MSI_IDX2, |
||
1839 | + IFX_PCIE_MSI_IDX3, |
||
1840 | +}; |
||
1841 | + |
||
1842 | +typedef struct ifx_msi_irq_idx { |
||
1843 | + const int irq; |
||
1844 | + const int idx; |
||
1845 | +}ifx_msi_irq_idx_t; |
||
1846 | + |
||
1847 | +struct ifx_msi_pic { |
||
1848 | + volatile u32 pic_table[IFX_MSI_IRQ_NUM]; |
||
1849 | + volatile u32 pic_endian; /* 0x40 */ |
||
1850 | +}; |
||
1851 | +typedef struct ifx_msi_pic *ifx_msi_pic_t; |
||
1852 | + |
||
1853 | +typedef struct ifx_msi_irq { |
||
1854 | + const volatile ifx_msi_pic_t msi_pic_p; |
||
1855 | + const u32 msi_phy_base; |
||
1856 | + const ifx_msi_irq_idx_t msi_irq_idx[IFX_MSI_IRQ_NUM]; |
||
1857 | + /* |
||
1858 | + * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is |
||
1859 | + * in use. |
||
1860 | + */ |
||
1861 | + u16 msi_free_irq_bitmask; |
||
1862 | + |
||
1863 | + /* |
||
1864 | + * Each bit in msi_multiple_irq_bitmask tells that the device using |
||
1865 | + * this bit in msi_free_irq_bitmask is also using the next bit. This |
||
1866 | + * is used so we can disable all of the MSI interrupts when a device |
||
1867 | + * uses multiple. |
||
1868 | + */ |
||
1869 | + u16 msi_multiple_irq_bitmask; |
||
1870 | +}ifx_msi_irq_t; |
||
1871 | + |
||
1872 | +static ifx_msi_irq_t msi_irqs[IFX_PCIE_CORE_NR] = { |
||
1873 | + { |
||
1874 | + .msi_pic_p = (const volatile ifx_msi_pic_t)IFX_MSI_PIC_REG_BASE, |
||
1875 | + .msi_phy_base = PCIE_MSI_PHY_BASE, |
||
1876 | + .msi_irq_idx = { |
||
1877 | + {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, |
||
1878 | + {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, |
||
1879 | + {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, |
||
1880 | + {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, |
||
1881 | + {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, |
||
1882 | + {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, |
||
1883 | + {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, |
||
1884 | + {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, |
||
1885 | + }, |
||
1886 | + .msi_free_irq_bitmask = 0, |
||
1887 | + .msi_multiple_irq_bitmask= 0, |
||
1888 | + }, |
||
1889 | +#ifdef CONFIG_IFX_PCIE_2ND_CORE |
||
1890 | + { |
||
1891 | + .msi_pic_p = (const volatile ifx_msi_pic_t)IFX_MSI1_PIC_REG_BASE, |
||
1892 | + .msi_phy_base = PCIE1_MSI_PHY_BASE, |
||
1893 | + .msi_irq_idx = { |
||
1894 | + {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, |
||
1895 | + {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, |
||
1896 | + {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, |
||
1897 | + {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, |
||
1898 | + {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, |
||
1899 | + {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, |
||
1900 | + {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, |
||
1901 | + {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, |
||
1902 | + }, |
||
1903 | + .msi_free_irq_bitmask = 0, |
||
1904 | + .msi_multiple_irq_bitmask= 0, |
||
1905 | + |
||
1906 | + }, |
||
1907 | +#endif /* CONFIG_IFX_PCIE_2ND_CORE */ |
||
1908 | +}; |
||
1909 | + |
||
1910 | +/* |
||
1911 | + * This lock controls updates to msi_free_irq_bitmask, |
||
1912 | + * msi_multiple_irq_bitmask and pic register settting |
||
1913 | + */ |
||
1914 | +static DEFINE_SPINLOCK(ifx_pcie_msi_lock); |
||
1915 | + |
||
1916 | +void pcie_msi_pic_init(int pcie_port) |
||
1917 | +{ |
||
1918 | + spin_lock(&ifx_pcie_msi_lock); |
||
1919 | + msi_irqs[pcie_port].msi_pic_p->pic_endian = IFX_MSI_PIC_BIG_ENDIAN; |
||
1920 | + spin_unlock(&ifx_pcie_msi_lock); |
||
1921 | +} |
||
1922 | + |
||
1923 | +/** |
||
1924 | + * \fn int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) |
||
1925 | + * \brief Called when a driver request MSI interrupts instead of the |
||
1926 | + * legacy INT A-D. This routine will allocate multiple interrupts |
||
1927 | + * for MSI devices that support them. A device can override this by |
||
1928 | + * programming the MSI control bits [6:4] before calling |
||
1929 | + * pci_enable_msi(). |
||
1930 | + * |
||
1931 | + * \param[in] pdev Device requesting MSI interrupts |
||
1932 | + * \param[in] desc MSI descriptor |
||
1933 | + * |
||
1934 | + * \return -EINVAL Invalid pcie root port or invalid msi bit |
||
1935 | + * \return 0 OK |
||
1936 | + * \ingroup IFX_PCIE_MSI |
||
1937 | + */ |
||
1938 | +int |
||
1939 | +arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) |
||
1940 | +{ |
||
1941 | + int irq, pos; |
||
1942 | + u16 control; |
||
1943 | + int irq_idx; |
||
1944 | + int irq_step; |
||
1945 | + int configured_private_bits; |
||
1946 | + int request_private_bits; |
||
1947 | + struct msi_msg msg; |
||
1948 | + u16 search_mask; |
||
1949 | + struct ifx_pci_controller *ctrl = pdev->bus->sysdata; |
||
1950 | + int pcie_port = ctrl->port; |
||
1951 | + |
||
1952 | + IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s %s enter\n", __func__, pci_name(pdev)); |
||
1953 | + |
||
1954 | + /* XXX, skip RC MSI itself */ |
||
1955 | + if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT) { |
||
1956 | + IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s RC itself doesn't use MSI interrupt\n", __func__); |
||
1957 | + return -EINVAL; |
||
1958 | + } |
||
1959 | + |
||
1960 | + /* |
||
1961 | + * Read the MSI config to figure out how many IRQs this device |
||
1962 | + * wants. Most devices only want 1, which will give |
||
1963 | + * configured_private_bits and request_private_bits equal 0. |
||
1964 | + */ |
||
1965 | + pci_read_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS, &control); |
||
1966 | + |
||
1967 | + /* |
||
1968 | + * If the number of private bits has been configured then use |
||
1969 | + * that value instead of the requested number. This gives the |
||
1970 | + * driver the chance to override the number of interrupts |
||
1971 | + * before calling pci_enable_msi(). |
||
1972 | + */ |
||
1973 | + configured_private_bits = (control & PCI_MSI_FLAGS_QSIZE) >> 4; |
||
1974 | + if (configured_private_bits == 0) { |
||
1975 | + /* Nothing is configured, so use the hardware requested size */ |
||
1976 | + request_private_bits = (control & PCI_MSI_FLAGS_QMASK) >> 1; |
||
1977 | + } |
||
1978 | + else { |
||
1979 | + /* |
||
1980 | + * Use the number of configured bits, assuming the |
||
1981 | + * driver wanted to override the hardware request |
||
1982 | + * value. |
||
1983 | + */ |
||
1984 | + request_private_bits = configured_private_bits; |
||
1985 | + } |
||
1986 | + |
||
1987 | + /* |
||
1988 | + * The PCI 2.3 spec mandates that there are at most 32 |
||
1989 | + * interrupts. If this device asks for more, only give it one. |
||
1990 | + */ |
||
1991 | + if (request_private_bits > 5) { |
||
1992 | + request_private_bits = 0; |
||
1993 | + } |
||
1994 | +again: |
||
1995 | + /* |
||
1996 | + * The IRQs have to be aligned on a power of two based on the |
||
1997 | + * number being requested. |
||
1998 | + */ |
||
1999 | + irq_step = (1 << request_private_bits); |
||
2000 | + |
||
2001 | + /* Mask with one bit for each IRQ */ |
||
2002 | + search_mask = (1 << irq_step) - 1; |
||
2003 | + |
||
2004 | + /* |
||
2005 | + * We're going to search msi_free_irq_bitmask_lock for zero |
||
2006 | + * bits. This represents an MSI interrupt number that isn't in |
||
2007 | + * use. |
||
2008 | + */ |
||
2009 | + spin_lock(&ifx_pcie_msi_lock); |
||
2010 | + for (pos = 0; pos < IFX_MSI_IRQ_NUM; pos += irq_step) { |
||
2011 | + if ((msi_irqs[pcie_port].msi_free_irq_bitmask & (search_mask << pos)) == 0) { |
||
2012 | + msi_irqs[pcie_port].msi_free_irq_bitmask |= search_mask << pos; |
||
2013 | + msi_irqs[pcie_port].msi_multiple_irq_bitmask |= (search_mask >> 1) << pos; |
||
2014 | + break; |
||
2015 | + } |
||
2016 | + } |
||
2017 | + spin_unlock(&ifx_pcie_msi_lock); |
||
2018 | + |
||
2019 | + /* Make sure the search for available interrupts didn't fail */ |
||
2020 | + if (pos >= IFX_MSI_IRQ_NUM) { |
||
2021 | + if (request_private_bits) { |
||
2022 | + IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s: Unable to find %d free " |
||
2023 | + "interrupts, trying just one", __func__, 1 << request_private_bits); |
||
2024 | + request_private_bits = 0; |
||
2025 | + goto again; |
||
2026 | + } |
||
2027 | + else { |
||
2028 | + printk(KERN_ERR "%s: Unable to find a free MSI interrupt\n", __func__); |
||
2029 | + return -EINVAL; |
||
2030 | + } |
||
2031 | + } |
||
2032 | + irq = msi_irqs[pcie_port].msi_irq_idx[pos].irq; |
||
2033 | + irq_idx = msi_irqs[pcie_port].msi_irq_idx[pos].idx; |
||
2034 | + |
||
2035 | + IFX_PCIE_PRINT(PCIE_MSG_MSI, "pos %d, irq %d irq_idx %d\n", pos, irq, irq_idx); |
||
2036 | + |
||
2037 | + /* |
||
2038 | + * Initialize MSI. This has to match the memory-write endianess from the device |
||
2039 | + * Address bits [23:12] |
||
2040 | + */ |
||
2041 | + spin_lock(&ifx_pcie_msi_lock); |
||
2042 | + msi_irqs[pcie_port].msi_pic_p->pic_table[pos] = SM(irq_idx, IFX_MSI_PIC_INT_LINE) | |
||
2043 | + SM((msi_irqs[pcie_port].msi_phy_base >> 12), IFX_MSI_PIC_MSG_ADDR) | |
||
2044 | + SM((1 << pos), IFX_MSI_PIC_MSG_DATA); |
||
2045 | + |
||
2046 | + /* Enable this entry */ |
||
2047 | + msi_irqs[pcie_port].msi_pic_p->pic_table[pos] &= ~IFX_MSI_PCI_INT_DISABLE; |
||
2048 | + spin_unlock(&ifx_pcie_msi_lock); |
||
2049 | + |
||
2050 | + IFX_PCIE_PRINT(PCIE_MSG_MSI, "pic_table[%d]: 0x%08x\n", |
||
2051 | + pos, msi_irqs[pcie_port].msi_pic_p->pic_table[pos]); |
||
2052 | + |
||
2053 | + /* Update the number of IRQs the device has available to it */ |
||
2054 | + control &= ~PCI_MSI_FLAGS_QSIZE; |
||
2055 | + control |= (request_private_bits << 4); |
||
2056 | + pci_write_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS, control); |
||
2057 | + |
||
2058 | + set_irq_msi(irq, desc); |
||
2059 | + msg.address_hi = 0x0; |
||
2060 | + msg.address_lo = msi_irqs[pcie_port].msi_phy_base; |
||
2061 | + msg.data = SM((1 << pos), IFX_MSI_PIC_MSG_DATA); |
||
2062 | + IFX_PCIE_PRINT(PCIE_MSG_MSI, "msi_data: pos %d 0x%08x\n", pos, msg.data); |
||
2063 | + |
||
2064 | + write_msi_msg(irq, &msg); |
||
2065 | + IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s exit\n", __func__); |
||
2066 | + return 0; |
||
2067 | +} |
||
2068 | + |
||
2069 | +static int |
||
2070 | +pcie_msi_irq_to_port(unsigned int irq, int *port) |
||
2071 | +{ |
||
2072 | + int ret = 0; |
||
2073 | + |
||
2074 | + if (irq == IFX_PCIE_MSI_IR0 || irq == IFX_PCIE_MSI_IR1 || |
||
2075 | + irq == IFX_PCIE_MSI_IR2 || irq == IFX_PCIE_MSI_IR3) { |
||
2076 | + *port = IFX_PCIE_PORT0; |
||
2077 | + } |
||
2078 | +#ifdef CONFIG_IFX_PCIE_2ND_CORE |
||
2079 | + else if (irq == IFX_PCIE1_MSI_IR0 || irq == IFX_PCIE1_MSI_IR1 || |
||
2080 | + irq == IFX_PCIE1_MSI_IR2 || irq == IFX_PCIE1_MSI_IR3) { |
||
2081 | + *port = IFX_PCIE_PORT1; |
||
2082 | + } |
||
2083 | +#endif /* CONFIG_IFX_PCIE_2ND_CORE */ |
||
2084 | + else { |
||
2085 | + printk(KERN_ERR "%s: Attempted to teardown illegal " |
||
2086 | + "MSI interrupt (%d)\n", __func__, irq); |
||
2087 | + ret = -EINVAL; |
||
2088 | + } |
||
2089 | + return ret; |
||
2090 | +} |
||
2091 | + |
||
2092 | +/** |
||
2093 | + * \fn void arch_teardown_msi_irq(unsigned int irq) |
||
2094 | + * \brief Called when a device no longer needs its MSI interrupts. All |
||
2095 | + * MSI interrupts for the device are freed. |
||
2096 | + * |
||
2097 | + * \param irq The devices first irq number. There may be multple in sequence. |
||
2098 | + * \return none |
||
2099 | + * \ingroup IFX_PCIE_MSI |
||
2100 | + */ |
||
2101 | +void |
||
2102 | +arch_teardown_msi_irq(unsigned int irq) |
||
2103 | +{ |
||
2104 | + int pos; |
||
2105 | + int number_irqs; |
||
2106 | + u16 bitmask; |
||
2107 | + int pcie_port; |
||
2108 | + |
||
2109 | + IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s enter\n", __func__); |
||
2110 | + |
||
2111 | + BUG_ON(irq > INT_NUM_IM4_IRL31); |
||
2112 | + |
||
2113 | + if (pcie_msi_irq_to_port(irq, &pcie_port) != 0) { |
||
2114 | + return; |
||
2115 | + } |
||
2116 | + |
||
2117 | + /* Shift the mask to the correct bit location, not always correct |
||
2118 | + * Probally, the first match will be chosen. |
||
2119 | + */ |
||
2120 | + for (pos = 0; pos < IFX_MSI_IRQ_NUM; pos++) { |
||
2121 | + if ((msi_irqs[pcie_port].msi_irq_idx[pos].irq == irq) |
||
2122 | + && (msi_irqs[pcie_port].msi_free_irq_bitmask & ( 1 << pos))) { |
||
2123 | + break; |
||
2124 | + } |
||
2125 | + } |
||
2126 | + if (pos >= IFX_MSI_IRQ_NUM) { |
||
2127 | + printk(KERN_ERR "%s: Unable to find a matched MSI interrupt\n", __func__); |
||
2128 | + return; |
||
2129 | + } |
||
2130 | + spin_lock(&ifx_pcie_msi_lock); |
||
2131 | + /* Disable this entry */ |
||
2132 | + msi_irqs[pcie_port].msi_pic_p->pic_table[pos] |= IFX_MSI_PCI_INT_DISABLE; |
||
2133 | + msi_irqs[pcie_port].msi_pic_p->pic_table[pos] &= ~(IFX_MSI_PIC_INT_LINE | IFX_MSI_PIC_MSG_ADDR | IFX_MSI_PIC_MSG_DATA); |
||
2134 | + spin_unlock(&ifx_pcie_msi_lock); |
||
2135 | + /* |
||
2136 | + * Count the number of IRQs we need to free by looking at the |
||
2137 | + * msi_multiple_irq_bitmask. Each bit set means that the next |
||
2138 | + * IRQ is also owned by this device. |
||
2139 | + */ |
||
2140 | + number_irqs = 0; |
||
2141 | + while (((pos + number_irqs) < IFX_MSI_IRQ_NUM) && |
||
2142 | + (msi_irqs[pcie_port].msi_multiple_irq_bitmask & (1 << (pos + number_irqs)))) { |
||
2143 | + number_irqs++; |
||
2144 | + } |
||
2145 | + number_irqs++; |
||
2146 | + |
||
2147 | + /* Mask with one bit for each IRQ */ |
||
2148 | + bitmask = (1 << number_irqs) - 1; |
||
2149 | + |
||
2150 | + bitmask <<= pos; |
||
2151 | + if ((msi_irqs[pcie_port].msi_free_irq_bitmask & bitmask) != bitmask) { |
||
2152 | + printk(KERN_ERR "%s: Attempted to teardown MSI " |
||
2153 | + "interrupt (%d) not in use\n", __func__, irq); |
||
2154 | + return; |
||
2155 | + } |
||
2156 | + /* Checks are done, update the in use bitmask */ |
||
2157 | + spin_lock(&ifx_pcie_msi_lock); |
||
2158 | + msi_irqs[pcie_port].msi_free_irq_bitmask &= ~bitmask; |
||
2159 | + msi_irqs[pcie_port].msi_multiple_irq_bitmask &= ~(bitmask >> 1); |
||
2160 | + spin_unlock(&ifx_pcie_msi_lock); |
||
2161 | + IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s exit\n", __func__); |
||
2162 | +} |
||
2163 | + |
||
2164 | +MODULE_LICENSE("GPL"); |
||
2165 | +MODULE_AUTHOR("Chuanhua.Lei@infineon.com"); |
||
2166 | +MODULE_SUPPORTED_DEVICE("Infineon PCIe IP builtin MSI PIC module"); |
||
2167 | +MODULE_DESCRIPTION("Infineon PCIe IP builtin MSI PIC driver"); |
||
2168 | + |
||
2169 | --- /dev/null |
||
2170 | +++ b/arch/mips/pci/ifxmips_pcie_phy.c |
||
2171 | @@ -0,0 +1,478 @@ |
||
2172 | +/****************************************************************************** |
||
2173 | +** |
||
2174 | +** FILE NAME : ifxmips_pcie_phy.c |
||
2175 | +** PROJECT : IFX UEIP for VRX200 |
||
2176 | +** MODULES : PCIe PHY sub module |
||
2177 | +** |
||
2178 | +** DATE : 14 May 2009 |
||
2179 | +** AUTHOR : Lei Chuanhua |
||
2180 | +** DESCRIPTION : PCIe Root Complex Driver |
||
2181 | +** COPYRIGHT : Copyright (c) 2009 |
||
2182 | +** Infineon Technologies AG |
||
2183 | +** Am Campeon 1-12, 85579 Neubiberg, Germany |
||
2184 | +** |
||
2185 | +** This program is free software; you can redistribute it and/or modify |
||
2186 | +** it under the terms of the GNU General Public License as published by |
||
2187 | +** the Free Software Foundation; either version 2 of the License, or |
||
2188 | +** (at your option) any later version. |
||
2189 | +** HISTORY |
||
2190 | +** $Version $Date $Author $Comment |
||
2191 | +** 0.0.1 14 May,2009 Lei Chuanhua Initial version |
||
2192 | +*******************************************************************************/ |
||
2193 | +/*! |
||
2194 | + \file ifxmips_pcie_phy.c |
||
2195 | + \ingroup IFX_PCIE |
||
2196 | + \brief PCIe PHY PLL register programming source file |
||
2197 | +*/ |
||
2198 | +#include <linux/types.h> |
||
2199 | +#include <linux/kernel.h> |
||
2200 | +#include <asm/paccess.h> |
||
2201 | +#include <linux/delay.h> |
||
2202 | + |
||
2203 | +#include "ifxmips_pcie_reg.h" |
||
2204 | +#include "ifxmips_pcie.h" |
||
2205 | + |
||
2206 | +/* PCIe PDI only supports 16 bit operation */ |
||
2207 | + |
||
2208 | +#define IFX_PCIE_PHY_REG_WRITE16(__addr, __data) \ |
||
2209 | + ((*(volatile u16 *) (__addr)) = (__data)) |
||
2210 | + |
||
2211 | +#define IFX_PCIE_PHY_REG_READ16(__addr) \ |
||
2212 | + (*(volatile u16 *) (__addr)) |
||
2213 | + |
||
2214 | +#define IFX_PCIE_PHY_REG16(__addr) \ |
||
2215 | + (*(volatile u16 *) (__addr)) |
||
2216 | + |
||
2217 | +#define IFX_PCIE_PHY_REG(__reg, __value, __mask) do { \ |
||
2218 | + u16 read_data; \ |
||
2219 | + u16 write_data; \ |
||
2220 | + read_data = IFX_PCIE_PHY_REG_READ16((__reg)); \ |
||
2221 | + write_data = (read_data & ((u16)~(__mask))) | (((u16)(__value)) & ((u16)(__mask)));\ |
||
2222 | + IFX_PCIE_PHY_REG_WRITE16((__reg), write_data); \ |
||
2223 | +} while (0) |
||
2224 | + |
||
2225 | +#define IFX_PCIE_PLL_TIMEOUT 1000 /* Tunnable */ |
||
2226 | + |
||
2227 | +//#define IFX_PCI_PHY_REG_DUMP |
||
2228 | + |
||
2229 | +#ifdef IFX_PCI_PHY_REG_DUMP |
||
2230 | +static void |
||
2231 | +pcie_phy_reg_dump(int pcie_port) |
||
2232 | +{ |
||
2233 | + printk("PLL REGFILE\n"); |
||
2234 | + printk("PCIE_PHY_PLL_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL1(pcie_port))); |
||
2235 | + printk("PCIE_PHY_PLL_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL2(pcie_port))); |
||
2236 | + printk("PCIE_PHY_PLL_CTRL3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL3(pcie_port))); |
||
2237 | + printk("PCIE_PHY_PLL_CTRL4 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL4(pcie_port))); |
||
2238 | + printk("PCIE_PHY_PLL_CTRL5 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL5(pcie_port))); |
||
2239 | + printk("PCIE_PHY_PLL_CTRL6 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL6(pcie_port))); |
||
2240 | + printk("PCIE_PHY_PLL_CTRL7 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL7(pcie_port))); |
||
2241 | + printk("PCIE_PHY_PLL_A_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL1(pcie_port))); |
||
2242 | + printk("PCIE_PHY_PLL_A_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL2(pcie_port))); |
||
2243 | + printk("PCIE_PHY_PLL_A_CTRL3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL3(pcie_port))); |
||
2244 | + printk("PCIE_PHY_PLL_STATUS 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_STATUS(pcie_port))); |
||
2245 | + |
||
2246 | + printk("TX1 REGFILE\n"); |
||
2247 | + printk("PCIE_PHY_TX1_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL1(pcie_port))); |
||
2248 | + printk("PCIE_PHY_TX1_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL2(pcie_port))); |
||
2249 | + printk("PCIE_PHY_TX1_CTRL3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL3(pcie_port))); |
||
2250 | + printk("PCIE_PHY_TX1_A_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_A_CTRL1(pcie_port))); |
||
2251 | + printk("PCIE_PHY_TX1_A_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_A_CTRL2(pcie_port))); |
||
2252 | + printk("PCIE_PHY_TX1_MOD1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD1(pcie_port))); |
||
2253 | + printk("PCIE_PHY_TX1_MOD2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD2(pcie_port))); |
||
2254 | + printk("PCIE_PHY_TX1_MOD3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD3(pcie_port))); |
||
2255 | + |
||
2256 | + printk("TX2 REGFILE\n"); |
||
2257 | + printk("PCIE_PHY_TX2_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_CTRL1(pcie_port))); |
||
2258 | + printk("PCIE_PHY_TX2_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_CTRL2(pcie_port))); |
||
2259 | + printk("PCIE_PHY_TX2_A_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_A_CTRL1(pcie_port))); |
||
2260 | + printk("PCIE_PHY_TX2_A_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_A_CTRL2(pcie_port))); |
||
2261 | + printk("PCIE_PHY_TX2_MOD1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD1(pcie_port))); |
||
2262 | + printk("PCIE_PHY_TX2_MOD2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD2(pcie_port))); |
||
2263 | + printk("PCIE_PHY_TX2_MOD3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD3(pcie_port))); |
||
2264 | + |
||
2265 | + printk("RX1 REGFILE\n"); |
||
2266 | + printk("PCIE_PHY_RX1_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CTRL1(pcie_port))); |
||
2267 | + printk("PCIE_PHY_RX1_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CTRL2(pcie_port))); |
||
2268 | + printk("PCIE_PHY_RX1_CDR 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CDR(pcie_port))); |
||
2269 | + printk("PCIE_PHY_RX1_EI 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_EI(pcie_port))); |
||
2270 | + printk("PCIE_PHY_RX1_A_CTRL 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_A_CTRL(pcie_port))); |
||
2271 | +} |
||
2272 | +#endif /* IFX_PCI_PHY_REG_DUMP */ |
||
2273 | + |
||
2274 | +static void |
||
2275 | +pcie_phy_comm_setup(int pcie_port) |
||
2276 | +{ |
||
2277 | + /* PLL Setting */ |
||
2278 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL1(pcie_port), 0x120e, 0xFFFF); |
||
2279 | + |
||
2280 | + /* increase the bias reference voltage */ |
||
2281 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x39D7, 0xFFFF); |
||
2282 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x0900, 0xFFFF); |
||
2283 | + |
||
2284 | + /* Endcnt */ |
||
2285 | + IFX_PCIE_PHY_REG(PCIE_PHY_RX1_EI(pcie_port), 0x0004, 0xFFFF); |
||
2286 | + IFX_PCIE_PHY_REG(PCIE_PHY_RX1_A_CTRL(pcie_port), 0x6803, 0xFFFF); |
||
2287 | + |
||
2288 | + /* force */ |
||
2289 | + IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0008, 0x0008); |
||
2290 | + |
||
2291 | + /* predrv_ser_en */ |
||
2292 | + IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL2(pcie_port), 0x0706, 0xFFFF); |
||
2293 | + |
||
2294 | + /* ctrl_lim */ |
||
2295 | + IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL3(pcie_port), 0x1FFF, 0xFFFF); |
||
2296 | + |
||
2297 | + /* ctrl */ |
||
2298 | + IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL1(pcie_port), 0x0800, 0xFF00); |
||
2299 | + |
||
2300 | + /* predrv_ser_en */ |
||
2301 | + IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4702, 0x7F00); |
||
2302 | + |
||
2303 | + /* RTERM*/ |
||
2304 | + IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL2(pcie_port), 0x2e00, 0xFFFF); |
||
2305 | + |
||
2306 | + /* Improved 100MHz clock output */ |
||
2307 | + IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL2(pcie_port), 0x3096, 0xFFFF); |
||
2308 | + IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4707, 0xFFFF); |
||
2309 | + |
||
2310 | + /* Reduced CDR BW to avoid glitches */ |
||
2311 | + IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CDR(pcie_port), 0x0235, 0xFFFF); |
||
2312 | +} |
||
2313 | + |
||
2314 | +#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_MODE |
||
2315 | +static void |
||
2316 | +pcie_phy_36mhz_mode_setup(int pcie_port) |
||
2317 | +{ |
||
2318 | + IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); |
||
2319 | +#ifdef IFX_PCI_PHY_REG_DUMP |
||
2320 | + IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); |
||
2321 | + pcie_phy_reg_dump(pcie_port); |
||
2322 | +#endif |
||
2323 | + |
||
2324 | + /* en_ext_mmd_div_ratio */ |
||
2325 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); |
||
2326 | + |
||
2327 | + /* ext_mmd_div_ratio*/ |
||
2328 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); |
||
2329 | + |
||
2330 | + /* pll_ensdm */ |
||
2331 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); |
||
2332 | + |
||
2333 | + /* en_const_sdm */ |
||
2334 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); |
||
2335 | + |
||
2336 | + /* mmd */ |
||
2337 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); |
||
2338 | + |
||
2339 | + /* lf_mode */ |
||
2340 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); |
||
2341 | + |
||
2342 | + /* const_sdm */ |
||
2343 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); |
||
2344 | + |
||
2345 | + /* const sdm */ |
||
2346 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); |
||
2347 | + |
||
2348 | + /* pllmod */ |
||
2349 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); |
||
2350 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); |
||
2351 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); |
||
2352 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1b72, 0xFFFF); |
||
2353 | + |
||
2354 | + IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); |
||
2355 | +} |
||
2356 | +#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_MODE */ |
||
2357 | + |
||
2358 | +#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE |
||
2359 | +static void |
||
2360 | +pcie_phy_36mhz_ssc_mode_setup(int pcie_port) |
||
2361 | +{ |
||
2362 | + IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); |
||
2363 | +#ifdef IFX_PCI_PHY_REG_DUMP |
||
2364 | + IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); |
||
2365 | + pcie_phy_reg_dump(pcie_port); |
||
2366 | +#endif |
||
2367 | + |
||
2368 | + /* PLL Setting */ |
||
2369 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL1(pcie_port), 0x120e, 0xFFFF); |
||
2370 | + |
||
2371 | + /* Increase the bias reference voltage */ |
||
2372 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x39D7, 0xFFFF); |
||
2373 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x0900, 0xFFFF); |
||
2374 | + |
||
2375 | + /* Endcnt */ |
||
2376 | + IFX_PCIE_PHY_REG(PCIE_PHY_RX1_EI(pcie_port), 0x0004, 0xFFFF); |
||
2377 | + IFX_PCIE_PHY_REG(PCIE_PHY_RX1_A_CTRL(pcie_port), 0x6803, 0xFFFF); |
||
2378 | + |
||
2379 | + /* Force */ |
||
2380 | + IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0008, 0x0008); |
||
2381 | + |
||
2382 | + /* Predrv_ser_en */ |
||
2383 | + IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL2(pcie_port), 0x0706, 0xFFFF); |
||
2384 | + |
||
2385 | + /* ctrl_lim */ |
||
2386 | + IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL3(pcie_port), 0x1FFF, 0xFFFF); |
||
2387 | + |
||
2388 | + /* ctrl */ |
||
2389 | + IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL1(pcie_port), 0x0800, 0xFF00); |
||
2390 | + |
||
2391 | + /* predrv_ser_en */ |
||
2392 | + IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4702, 0x7F00); |
||
2393 | + |
||
2394 | + /* RTERM*/ |
||
2395 | + IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL2(pcie_port), 0x2e00, 0xFFFF); |
||
2396 | + |
||
2397 | + /* en_ext_mmd_div_ratio */ |
||
2398 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); |
||
2399 | + |
||
2400 | + /* ext_mmd_div_ratio*/ |
||
2401 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); |
||
2402 | + |
||
2403 | + /* pll_ensdm */ |
||
2404 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0400, 0x0400); |
||
2405 | + |
||
2406 | + /* en_const_sdm */ |
||
2407 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); |
||
2408 | + |
||
2409 | + /* mmd */ |
||
2410 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); |
||
2411 | + |
||
2412 | + /* lf_mode */ |
||
2413 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); |
||
2414 | + |
||
2415 | + /* const_sdm */ |
||
2416 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); |
||
2417 | + |
||
2418 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0000, 0x0100); |
||
2419 | + /* const sdm */ |
||
2420 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); |
||
2421 | + |
||
2422 | + /* pllmod */ |
||
2423 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); |
||
2424 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); |
||
2425 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); |
||
2426 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1c72, 0xFFFF); |
||
2427 | + |
||
2428 | + /* improved 100MHz clock output */ |
||
2429 | + IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL2(pcie_port), 0x3096, 0xFFFF); |
||
2430 | + IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4707, 0xFFFF); |
||
2431 | + |
||
2432 | + /* reduced CDR BW to avoid glitches */ |
||
2433 | + IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CDR(pcie_port), 0x0235, 0xFFFF); |
||
2434 | + |
||
2435 | + IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); |
||
2436 | +} |
||
2437 | +#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE */ |
||
2438 | + |
||
2439 | +#ifdef CONFIG_IFX_PCIE_PHY_25MHZ_MODE |
||
2440 | +static void |
||
2441 | +pcie_phy_25mhz_mode_setup(int pcie_port) |
||
2442 | +{ |
||
2443 | + IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); |
||
2444 | +#ifdef IFX_PCI_PHY_REG_DUMP |
||
2445 | + IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); |
||
2446 | + pcie_phy_reg_dump(pcie_port); |
||
2447 | +#endif |
||
2448 | + /* en_const_sdm */ |
||
2449 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); |
||
2450 | + |
||
2451 | + /* pll_ensdm */ |
||
2452 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0000, 0x0200); |
||
2453 | + |
||
2454 | + /* en_ext_mmd_div_ratio*/ |
||
2455 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0002, 0x0002); |
||
2456 | + |
||
2457 | + /* ext_mmd_div_ratio*/ |
||
2458 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0040, 0x0070); |
||
2459 | + |
||
2460 | + /* mmd */ |
||
2461 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x6000, 0xe000); |
||
2462 | + |
||
2463 | + /* lf_mode */ |
||
2464 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x4000, 0x4000); |
||
2465 | + |
||
2466 | + IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); |
||
2467 | +} |
||
2468 | +#endif /* CONFIG_IFX_PCIE_PHY_25MHZ_MODE */ |
||
2469 | + |
||
2470 | +#ifdef CONFIG_IFX_PCIE_PHY_100MHZ_MODE |
||
2471 | +static void |
||
2472 | +pcie_phy_100mhz_mode_setup(int pcie_port) |
||
2473 | +{ |
||
2474 | + IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); |
||
2475 | +#ifdef IFX_PCI_PHY_REG_DUMP |
||
2476 | + IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); |
||
2477 | + pcie_phy_reg_dump(pcie_port); |
||
2478 | +#endif |
||
2479 | + /* en_ext_mmd_div_ratio */ |
||
2480 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); |
||
2481 | + |
||
2482 | + /* ext_mmd_div_ratio*/ |
||
2483 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); |
||
2484 | + |
||
2485 | + /* pll_ensdm */ |
||
2486 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); |
||
2487 | + |
||
2488 | + /* en_const_sdm */ |
||
2489 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); |
||
2490 | + |
||
2491 | + /* mmd */ |
||
2492 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); |
||
2493 | + |
||
2494 | + /* lf_mode */ |
||
2495 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); |
||
2496 | + |
||
2497 | + /* const_sdm */ |
||
2498 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); |
||
2499 | + |
||
2500 | + /* const sdm */ |
||
2501 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); |
||
2502 | + |
||
2503 | + /* pllmod */ |
||
2504 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); |
||
2505 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); |
||
2506 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); |
||
2507 | + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1b72, 0xFFFF); |
||
2508 | + |
||
2509 | + IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); |
||
2510 | +} |
||
2511 | +#endif /* CONFIG_IFX_PCIE_PHY_100MHZ_MODE */ |
||
2512 | + |
||
2513 | +static int |
||
2514 | +pcie_phy_wait_startup_ready(int pcie_port) |
||
2515 | +{ |
||
2516 | + int i; |
||
2517 | + |
||
2518 | + for (i = 0; i < IFX_PCIE_PLL_TIMEOUT; i++) { |
||
2519 | + if ((IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_STATUS(pcie_port)) & 0x0040) != 0) { |
||
2520 | + break; |
||
2521 | + } |
||
2522 | + udelay(10); |
||
2523 | + } |
||
2524 | + if (i >= IFX_PCIE_PLL_TIMEOUT) { |
||
2525 | + printk(KERN_ERR "%s PLL Link timeout\n", __func__); |
||
2526 | + return -1; |
||
2527 | + } |
||
2528 | + return 0; |
||
2529 | +} |
||
2530 | + |
||
2531 | +static void |
||
2532 | +pcie_phy_load_enable(int pcie_port, int slice) |
||
2533 | +{ |
||
2534 | + /* Set the load_en of tx/rx slice to '1' */ |
||
2535 | + switch (slice) { |
||
2536 | + case 1: |
||
2537 | + IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0010, 0x0010); |
||
2538 | + break; |
||
2539 | + case 2: |
||
2540 | + IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL1(pcie_port), 0x0010, 0x0010); |
||
2541 | + break; |
||
2542 | + case 3: |
||
2543 | + IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CTRL1(pcie_port), 0x0002, 0x0002); |
||
2544 | + break; |
||
2545 | + } |
||
2546 | +} |
||
2547 | + |
||
2548 | +static void |
||
2549 | +pcie_phy_load_disable(int pcie_port, int slice) |
||
2550 | +{ |
||
2551 | + /* set the load_en of tx/rx slice to '0' */ |
||
2552 | + switch (slice) { |
||
2553 | + case 1: |
||
2554 | + IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0000, 0x0010); |
||
2555 | + break; |
||
2556 | + case 2: |
||
2557 | + IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL1(pcie_port), 0x0000, 0x0010); |
||
2558 | + break; |
||
2559 | + case 3: |
||
2560 | + IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CTRL1(pcie_port), 0x0000, 0x0002); |
||
2561 | + break; |
||
2562 | + } |
||
2563 | +} |
||
2564 | + |
||
2565 | +static void |
||
2566 | +pcie_phy_load_war(int pcie_port) |
||
2567 | +{ |
||
2568 | + int slice; |
||
2569 | + |
||
2570 | + for (slice = 1; slice < 4; slice++) { |
||
2571 | + pcie_phy_load_enable(pcie_port, slice); |
||
2572 | + udelay(1); |
||
2573 | + pcie_phy_load_disable(pcie_port, slice); |
||
2574 | + } |
||
2575 | +} |
||
2576 | + |
||
2577 | +static void |
||
2578 | +pcie_phy_tx2_modulation(int pcie_port) |
||
2579 | +{ |
||
2580 | + IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD1(pcie_port), 0x1FFE, 0xFFFF); |
||
2581 | + IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD2(pcie_port), 0xFFFE, 0xFFFF); |
||
2582 | + IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD3(pcie_port), 0x0601, 0xFFFF); |
||
2583 | + mdelay(1); |
||
2584 | + IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD3(pcie_port), 0x0001, 0xFFFF); |
||
2585 | +} |
||
2586 | + |
||
2587 | +static void |
||
2588 | +pcie_phy_tx1_modulation(int pcie_port) |
||
2589 | +{ |
||
2590 | + IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD1(pcie_port), 0x1FFE, 0xFFFF); |
||
2591 | + IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD2(pcie_port), 0xFFFE, 0xFFFF); |
||
2592 | + IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD3(pcie_port), 0x0601, 0xFFFF); |
||
2593 | + mdelay(1); |
||
2594 | + IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD3(pcie_port), 0x0001, 0xFFFF); |
||
2595 | +} |
||
2596 | + |
||
2597 | +static void |
||
2598 | +pcie_phy_tx_modulation_war(int pcie_port) |
||
2599 | +{ |
||
2600 | + int i; |
||
2601 | + |
||
2602 | +#define PCIE_PHY_MODULATION_NUM 5 |
||
2603 | + for (i = 0; i < PCIE_PHY_MODULATION_NUM; i++) { |
||
2604 | + pcie_phy_tx2_modulation(pcie_port); |
||
2605 | + pcie_phy_tx1_modulation(pcie_port); |
||
2606 | + } |
||
2607 | +#undef PCIE_PHY_MODULATION_NUM |
||
2608 | +} |
||
2609 | + |
||
2610 | +void |
||
2611 | +pcie_phy_clock_mode_setup(int pcie_port) |
||
2612 | +{ |
||
2613 | + pcie_pdi_big_endian(pcie_port); |
||
2614 | + |
||
2615 | + /* Enable PDI to access PCIe PHY register */ |
||
2616 | + pcie_pdi_pmu_enable(pcie_port); |
||
2617 | + |
||
2618 | + /* Configure PLL and PHY clock */ |
||
2619 | + pcie_phy_comm_setup(pcie_port); |
||
2620 | + |
||
2621 | +#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_MODE |
||
2622 | + pcie_phy_36mhz_mode_setup(pcie_port); |
||
2623 | +#elif defined(CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE) |
||
2624 | + pcie_phy_36mhz_ssc_mode_setup(pcie_port); |
||
2625 | +#elif defined(CONFIG_IFX_PCIE_PHY_25MHZ_MODE) |
||
2626 | + pcie_phy_25mhz_mode_setup(pcie_port); |
||
2627 | +#elif defined (CONFIG_IFX_PCIE_PHY_100MHZ_MODE) |
||
2628 | + pcie_phy_100mhz_mode_setup(pcie_port); |
||
2629 | +#else |
||
2630 | + #error "PCIE PHY Clock Mode must be chosen first!!!!" |
||
2631 | +#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_MODE */ |
||
2632 | + |
||
2633 | + /* Enable PCIe PHY and make PLL setting take effect */ |
||
2634 | + pcie_phy_pmu_enable(pcie_port); |
||
2635 | + |
||
2636 | + /* Check if we are in startup_ready status */ |
||
2637 | + pcie_phy_wait_startup_ready(pcie_port); |
||
2638 | + |
||
2639 | + pcie_phy_load_war(pcie_port); |
||
2640 | + |
||
2641 | + /* Apply TX modulation workarounds */ |
||
2642 | + pcie_phy_tx_modulation_war(pcie_port); |
||
2643 | + |
||
2644 | +#ifdef IFX_PCI_PHY_REG_DUMP |
||
2645 | + IFX_PCIE_PRINT(PCIE_MSG_PHY, "Modified PHY register dump\n"); |
||
2646 | + pcie_phy_reg_dump(pcie_port); |
||
2647 | +#endif |
||
2648 | +} |
||
2649 | + |
||
2650 | --- /dev/null |
||
2651 | +++ b/arch/mips/pci/ifxmips_pcie_pm.c |
||
2652 | @@ -0,0 +1,176 @@ |
||
2653 | +/****************************************************************************** |
||
2654 | +** |
||
2655 | +** FILE NAME : ifxmips_pcie_pm.c |
||
2656 | +** PROJECT : IFX UEIP |
||
2657 | +** MODULES : PCIE Root Complex Driver |
||
2658 | +** |
||
2659 | +** DATE : 21 Dec 2009 |
||
2660 | +** AUTHOR : Lei Chuanhua |
||
2661 | +** DESCRIPTION : PCIE Root Complex Driver Power Managment |
||
2662 | +** COPYRIGHT : Copyright (c) 2009 |
||
2663 | +** Lantiq Deutschland GmbH |
||
2664 | +** Am Campeon 3, 85579 Neubiberg, Germany |
||
2665 | +** |
||
2666 | +** This program is free software; you can redistribute it and/or modify |
||
2667 | +** it under the terms of the GNU General Public License as published by |
||
2668 | +** the Free Software Foundation; either version 2 of the License, or |
||
2669 | +** (at your option) any later version. |
||
2670 | +** |
||
2671 | +** HISTORY |
||
2672 | +** $Date $Author $Comment |
||
2673 | +** 21 Dec,2009 Lei Chuanhua First UEIP release |
||
2674 | +*******************************************************************************/ |
||
2675 | +/*! |
||
2676 | + \defgroup IFX_PCIE_PM Power Management functions |
||
2677 | + \ingroup IFX_PCIE |
||
2678 | + \brief IFX PCIE Root Complex Driver power management functions |
||
2679 | +*/ |
||
2680 | + |
||
2681 | +/*! |
||
2682 | + \file ifxmips_pcie_pm.c |
||
2683 | + \ingroup IFX_PCIE |
||
2684 | + \brief source file for PCIE Root Complex Driver Power Management |
||
2685 | +*/ |
||
2686 | + |
||
2687 | +#ifndef EXPORT_SYMTAB |
||
2688 | +#define EXPORT_SYMTAB |
||
2689 | +#endif |
||
2690 | +#ifndef AUTOCONF_INCLUDED |
||
2691 | +#include <linux/config.h> |
||
2692 | +#endif /* AUTOCONF_INCLUDED */ |
||
2693 | +#include <linux/version.h> |
||
2694 | +#include <linux/module.h> |
||
2695 | +#include <linux/types.h> |
||
2696 | +#include <linux/kernel.h> |
||
2697 | +#include <asm/system.h> |
||
2698 | + |
||
2699 | +/* Project header */ |
||
2700 | +#include <asm/ifx/ifx_types.h> |
||
2701 | +#include <asm/ifx/ifx_regs.h> |
||
2702 | +#include <asm/ifx/common_routines.h> |
||
2703 | +#include <asm/ifx/ifx_pmcu.h> |
||
2704 | +#include "ifxmips_pcie_pm.h" |
||
2705 | + |
||
2706 | +/** |
||
2707 | + * \fn static IFX_PMCU_RETURN_t ifx_pcie_pmcu_state_change(IFX_PMCU_STATE_t pmcuState) |
||
2708 | + * \brief the callback function to request pmcu state in the power management hardware-dependent module |
||
2709 | + * |
||
2710 | + * \param pmcuState This parameter is a PMCU state. |
||
2711 | + * |
||
2712 | + * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully |
||
2713 | + * \return IFX_PMCU_RETURN_ERROR Failed to set power state. |
||
2714 | + * \return IFX_PMCU_RETURN_DENIED Not allowed to operate power state |
||
2715 | + * \ingroup IFX_PCIE_PM |
||
2716 | + */ |
||
2717 | +static IFX_PMCU_RETURN_t |
||
2718 | +ifx_pcie_pmcu_state_change(IFX_PMCU_STATE_t pmcuState) |
||
2719 | +{ |
||
2720 | + switch(pmcuState) |
||
2721 | + { |
||
2722 | + case IFX_PMCU_STATE_D0: |
||
2723 | + return IFX_PMCU_RETURN_SUCCESS; |
||
2724 | + case IFX_PMCU_STATE_D1: // Not Applicable |
||
2725 | + return IFX_PMCU_RETURN_DENIED; |
||
2726 | + case IFX_PMCU_STATE_D2: // Not Applicable |
||
2727 | + return IFX_PMCU_RETURN_DENIED; |
||
2728 | + case IFX_PMCU_STATE_D3: // Module clock gating and Power gating |
||
2729 | + return IFX_PMCU_RETURN_SUCCESS; |
||
2730 | + default: |
||
2731 | + return IFX_PMCU_RETURN_DENIED; |
||
2732 | + } |
||
2733 | +} |
||
2734 | + |
||
2735 | +/** |
||
2736 | + * \fn static IFX_PMCU_RETURN_t ifx_pcie_pmcu_state_get(IFX_PMCU_STATE_t *pmcuState) |
||
2737 | + * \brief the callback function to get pmcu state in the power management hardware-dependent module |
||
2738 | + |
||
2739 | + * \param pmcuState Pointer to return power state. |
||
2740 | + * |
||
2741 | + * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully |
||
2742 | + * \return IFX_PMCU_RETURN_ERROR Failed to set power state. |
||
2743 | + * \return IFX_PMCU_RETURN_DENIED Not allowed to operate power state |
||
2744 | + * \ingroup IFX_PCIE_PM |
||
2745 | + */ |
||
2746 | +static IFX_PMCU_RETURN_t |
||
2747 | +ifx_pcie_pmcu_state_get(IFX_PMCU_STATE_t *pmcuState) |
||
2748 | +{ |
||
2749 | + return IFX_PMCU_RETURN_SUCCESS; |
||
2750 | +} |
||
2751 | + |
||
2752 | +/** |
||
2753 | + * \fn IFX_PMCU_RETURN_t ifx_pcie_pmcu_prechange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) |
||
2754 | + * \brief Apply all callbacks registered to be executed before a state change for pmcuModule |
||
2755 | + * |
||
2756 | + * \param pmcuModule Module |
||
2757 | + * \param newState New state |
||
2758 | + * \param oldState Old state |
||
2759 | + * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully |
||
2760 | + * \return IFX_PMCU_RETURN_ERROR Failed to set power state. |
||
2761 | + * \ingroup IFX_PCIE_PM |
||
2762 | + */ |
||
2763 | +static IFX_PMCU_RETURN_t |
||
2764 | +ifx_pcie_pmcu_prechange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) |
||
2765 | +{ |
||
2766 | + return IFX_PMCU_RETURN_SUCCESS; |
||
2767 | +} |
||
2768 | + |
||
2769 | +/** |
||
2770 | + * \fn IFX_PMCU_RETURN_t ifx_pcie_pmcu_postchange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) |
||
2771 | + * \brief Apply all callbacks registered to be executed before a state change for pmcuModule |
||
2772 | + * |
||
2773 | + * \param pmcuModule Module |
||
2774 | + * \param newState New state |
||
2775 | + * \param oldState Old state |
||
2776 | + * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully |
||
2777 | + * \return IFX_PMCU_RETURN_ERROR Failed to set power state. |
||
2778 | + * \ingroup IFX_PCIE_PM |
||
2779 | + */ |
||
2780 | +static IFX_PMCU_RETURN_t |
||
2781 | +ifx_pcie_pmcu_postchange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) |
||
2782 | +{ |
||
2783 | + return IFX_PMCU_RETURN_SUCCESS; |
||
2784 | +} |
||
2785 | + |
||
2786 | +/** |
||
2787 | + * \fn static void ifx_pcie_pmcu_init(void) |
||
2788 | + * \brief Register with central PMCU module |
||
2789 | + * \return none |
||
2790 | + * \ingroup IFX_PCIE_PM |
||
2791 | + */ |
||
2792 | +void |
||
2793 | +ifx_pcie_pmcu_init(void) |
||
2794 | +{ |
||
2795 | + IFX_PMCU_REGISTER_t pmcuRegister; |
||
2796 | + |
||
2797 | + /* XXX, hook driver context */ |
||
2798 | + |
||
2799 | + /* State function register */ |
||
2800 | + memset(&pmcuRegister, 0, sizeof(IFX_PMCU_REGISTER_t)); |
||
2801 | + pmcuRegister.pmcuModule = IFX_PMCU_MODULE_PCIE; |
||
2802 | + pmcuRegister.pmcuModuleNr = 0; |
||
2803 | + pmcuRegister.ifx_pmcu_state_change = ifx_pcie_pmcu_state_change; |
||
2804 | + pmcuRegister.ifx_pmcu_state_get = ifx_pcie_pmcu_state_get; |
||
2805 | + pmcuRegister.pre = ifx_pcie_pmcu_prechange; |
||
2806 | + pmcuRegister.post= ifx_pcie_pmcu_postchange; |
||
2807 | + ifx_pmcu_register(&pmcuRegister); |
||
2808 | +} |
||
2809 | + |
||
2810 | +/** |
||
2811 | + * \fn static void ifx_pcie_pmcu_exit(void) |
||
2812 | + * \brief Unregister with central PMCU module |
||
2813 | + * |
||
2814 | + * \return none |
||
2815 | + * \ingroup IFX_PCIE_PM |
||
2816 | + */ |
||
2817 | +void |
||
2818 | +ifx_pcie_pmcu_exit(void) |
||
2819 | +{ |
||
2820 | + IFX_PMCU_REGISTER_t pmcuUnRegister; |
||
2821 | + |
||
2822 | + /* XXX, hook driver context */ |
||
2823 | + |
||
2824 | + pmcuUnRegister.pmcuModule = IFX_PMCU_MODULE_PCIE; |
||
2825 | + pmcuUnRegister.pmcuModuleNr = 0; |
||
2826 | + ifx_pmcu_unregister(&pmcuUnRegister); |
||
2827 | +} |
||
2828 | + |
||
2829 | --- /dev/null |
||
2830 | +++ b/arch/mips/pci/ifxmips_pcie_pm.h |
||
2831 | @@ -0,0 +1,36 @@ |
||
2832 | +/****************************************************************************** |
||
2833 | +** |
||
2834 | +** FILE NAME : ifxmips_pcie_pm.h |
||
2835 | +** PROJECT : IFX UEIP |
||
2836 | +** MODULES : PCIe Root Complex Driver |
||
2837 | +** |
||
2838 | +** DATE : 21 Dec 2009 |
||
2839 | +** AUTHOR : Lei Chuanhua |
||
2840 | +** DESCRIPTION : PCIe Root Complex Driver Power Managment |
||
2841 | +** COPYRIGHT : Copyright (c) 2009 |
||
2842 | +** Lantiq Deutschland GmbH |
||
2843 | +** Am Campeon 3, 85579 Neubiberg, Germany |
||
2844 | +** |
||
2845 | +** This program is free software; you can redistribute it and/or modify |
||
2846 | +** it under the terms of the GNU General Public License as published by |
||
2847 | +** the Free Software Foundation; either version 2 of the License, or |
||
2848 | +** (at your option) any later version. |
||
2849 | +** |
||
2850 | +** HISTORY |
||
2851 | +** $Date $Author $Comment |
||
2852 | +** 21 Dec,2009 Lei Chuanhua First UEIP release |
||
2853 | +*******************************************************************************/ |
||
2854 | +/*! |
||
2855 | + \file ifxmips_pcie_pm.h |
||
2856 | + \ingroup IFX_PCIE |
||
2857 | + \brief header file for PCIe Root Complex Driver Power Management |
||
2858 | +*/ |
||
2859 | + |
||
2860 | +#ifndef IFXMIPS_PCIE_PM_H |
||
2861 | +#define IFXMIPS_PCIE_PM_H |
||
2862 | + |
||
2863 | +void ifx_pcie_pmcu_init(void); |
||
2864 | +void ifx_pcie_pmcu_exit(void); |
||
2865 | + |
||
2866 | +#endif /* IFXMIPS_PCIE_PM_H */ |
||
2867 | + |
||
2868 | --- /dev/null |
||
2869 | +++ b/arch/mips/pci/ifxmips_pcie_reg.h |
||
2870 | @@ -0,0 +1,1001 @@ |
||
2871 | +/****************************************************************************** |
||
2872 | +** |
||
2873 | +** FILE NAME : ifxmips_pcie_reg.h |
||
2874 | +** PROJECT : IFX UEIP for VRX200 |
||
2875 | +** MODULES : PCIe module |
||
2876 | +** |
||
2877 | +** DATE : 02 Mar 2009 |
||
2878 | +** AUTHOR : Lei Chuanhua |
||
2879 | +** DESCRIPTION : PCIe Root Complex Driver |
||
2880 | +** COPYRIGHT : Copyright (c) 2009 |
||
2881 | +** Infineon Technologies AG |
||
2882 | +** Am Campeon 1-12, 85579 Neubiberg, Germany |
||
2883 | +** |
||
2884 | +** This program is free software; you can redistribute it and/or modify |
||
2885 | +** it under the terms of the GNU General Public License as published by |
||
2886 | +** the Free Software Foundation; either version 2 of the License, or |
||
2887 | +** (at your option) any later version. |
||
2888 | +** HISTORY |
||
2889 | +** $Version $Date $Author $Comment |
||
2890 | +** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version |
||
2891 | +*******************************************************************************/ |
||
2892 | +#ifndef IFXMIPS_PCIE_REG_H |
||
2893 | +#define IFXMIPS_PCIE_REG_H |
||
2894 | +/*! |
||
2895 | + \file ifxmips_pcie_reg.h |
||
2896 | + \ingroup IFX_PCIE |
||
2897 | + \brief header file for PCIe module register definition |
||
2898 | +*/ |
||
2899 | +/* PCIe Address Mapping Base */ |
||
2900 | +#define PCIE_CFG_PHY_BASE 0x1D000000UL |
||
2901 | +#define PCIE_CFG_BASE (KSEG1 + PCIE_CFG_PHY_BASE) |
||
2902 | +#define PCIE_CFG_SIZE (8 * 1024 * 1024) |
||
2903 | + |
||
2904 | +#define PCIE_MEM_PHY_BASE 0x1C000000UL |
||
2905 | +#define PCIE_MEM_BASE (KSEG1 + PCIE_MEM_PHY_BASE) |
||
2906 | +#define PCIE_MEM_SIZE (16 * 1024 * 1024) |
||
2907 | +#define PCIE_MEM_PHY_END (PCIE_MEM_PHY_BASE + PCIE_MEM_SIZE - 1) |
||
2908 | + |
||
2909 | +#define PCIE_IO_PHY_BASE 0x1D800000UL |
||
2910 | +#define PCIE_IO_BASE (KSEG1 + PCIE_IO_PHY_BASE) |
||
2911 | +#define PCIE_IO_SIZE (1 * 1024 * 1024) |
||
2912 | +#define PCIE_IO_PHY_END (PCIE_IO_PHY_BASE + PCIE_IO_SIZE - 1) |
||
2913 | + |
||
2914 | +#define PCIE_RC_CFG_BASE (KSEG1 + 0x1D900000) |
||
2915 | +#define PCIE_APP_LOGIC_REG (KSEG1 + 0x1E100900) |
||
2916 | +#define PCIE_MSI_PHY_BASE 0x1F600000UL |
||
2917 | + |
||
2918 | +#define PCIE_PDI_PHY_BASE 0x1F106800UL |
||
2919 | +#define PCIE_PDI_BASE (KSEG1 + PCIE_PDI_PHY_BASE) |
||
2920 | +#define PCIE_PDI_SIZE 0x400 |
||
2921 | + |
||
2922 | +#define PCIE1_CFG_PHY_BASE 0x19000000UL |
||
2923 | +#define PCIE1_CFG_BASE (KSEG1 + PCIE1_CFG_PHY_BASE) |
||
2924 | +#define PCIE1_CFG_SIZE (8 * 1024 * 1024) |
||
2925 | + |
||
2926 | +#define PCIE1_MEM_PHY_BASE 0x18000000UL |
||
2927 | +#define PCIE1_MEM_BASE (KSEG1 + PCIE1_MEM_PHY_BASE) |
||
2928 | +#define PCIE1_MEM_SIZE (16 * 1024 * 1024) |
||
2929 | +#define PCIE1_MEM_PHY_END (PCIE1_MEM_PHY_BASE + PCIE1_MEM_SIZE - 1) |
||
2930 | + |
||
2931 | +#define PCIE1_IO_PHY_BASE 0x19800000UL |
||
2932 | +#define PCIE1_IO_BASE (KSEG1 + PCIE1_IO_PHY_BASE) |
||
2933 | +#define PCIE1_IO_SIZE (1 * 1024 * 1024) |
||
2934 | +#define PCIE1_IO_PHY_END (PCIE1_IO_PHY_BASE + PCIE1_IO_SIZE - 1) |
||
2935 | + |
||
2936 | +#define PCIE1_RC_CFG_BASE (KSEG1 + 0x19900000) |
||
2937 | +#define PCIE1_APP_LOGIC_REG (KSEG1 + 0x1E100700) |
||
2938 | +#define PCIE1_MSI_PHY_BASE 0x1F400000UL |
||
2939 | + |
||
2940 | +#define PCIE1_PDI_PHY_BASE 0x1F700400UL |
||
2941 | +#define PCIE1_PDI_BASE (KSEG1 + PCIE1_PDI_PHY_BASE) |
||
2942 | +#define PCIE1_PDI_SIZE 0x400 |
||
2943 | + |
||
2944 | +#define PCIE_CFG_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_CFG_BASE) : (PCIE_CFG_BASE)) |
||
2945 | +#define PCIE_MEM_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_BASE) : (PCIE_MEM_BASE)) |
||
2946 | +#define PCIE_IO_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_BASE) : (PCIE_IO_BASE)) |
||
2947 | +#define PCIE_MEM_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_PHY_BASE) : (PCIE_MEM_PHY_BASE)) |
||
2948 | +#define PCIE_MEM_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_MEM_PHY_END) : (PCIE_MEM_PHY_END)) |
||
2949 | +#define PCIE_IO_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_PHY_BASE) : (PCIE_IO_PHY_BASE)) |
||
2950 | +#define PCIE_IO_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_IO_PHY_END) : (PCIE_IO_PHY_END)) |
||
2951 | +#define PCIE_APP_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_APP_LOGIC_REG) : (PCIE_APP_LOGIC_REG)) |
||
2952 | +#define PCIE_RC_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_RC_CFG_BASE) : (PCIE_RC_CFG_BASE)) |
||
2953 | +#define PCIE_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_PDI_BASE) : (PCIE_PDI_BASE)) |
||
2954 | + |
||
2955 | +/* PCIe Application Logic Register */ |
||
2956 | +/* RC Core Control Register */ |
||
2957 | +#define PCIE_RC_CCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x10) |
||
2958 | +/* This should be enabled after initializing configuratin registers |
||
2959 | + * Also should check link status retraining bit |
||
2960 | + */ |
||
2961 | +#define PCIE_RC_CCR_LTSSM_ENABLE 0x00000001 /* Enable LTSSM to continue link establishment */ |
||
2962 | + |
||
2963 | +/* RC Core Debug Register */ |
||
2964 | +#define PCIE_RC_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x14) |
||
2965 | +#define PCIE_RC_DR_DLL_UP 0x00000001 /* Data Link Layer Up */ |
||
2966 | +#define PCIE_RC_DR_CURRENT_POWER_STATE 0x0000000E /* Current Power State */ |
||
2967 | +#define PCIE_RC_DR_CURRENT_POWER_STATE_S 1 |
||
2968 | +#define PCIE_RC_DR_CURRENT_LTSSM_STATE 0x000001F0 /* Current LTSSM State */ |
||
2969 | +#define PCIE_RC_DR_CURRENT_LTSSM_STATE_S 4 |
||
2970 | + |
||
2971 | +#define PCIE_RC_DR_PM_DEV_STATE 0x00000E00 /* Power Management D-State */ |
||
2972 | +#define PCIE_RC_DR_PM_DEV_STATE_S 9 |
||
2973 | + |
||
2974 | +#define PCIE_RC_DR_PM_ENABLED 0x00001000 /* Power Management State from PMU */ |
||
2975 | +#define PCIE_RC_DR_PME_EVENT_ENABLED 0x00002000 /* Power Management Event Enable State */ |
||
2976 | +#define PCIE_RC_DR_AUX_POWER_ENABLED 0x00004000 /* Auxiliary Power Enable */ |
||
2977 | + |
||
2978 | +/* Current Power State Definition */ |
||
2979 | +enum { |
||
2980 | + PCIE_RC_DR_D0 = 0, |
||
2981 | + PCIE_RC_DR_D1, /* Not supported */ |
||
2982 | + PCIE_RC_DR_D2, /* Not supported */ |
||
2983 | + PCIE_RC_DR_D3, |
||
2984 | + PCIE_RC_DR_UN, |
||
2985 | +}; |
||
2986 | + |
||
2987 | +/* PHY Link Status Register */ |
||
2988 | +#define PCIE_PHY_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x18) |
||
2989 | +#define PCIE_PHY_SR_PHY_LINK_UP 0x00000001 /* PHY Link Up/Down Indicator */ |
||
2990 | + |
||
2991 | +/* Electromechanical Control Register */ |
||
2992 | +#define PCIE_EM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x1C) |
||
2993 | +#define PCIE_EM_CR_CARD_IS_PRESENT 0x00000001 /* Card Presence Detect State */ |
||
2994 | +#define PCIE_EM_CR_MRL_OPEN 0x00000002 /* MRL Sensor State */ |
||
2995 | +#define PCIE_EM_CR_POWER_FAULT_SET 0x00000004 /* Power Fault Detected */ |
||
2996 | +#define PCIE_EM_CR_MRL_SENSOR_SET 0x00000008 /* MRL Sensor Changed */ |
||
2997 | +#define PCIE_EM_CR_PRESENT_DETECT_SET 0x00000010 /* Card Presense Detect Changed */ |
||
2998 | +#define PCIE_EM_CR_CMD_CPL_INT_SET 0x00000020 /* Command Complete Interrupt */ |
||
2999 | +#define PCIE_EM_CR_SYS_INTERLOCK_SET 0x00000040 /* System Electromechanical IterLock Engaged */ |
||
3000 | +#define PCIE_EM_CR_ATTENTION_BUTTON_SET 0x00000080 /* Attention Button Pressed */ |
||
3001 | + |
||
3002 | +/* Interrupt Status Register */ |
||
3003 | +#define PCIE_IR_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x20) |
||
3004 | +#define PCIE_IR_SR_PME_CAUSE_MSI 0x00000002 /* MSI caused by PME */ |
||
3005 | +#define PCIE_IR_SR_HP_PME_WAKE_GEN 0x00000004 /* Hotplug PME Wake Generation */ |
||
3006 | +#define PCIE_IR_SR_HP_MSI 0x00000008 /* Hotplug MSI */ |
||
3007 | +#define PCIE_IR_SR_AHB_LU_ERR 0x00000030 /* AHB Bridge Lookup Error Signals */ |
||
3008 | +#define PCIE_IR_SR_AHB_LU_ERR_S 4 |
||
3009 | +#define PCIE_IR_SR_INT_MSG_NUM 0x00003E00 /* Interrupt Message Number */ |
||
3010 | +#define PCIE_IR_SR_INT_MSG_NUM_S 9 |
||
3011 | +#define PCIE_IR_SR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ |
||
3012 | +#define PCIE_IR_SR_AER_INT_MSG_NUM_S 27 |
||
3013 | + |
||
3014 | +/* Message Control Register */ |
||
3015 | +#define PCIE_MSG_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x30) |
||
3016 | +#define PCIE_MSG_CR_GEN_PME_TURN_OFF_MSG 0x00000001 /* Generate PME Turn Off Message */ |
||
3017 | +#define PCIE_MSG_CR_GEN_UNLOCK_MSG 0x00000002 /* Generate Unlock Message */ |
||
3018 | + |
||
3019 | +#define PCIE_VDM_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x34) |
||
3020 | + |
||
3021 | +/* Vendor-Defined Message Requester ID Register */ |
||
3022 | +#define PCIE_VDM_RID(X) (PCIE_APP_PORT_TO_BASE (X) + 0x38) |
||
3023 | +#define PCIE_VDM_RID_VENROR_MSG_REQ_ID 0x0000FFFF |
||
3024 | +#define PCIE_VDM_RID_VDMRID_S 0 |
||
3025 | + |
||
3026 | +/* ASPM Control Register */ |
||
3027 | +#define PCIE_ASPM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x40) |
||
3028 | +#define PCIE_ASPM_CR_HOT_RST 0x00000001 /* Hot Reset Request to the downstream device */ |
||
3029 | +#define PCIE_ASPM_CR_REQ_EXIT_L1 0x00000002 /* Request to Exit L1 */ |
||
3030 | +#define PCIE_ASPM_CR_REQ_ENTER_L1 0x00000004 /* Request to Enter L1 */ |
||
3031 | + |
||
3032 | +/* Vendor Message DW0 Register */ |
||
3033 | +#define PCIE_VM_MSG_DW0(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x50) |
||
3034 | +#define PCIE_VM_MSG_DW0_TYPE 0x0000001F /* Message type */ |
||
3035 | +#define PCIE_VM_MSG_DW0_TYPE_S 0 |
||
3036 | +#define PCIE_VM_MSG_DW0_FORMAT 0x00000060 /* Format */ |
||
3037 | +#define PCIE_VM_MSG_DW0_FORMAT_S 5 |
||
3038 | +#define PCIE_VM_MSG_DW0_TC 0x00007000 /* Traffic Class */ |
||
3039 | +#define PCIE_VM_MSG_DW0_TC_S 12 |
||
3040 | +#define PCIE_VM_MSG_DW0_ATTR 0x000C0000 /* Atrributes */ |
||
3041 | +#define PCIE_VM_MSG_DW0_ATTR_S 18 |
||
3042 | +#define PCIE_VM_MSG_DW0_EP_TLP 0x00100000 /* Poisoned TLP */ |
||
3043 | +#define PCIE_VM_MSG_DW0_TD 0x00200000 /* TLP Digest */ |
||
3044 | +#define PCIE_VM_MSG_DW0_LEN 0xFFC00000 /* Length */ |
||
3045 | +#define PCIE_VM_MSG_DW0_LEN_S 22 |
||
3046 | + |
||
3047 | +/* Format Definition */ |
||
3048 | +enum { |
||
3049 | + PCIE_VM_MSG_FORMAT_00 = 0, /* 3DW Hdr, no data*/ |
||
3050 | + PCIE_VM_MSG_FORMAT_01, /* 4DW Hdr, no data */ |
||
3051 | + PCIE_VM_MSG_FORMAT_10, /* 3DW Hdr, with data */ |
||
3052 | + PCIE_VM_MSG_FORMAT_11, /* 4DW Hdr, with data */ |
||
3053 | +}; |
||
3054 | + |
||
3055 | +/* Traffic Class Definition */ |
||
3056 | +enum { |
||
3057 | + PCIE_VM_MSG_TC0 = 0, |
||
3058 | + PCIE_VM_MSG_TC1, |
||
3059 | + PCIE_VM_MSG_TC2, |
||
3060 | + PCIE_VM_MSG_TC3, |
||
3061 | + PCIE_VM_MSG_TC4, |
||
3062 | + PCIE_VM_MSG_TC5, |
||
3063 | + PCIE_VM_MSG_TC6, |
||
3064 | + PCIE_VM_MSG_TC7, |
||
3065 | +}; |
||
3066 | + |
||
3067 | +/* Attributes Definition */ |
||
3068 | +enum { |
||
3069 | + PCIE_VM_MSG_ATTR_00 = 0, /* RO and No Snoop cleared */ |
||
3070 | + PCIE_VM_MSG_ATTR_01, /* RO cleared , No Snoop set */ |
||
3071 | + PCIE_VM_MSG_ATTR_10, /* RO set, No Snoop cleared*/ |
||
3072 | + PCIE_VM_MSG_ATTR_11, /* RO and No Snoop set */ |
||
3073 | +}; |
||
3074 | + |
||
3075 | +/* Payload Size Definition */ |
||
3076 | +#define PCIE_VM_MSG_LEN_MIN 0 |
||
3077 | +#define PCIE_VM_MSG_LEN_MAX 1024 |
||
3078 | + |
||
3079 | +/* Vendor Message DW1 Register */ |
||
3080 | +#define PCIE_VM_MSG_DW1(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x54) |
||
3081 | +#define PCIE_VM_MSG_DW1_FUNC_NUM 0x00000070 /* Function Number */ |
||
3082 | +#define PCIE_VM_MSG_DW1_FUNC_NUM_S 8 |
||
3083 | +#define PCIE_VM_MSG_DW1_CODE 0x00FF0000 /* Message Code */ |
||
3084 | +#define PCIE_VM_MSG_DW1_CODE_S 16 |
||
3085 | +#define PCIE_VM_MSG_DW1_TAG 0xFF000000 /* Tag */ |
||
3086 | +#define PCIE_VM_MSG_DW1_TAG_S 24 |
||
3087 | + |
||
3088 | +#define PCIE_VM_MSG_DW2(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x58) |
||
3089 | +#define PCIE_VM_MSG_DW3(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x5C) |
||
3090 | + |
||
3091 | +/* Vendor Message Request Register */ |
||
3092 | +#define PCIE_VM_MSG_REQR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x60) |
||
3093 | +#define PCIE_VM_MSG_REQR_REQ 0x00000001 /* Vendor Message Request */ |
||
3094 | + |
||
3095 | + |
||
3096 | +/* AHB Slave Side Band Control Register */ |
||
3097 | +#define PCIE_AHB_SSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x70) |
||
3098 | +#define PCIE_AHB_SSB_REQ_BCM 0x00000001 /* Slave Reques BCM filed */ |
||
3099 | +#define PCIE_AHB_SSB_REQ_EP 0x00000002 /* Slave Reques EP filed */ |
||
3100 | +#define PCIE_AHB_SSB_REQ_TD 0x00000004 /* Slave Reques TD filed */ |
||
3101 | +#define PCIE_AHB_SSB_REQ_ATTR 0x00000018 /* Slave Reques Attribute number */ |
||
3102 | +#define PCIE_AHB_SSB_REQ_ATTR_S 3 |
||
3103 | +#define PCIE_AHB_SSB_REQ_TC 0x000000E0 /* Slave Request TC Field */ |
||
3104 | +#define PCIE_AHB_SSB_REQ_TC_S 5 |
||
3105 | + |
||
3106 | +/* AHB Master SideBand Ctrl Register */ |
||
3107 | +#define PCIE_AHB_MSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x74) |
||
3108 | +#define PCIE_AHB_MSB_RESP_ATTR 0x00000003 /* Master Response Attribute number */ |
||
3109 | +#define PCIE_AHB_MSB_RESP_ATTR_S 0 |
||
3110 | +#define PCIE_AHB_MSB_RESP_BAD_EOT 0x00000004 /* Master Response Badeot filed */ |
||
3111 | +#define PCIE_AHB_MSB_RESP_BCM 0x00000008 /* Master Response BCM filed */ |
||
3112 | +#define PCIE_AHB_MSB_RESP_EP 0x00000010 /* Master Response EP filed */ |
||
3113 | +#define PCIE_AHB_MSB_RESP_TD 0x00000020 /* Master Response TD filed */ |
||
3114 | +#define PCIE_AHB_MSB_RESP_FUN_NUM 0x000003C0 /* Master Response Function number */ |
||
3115 | +#define PCIE_AHB_MSB_RESP_FUN_NUM_S 6 |
||
3116 | + |
||
3117 | +/* AHB Control Register, fixed bus enumeration exception */ |
||
3118 | +#define PCIE_AHB_CTRL(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x78) |
||
3119 | +#define PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS 0x00000001 |
||
3120 | + |
||
3121 | +/* Interrupt Enalbe Register */ |
||
3122 | +#define PCIE_IRNEN(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF4) |
||
3123 | +#define PCIE_IRNCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF8) |
||
3124 | +#define PCIE_IRNICR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xFC) |
||
3125 | + |
||
3126 | +/* PCIe interrupt enable/control/capture register definition */ |
||
3127 | +#define PCIE_IRN_AER_REPORT 0x00000001 /* AER Interrupt */ |
||
3128 | +#define PCIE_IRN_AER_MSIX 0x00000002 /* Advanced Error MSI-X Interrupt */ |
||
3129 | +#define PCIE_IRN_PME 0x00000004 /* PME Interrupt */ |
||
3130 | +#define PCIE_IRN_HOTPLUG 0x00000008 /* Hotplug Interrupt */ |
||
3131 | +#define PCIE_IRN_RX_VDM_MSG 0x00000010 /* Vendor-Defined Message Interrupt */ |
||
3132 | +#define PCIE_IRN_RX_CORRECTABLE_ERR_MSG 0x00000020 /* Correctable Error Message Interrupt */ |
||
3133 | +#define PCIE_IRN_RX_NON_FATAL_ERR_MSG 0x00000040 /* Non-fatal Error Message */ |
||
3134 | +#define PCIE_IRN_RX_FATAL_ERR_MSG 0x00000080 /* Fatal Error Message */ |
||
3135 | +#define PCIE_IRN_RX_PME_MSG 0x00000100 /* PME Message Interrupt */ |
||
3136 | +#define PCIE_IRN_RX_PME_TURNOFF_ACK 0x00000200 /* PME Turnoff Ack Message Interrupt */ |
||
3137 | +#define PCIE_IRN_AHB_BR_FATAL_ERR 0x00000400 /* AHB Fatal Error Interrupt */ |
||
3138 | +#define PCIE_IRN_LINK_AUTO_BW_STATUS 0x00000800 /* Link Auto Bandwidth Status Interrupt */ |
||
3139 | +#define PCIE_IRN_BW_MGT 0x00001000 /* Bandwidth Managment Interrupt */ |
||
3140 | +#define PCIE_IRN_INTA 0x00002000 /* INTA */ |
||
3141 | +#define PCIE_IRN_INTB 0x00004000 /* INTB */ |
||
3142 | +#define PCIE_IRN_INTC 0x00008000 /* INTC */ |
||
3143 | +#define PCIE_IRN_INTD 0x00010000 /* INTD */ |
||
3144 | +#define PCIE_IRN_WAKEUP 0x00020000 /* Wake up Interrupt */ |
||
3145 | + |
||
3146 | +#define PCIE_RC_CORE_COMBINED_INT (PCIE_IRN_AER_REPORT | PCIE_IRN_AER_MSIX | PCIE_IRN_PME | \ |
||
3147 | + PCIE_IRN_HOTPLUG | PCIE_IRN_RX_VDM_MSG | PCIE_IRN_RX_CORRECTABLE_ERR_MSG |\ |
||
3148 | + PCIE_IRN_RX_NON_FATAL_ERR_MSG | PCIE_IRN_RX_FATAL_ERR_MSG | \ |
||
3149 | + PCIE_IRN_RX_PME_MSG | PCIE_IRN_RX_PME_TURNOFF_ACK | PCIE_IRN_AHB_BR_FATAL_ERR | \ |
||
3150 | + PCIE_IRN_LINK_AUTO_BW_STATUS | PCIE_IRN_BW_MGT) |
||
3151 | +/* PCIe RC Configuration Register */ |
||
3152 | +#define PCIE_VDID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x00) |
||
3153 | + |
||
3154 | +/* Bit definition from pci_reg.h */ |
||
3155 | +#define PCIE_PCICMDSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x04) |
||
3156 | +#define PCIE_CCRID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x08) |
||
3157 | +#define PCIE_CLSLTHTBR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x0C) /* EP only */ |
||
3158 | +/* BAR0, BAR1,Only necessary if the bridges implements a device-specific register set or memory buffer */ |
||
3159 | +#define PCIE_BAR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10) /* Not used*/ |
||
3160 | +#define PCIE_BAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14) /* Not used */ |
||
3161 | + |
||
3162 | +#define PCIE_BNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x18) /* Mandatory */ |
||
3163 | +/* Bus Number Register bits */ |
||
3164 | +#define PCIE_BNR_PRIMARY_BUS_NUM 0x000000FF |
||
3165 | +#define PCIE_BNR_PRIMARY_BUS_NUM_S 0 |
||
3166 | +#define PCIE_PNR_SECONDARY_BUS_NUM 0x0000FF00 |
||
3167 | +#define PCIE_PNR_SECONDARY_BUS_NUM_S 8 |
||
3168 | +#define PCIE_PNR_SUB_BUS_NUM 0x00FF0000 |
||
3169 | +#define PCIE_PNR_SUB_BUS_NUM_S 16 |
||
3170 | + |
||
3171 | +/* IO Base/Limit Register bits */ |
||
3172 | +#define PCIE_IOBLSECS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x1C) /* RC only */ |
||
3173 | +#define PCIE_IOBLSECS_32BIT_IO_ADDR 0x00000001 |
||
3174 | +#define PCIE_IOBLSECS_IO_BASE_ADDR 0x000000F0 |
||
3175 | +#define PCIE_IOBLSECS_IO_BASE_ADDR_S 4 |
||
3176 | +#define PCIE_IOBLSECS_32BIT_IOLIMT 0x00000100 |
||
3177 | +#define PCIE_IOBLSECS_IO_LIMIT_ADDR 0x0000F000 |
||
3178 | +#define PCIE_IOBLSECS_IO_LIMIT_ADDR_S 12 |
||
3179 | + |
||
3180 | +/* Non-prefetchable Memory Base/Limit Register bit */ |
||
3181 | +#define PCIE_MBML(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x20) /* RC only */ |
||
3182 | +#define PCIE_MBML_MEM_BASE_ADDR 0x0000FFF0 |
||
3183 | +#define PCIE_MBML_MEM_BASE_ADDR_S 4 |
||
3184 | +#define PCIE_MBML_MEM_LIMIT_ADDR 0xFFF00000 |
||
3185 | +#define PCIE_MBML_MEM_LIMIT_ADDR_S 20 |
||
3186 | + |
||
3187 | +/* Prefetchable Memory Base/Limit Register bit */ |
||
3188 | +#define PCIE_PMBL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x24) /* RC only */ |
||
3189 | +#define PCIE_PMBL_64BIT_ADDR 0x00000001 |
||
3190 | +#define PCIE_PMBL_UPPER_12BIT 0x0000FFF0 |
||
3191 | +#define PCIE_PMBL_UPPER_12BIT_S 4 |
||
3192 | +#define PCIE_PMBL_E64MA 0x00010000 |
||
3193 | +#define PCIE_PMBL_END_ADDR 0xFFF00000 |
||
3194 | +#define PCIE_PMBL_END_ADDR_S 20 |
||
3195 | +#define PCIE_PMBU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x28) /* RC only */ |
||
3196 | +#define PCIE_PMLU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x2C) /* RC only */ |
||
3197 | + |
||
3198 | +/* I/O Base/Limit Upper 16 bits register */ |
||
3199 | +#define PCIE_IO_BANDL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x30) /* RC only */ |
||
3200 | +#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE 0x0000FFFF |
||
3201 | +#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE_S 0 |
||
3202 | +#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT 0xFFFF0000 |
||
3203 | +#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT_S 16 |
||
3204 | + |
||
3205 | +#define PCIE_CPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x34) |
||
3206 | +#define PCIE_EBBAR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x38) |
||
3207 | + |
||
3208 | +/* Interrupt and Secondary Bridge Control Register */ |
||
3209 | +#define PCIE_INTRBCTRL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x3C) |
||
3210 | + |
||
3211 | +#define PCIE_INTRBCTRL_INT_LINE 0x000000FF |
||
3212 | +#define PCIE_INTRBCTRL_INT_LINE_S 0 |
||
3213 | +#define PCIE_INTRBCTRL_INT_PIN 0x0000FF00 |
||
3214 | +#define PCIE_INTRBCTRL_INT_PIN_S 8 |
||
3215 | +#define PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE 0x00010000 /* #PERR */ |
||
3216 | +#define PCIE_INTRBCTRL_SERR_ENABLE 0x00020000 /* #SERR */ |
||
3217 | +#define PCIE_INTRBCTRL_ISA_ENABLE 0x00040000 /* ISA enable, IO 64KB only */ |
||
3218 | +#define PCIE_INTRBCTRL_VGA_ENABLE 0x00080000 /* VGA enable */ |
||
3219 | +#define PCIE_INTRBCTRL_VGA_16BIT_DECODE 0x00100000 /* VGA 16bit decode */ |
||
3220 | +#define PCIE_INTRBCTRL_RST_SECONDARY_BUS 0x00400000 /* Secondary bus rest, hot rest, 1ms */ |
||
3221 | +/* Others are read only */ |
||
3222 | +enum { |
||
3223 | + PCIE_INTRBCTRL_INT_NON = 0, |
||
3224 | + PCIE_INTRBCTRL_INTA, |
||
3225 | + PCIE_INTRBCTRL_INTB, |
||
3226 | + PCIE_INTRBCTRL_INTC, |
||
3227 | + PCIE_INTRBCTRL_INTD, |
||
3228 | +}; |
||
3229 | + |
||
3230 | +#define PCIE_PM_CAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x40) |
||
3231 | + |
||
3232 | +/* Power Management Control and Status Register */ |
||
3233 | +#define PCIE_PM_CSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x44) |
||
3234 | + |
||
3235 | +#define PCIE_PM_CSR_POWER_STATE 0x00000003 /* Power State */ |
||
3236 | +#define PCIE_PM_CSR_POWER_STATE_S 0 |
||
3237 | +#define PCIE_PM_CSR_SW_RST 0x00000008 /* Soft Reset Enabled */ |
||
3238 | +#define PCIE_PM_CSR_PME_ENABLE 0x00000100 /* PME Enable */ |
||
3239 | +#define PCIE_PM_CSR_PME_STATUS 0x00008000 /* PME status */ |
||
3240 | + |
||
3241 | +/* MSI Capability Register for EP */ |
||
3242 | +#define PCIE_MCAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x50) |
||
3243 | + |
||
3244 | +#define PCIE_MCAPR_MSI_CAP_ID 0x000000FF /* MSI Capability ID */ |
||
3245 | +#define PCIE_MCAPR_MSI_CAP_ID_S 0 |
||
3246 | +#define PCIE_MCAPR_MSI_NEXT_CAP_PTR 0x0000FF00 /* Next Capability Pointer */ |
||
3247 | +#define PCIE_MCAPR_MSI_NEXT_CAP_PTR_S 8 |
||
3248 | +#define PCIE_MCAPR_MSI_ENABLE 0x00010000 /* MSI Enable */ |
||
3249 | +#define PCIE_MCAPR_MULTI_MSG_CAP 0x000E0000 /* Multiple Message Capable */ |
||
3250 | +#define PCIE_MCAPR_MULTI_MSG_CAP_S 17 |
||
3251 | +#define PCIE_MCAPR_MULTI_MSG_ENABLE 0x00700000 /* Multiple Message Enable */ |
||
3252 | +#define PCIE_MCAPR_MULTI_MSG_ENABLE_S 20 |
||
3253 | +#define PCIE_MCAPR_ADDR64_CAP 0X00800000 /* 64-bit Address Capable */ |
||
3254 | + |
||
3255 | +/* MSI Message Address Register */ |
||
3256 | +#define PCIE_MA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x54) |
||
3257 | + |
||
3258 | +#define PCIE_MA_ADDR_MASK 0xFFFFFFFC /* Message Address */ |
||
3259 | + |
||
3260 | +/* MSI Message Upper Address Register */ |
||
3261 | +#define PCIE_MUA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x58) |
||
3262 | + |
||
3263 | +/* MSI Message Data Register */ |
||
3264 | +#define PCIE_MD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x5C) |
||
3265 | + |
||
3266 | +#define PCIE_MD_DATA 0x0000FFFF /* Message Data */ |
||
3267 | +#define PCIE_MD_DATA_S 0 |
||
3268 | + |
||
3269 | +/* PCI Express Capability Register */ |
||
3270 | +#define PCIE_XCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70) |
||
3271 | + |
||
3272 | +#define PCIE_XCAP_ID 0x000000FF /* PCI Express Capability ID */ |
||
3273 | +#define PCIE_XCAP_ID_S 0 |
||
3274 | +#define PCIE_XCAP_NEXT_CAP 0x0000FF00 /* Next Capability Pointer */ |
||
3275 | +#define PCIE_XCAP_NEXT_CAP_S 8 |
||
3276 | +#define PCIE_XCAP_VER 0x000F0000 /* PCI Express Capability Version */ |
||
3277 | +#define PCIE_XCAP_VER_S 16 |
||
3278 | +#define PCIE_XCAP_DEV_PORT_TYPE 0x00F00000 /* Device Port Type */ |
||
3279 | +#define PCIE_XCAP_DEV_PORT_TYPE_S 20 |
||
3280 | +#define PCIE_XCAP_SLOT_IMPLEMENTED 0x01000000 /* Slot Implemented */ |
||
3281 | +#define PCIE_XCAP_MSG_INT_NUM 0x3E000000 /* Interrupt Message Number */ |
||
3282 | +#define PCIE_XCAP_MSG_INT_NUM_S 25 |
||
3283 | + |
||
3284 | +/* Device Capability Register */ |
||
3285 | +#define PCIE_DCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74) |
||
3286 | + |
||
3287 | +#define PCIE_DCAP_MAX_PAYLOAD_SIZE 0x00000007 /* Max Payload size */ |
||
3288 | +#define PCIE_DCAP_MAX_PAYLOAD_SIZE_S 0 |
||
3289 | +#define PCIE_DCAP_PHANTOM_FUNC 0x00000018 /* Phanton Function, not supported */ |
||
3290 | +#define PCIE_DCAP_PHANTOM_FUNC_S 3 |
||
3291 | +#define PCIE_DCAP_EXT_TAG 0x00000020 /* Extended Tag Field */ |
||
3292 | +#define PCIE_DCAP_EP_L0S_LATENCY 0x000001C0 /* EP L0s latency only */ |
||
3293 | +#define PCIE_DCAP_EP_L0S_LATENCY_S 6 |
||
3294 | +#define PCIE_DCAP_EP_L1_LATENCY 0x00000E00 /* EP L1 latency only */ |
||
3295 | +#define PCIE_DCAP_EP_L1_LATENCY_S 9 |
||
3296 | +#define PCIE_DCAP_ROLE_BASE_ERR_REPORT 0x00008000 /* Role Based ERR */ |
||
3297 | + |
||
3298 | +/* Maximum payload size supported */ |
||
3299 | +enum { |
||
3300 | + PCIE_MAX_PAYLOAD_128 = 0, |
||
3301 | + PCIE_MAX_PAYLOAD_256, |
||
3302 | + PCIE_MAX_PAYLOAD_512, |
||
3303 | + PCIE_MAX_PAYLOAD_1024, |
||
3304 | + PCIE_MAX_PAYLOAD_2048, |
||
3305 | + PCIE_MAX_PAYLOAD_4096, |
||
3306 | +}; |
||
3307 | + |
||
3308 | +/* Device Control and Status Register */ |
||
3309 | +#define PCIE_DCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x78) |
||
3310 | + |
||
3311 | +#define PCIE_DCTLSTS_CORRECTABLE_ERR_EN 0x00000001 /* COR-ERR */ |
||
3312 | +#define PCIE_DCTLSTS_NONFATAL_ERR_EN 0x00000002 /* Non-fatal ERR */ |
||
3313 | +#define PCIE_DCTLSTS_FATAL_ERR_EN 0x00000004 /* Fatal ERR */ |
||
3314 | +#define PCIE_DCTLSYS_UR_REQ_EN 0x00000008 /* UR ERR */ |
||
3315 | +#define PCIE_DCTLSTS_RELAXED_ORDERING_EN 0x00000010 /* Enable relaxing ordering */ |
||
3316 | +#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE 0x000000E0 /* Max payload mask */ |
||
3317 | +#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE_S 5 |
||
3318 | +#define PCIE_DCTLSTS_EXT_TAG_EN 0x00000100 /* Extended tag field */ |
||
3319 | +#define PCIE_DCTLSTS_PHANTOM_FUNC_EN 0x00000200 /* Phantom Function Enable */ |
||
3320 | +#define PCIE_DCTLSTS_AUX_PM_EN 0x00000400 /* AUX Power PM Enable */ |
||
3321 | +#define PCIE_DCTLSTS_NO_SNOOP_EN 0x00000800 /* Enable no snoop, except root port*/ |
||
3322 | +#define PCIE_DCTLSTS_MAX_READ_SIZE 0x00007000 /* Max Read Request size*/ |
||
3323 | +#define PCIE_DCTLSTS_MAX_READ_SIZE_S 12 |
||
3324 | +#define PCIE_DCTLSTS_CORRECTABLE_ERR 0x00010000 /* COR-ERR Detected */ |
||
3325 | +#define PCIE_DCTLSTS_NONFATAL_ERR 0x00020000 /* Non-Fatal ERR Detected */ |
||
3326 | +#define PCIE_DCTLSTS_FATAL_ER 0x00040000 /* Fatal ERR Detected */ |
||
3327 | +#define PCIE_DCTLSTS_UNSUPPORTED_REQ 0x00080000 /* UR Detected */ |
||
3328 | +#define PCIE_DCTLSTS_AUX_POWER 0x00100000 /* Aux Power Detected */ |
||
3329 | +#define PCIE_DCTLSTS_TRANSACT_PENDING 0x00200000 /* Transaction pending */ |
||
3330 | + |
||
3331 | +#define PCIE_DCTLSTS_ERR_EN (PCIE_DCTLSTS_CORRECTABLE_ERR_EN | \ |
||
3332 | + PCIE_DCTLSTS_NONFATAL_ERR_EN | PCIE_DCTLSTS_FATAL_ERR_EN | \ |
||
3333 | + PCIE_DCTLSYS_UR_REQ_EN) |
||
3334 | + |
||
3335 | +/* Link Capability Register */ |
||
3336 | +#define PCIE_LCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7C) |
||
3337 | +#define PCIE_LCAP_MAX_LINK_SPEED 0x0000000F /* Max link speed, 0x1 by default */ |
||
3338 | +#define PCIE_LCAP_MAX_LINK_SPEED_S 0 |
||
3339 | +#define PCIE_LCAP_MAX_LENGTH_WIDTH 0x000003F0 /* Maxium Length Width */ |
||
3340 | +#define PCIE_LCAP_MAX_LENGTH_WIDTH_S 4 |
||
3341 | +#define PCIE_LCAP_ASPM_LEVEL 0x00000C00 /* Active State Link PM Support */ |
||
3342 | +#define PCIE_LCAP_ASPM_LEVEL_S 10 |
||
3343 | +#define PCIE_LCAP_L0S_EIXT_LATENCY 0x00007000 /* L0s Exit Latency */ |
||
3344 | +#define PCIE_LCAP_L0S_EIXT_LATENCY_S 12 |
||
3345 | +#define PCIE_LCAP_L1_EXIT_LATENCY 0x00038000 /* L1 Exit Latency */ |
||
3346 | +#define PCIE_LCAP_L1_EXIT_LATENCY_S 15 |
||
3347 | +#define PCIE_LCAP_CLK_PM 0x00040000 /* Clock Power Management */ |
||
3348 | +#define PCIE_LCAP_SDER 0x00080000 /* Surprise Down Error Reporting */ |
||
3349 | +#define PCIE_LCAP_DLL_ACTIVE_REPROT 0x00100000 /* Data Link Layer Active Reporting Capable */ |
||
3350 | +#define PCIE_LCAP_PORT_NUM 0xFF0000000 /* Port number */ |
||
3351 | +#define PCIE_LCAP_PORT_NUM_S 24 |
||
3352 | + |
||
3353 | +/* Maximum Length width definition */ |
||
3354 | +#define PCIE_MAX_LENGTH_WIDTH_RES 0x00 |
||
3355 | +#define PCIE_MAX_LENGTH_WIDTH_X1 0x01 /* Default */ |
||
3356 | +#define PCIE_MAX_LENGTH_WIDTH_X2 0x02 |
||
3357 | +#define PCIE_MAX_LENGTH_WIDTH_X4 0x04 |
||
3358 | +#define PCIE_MAX_LENGTH_WIDTH_X8 0x08 |
||
3359 | +#define PCIE_MAX_LENGTH_WIDTH_X12 0x0C |
||
3360 | +#define PCIE_MAX_LENGTH_WIDTH_X16 0x10 |
||
3361 | +#define PCIE_MAX_LENGTH_WIDTH_X32 0x20 |
||
3362 | + |
||
3363 | +/* Active State Link PM definition */ |
||
3364 | +enum { |
||
3365 | + PCIE_ASPM_RES0 = 0, |
||
3366 | + PCIE_ASPM_L0S_ENTRY_SUPPORT, /* L0s */ |
||
3367 | + PCIE_ASPM_RES1, |
||
3368 | + PCIE_ASPM_L0S_L1_ENTRY_SUPPORT, /* L0s and L1, default */ |
||
3369 | +}; |
||
3370 | + |
||
3371 | +/* L0s Exit Latency definition */ |
||
3372 | +enum { |
||
3373 | + PCIE_L0S_EIXT_LATENCY_L64NS = 0, /* < 64 ns */ |
||
3374 | + PCIE_L0S_EIXT_LATENCY_B64A128, /* > 64 ns < 128 ns */ |
||
3375 | + PCIE_L0S_EIXT_LATENCY_B128A256, /* > 128 ns < 256 ns */ |
||
3376 | + PCIE_L0S_EIXT_LATENCY_B256A512, /* > 256 ns < 512 ns */ |
||
3377 | + PCIE_L0S_EIXT_LATENCY_B512TO1U, /* > 512 ns < 1 us */ |
||
3378 | + PCIE_L0S_EIXT_LATENCY_B1A2U, /* > 1 us < 2 us */ |
||
3379 | + PCIE_L0S_EIXT_LATENCY_B2A4U, /* > 2 us < 4 us */ |
||
3380 | + PCIE_L0S_EIXT_LATENCY_M4US, /* > 4 us */ |
||
3381 | +}; |
||
3382 | + |
||
3383 | +/* L1 Exit Latency definition */ |
||
3384 | +enum { |
||
3385 | + PCIE_L1_EXIT_LATENCY_L1US = 0, /* < 1 us */ |
||
3386 | + PCIE_L1_EXIT_LATENCY_B1A2, /* > 1 us < 2 us */ |
||
3387 | + PCIE_L1_EXIT_LATENCY_B2A4, /* > 2 us < 4 us */ |
||
3388 | + PCIE_L1_EXIT_LATENCY_B4A8, /* > 4 us < 8 us */ |
||
3389 | + PCIE_L1_EXIT_LATENCY_B8A16, /* > 8 us < 16 us */ |
||
3390 | + PCIE_L1_EXIT_LATENCY_B16A32, /* > 16 us < 32 us */ |
||
3391 | + PCIE_L1_EXIT_LATENCY_B32A64, /* > 32 us < 64 us */ |
||
3392 | + PCIE_L1_EXIT_LATENCY_M64US, /* > 64 us */ |
||
3393 | +}; |
||
3394 | + |
||
3395 | +/* Link Control and Status Register */ |
||
3396 | +#define PCIE_LCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x80) |
||
3397 | +#define PCIE_LCTLSTS_ASPM_ENABLE 0x00000003 /* Active State Link PM Control */ |
||
3398 | +#define PCIE_LCTLSTS_ASPM_ENABLE_S 0 |
||
3399 | +#define PCIE_LCTLSTS_RCB128 0x00000008 /* Read Completion Boundary 128*/ |
||
3400 | +#define PCIE_LCTLSTS_LINK_DISABLE 0x00000010 /* Link Disable */ |
||
3401 | +#define PCIE_LCTLSTS_RETRIAN_LINK 0x00000020 /* Retrain Link */ |
||
3402 | +#define PCIE_LCTLSTS_COM_CLK_CFG 0x00000040 /* Common Clock Configuration */ |
||
3403 | +#define PCIE_LCTLSTS_EXT_SYNC 0x00000080 /* Extended Synch */ |
||
3404 | +#define PCIE_LCTLSTS_CLK_PM_EN 0x00000100 /* Enable Clock Powerm Management */ |
||
3405 | +#define PCIE_LCTLSTS_LINK_SPEED 0x000F0000 /* Link Speed */ |
||
3406 | +#define PCIE_LCTLSTS_LINK_SPEED_S 16 |
||
3407 | +#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH 0x03F00000 /* Negotiated Link Width */ |
||
3408 | +#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH_S 20 |
||
3409 | +#define PCIE_LCTLSTS_RETRAIN_PENDING 0x08000000 /* Link training is ongoing */ |
||
3410 | +#define PCIE_LCTLSTS_SLOT_CLK_CFG 0x10000000 /* Slot Clock Configuration */ |
||
3411 | +#define PCIE_LCTLSTS_DLL_ACTIVE 0x20000000 /* Data Link Layer Active */ |
||
3412 | + |
||
3413 | +/* Slot Capabilities Register */ |
||
3414 | +#define PCIE_SLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x84) |
||
3415 | + |
||
3416 | +/* Slot Capabilities */ |
||
3417 | +#define PCIE_SLCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x88) |
||
3418 | + |
||
3419 | +/* Root Control and Capability Register */ |
||
3420 | +#define PCIE_RCTLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x8C) |
||
3421 | +#define PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR 0x00000001 /* #SERR on COR-ERR */ |
||
3422 | +#define PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR 0x00000002 /* #SERR on Non-Fatal ERR */ |
||
3423 | +#define PCIE_RCTLCAP_SERR_ON_FATAL_ERR 0x00000004 /* #SERR on Fatal ERR */ |
||
3424 | +#define PCIE_RCTLCAP_PME_INT_EN 0x00000008 /* PME Interrupt Enable */ |
||
3425 | +#define PCIE_RCTLCAP_SERR_ENABLE (PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR | \ |
||
3426 | + PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR | PCIE_RCTLCAP_SERR_ON_FATAL_ERR) |
||
3427 | +/* Root Status Register */ |
||
3428 | +#define PCIE_RSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x90) |
||
3429 | +#define PCIE_RSTS_PME_REQ_ID 0x0000FFFF /* PME Request ID */ |
||
3430 | +#define PCIE_RSTS_PME_REQ_ID_S 0 |
||
3431 | +#define PCIE_RSTS_PME_STATUS 0x00010000 /* PME Status */ |
||
3432 | +#define PCIE_RSTS_PME_PENDING 0x00020000 /* PME Pending */ |
||
3433 | + |
||
3434 | +/* PCI Express Enhanced Capability Header */ |
||
3435 | +#define PCIE_ENHANCED_CAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x100) |
||
3436 | +#define PCIE_ENHANCED_CAP_ID 0x0000FFFF /* PCI Express Extended Capability ID */ |
||
3437 | +#define PCIE_ENHANCED_CAP_ID_S 0 |
||
3438 | +#define PCIE_ENHANCED_CAP_VER 0x000F0000 /* Capability Version */ |
||
3439 | +#define PCIE_ENHANCED_CAP_VER_S 16 |
||
3440 | +#define PCIE_ENHANCED_CAP_NEXT_OFFSET 0xFFF00000 /* Next Capability Offset */ |
||
3441 | +#define PCIE_ENHANCED_CAP_NEXT_OFFSET_S 20 |
||
3442 | + |
||
3443 | +/* Uncorrectable Error Status Register */ |
||
3444 | +#define PCIE_UES_R(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x104) |
||
3445 | +#define PCIE_DATA_LINK_PROTOCOL_ERR 0x00000010 /* Data Link Protocol Error Status */ |
||
3446 | +#define PCIE_SURPRISE_DOWN_ERROR 0x00000020 /* Surprise Down Error Status */ |
||
3447 | +#define PCIE_POISONED_TLP 0x00001000 /* Poisoned TLP Status */ |
||
3448 | +#define PCIE_FC_PROTOCOL_ERR 0x00002000 /* Flow Control Protocol Error Status */ |
||
3449 | +#define PCIE_COMPLETION_TIMEOUT 0x00004000 /* Completion Timeout Status */ |
||
3450 | +#define PCIE_COMPLETOR_ABORT 0x00008000 /* Completer Abort Error */ |
||
3451 | +#define PCIE_UNEXPECTED_COMPLETION 0x00010000 /* Unexpected Completion Status */ |
||
3452 | +#define PCIE_RECEIVER_OVERFLOW 0x00020000 /* Receive Overflow Status */ |
||
3453 | +#define PCIE_MALFORNED_TLP 0x00040000 /* Malformed TLP Stauts */ |
||
3454 | +#define PCIE_ECRC_ERR 0x00080000 /* ECRC Error Stauts */ |
||
3455 | +#define PCIE_UR_REQ 0x00100000 /* Unsupported Request Error Status */ |
||
3456 | +#define PCIE_ALL_UNCORRECTABLE_ERR (PCIE_DATA_LINK_PROTOCOL_ERR | PCIE_SURPRISE_DOWN_ERROR | \ |
||
3457 | + PCIE_POISONED_TLP | PCIE_FC_PROTOCOL_ERR | PCIE_COMPLETION_TIMEOUT | \ |
||
3458 | + PCIE_COMPLETOR_ABORT | PCIE_UNEXPECTED_COMPLETION | PCIE_RECEIVER_OVERFLOW |\ |
||
3459 | + PCIE_MALFORNED_TLP | PCIE_ECRC_ERR | PCIE_UR_REQ) |
||
3460 | + |
||
3461 | +/* Uncorrectable Error Mask Register, Mask means no report */ |
||
3462 | +#define PCIE_UEMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x108) |
||
3463 | + |
||
3464 | +/* Uncorrectable Error Severity Register */ |
||
3465 | +#define PCIE_UESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10C) |
||
3466 | + |
||
3467 | +/* Correctable Error Status Register */ |
||
3468 | +#define PCIE_CESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x110) |
||
3469 | +#define PCIE_RX_ERR 0x00000001 /* Receive Error Status */ |
||
3470 | +#define PCIE_BAD_TLP 0x00000040 /* Bad TLP Status */ |
||
3471 | +#define PCIE_BAD_DLLP 0x00000080 /* Bad DLLP Status */ |
||
3472 | +#define PCIE_REPLAY_NUM_ROLLOVER 0x00000100 /* Replay Number Rollover Status */ |
||
3473 | +#define PCIE_REPLAY_TIMER_TIMEOUT_ERR 0x00001000 /* Reply Timer Timeout Status */ |
||
3474 | +#define PCIE_ADVISORY_NONFTAL_ERR 0x00002000 /* Advisory Non-Fatal Error Status */ |
||
3475 | +#define PCIE_CORRECTABLE_ERR (PCIE_RX_ERR | PCIE_BAD_TLP | PCIE_BAD_DLLP | PCIE_REPLAY_NUM_ROLLOVER |\ |
||
3476 | + PCIE_REPLAY_TIMER_TIMEOUT_ERR | PCIE_ADVISORY_NONFTAL_ERR) |
||
3477 | + |
||
3478 | +/* Correctable Error Mask Register */ |
||
3479 | +#define PCIE_CEMR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x114) |
||
3480 | + |
||
3481 | +/* Advanced Error Capabilities and Control Register */ |
||
3482 | +#define PCIE_AECCR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x118) |
||
3483 | +#define PCIE_AECCR_FIRST_ERR_PTR 0x0000001F /* First Error Pointer */ |
||
3484 | +#define PCIE_AECCR_FIRST_ERR_PTR_S 0 |
||
3485 | +#define PCIE_AECCR_ECRC_GEN_CAP 0x00000020 /* ECRC Generation Capable */ |
||
3486 | +#define PCIE_AECCR_ECRC_GEN_EN 0x00000040 /* ECRC Generation Enable */ |
||
3487 | +#define PCIE_AECCR_ECRC_CHECK_CAP 0x00000080 /* ECRC Check Capable */ |
||
3488 | +#define PCIE_AECCR_ECRC_CHECK_EN 0x00000100 /* ECRC Check Enable */ |
||
3489 | + |
||
3490 | +/* Header Log Register 1 */ |
||
3491 | +#define PCIE_HLR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x11C) |
||
3492 | + |
||
3493 | +/* Header Log Register 2 */ |
||
3494 | +#define PCIE_HLR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x120) |
||
3495 | + |
||
3496 | +/* Header Log Register 3 */ |
||
3497 | +#define PCIE_HLR3(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x124) |
||
3498 | + |
||
3499 | +/* Header Log Register 4 */ |
||
3500 | +#define PCIE_HLR4(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x128) |
||
3501 | + |
||
3502 | +/* Root Error Command Register */ |
||
3503 | +#define PCIE_RECR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x12C) |
||
3504 | +#define PCIE_RECR_CORRECTABLE_ERR_REPORT_EN 0x00000001 /* COR-ERR */ |
||
3505 | +#define PCIE_RECR_NONFATAL_ERR_REPORT_EN 0x00000002 /* Non-Fatal ERR */ |
||
3506 | +#define PCIE_RECR_FATAL_ERR_REPORT_EN 0x00000004 /* Fatal ERR */ |
||
3507 | +#define PCIE_RECR_ERR_REPORT_EN (PCIE_RECR_CORRECTABLE_ERR_REPORT_EN | \ |
||
3508 | + PCIE_RECR_NONFATAL_ERR_REPORT_EN | PCIE_RECR_FATAL_ERR_REPORT_EN) |
||
3509 | + |
||
3510 | +/* Root Error Status Register */ |
||
3511 | +#define PCIE_RESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x130) |
||
3512 | +#define PCIE_RESR_CORRECTABLE_ERR 0x00000001 /* COR-ERR Receveid */ |
||
3513 | +#define PCIE_RESR_MULTI_CORRECTABLE_ERR 0x00000002 /* Multiple COR-ERR Received */ |
||
3514 | +#define PCIE_RESR_FATAL_NOFATAL_ERR 0x00000004 /* ERR Fatal/Non-Fatal Received */ |
||
3515 | +#define PCIE_RESR_MULTI_FATAL_NOFATAL_ERR 0x00000008 /* Multiple ERR Fatal/Non-Fatal Received */ |
||
3516 | +#define PCIE_RESR_FIRST_UNCORRECTABLE_FATAL_ERR 0x00000010 /* First UN-COR Fatal */ |
||
3517 | +#define PCIR_RESR_NON_FATAL_ERR 0x00000020 /* Non-Fatal Error Message Received */ |
||
3518 | +#define PCIE_RESR_FATAL_ERR 0x00000040 /* Fatal Message Received */ |
||
3519 | +#define PCIE_RESR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ |
||
3520 | +#define PCIE_RESR_AER_INT_MSG_NUM_S 27 |
||
3521 | + |
||
3522 | +/* Error Source Indentification Register */ |
||
3523 | +#define PCIE_ESIR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x134) |
||
3524 | +#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID 0x0000FFFF |
||
3525 | +#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID_S 0 |
||
3526 | +#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID 0xFFFF0000 |
||
3527 | +#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID_S 16 |
||
3528 | + |
||
3529 | +/* VC Enhanced Capability Header */ |
||
3530 | +#define PCIE_VC_ECH(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x140) |
||
3531 | + |
||
3532 | +/* Port VC Capability Register */ |
||
3533 | +#define PCIE_PVC1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x144) |
||
3534 | +#define PCIE_PVC1_EXT_VC_CNT 0x00000007 /* Extended VC Count */ |
||
3535 | +#define PCIE_PVC1_EXT_VC_CNT_S 0 |
||
3536 | +#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT 0x00000070 /* Low Priority Extended VC Count */ |
||
3537 | +#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT_S 4 |
||
3538 | +#define PCIE_PVC1_REF_CLK 0x00000300 /* Reference Clock */ |
||
3539 | +#define PCIE_PVC1_REF_CLK_S 8 |
||
3540 | +#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE 0x00000C00 /* Port Arbitration Table Entry Size */ |
||
3541 | +#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE_S 10 |
||
3542 | + |
||
3543 | +/* Extended Virtual Channel Count Defintion */ |
||
3544 | +#define PCIE_EXT_VC_CNT_MIN 0 |
||
3545 | +#define PCIE_EXT_VC_CNT_MAX 7 |
||
3546 | + |
||
3547 | +/* Port Arbitration Table Entry Size Definition */ |
||
3548 | +enum { |
||
3549 | + PCIE_PORT_ARB_TAB_ENTRY_SIZE_S1BIT = 0, |
||
3550 | + PCIE_PORT_ARB_TAB_ENTRY_SIZE_S2BIT, |
||
3551 | + PCIE_PORT_ARB_TAB_ENTRY_SIZE_S4BIT, |
||
3552 | + PCIE_PORT_ARB_TAB_ENTRY_SIZE_S8BIT, |
||
3553 | +}; |
||
3554 | + |
||
3555 | +/* Port VC Capability Register 2 */ |
||
3556 | +#define PCIE_PVC2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x148) |
||
3557 | +#define PCIE_PVC2_VC_ARB_16P_FIXED_WRR 0x00000001 /* HW Fixed arbitration, 16 phase WRR */ |
||
3558 | +#define PCIE_PVC2_VC_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ |
||
3559 | +#define PCIE_PVC2_VC_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ |
||
3560 | +#define PCIE_PVC2_VC_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ |
||
3561 | +#define PCIE_PVC2_VC_ARB_WRR 0x0000000F |
||
3562 | +#define PCIE_PVC2_VC_ARB_TAB_OFFSET 0xFF000000 /* VC arbitration table offset, not support */ |
||
3563 | +#define PCIE_PVC2_VC_ARB_TAB_OFFSET_S 24 |
||
3564 | + |
||
3565 | +/* Port VC Control and Status Register */ |
||
3566 | +#define PCIE_PVCCRSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14C) |
||
3567 | +#define PCIE_PVCCRSR_LOAD_VC_ARB_TAB 0x00000001 /* Load VC Arbitration Table */ |
||
3568 | +#define PCIE_PVCCRSR_VC_ARB_SEL 0x0000000E /* VC Arbitration Select */ |
||
3569 | +#define PCIE_PVCCRSR_VC_ARB_SEL_S 1 |
||
3570 | +#define PCIE_PVCCRSR_VC_ARB_TAB_STATUS 0x00010000 /* Arbitration Status */ |
||
3571 | + |
||
3572 | +/* VC0 Resource Capability Register */ |
||
3573 | +#define PCIE_VC0_RC(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x150) |
||
3574 | +#define PCIE_VC0_RC_PORT_ARB_HW_FIXED 0x00000001 /* HW Fixed arbitration */ |
||
3575 | +#define PCIE_VC0_RC_PORT_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ |
||
3576 | +#define PCIE_VC0_RC_PORT_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ |
||
3577 | +#define PCIE_VC0_RC_PORT_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ |
||
3578 | +#define PCIE_VC0_RC_PORT_ARB_TM_128P_WRR 0x00000010 /* Time-based 128 phase WRR */ |
||
3579 | +#define PCIE_VC0_RC_PORT_ARB_TM_256P_WRR 0x00000020 /* Time-based 256 phase WRR */ |
||
3580 | +#define PCIE_VC0_RC_PORT_ARB (PCIE_VC0_RC_PORT_ARB_HW_FIXED | PCIE_VC0_RC_PORT_ARB_32P_WRR |\ |
||
3581 | + PCIE_VC0_RC_PORT_ARB_64P_WRR | PCIE_VC0_RC_PORT_ARB_128P_WRR | \ |
||
3582 | + PCIE_VC0_RC_PORT_ARB_TM_128P_WRR | PCIE_VC0_RC_PORT_ARB_TM_256P_WRR) |
||
3583 | + |
||
3584 | +#define PCIE_VC0_RC_REJECT_SNOOP 0x00008000 /* Reject Snoop Transactioin */ |
||
3585 | +#define PCIE_VC0_RC_MAX_TIMESLOTS 0x007F0000 /* Maximum time Slots */ |
||
3586 | +#define PCIE_VC0_RC_MAX_TIMESLOTS_S 16 |
||
3587 | +#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET 0xFF000000 /* Port Arbitration Table Offset */ |
||
3588 | +#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET_S 24 |
||
3589 | + |
||
3590 | +/* VC0 Resource Control Register */ |
||
3591 | +#define PCIE_VC0_RC0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x154) |
||
3592 | +#define PCIE_VC0_RC0_TVM0 0x00000001 /* TC0 and VC0 */ |
||
3593 | +#define PCIE_VC0_RC0_TVM1 0x00000002 /* TC1 and VC1 */ |
||
3594 | +#define PCIE_VC0_RC0_TVM2 0x00000004 /* TC2 and VC2 */ |
||
3595 | +#define PCIE_VC0_RC0_TVM3 0x00000008 /* TC3 and VC3 */ |
||
3596 | +#define PCIE_VC0_RC0_TVM4 0x00000010 /* TC4 and VC4 */ |
||
3597 | +#define PCIE_VC0_RC0_TVM5 0x00000020 /* TC5 and VC5 */ |
||
3598 | +#define PCIE_VC0_RC0_TVM6 0x00000040 /* TC6 and VC6 */ |
||
3599 | +#define PCIE_VC0_RC0_TVM7 0x00000080 /* TC7 and VC7 */ |
||
3600 | +#define PCIE_VC0_RC0_TC_VC 0x000000FF /* TC/VC mask */ |
||
3601 | + |
||
3602 | +#define PCIE_VC0_RC0_LOAD_PORT_ARB_TAB 0x00010000 /* Load Port Arbitration Table */ |
||
3603 | +#define PCIE_VC0_RC0_PORT_ARB_SEL 0x000E0000 /* Port Arbitration Select */ |
||
3604 | +#define PCIE_VC0_RC0_PORT_ARB_SEL_S 17 |
||
3605 | +#define PCIE_VC0_RC0_VC_ID 0x07000000 /* VC ID */ |
||
3606 | +#define PCIE_VC0_RC0_VC_ID_S 24 |
||
3607 | +#define PCIE_VC0_RC0_VC_EN 0x80000000 /* VC Enable */ |
||
3608 | + |
||
3609 | +/* VC0 Resource Status Register */ |
||
3610 | +#define PCIE_VC0_RSR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x158) |
||
3611 | +#define PCIE_VC0_RSR0_PORT_ARB_TAB_STATUS 0x00010000 /* Port Arbitration Table Status,not used */ |
||
3612 | +#define PCIE_VC0_RSR0_VC_NEG_PENDING 0x00020000 /* VC Negotiation Pending */ |
||
3613 | + |
||
3614 | +/* Ack Latency Timer and Replay Timer Register */ |
||
3615 | +#define PCIE_ALTRT(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x700) |
||
3616 | +#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT 0x0000FFFF /* Round Trip Latency Time Limit */ |
||
3617 | +#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT_S 0 |
||
3618 | +#define PCIE_ALTRT_REPLAY_TIME_LIMIT 0xFFFF0000 /* Replay Time Limit */ |
||
3619 | +#define PCIE_ALTRT_REPLAY_TIME_LIMIT_S 16 |
||
3620 | + |
||
3621 | +/* Other Message Register */ |
||
3622 | +#define PCIE_OMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x704) |
||
3623 | + |
||
3624 | +/* Port Force Link Register */ |
||
3625 | +#define PCIE_PFLR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x708) |
||
3626 | +#define PCIE_PFLR_LINK_NUM 0x000000FF /* Link Number */ |
||
3627 | +#define PCIE_PFLR_LINK_NUM_S 0 |
||
3628 | +#define PCIE_PFLR_FORCE_LINK 0x00008000 /* Force link */ |
||
3629 | +#define PCIE_PFLR_LINK_STATE 0x003F0000 /* Link State */ |
||
3630 | +#define PCIE_PFLR_LINK_STATE_S 16 |
||
3631 | +#define PCIE_PFLR_LOW_POWER_ENTRY_CNT 0xFF000000 /* Low Power Entrance Count, only for EP */ |
||
3632 | +#define PCIE_PFLR_LOW_POWER_ENTRY_CNT_S 24 |
||
3633 | + |
||
3634 | +/* Ack Frequency Register */ |
||
3635 | +#define PCIE_AFR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70C) |
||
3636 | +#define PCIE_AFR_AF 0x000000FF /* Ack Frequency */ |
||
3637 | +#define PCIE_AFR_AF_S 0 |
||
3638 | +#define PCIE_AFR_FTS_NUM 0x0000FF00 /* The number of Fast Training Sequence from L0S to L0 */ |
||
3639 | +#define PCIE_AFR_FTS_NUM_S 8 |
||
3640 | +#define PCIE_AFR_COM_FTS_NUM 0x00FF0000 /* N_FTS; when common clock is used*/ |
||
3641 | +#define PCIE_AFR_COM_FTS_NUM_S 16 |
||
3642 | +#define PCIE_AFR_L0S_ENTRY_LATENCY 0x07000000 /* L0s Entrance Latency */ |
||
3643 | +#define PCIE_AFR_L0S_ENTRY_LATENCY_S 24 |
||
3644 | +#define PCIE_AFR_L1_ENTRY_LATENCY 0x38000000 /* L1 Entrance Latency */ |
||
3645 | +#define PCIE_AFR_L1_ENTRY_LATENCY_S 27 |
||
3646 | +#define PCIE_AFR_FTS_NUM_DEFAULT 32 |
||
3647 | +#define PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT 7 |
||
3648 | +#define PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT 5 |
||
3649 | + |
||
3650 | +/* Port Link Control Register */ |
||
3651 | +#define PCIE_PLCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x710) |
||
3652 | +#define PCIE_PLCR_OTHER_MSG_REQ 0x00000001 /* Other Message Request */ |
||
3653 | +#define PCIE_PLCR_SCRAMBLE_DISABLE 0x00000002 /* Scramble Disable */ |
||
3654 | +#define PCIE_PLCR_LOOPBACK_EN 0x00000004 /* Loopback Enable */ |
||
3655 | +#define PCIE_PLCR_LTSSM_HOT_RST 0x00000008 /* Force LTSSM to the hot reset */ |
||
3656 | +#define PCIE_PLCR_DLL_LINK_EN 0x00000020 /* Enable Link initialization */ |
||
3657 | +#define PCIE_PLCR_FAST_LINK_SIM_EN 0x00000080 /* Sets all internal timers to fast mode for simulation purposes */ |
||
3658 | +#define PCIE_PLCR_LINK_MODE 0x003F0000 /* Link Mode Enable Mask */ |
||
3659 | +#define PCIE_PLCR_LINK_MODE_S 16 |
||
3660 | +#define PCIE_PLCR_CORRUPTED_CRC_EN 0x02000000 /* Enabled Corrupt CRC */ |
||
3661 | + |
||
3662 | +/* Lane Skew Register */ |
||
3663 | +#define PCIE_LSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x714) |
||
3664 | +#define PCIE_LSR_LANE_SKEW_NUM 0x00FFFFFF /* Insert Lane Skew for Transmit, not applicable */ |
||
3665 | +#define PCIE_LSR_LANE_SKEW_NUM_S 0 |
||
3666 | +#define PCIE_LSR_FC_DISABLE 0x01000000 /* Disable of Flow Control */ |
||
3667 | +#define PCIE_LSR_ACKNAK_DISABLE 0x02000000 /* Disable of Ack/Nak */ |
||
3668 | +#define PCIE_LSR_LANE_DESKEW_DISABLE 0x80000000 /* Disable of Lane-to-Lane Skew */ |
||
3669 | + |
||
3670 | +/* Symbol Number Register */ |
||
3671 | +#define PCIE_SNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x718) |
||
3672 | +#define PCIE_SNR_TS 0x0000000F /* Number of TS Symbol */ |
||
3673 | +#define PCIE_SNR_TS_S 0 |
||
3674 | +#define PCIE_SNR_SKP 0x00000700 /* Number of SKP Symbol */ |
||
3675 | +#define PCIE_SNR_SKP_S 8 |
||
3676 | +#define PCIE_SNR_REPLAY_TIMER 0x0007C000 /* Timer Modifier for Replay Timer */ |
||
3677 | +#define PCIE_SNR_REPLAY_TIMER_S 14 |
||
3678 | +#define PCIE_SNR_ACKNAK_LATENCY_TIMER 0x00F80000 /* Timer Modifier for Ack/Nak Latency Timer */ |
||
3679 | +#define PCIE_SNR_ACKNAK_LATENCY_TIMER_S 19 |
||
3680 | +#define PCIE_SNR_FC_TIMER 0x1F000000 /* Timer Modifier for Flow Control Watchdog Timer */ |
||
3681 | +#define PCIE_SNR_FC_TIMER_S 28 |
||
3682 | + |
||
3683 | +/* Symbol Timer Register and Filter Mask Register 1 */ |
||
3684 | +#define PCIE_STRFMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x71C) |
||
3685 | +#define PCIE_STRFMR_SKP_INTERVAL 0x000007FF /* SKP lnterval Value */ |
||
3686 | +#define PCIE_STRFMR_SKP_INTERVAL_S 0 |
||
3687 | +#define PCIE_STRFMR_FC_WDT_DISABLE 0x00008000 /* Disable of FC Watchdog Timer */ |
||
3688 | +#define PCIE_STRFMR_TLP_FUNC_MISMATCH_OK 0x00010000 /* Mask Function Mismatch Filtering for Incoming Requests */ |
||
3689 | +#define PCIE_STRFMR_POISONED_TLP_OK 0x00020000 /* Mask Poisoned TLP Filtering */ |
||
3690 | +#define PCIE_STRFMR_BAR_MATCH_OK 0x00040000 /* Mask BAR Match Filtering */ |
||
3691 | +#define PCIE_STRFMR_TYPE1_CFG_REQ_OK 0x00080000 /* Mask Type 1 Configuration Request Filtering */ |
||
3692 | +#define PCIE_STRFMR_LOCKED_REQ_OK 0x00100000 /* Mask Locked Request Filtering */ |
||
3693 | +#define PCIE_STRFMR_CPL_TAG_ERR_RULES_OK 0x00200000 /* Mask Tag Error Rules for Received Completions */ |
||
3694 | +#define PCIE_STRFMR_CPL_REQUESTOR_ID_MISMATCH_OK 0x00400000 /* Mask Requester ID Mismatch Error for Received Completions */ |
||
3695 | +#define PCIE_STRFMR_CPL_FUNC_MISMATCH_OK 0x00800000 /* Mask Function Mismatch Error for Received Completions */ |
||
3696 | +#define PCIE_STRFMR_CPL_TC_MISMATCH_OK 0x01000000 /* Mask Traffic Class Mismatch Error for Received Completions */ |
||
3697 | +#define PCIE_STRFMR_CPL_ATTR_MISMATCH_OK 0x02000000 /* Mask Attribute Mismatch Error for Received Completions */ |
||
3698 | +#define PCIE_STRFMR_CPL_LENGTH_MISMATCH_OK 0x04000000 /* Mask Length Mismatch Error for Received Completions */ |
||
3699 | +#define PCIE_STRFMR_TLP_ECRC_ERR_OK 0x08000000 /* Mask ECRC Error Filtering */ |
||
3700 | +#define PCIE_STRFMR_CPL_TLP_ECRC_OK 0x10000000 /* Mask ECRC Error Filtering for Completions */ |
||
3701 | +#define PCIE_STRFMR_RX_TLP_MSG_NO_DROP 0x20000000 /* Send Message TLPs */ |
||
3702 | +#define PCIE_STRFMR_RX_IO_TRANS_ENABLE 0x40000000 /* Mask Filtering of received I/O Requests */ |
||
3703 | +#define PCIE_STRFMR_RX_CFG_TRANS_ENABLE 0x80000000 /* Mask Filtering of Received Configuration Requests */ |
||
3704 | + |
||
3705 | +#define PCIE_DEF_SKP_INTERVAL 700 /* 1180 ~1538 , 125MHz * 2, 250MHz * 1 */ |
||
3706 | + |
||
3707 | +/* Filter Masker Register 2 */ |
||
3708 | +#define PCIE_FMR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x720) |
||
3709 | +#define PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1 0x00000001 /* Mask RADM Filtering and Error Handling Rules */ |
||
3710 | +#define PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 0x00000002 /* Mask RADM Filtering and Error Handling Rules */ |
||
3711 | + |
||
3712 | +/* Debug Register 0 */ |
||
3713 | +#define PCIE_DBR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x728) |
||
3714 | + |
||
3715 | +/* Debug Register 1 */ |
||
3716 | +#define PCIE_DBR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x72C) |
||
3717 | + |
||
3718 | +/* Transmit Posted FC Credit Status Register */ |
||
3719 | +#define PCIE_TPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x730) |
||
3720 | +#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS 0x00000FFF /* Transmit Posted Data FC Credits */ |
||
3721 | +#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS_S 0 |
||
3722 | +#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS 0x000FF000 /* Transmit Posted Header FC Credits */ |
||
3723 | +#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS_S 12 |
||
3724 | + |
||
3725 | +/* Transmit Non-Posted FC Credit Status */ |
||
3726 | +#define PCIE_TNPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x734) |
||
3727 | +#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS 0x00000FFF /* Transmit Non-Posted Data FC Credits */ |
||
3728 | +#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS_S 0 |
||
3729 | +#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS 0x000FF000 /* Transmit Non-Posted Header FC Credits */ |
||
3730 | +#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS_S 12 |
||
3731 | + |
||
3732 | +/* Transmit Complete FC Credit Status Register */ |
||
3733 | +#define PCIE_TCFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x738) |
||
3734 | +#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS 0x00000FFF /* Transmit Completion Data FC Credits */ |
||
3735 | +#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS_S 0 |
||
3736 | +#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS 0x000FF000 /* Transmit Completion Header FC Credits */ |
||
3737 | +#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS_S 12 |
||
3738 | + |
||
3739 | +/* Queue Status Register */ |
||
3740 | +#define PCIE_QSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x73C) |
||
3741 | +#define PCIE_QSR_WAIT_UPDATE_FC_DLL 0x00000001 /* Received TLP FC Credits Not Returned */ |
||
3742 | +#define PCIE_QSR_TX_RETRY_BUF_NOT_EMPTY 0x00000002 /* Transmit Retry Buffer Not Empty */ |
||
3743 | +#define PCIE_QSR_RX_QUEUE_NOT_EMPTY 0x00000004 /* Received Queue Not Empty */ |
||
3744 | + |
||
3745 | +/* VC Transmit Arbitration Register 1 */ |
||
3746 | +#define PCIE_VCTAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x740) |
||
3747 | +#define PCIE_VCTAR1_WRR_WEIGHT_VC0 0x000000FF /* WRR Weight for VC0 */ |
||
3748 | +#define PCIE_VCTAR1_WRR_WEIGHT_VC1 0x0000FF00 /* WRR Weight for VC1 */ |
||
3749 | +#define PCIE_VCTAR1_WRR_WEIGHT_VC2 0x00FF0000 /* WRR Weight for VC2 */ |
||
3750 | +#define PCIE_VCTAR1_WRR_WEIGHT_VC3 0xFF000000 /* WRR Weight for VC3 */ |
||
3751 | + |
||
3752 | +/* VC Transmit Arbitration Register 2 */ |
||
3753 | +#define PCIE_VCTAR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x744) |
||
3754 | +#define PCIE_VCTAR2_WRR_WEIGHT_VC4 0x000000FF /* WRR Weight for VC4 */ |
||
3755 | +#define PCIE_VCTAR2_WRR_WEIGHT_VC5 0x0000FF00 /* WRR Weight for VC5 */ |
||
3756 | +#define PCIE_VCTAR2_WRR_WEIGHT_VC6 0x00FF0000 /* WRR Weight for VC6 */ |
||
3757 | +#define PCIE_VCTAR2_WRR_WEIGHT_VC7 0xFF000000 /* WRR Weight for VC7 */ |
||
3758 | + |
||
3759 | +/* VC0 Posted Receive Queue Control Register */ |
||
3760 | +#define PCIE_VC0_PRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x748) |
||
3761 | +#define PCIE_VC0_PRQCR_P_DATA_CREDITS 0x00000FFF /* VC0 Posted Data Credits */ |
||
3762 | +#define PCIE_VC0_PRQCR_P_DATA_CREDITS_S 0 |
||
3763 | +#define PCIE_VC0_PRQCR_P_HDR_CREDITS 0x000FF000 /* VC0 Posted Header Credits */ |
||
3764 | +#define PCIE_VC0_PRQCR_P_HDR_CREDITS_S 12 |
||
3765 | +#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE 0x00E00000 /* VC0 Posted TLP Queue Mode */ |
||
3766 | +#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE_S 20 |
||
3767 | +#define PCIE_VC0_PRQCR_TLP_RELAX_ORDER 0x40000000 /* TLP Type Ordering for VC0 */ |
||
3768 | +#define PCIE_VC0_PRQCR_VC_STRICT_ORDER 0x80000000 /* VC0 Ordering for Receive Queues */ |
||
3769 | + |
||
3770 | +/* VC0 Non-Posted Receive Queue Control */ |
||
3771 | +#define PCIE_VC0_NPRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74C) |
||
3772 | +#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS 0x00000FFF /* VC0 Non-Posted Data Credits */ |
||
3773 | +#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS_S 0 |
||
3774 | +#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS 0x000FF000 /* VC0 Non-Posted Header Credits */ |
||
3775 | +#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS_S 12 |
||
3776 | +#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE 0x00E00000 /* VC0 Non-Posted TLP Queue Mode */ |
||
3777 | +#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE_S 20 |
||
3778 | + |
||
3779 | +/* VC0 Completion Receive Queue Control */ |
||
3780 | +#define PCIE_VC0_CRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x750) |
||
3781 | +#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS 0x00000FFF /* VC0 Completion TLP Queue Mode */ |
||
3782 | +#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS_S 0 |
||
3783 | +#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS 0x000FF000 /* VC0 Completion Header Credits */ |
||
3784 | +#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS_S 12 |
||
3785 | +#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE 0x00E00000 /* VC0 Completion Data Credits */ |
||
3786 | +#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE_S 21 |
||
3787 | + |
||
3788 | +/* Applicable to the above three registers */ |
||
3789 | +enum { |
||
3790 | + PCIE_VC0_TLP_QUEUE_MODE_STORE_FORWARD = 1, |
||
3791 | + PCIE_VC0_TLP_QUEUE_MODE_CUT_THROUGH = 2, |
||
3792 | + PCIE_VC0_TLP_QUEUE_MODE_BYPASS = 4, |
||
3793 | +}; |
||
3794 | + |
||
3795 | +/* VC0 Posted Buffer Depth Register */ |
||
3796 | +#define PCIE_VC0_PBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7A8) |
||
3797 | +#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Posted Data Queue Depth */ |
||
3798 | +#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES_S 0 |
||
3799 | +#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Posted Header Queue Depth */ |
||
3800 | +#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES_S 16 |
||
3801 | + |
||
3802 | +/* VC0 Non-Posted Buffer Depth Register */ |
||
3803 | +#define PCIE_VC0_NPBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7AC) |
||
3804 | +#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Non-Posted Data Queue Depth */ |
||
3805 | +#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES_S 0 |
||
3806 | +#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Non-Posted Header Queue Depth */ |
||
3807 | +#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES_S 16 |
||
3808 | + |
||
3809 | +/* VC0 Completion Buffer Depth Register */ |
||
3810 | +#define PCIE_VC0_CBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7B0) |
||
3811 | +#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES 0x00003FFF /* C0 Completion Data Queue Depth */ |
||
3812 | +#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES_S 0 |
||
3813 | +#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Completion Header Queue Depth */ |
||
3814 | +#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES_S 16 |
||
3815 | + |
||
3816 | +/* PHY Status Register, all zeros in VR9 */ |
||
3817 | +#define PCIE_PHYSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x810) |
||
3818 | + |
||
3819 | +/* PHY Control Register, all zeros in VR9 */ |
||
3820 | +#define PCIE_PHYCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x814) |
||
3821 | + |
||
3822 | +/* |
||
3823 | + * PCIe PDI PHY register definition, suppose all the following |
||
3824 | + * stuff is confidential. |
||
3825 | + * XXX, detailed bit definition |
||
3826 | + */ |
||
3827 | +#define PCIE_PHY_PLL_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x22 << 1)) |
||
3828 | +#define PCIE_PHY_PLL_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x23 << 1)) |
||
3829 | +#define PCIE_PHY_PLL_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x24 << 1)) |
||
3830 | +#define PCIE_PHY_PLL_CTRL4(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x25 << 1)) |
||
3831 | +#define PCIE_PHY_PLL_CTRL5(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x26 << 1)) |
||
3832 | +#define PCIE_PHY_PLL_CTRL6(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x27 << 1)) |
||
3833 | +#define PCIE_PHY_PLL_CTRL7(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x28 << 1)) |
||
3834 | +#define PCIE_PHY_PLL_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x29 << 1)) |
||
3835 | +#define PCIE_PHY_PLL_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2A << 1)) |
||
3836 | +#define PCIE_PHY_PLL_A_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2B << 1)) |
||
3837 | +#define PCIE_PHY_PLL_STATUS(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2C << 1)) |
||
3838 | + |
||
3839 | +#define PCIE_PHY_TX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x30 << 1)) |
||
3840 | +#define PCIE_PHY_TX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x31 << 1)) |
||
3841 | +#define PCIE_PHY_TX1_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x32 << 1)) |
||
3842 | +#define PCIE_PHY_TX1_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x33 << 1)) |
||
3843 | +#define PCIE_PHY_TX1_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x34 << 1)) |
||
3844 | +#define PCIE_PHY_TX1_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x35 << 1)) |
||
3845 | +#define PCIE_PHY_TX1_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x36 << 1)) |
||
3846 | +#define PCIE_PHY_TX1_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x37 << 1)) |
||
3847 | + |
||
3848 | +#define PCIE_PHY_TX2_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x38 << 1)) |
||
3849 | +#define PCIE_PHY_TX2_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x39 << 1)) |
||
3850 | +#define PCIE_PHY_TX2_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3B << 1)) |
||
3851 | +#define PCIE_PHY_TX2_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3C << 1)) |
||
3852 | +#define PCIE_PHY_TX2_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3D << 1)) |
||
3853 | +#define PCIE_PHY_TX2_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3E << 1)) |
||
3854 | +#define PCIE_PHY_TX2_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3F << 1)) |
||
3855 | + |
||
3856 | +#define PCIE_PHY_RX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x50 << 1)) |
||
3857 | +#define PCIE_PHY_RX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x51 << 1)) |
||
3858 | +#define PCIE_PHY_RX1_CDR(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x52 << 1)) |
||
3859 | +#define PCIE_PHY_RX1_EI(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x53 << 1)) |
||
3860 | +#define PCIE_PHY_RX1_A_CTRL(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x55 << 1)) |
||
3861 | + |
||
3862 | +/* Interrupt related stuff */ |
||
3863 | +#define PCIE_LEGACY_DISABLE 0 |
||
3864 | +#define PCIE_LEGACY_INTA 1 |
||
3865 | +#define PCIE_LEGACY_INTB 2 |
||
3866 | +#define PCIE_LEGACY_INTC 3 |
||
3867 | +#define PCIE_LEGACY_INTD 4 |
||
3868 | +#define PCIE_LEGACY_INT_MAX PCIE_LEGACY_INTD |
||
3869 | + |
||
3870 | +#endif /* IFXMIPS_PCIE_REG_H */ |
||
3871 | + |
||
3872 | --- /dev/null |
||
3873 | +++ b/arch/mips/pci/ifxmips_pcie_vr9.h |
||
3874 | @@ -0,0 +1,269 @@ |
||
3875 | +/**************************************************************************** |
||
3876 | + Copyright (c) 2010 |
||
3877 | + Lantiq Deutschland GmbH |
||
3878 | + Am Campeon 3; 85579 Neubiberg, Germany |
||
3879 | + |
||
3880 | + For licensing information, see the file 'LICENSE' in the root folder of |
||
3881 | + this software module. |
||
3882 | + |
||
3883 | + *****************************************************************************/ |
||
3884 | +/*! |
||
3885 | + \file ifxmips_pcie_vr9.h |
||
3886 | + \ingroup IFX_PCIE |
||
3887 | + \brief PCIe RC driver vr9 specific file |
||
3888 | +*/ |
||
3889 | + |
||
3890 | +#ifndef IFXMIPS_PCIE_VR9_H |
||
3891 | +#define IFXMIPS_PCIE_VR9_H |
||
3892 | + |
||
3893 | +#include <linux/types.h> |
||
3894 | +#include <linux/delay.h> |
||
3895 | + |
||
3896 | +#include <linux/gpio.h> |
||
3897 | +#include <lantiq_soc.h> |
||
3898 | + |
||
3899 | +#define IFX_PCIE_GPIO_RESET 494 |
||
3900 | + |
||
3901 | +#define IFX_REG_R32 ltq_r32 |
||
3902 | +#define IFX_REG_W32 ltq_w32 |
||
3903 | +#define CONFIG_IFX_PCIE_HW_SWAP |
||
3904 | +#define IFX_RCU_AHB_ENDIAN ((volatile u32*)(IFX_RCU + 0x004C)) |
||
3905 | +#define IFX_RCU_RST_REQ ((volatile u32*)(IFX_RCU + 0x0010)) |
||
3906 | +#define IFX_RCU_AHB_BE_PCIE_PDI 0x00000080 /* Configure PCIE PDI module in big endian*/ |
||
3907 | + |
||
3908 | +#define IFX_RCU (KSEG1 | 0x1F203000) |
||
3909 | +#define IFX_RCU_AHB_BE_PCIE_M 0x00000001 /* Configure AHB master port that connects to PCIe RC in big endian */ |
||
3910 | +#define IFX_RCU_AHB_BE_PCIE_S 0x00000010 /* Configure AHB slave port that connects to PCIe RC in little endian */ |
||
3911 | +#define IFX_RCU_AHB_BE_XBAR_M 0x00000002 /* Configure AHB master port that connects to XBAR in big endian */ |
||
3912 | +#define CONFIG_IFX_PCIE_PHY_36MHZ_MODE |
||
3913 | + |
||
3914 | +#define IFX_PMU1_MODULE_PCIE_PHY (0) |
||
3915 | +#define IFX_PMU1_MODULE_PCIE_CTRL (1) |
||
3916 | +#define IFX_PMU1_MODULE_PDI (4) |
||
3917 | +#define IFX_PMU1_MODULE_MSI (5) |
||
3918 | + |
||
3919 | +#define IFX_PMU_MODULE_PCIE_L0_CLK (31) |
||
3920 | + |
||
3921 | + |
||
3922 | +#define IFX_GPIO (KSEG1 | 0x1E100B00) |
||
3923 | +#define ALT0 ((volatile u32*)(IFX_GPIO + 0x007c)) |
||
3924 | +#define ALT1 ((volatile u32*)(IFX_GPIO + 0x0080)) |
||
3925 | +#define OD ((volatile u32*)(IFX_GPIO + 0x0084)) |
||
3926 | +#define DIR ((volatile u32*)(IFX_GPIO + 0x0078)) |
||
3927 | +#define OUT ((volatile u32*)(IFX_GPIO + 0x0070)) |
||
3928 | + |
||
3929 | + |
||
3930 | +static inline void pcie_ep_gpio_rst_init(int pcie_port) |
||
3931 | +{ |
||
3932 | + |
||
3933 | + gpio_request(IFX_PCIE_GPIO_RESET, "pcie-reset"); |
||
3934 | + gpio_direction_output(IFX_PCIE_GPIO_RESET, 1); |
||
3935 | + gpio_set_value(IFX_PCIE_GPIO_RESET, 1); |
||
3936 | + |
||
3937 | +/* ifx_gpio_pin_reserve(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); |
||
3938 | + ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); |
||
3939 | + ifx_gpio_dir_out_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); |
||
3940 | + ifx_gpio_altsel0_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); |
||
3941 | + ifx_gpio_altsel1_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); |
||
3942 | + ifx_gpio_open_drain_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);*/ |
||
3943 | +} |
||
3944 | + |
||
3945 | +static inline void pcie_ahb_pmu_setup(void) |
||
3946 | +{ |
||
3947 | + /* Enable AHB bus master/slave */ |
||
3948 | + struct clk *clk; |
||
3949 | + clk = clk_get_sys("1d900000.pcie", "ahb"); |
||
3950 | + clk_enable(clk); |
||
3951 | + |
||
3952 | + //AHBM_PMU_SETUP(IFX_PMU_ENABLE); |
||
3953 | + //AHBS_PMU_SETUP(IFX_PMU_ENABLE); |
||
3954 | +} |
||
3955 | + |
||
3956 | +static inline void pcie_rcu_endian_setup(int pcie_port) |
||
3957 | +{ |
||
3958 | + u32 reg; |
||
3959 | + |
||
3960 | + reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); |
||
3961 | +#ifdef CONFIG_IFX_PCIE_HW_SWAP |
||
3962 | + reg |= IFX_RCU_AHB_BE_PCIE_M; |
||
3963 | + reg |= IFX_RCU_AHB_BE_PCIE_S; |
||
3964 | + reg &= ~IFX_RCU_AHB_BE_XBAR_M; |
||
3965 | +#else |
||
3966 | + reg |= IFX_RCU_AHB_BE_PCIE_M; |
||
3967 | + reg &= ~IFX_RCU_AHB_BE_PCIE_S; |
||
3968 | + reg &= ~IFX_RCU_AHB_BE_XBAR_M; |
||
3969 | +#endif /* CONFIG_IFX_PCIE_HW_SWAP */ |
||
3970 | + IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); |
||
3971 | + IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN)); |
||
3972 | +} |
||
3973 | + |
||
3974 | +static inline void pcie_phy_pmu_enable(int pcie_port) |
||
3975 | +{ |
||
3976 | + struct clk *clk; |
||
3977 | + clk = clk_get_sys("1d900000.pcie", "phy"); |
||
3978 | + clk_enable(clk); |
||
3979 | + |
||
3980 | + //PCIE_PHY_PMU_SETUP(IFX_PMU_ENABLE); |
||
3981 | +} |
||
3982 | + |
||
3983 | +static inline void pcie_phy_pmu_disable(int pcie_port) |
||
3984 | +{ |
||
3985 | + struct clk *clk; |
||
3986 | + clk = clk_get_sys("1d900000.pcie", "phy"); |
||
3987 | + clk_disable(clk); |
||
3988 | + |
||
3989 | +// PCIE_PHY_PMU_SETUP(IFX_PMU_DISABLE); |
||
3990 | +} |
||
3991 | + |
||
3992 | +static inline void pcie_pdi_big_endian(int pcie_port) |
||
3993 | +{ |
||
3994 | + u32 reg; |
||
3995 | + |
||
3996 | + /* SRAM2PDI endianness control. */ |
||
3997 | + reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); |
||
3998 | + /* Config AHB->PCIe and PDI endianness */ |
||
3999 | + reg |= IFX_RCU_AHB_BE_PCIE_PDI; |
||
4000 | + IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); |
||
4001 | +} |
||
4002 | + |
||
4003 | +static inline void pcie_pdi_pmu_enable(int pcie_port) |
||
4004 | +{ |
||
4005 | + /* Enable PDI to access PCIe PHY register */ |
||
4006 | + struct clk *clk; |
||
4007 | + clk = clk_get_sys("1d900000.pcie", "pdi"); |
||
4008 | + clk_enable(clk); |
||
4009 | + //PDI_PMU_SETUP(IFX_PMU_ENABLE); |
||
4010 | +} |
||
4011 | + |
||
4012 | +static inline void pcie_core_rst_assert(int pcie_port) |
||
4013 | +{ |
||
4014 | + u32 reg; |
||
4015 | + |
||
4016 | + reg = IFX_REG_R32(IFX_RCU_RST_REQ); |
||
4017 | + |
||
4018 | + /* Reset PCIe PHY & Core, bit 22, bit 26 may be affected if write it directly */ |
||
4019 | + reg |= 0x00400000; |
||
4020 | + IFX_REG_W32(reg, IFX_RCU_RST_REQ); |
||
4021 | +} |
||
4022 | + |
||
4023 | +static inline void pcie_core_rst_deassert(int pcie_port) |
||
4024 | +{ |
||
4025 | + u32 reg; |
||
4026 | + |
||
4027 | + /* Make sure one micro-second delay */ |
||
4028 | + udelay(1); |
||
4029 | + |
||
4030 | + /* Reset PCIe PHY & Core, bit 22 */ |
||
4031 | + reg = IFX_REG_R32(IFX_RCU_RST_REQ); |
||
4032 | + reg &= ~0x00400000; |
||
4033 | + IFX_REG_W32(reg, IFX_RCU_RST_REQ); |
||
4034 | +} |
||
4035 | + |
||
4036 | +static inline void pcie_phy_rst_assert(int pcie_port) |
||
4037 | +{ |
||
4038 | + u32 reg; |
||
4039 | + |
||
4040 | + reg = IFX_REG_R32(IFX_RCU_RST_REQ); |
||
4041 | + reg |= 0x00001000; /* Bit 12 */ |
||
4042 | + IFX_REG_W32(reg, IFX_RCU_RST_REQ); |
||
4043 | +} |
||
4044 | + |
||
4045 | +static inline void pcie_phy_rst_deassert(int pcie_port) |
||
4046 | +{ |
||
4047 | + u32 reg; |
||
4048 | + |
||
4049 | + /* Make sure one micro-second delay */ |
||
4050 | + udelay(1); |
||
4051 | + |
||
4052 | + reg = IFX_REG_R32(IFX_RCU_RST_REQ); |
||
4053 | + reg &= ~0x00001000; /* Bit 12 */ |
||
4054 | + IFX_REG_W32(reg, IFX_RCU_RST_REQ); |
||
4055 | +} |
||
4056 | + |
||
4057 | +static inline void pcie_device_rst_assert(int pcie_port) |
||
4058 | +{ |
||
4059 | + gpio_set_value(IFX_PCIE_GPIO_RESET, 0); |
||
4060 | +// ifx_gpio_output_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); |
||
4061 | +} |
||
4062 | + |
||
4063 | +static inline void pcie_device_rst_deassert(int pcie_port) |
||
4064 | +{ |
||
4065 | + mdelay(100); |
||
4066 | + gpio_direction_output(IFX_PCIE_GPIO_RESET, 1); |
||
4067 | +// gpio_set_value(IFX_PCIE_GPIO_RESET, 1); |
||
4068 | + //ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); |
||
4069 | +} |
||
4070 | + |
||
4071 | +static inline void pcie_core_pmu_setup(int pcie_port) |
||
4072 | +{ |
||
4073 | + struct clk *clk; |
||
4074 | + clk = clk_get_sys("1d900000.pcie", "ctl"); |
||
4075 | + clk_enable(clk); |
||
4076 | + clk = clk_get_sys("1d900000.pcie", "bus"); |
||
4077 | + clk_enable(clk); |
||
4078 | + |
||
4079 | + /* PCIe Core controller enabled */ |
||
4080 | +// PCIE_CTRL_PMU_SETUP(IFX_PMU_ENABLE); |
||
4081 | + |
||
4082 | + /* Enable PCIe L0 Clock */ |
||
4083 | +// PCIE_L0_CLK_PMU_SETUP(IFX_PMU_ENABLE); |
||
4084 | +} |
||
4085 | + |
||
4086 | +static inline void pcie_msi_init(int pcie_port) |
||
4087 | +{ |
||
4088 | + struct clk *clk; |
||
4089 | + pcie_msi_pic_init(pcie_port); |
||
4090 | + clk = clk_get_sys("ltq_pcie", "msi"); |
||
4091 | + clk_enable(clk); |
||
4092 | +// MSI_PMU_SETUP(IFX_PMU_ENABLE); |
||
4093 | +} |
||
4094 | + |
||
4095 | +static inline u32 |
||
4096 | +ifx_pcie_bus_nr_deduct(u32 bus_number, int pcie_port) |
||
4097 | +{ |
||
4098 | + u32 tbus_number = bus_number; |
||
4099 | + |
||
4100 | +#ifdef CONFIG_PCI_LANTIQ |
||
4101 | + if (pcibios_host_nr() > 1) { |
||
4102 | + tbus_number -= pcibios_1st_host_bus_nr(); |
||
4103 | + } |
||
4104 | +#endif /* CONFIG_PCI_LANTIQ */ |
||
4105 | + return tbus_number; |
||
4106 | +} |
||
4107 | + |
||
4108 | +static inline u32 |
||
4109 | +ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read) |
||
4110 | +{ |
||
4111 | + struct pci_dev *pdev; |
||
4112 | + u32 tvalue = value; |
||
4113 | + |
||
4114 | + /* Sanity check */ |
||
4115 | + pdev = pci_get_slot(bus, devfn); |
||
4116 | + if (pdev == NULL) { |
||
4117 | + return tvalue; |
||
4118 | + } |
||
4119 | + |
||
4120 | + /* Only care about PCI bridge */ |
||
4121 | + if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) { |
||
4122 | + return tvalue; |
||
4123 | + } |
||
4124 | + |
||
4125 | + if (read) { /* Read hack */ |
||
4126 | + #ifdef CONFIG_PCI_LANTIQ |
||
4127 | + if (pcibios_host_nr() > 1) { |
||
4128 | + tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue); |
||
4129 | + } |
||
4130 | + #endif /* CONFIG_PCI_LANTIQ */ |
||
4131 | + } |
||
4132 | + else { /* Write hack */ |
||
4133 | + #ifdef CONFIG_PCI_LANTIQ |
||
4134 | + if (pcibios_host_nr() > 1) { |
||
4135 | + tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue); |
||
4136 | + } |
||
4137 | + #endif |
||
4138 | + } |
||
4139 | + return tvalue; |
||
4140 | +} |
||
4141 | + |
||
4142 | +#endif /* IFXMIPS_PCIE_VR9_H */ |
||
4143 | + |
||
4144 | --- a/arch/mips/pci/pci-legacy.c |
||
4145 | +++ b/arch/mips/pci/pci-legacy.c |
||
3 | office | 4146 | @@ -309,3 +309,30 @@ char *__init pcibios_setup(char *str) |
1 | office | 4147 | return pcibios_plat_setup(str); |
4148 | return str; |
||
4149 | } |
||
4150 | + |
||
4151 | +int pcibios_host_nr(void) |
||
4152 | +{ |
||
4153 | + int count = 0; |
||
4154 | + struct pci_controller *hose; |
||
4155 | + list_for_each_entry(hose, &controllers, list) { |
||
4156 | + count++; |
||
4157 | + } |
||
4158 | + return count; |
||
4159 | +} |
||
4160 | +EXPORT_SYMBOL(pcibios_host_nr); |
||
4161 | + |
||
4162 | +int pcibios_1st_host_bus_nr(void) |
||
4163 | +{ |
||
4164 | + int bus_nr = 0; |
||
4165 | + struct pci_controller *hose; |
||
4166 | + |
||
4167 | + hose = list_first_entry_or_null(&controllers, struct pci_controller, list); |
||
4168 | + |
||
4169 | + if (hose != NULL) { |
||
4170 | + if (hose->bus != NULL) { |
||
4171 | + bus_nr = hose->bus->number + 1; |
||
4172 | + } |
||
4173 | + } |
||
4174 | + return bus_nr; |
||
4175 | +} |
||
4176 | +EXPORT_SYMBOL(pcibios_1st_host_bus_nr); |
||
4177 | --- /dev/null |
||
4178 | +++ b/arch/mips/pci/pcie-lantiq.h |
||
4179 | @@ -0,0 +1,1305 @@ |
||
4180 | +/****************************************************************************** |
||
4181 | +** |
||
4182 | +** FILE NAME : ifxmips_pcie_reg.h |
||
4183 | +** PROJECT : IFX UEIP for VRX200 |
||
4184 | +** MODULES : PCIe module |
||
4185 | +** |
||
4186 | +** DATE : 02 Mar 2009 |
||
4187 | +** AUTHOR : Lei Chuanhua |
||
4188 | +** DESCRIPTION : PCIe Root Complex Driver |
||
4189 | +** COPYRIGHT : Copyright (c) 2009 |
||
4190 | +** Infineon Technologies AG |
||
4191 | +** Am Campeon 1-12, 85579 Neubiberg, Germany |
||
4192 | +** |
||
4193 | +** This program is free software; you can redistribute it and/or modify |
||
4194 | +** it under the terms of the GNU General Public License as published by |
||
4195 | +** the Free Software Foundation; either version 2 of the License, or |
||
4196 | +** (at your option) any later version. |
||
4197 | +** HISTORY |
||
4198 | +** $Version $Date $Author $Comment |
||
4199 | +** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version |
||
4200 | +*******************************************************************************/ |
||
4201 | +#ifndef IFXMIPS_PCIE_REG_H |
||
4202 | +#define IFXMIPS_PCIE_REG_H |
||
4203 | +#include <linux/version.h> |
||
4204 | +#include <linux/types.h> |
||
4205 | +#include <linux/pci.h> |
||
4206 | +#include <linux/interrupt.h> |
||
4207 | +/*! |
||
4208 | + \file ifxmips_pcie_reg.h |
||
4209 | + \ingroup IFX_PCIE |
||
4210 | + \brief header file for PCIe module register definition |
||
4211 | +*/ |
||
4212 | +/* PCIe Address Mapping Base */ |
||
4213 | +#define PCIE_CFG_PHY_BASE 0x1D000000UL |
||
4214 | +#define PCIE_CFG_BASE (KSEG1 + PCIE_CFG_PHY_BASE) |
||
4215 | +#define PCIE_CFG_SIZE (8 * 1024 * 1024) |
||
4216 | + |
||
4217 | +#define PCIE_MEM_PHY_BASE 0x1C000000UL |
||
4218 | +#define PCIE_MEM_BASE (KSEG1 + PCIE_MEM_PHY_BASE) |
||
4219 | +#define PCIE_MEM_SIZE (16 * 1024 * 1024) |
||
4220 | +#define PCIE_MEM_PHY_END (PCIE_MEM_PHY_BASE + PCIE_MEM_SIZE - 1) |
||
4221 | + |
||
4222 | +#define PCIE_IO_PHY_BASE 0x1D800000UL |
||
4223 | +#define PCIE_IO_BASE (KSEG1 + PCIE_IO_PHY_BASE) |
||
4224 | +#define PCIE_IO_SIZE (1 * 1024 * 1024) |
||
4225 | +#define PCIE_IO_PHY_END (PCIE_IO_PHY_BASE + PCIE_IO_SIZE - 1) |
||
4226 | + |
||
4227 | +#define PCIE_RC_CFG_BASE (KSEG1 + 0x1D900000) |
||
4228 | +#define PCIE_APP_LOGIC_REG (KSEG1 + 0x1E100900) |
||
4229 | +#define PCIE_MSI_PHY_BASE 0x1F600000UL |
||
4230 | + |
||
4231 | +#define PCIE_PDI_PHY_BASE 0x1F106800UL |
||
4232 | +#define PCIE_PDI_BASE (KSEG1 + PCIE_PDI_PHY_BASE) |
||
4233 | +#define PCIE_PDI_SIZE 0x400 |
||
4234 | + |
||
4235 | +#define PCIE1_CFG_PHY_BASE 0x19000000UL |
||
4236 | +#define PCIE1_CFG_BASE (KSEG1 + PCIE1_CFG_PHY_BASE) |
||
4237 | +#define PCIE1_CFG_SIZE (8 * 1024 * 1024) |
||
4238 | + |
||
4239 | +#define PCIE1_MEM_PHY_BASE 0x18000000UL |
||
4240 | +#define PCIE1_MEM_BASE (KSEG1 + PCIE1_MEM_PHY_BASE) |
||
4241 | +#define PCIE1_MEM_SIZE (16 * 1024 * 1024) |
||
4242 | +#define PCIE1_MEM_PHY_END (PCIE1_MEM_PHY_BASE + PCIE1_MEM_SIZE - 1) |
||
4243 | + |
||
4244 | +#define PCIE1_IO_PHY_BASE 0x19800000UL |
||
4245 | +#define PCIE1_IO_BASE (KSEG1 + PCIE1_IO_PHY_BASE) |
||
4246 | +#define PCIE1_IO_SIZE (1 * 1024 * 1024) |
||
4247 | +#define PCIE1_IO_PHY_END (PCIE1_IO_PHY_BASE + PCIE1_IO_SIZE - 1) |
||
4248 | + |
||
4249 | +#define PCIE1_RC_CFG_BASE (KSEG1 + 0x19900000) |
||
4250 | +#define PCIE1_APP_LOGIC_REG (KSEG1 + 0x1E100700) |
||
4251 | +#define PCIE1_MSI_PHY_BASE 0x1F400000UL |
||
4252 | + |
||
4253 | +#define PCIE1_PDI_PHY_BASE 0x1F700400UL |
||
4254 | +#define PCIE1_PDI_BASE (KSEG1 + PCIE1_PDI_PHY_BASE) |
||
4255 | +#define PCIE1_PDI_SIZE 0x400 |
||
4256 | + |
||
4257 | +#define PCIE_CFG_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_CFG_BASE) : (PCIE_CFG_BASE)) |
||
4258 | +#define PCIE_MEM_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_BASE) : (PCIE_MEM_BASE)) |
||
4259 | +#define PCIE_IO_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_BASE) : (PCIE_IO_BASE)) |
||
4260 | +#define PCIE_MEM_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_PHY_BASE) : (PCIE_MEM_PHY_BASE)) |
||
4261 | +#define PCIE_MEM_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_MEM_PHY_END) : (PCIE_MEM_PHY_END)) |
||
4262 | +#define PCIE_IO_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_PHY_BASE) : (PCIE_IO_PHY_BASE)) |
||
4263 | +#define PCIE_IO_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_IO_PHY_END) : (PCIE_IO_PHY_END)) |
||
4264 | +#define PCIE_APP_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_APP_LOGIC_REG) : (PCIE_APP_LOGIC_REG)) |
||
4265 | +#define PCIE_RC_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_RC_CFG_BASE) : (PCIE_RC_CFG_BASE)) |
||
4266 | +#define PCIE_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_PDI_BASE) : (PCIE_PDI_BASE)) |
||
4267 | + |
||
4268 | +/* PCIe Application Logic Register */ |
||
4269 | +/* RC Core Control Register */ |
||
4270 | +#define PCIE_RC_CCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x10) |
||
4271 | +/* This should be enabled after initializing configuratin registers |
||
4272 | + * Also should check link status retraining bit |
||
4273 | + */ |
||
4274 | +#define PCIE_RC_CCR_LTSSM_ENABLE 0x00000001 /* Enable LTSSM to continue link establishment */ |
||
4275 | + |
||
4276 | +/* RC Core Debug Register */ |
||
4277 | +#define PCIE_RC_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x14) |
||
4278 | +#define PCIE_RC_DR_DLL_UP 0x00000001 /* Data Link Layer Up */ |
||
4279 | +#define PCIE_RC_DR_CURRENT_POWER_STATE 0x0000000E /* Current Power State */ |
||
4280 | +#define PCIE_RC_DR_CURRENT_POWER_STATE_S 1 |
||
4281 | +#define PCIE_RC_DR_CURRENT_LTSSM_STATE 0x000001F0 /* Current LTSSM State */ |
||
4282 | +#define PCIE_RC_DR_CURRENT_LTSSM_STATE_S 4 |
||
4283 | + |
||
4284 | +#define PCIE_RC_DR_PM_DEV_STATE 0x00000E00 /* Power Management D-State */ |
||
4285 | +#define PCIE_RC_DR_PM_DEV_STATE_S 9 |
||
4286 | + |
||
4287 | +#define PCIE_RC_DR_PM_ENABLED 0x00001000 /* Power Management State from PMU */ |
||
4288 | +#define PCIE_RC_DR_PME_EVENT_ENABLED 0x00002000 /* Power Management Event Enable State */ |
||
4289 | +#define PCIE_RC_DR_AUX_POWER_ENABLED 0x00004000 /* Auxiliary Power Enable */ |
||
4290 | + |
||
4291 | +/* Current Power State Definition */ |
||
4292 | +enum { |
||
4293 | + PCIE_RC_DR_D0 = 0, |
||
4294 | + PCIE_RC_DR_D1, /* Not supported */ |
||
4295 | + PCIE_RC_DR_D2, /* Not supported */ |
||
4296 | + PCIE_RC_DR_D3, |
||
4297 | + PCIE_RC_DR_UN, |
||
4298 | +}; |
||
4299 | + |
||
4300 | +/* PHY Link Status Register */ |
||
4301 | +#define PCIE_PHY_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x18) |
||
4302 | +#define PCIE_PHY_SR_PHY_LINK_UP 0x00000001 /* PHY Link Up/Down Indicator */ |
||
4303 | + |
||
4304 | +/* Electromechanical Control Register */ |
||
4305 | +#define PCIE_EM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x1C) |
||
4306 | +#define PCIE_EM_CR_CARD_IS_PRESENT 0x00000001 /* Card Presence Detect State */ |
||
4307 | +#define PCIE_EM_CR_MRL_OPEN 0x00000002 /* MRL Sensor State */ |
||
4308 | +#define PCIE_EM_CR_POWER_FAULT_SET 0x00000004 /* Power Fault Detected */ |
||
4309 | +#define PCIE_EM_CR_MRL_SENSOR_SET 0x00000008 /* MRL Sensor Changed */ |
||
4310 | +#define PCIE_EM_CR_PRESENT_DETECT_SET 0x00000010 /* Card Presense Detect Changed */ |
||
4311 | +#define PCIE_EM_CR_CMD_CPL_INT_SET 0x00000020 /* Command Complete Interrupt */ |
||
4312 | +#define PCIE_EM_CR_SYS_INTERLOCK_SET 0x00000040 /* System Electromechanical IterLock Engaged */ |
||
4313 | +#define PCIE_EM_CR_ATTENTION_BUTTON_SET 0x00000080 /* Attention Button Pressed */ |
||
4314 | + |
||
4315 | +/* Interrupt Status Register */ |
||
4316 | +#define PCIE_IR_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x20) |
||
4317 | +#define PCIE_IR_SR_PME_CAUSE_MSI 0x00000002 /* MSI caused by PME */ |
||
4318 | +#define PCIE_IR_SR_HP_PME_WAKE_GEN 0x00000004 /* Hotplug PME Wake Generation */ |
||
4319 | +#define PCIE_IR_SR_HP_MSI 0x00000008 /* Hotplug MSI */ |
||
4320 | +#define PCIE_IR_SR_AHB_LU_ERR 0x00000030 /* AHB Bridge Lookup Error Signals */ |
||
4321 | +#define PCIE_IR_SR_AHB_LU_ERR_S 4 |
||
4322 | +#define PCIE_IR_SR_INT_MSG_NUM 0x00003E00 /* Interrupt Message Number */ |
||
4323 | +#define PCIE_IR_SR_INT_MSG_NUM_S 9 |
||
4324 | +#define PCIE_IR_SR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ |
||
4325 | +#define PCIE_IR_SR_AER_INT_MSG_NUM_S 27 |
||
4326 | + |
||
4327 | +/* Message Control Register */ |
||
4328 | +#define PCIE_MSG_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x30) |
||
4329 | +#define PCIE_MSG_CR_GEN_PME_TURN_OFF_MSG 0x00000001 /* Generate PME Turn Off Message */ |
||
4330 | +#define PCIE_MSG_CR_GEN_UNLOCK_MSG 0x00000002 /* Generate Unlock Message */ |
||
4331 | + |
||
4332 | +#define PCIE_VDM_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x34) |
||
4333 | + |
||
4334 | +/* Vendor-Defined Message Requester ID Register */ |
||
4335 | +#define PCIE_VDM_RID(X) (PCIE_APP_PORT_TO_BASE (X) + 0x38) |
||
4336 | +#define PCIE_VDM_RID_VENROR_MSG_REQ_ID 0x0000FFFF |
||
4337 | +#define PCIE_VDM_RID_VDMRID_S 0 |
||
4338 | + |
||
4339 | +/* ASPM Control Register */ |
||
4340 | +#define PCIE_ASPM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x40) |
||
4341 | +#define PCIE_ASPM_CR_HOT_RST 0x00000001 /* Hot Reset Request to the downstream device */ |
||
4342 | +#define PCIE_ASPM_CR_REQ_EXIT_L1 0x00000002 /* Request to Exit L1 */ |
||
4343 | +#define PCIE_ASPM_CR_REQ_ENTER_L1 0x00000004 /* Request to Enter L1 */ |
||
4344 | + |
||
4345 | +/* Vendor Message DW0 Register */ |
||
4346 | +#define PCIE_VM_MSG_DW0(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x50) |
||
4347 | +#define PCIE_VM_MSG_DW0_TYPE 0x0000001F /* Message type */ |
||
4348 | +#define PCIE_VM_MSG_DW0_TYPE_S 0 |
||
4349 | +#define PCIE_VM_MSG_DW0_FORMAT 0x00000060 /* Format */ |
||
4350 | +#define PCIE_VM_MSG_DW0_FORMAT_S 5 |
||
4351 | +#define PCIE_VM_MSG_DW0_TC 0x00007000 /* Traffic Class */ |
||
4352 | +#define PCIE_VM_MSG_DW0_TC_S 12 |
||
4353 | +#define PCIE_VM_MSG_DW0_ATTR 0x000C0000 /* Atrributes */ |
||
4354 | +#define PCIE_VM_MSG_DW0_ATTR_S 18 |
||
4355 | +#define PCIE_VM_MSG_DW0_EP_TLP 0x00100000 /* Poisoned TLP */ |
||
4356 | +#define PCIE_VM_MSG_DW0_TD 0x00200000 /* TLP Digest */ |
||
4357 | +#define PCIE_VM_MSG_DW0_LEN 0xFFC00000 /* Length */ |
||
4358 | +#define PCIE_VM_MSG_DW0_LEN_S 22 |
||
4359 | + |
||
4360 | +/* Format Definition */ |
||
4361 | +enum { |
||
4362 | + PCIE_VM_MSG_FORMAT_00 = 0, /* 3DW Hdr, no data*/ |
||
4363 | + PCIE_VM_MSG_FORMAT_01, /* 4DW Hdr, no data */ |
||
4364 | + PCIE_VM_MSG_FORMAT_10, /* 3DW Hdr, with data */ |
||
4365 | + PCIE_VM_MSG_FORMAT_11, /* 4DW Hdr, with data */ |
||
4366 | +}; |
||
4367 | + |
||
4368 | +/* Traffic Class Definition */ |
||
4369 | +enum { |
||
4370 | + PCIE_VM_MSG_TC0 = 0, |
||
4371 | + PCIE_VM_MSG_TC1, |
||
4372 | + PCIE_VM_MSG_TC2, |
||
4373 | + PCIE_VM_MSG_TC3, |
||
4374 | + PCIE_VM_MSG_TC4, |
||
4375 | + PCIE_VM_MSG_TC5, |
||
4376 | + PCIE_VM_MSG_TC6, |
||
4377 | + PCIE_VM_MSG_TC7, |
||
4378 | +}; |
||
4379 | + |
||
4380 | +/* Attributes Definition */ |
||
4381 | +enum { |
||
4382 | + PCIE_VM_MSG_ATTR_00 = 0, /* RO and No Snoop cleared */ |
||
4383 | + PCIE_VM_MSG_ATTR_01, /* RO cleared , No Snoop set */ |
||
4384 | + PCIE_VM_MSG_ATTR_10, /* RO set, No Snoop cleared*/ |
||
4385 | + PCIE_VM_MSG_ATTR_11, /* RO and No Snoop set */ |
||
4386 | +}; |
||
4387 | + |
||
4388 | +/* Payload Size Definition */ |
||
4389 | +#define PCIE_VM_MSG_LEN_MIN 0 |
||
4390 | +#define PCIE_VM_MSG_LEN_MAX 1024 |
||
4391 | + |
||
4392 | +/* Vendor Message DW1 Register */ |
||
4393 | +#define PCIE_VM_MSG_DW1(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x54) |
||
4394 | +#define PCIE_VM_MSG_DW1_FUNC_NUM 0x00000070 /* Function Number */ |
||
4395 | +#define PCIE_VM_MSG_DW1_FUNC_NUM_S 8 |
||
4396 | +#define PCIE_VM_MSG_DW1_CODE 0x00FF0000 /* Message Code */ |
||
4397 | +#define PCIE_VM_MSG_DW1_CODE_S 16 |
||
4398 | +#define PCIE_VM_MSG_DW1_TAG 0xFF000000 /* Tag */ |
||
4399 | +#define PCIE_VM_MSG_DW1_TAG_S 24 |
||
4400 | + |
||
4401 | +#define PCIE_VM_MSG_DW2(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x58) |
||
4402 | +#define PCIE_VM_MSG_DW3(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x5C) |
||
4403 | + |
||
4404 | +/* Vendor Message Request Register */ |
||
4405 | +#define PCIE_VM_MSG_REQR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x60) |
||
4406 | +#define PCIE_VM_MSG_REQR_REQ 0x00000001 /* Vendor Message Request */ |
||
4407 | + |
||
4408 | + |
||
4409 | +/* AHB Slave Side Band Control Register */ |
||
4410 | +#define PCIE_AHB_SSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x70) |
||
4411 | +#define PCIE_AHB_SSB_REQ_BCM 0x00000001 /* Slave Reques BCM filed */ |
||
4412 | +#define PCIE_AHB_SSB_REQ_EP 0x00000002 /* Slave Reques EP filed */ |
||
4413 | +#define PCIE_AHB_SSB_REQ_TD 0x00000004 /* Slave Reques TD filed */ |
||
4414 | +#define PCIE_AHB_SSB_REQ_ATTR 0x00000018 /* Slave Reques Attribute number */ |
||
4415 | +#define PCIE_AHB_SSB_REQ_ATTR_S 3 |
||
4416 | +#define PCIE_AHB_SSB_REQ_TC 0x000000E0 /* Slave Request TC Field */ |
||
4417 | +#define PCIE_AHB_SSB_REQ_TC_S 5 |
||
4418 | + |
||
4419 | +/* AHB Master SideBand Ctrl Register */ |
||
4420 | +#define PCIE_AHB_MSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x74) |
||
4421 | +#define PCIE_AHB_MSB_RESP_ATTR 0x00000003 /* Master Response Attribute number */ |
||
4422 | +#define PCIE_AHB_MSB_RESP_ATTR_S 0 |
||
4423 | +#define PCIE_AHB_MSB_RESP_BAD_EOT 0x00000004 /* Master Response Badeot filed */ |
||
4424 | +#define PCIE_AHB_MSB_RESP_BCM 0x00000008 /* Master Response BCM filed */ |
||
4425 | +#define PCIE_AHB_MSB_RESP_EP 0x00000010 /* Master Response EP filed */ |
||
4426 | +#define PCIE_AHB_MSB_RESP_TD 0x00000020 /* Master Response TD filed */ |
||
4427 | +#define PCIE_AHB_MSB_RESP_FUN_NUM 0x000003C0 /* Master Response Function number */ |
||
4428 | +#define PCIE_AHB_MSB_RESP_FUN_NUM_S 6 |
||
4429 | + |
||
4430 | +/* AHB Control Register, fixed bus enumeration exception */ |
||
4431 | +#define PCIE_AHB_CTRL(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x78) |
||
4432 | +#define PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS 0x00000001 |
||
4433 | + |
||
4434 | +/* Interrupt Enalbe Register */ |
||
4435 | +#define PCIE_IRNEN(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF4) |
||
4436 | +#define PCIE_IRNCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF8) |
||
4437 | +#define PCIE_IRNICR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xFC) |
||
4438 | + |
||
4439 | +/* PCIe interrupt enable/control/capture register definition */ |
||
4440 | +#define PCIE_IRN_AER_REPORT 0x00000001 /* AER Interrupt */ |
||
4441 | +#define PCIE_IRN_AER_MSIX 0x00000002 /* Advanced Error MSI-X Interrupt */ |
||
4442 | +#define PCIE_IRN_PME 0x00000004 /* PME Interrupt */ |
||
4443 | +#define PCIE_IRN_HOTPLUG 0x00000008 /* Hotplug Interrupt */ |
||
4444 | +#define PCIE_IRN_RX_VDM_MSG 0x00000010 /* Vendor-Defined Message Interrupt */ |
||
4445 | +#define PCIE_IRN_RX_CORRECTABLE_ERR_MSG 0x00000020 /* Correctable Error Message Interrupt */ |
||
4446 | +#define PCIE_IRN_RX_NON_FATAL_ERR_MSG 0x00000040 /* Non-fatal Error Message */ |
||
4447 | +#define PCIE_IRN_RX_FATAL_ERR_MSG 0x00000080 /* Fatal Error Message */ |
||
4448 | +#define PCIE_IRN_RX_PME_MSG 0x00000100 /* PME Message Interrupt */ |
||
4449 | +#define PCIE_IRN_RX_PME_TURNOFF_ACK 0x00000200 /* PME Turnoff Ack Message Interrupt */ |
||
4450 | +#define PCIE_IRN_AHB_BR_FATAL_ERR 0x00000400 /* AHB Fatal Error Interrupt */ |
||
4451 | +#define PCIE_IRN_LINK_AUTO_BW_STATUS 0x00000800 /* Link Auto Bandwidth Status Interrupt */ |
||
4452 | +#define PCIE_IRN_BW_MGT 0x00001000 /* Bandwidth Managment Interrupt */ |
||
4453 | +#define PCIE_IRN_INTA 0x00002000 /* INTA */ |
||
4454 | +#define PCIE_IRN_INTB 0x00004000 /* INTB */ |
||
4455 | +#define PCIE_IRN_INTC 0x00008000 /* INTC */ |
||
4456 | +#define PCIE_IRN_INTD 0x00010000 /* INTD */ |
||
4457 | +#define PCIE_IRN_WAKEUP 0x00020000 /* Wake up Interrupt */ |
||
4458 | + |
||
4459 | +#define PCIE_RC_CORE_COMBINED_INT (PCIE_IRN_AER_REPORT | PCIE_IRN_AER_MSIX | PCIE_IRN_PME | \ |
||
4460 | + PCIE_IRN_HOTPLUG | PCIE_IRN_RX_VDM_MSG | PCIE_IRN_RX_CORRECTABLE_ERR_MSG |\ |
||
4461 | + PCIE_IRN_RX_NON_FATAL_ERR_MSG | PCIE_IRN_RX_FATAL_ERR_MSG | \ |
||
4462 | + PCIE_IRN_RX_PME_MSG | PCIE_IRN_RX_PME_TURNOFF_ACK | PCIE_IRN_AHB_BR_FATAL_ERR | \ |
||
4463 | + PCIE_IRN_LINK_AUTO_BW_STATUS | PCIE_IRN_BW_MGT) |
||
4464 | +/* PCIe RC Configuration Register */ |
||
4465 | +#define PCIE_VDID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x00) |
||
4466 | + |
||
4467 | +/* Bit definition from pci_reg.h */ |
||
4468 | +#define PCIE_PCICMDSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x04) |
||
4469 | +#define PCIE_CCRID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x08) |
||
4470 | +#define PCIE_CLSLTHTBR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x0C) /* EP only */ |
||
4471 | +/* BAR0, BAR1,Only necessary if the bridges implements a device-specific register set or memory buffer */ |
||
4472 | +#define PCIE_BAR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10) /* Not used*/ |
||
4473 | +#define PCIE_BAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14) /* Not used */ |
||
4474 | + |
||
4475 | +#define PCIE_BNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x18) /* Mandatory */ |
||
4476 | +/* Bus Number Register bits */ |
||
4477 | +#define PCIE_BNR_PRIMARY_BUS_NUM 0x000000FF |
||
4478 | +#define PCIE_BNR_PRIMARY_BUS_NUM_S 0 |
||
4479 | +#define PCIE_PNR_SECONDARY_BUS_NUM 0x0000FF00 |
||
4480 | +#define PCIE_PNR_SECONDARY_BUS_NUM_S 8 |
||
4481 | +#define PCIE_PNR_SUB_BUS_NUM 0x00FF0000 |
||
4482 | +#define PCIE_PNR_SUB_BUS_NUM_S 16 |
||
4483 | + |
||
4484 | +/* IO Base/Limit Register bits */ |
||
4485 | +#define PCIE_IOBLSECS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x1C) /* RC only */ |
||
4486 | +#define PCIE_IOBLSECS_32BIT_IO_ADDR 0x00000001 |
||
4487 | +#define PCIE_IOBLSECS_IO_BASE_ADDR 0x000000F0 |
||
4488 | +#define PCIE_IOBLSECS_IO_BASE_ADDR_S 4 |
||
4489 | +#define PCIE_IOBLSECS_32BIT_IOLIMT 0x00000100 |
||
4490 | +#define PCIE_IOBLSECS_IO_LIMIT_ADDR 0x0000F000 |
||
4491 | +#define PCIE_IOBLSECS_IO_LIMIT_ADDR_S 12 |
||
4492 | + |
||
4493 | +/* Non-prefetchable Memory Base/Limit Register bit */ |
||
4494 | +#define PCIE_MBML(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x20) /* RC only */ |
||
4495 | +#define PCIE_MBML_MEM_BASE_ADDR 0x0000FFF0 |
||
4496 | +#define PCIE_MBML_MEM_BASE_ADDR_S 4 |
||
4497 | +#define PCIE_MBML_MEM_LIMIT_ADDR 0xFFF00000 |
||
4498 | +#define PCIE_MBML_MEM_LIMIT_ADDR_S 20 |
||
4499 | + |
||
4500 | +/* Prefetchable Memory Base/Limit Register bit */ |
||
4501 | +#define PCIE_PMBL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x24) /* RC only */ |
||
4502 | +#define PCIE_PMBL_64BIT_ADDR 0x00000001 |
||
4503 | +#define PCIE_PMBL_UPPER_12BIT 0x0000FFF0 |
||
4504 | +#define PCIE_PMBL_UPPER_12BIT_S 4 |
||
4505 | +#define PCIE_PMBL_E64MA 0x00010000 |
||
4506 | +#define PCIE_PMBL_END_ADDR 0xFFF00000 |
||
4507 | +#define PCIE_PMBL_END_ADDR_S 20 |
||
4508 | +#define PCIE_PMBU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x28) /* RC only */ |
||
4509 | +#define PCIE_PMLU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x2C) /* RC only */ |
||
4510 | + |
||
4511 | +/* I/O Base/Limit Upper 16 bits register */ |
||
4512 | +#define PCIE_IO_BANDL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x30) /* RC only */ |
||
4513 | +#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE 0x0000FFFF |
||
4514 | +#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE_S 0 |
||
4515 | +#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT 0xFFFF0000 |
||
4516 | +#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT_S 16 |
||
4517 | + |
||
4518 | +#define PCIE_CPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x34) |
||
4519 | +#define PCIE_EBBAR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x38) |
||
4520 | + |
||
4521 | +/* Interrupt and Secondary Bridge Control Register */ |
||
4522 | +#define PCIE_INTRBCTRL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x3C) |
||
4523 | + |
||
4524 | +#define PCIE_INTRBCTRL_INT_LINE 0x000000FF |
||
4525 | +#define PCIE_INTRBCTRL_INT_LINE_S 0 |
||
4526 | +#define PCIE_INTRBCTRL_INT_PIN 0x0000FF00 |
||
4527 | +#define PCIE_INTRBCTRL_INT_PIN_S 8 |
||
4528 | +#define PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE 0x00010000 /* #PERR */ |
||
4529 | +#define PCIE_INTRBCTRL_SERR_ENABLE 0x00020000 /* #SERR */ |
||
4530 | +#define PCIE_INTRBCTRL_ISA_ENABLE 0x00040000 /* ISA enable, IO 64KB only */ |
||
4531 | +#define PCIE_INTRBCTRL_VGA_ENABLE 0x00080000 /* VGA enable */ |
||
4532 | +#define PCIE_INTRBCTRL_VGA_16BIT_DECODE 0x00100000 /* VGA 16bit decode */ |
||
4533 | +#define PCIE_INTRBCTRL_RST_SECONDARY_BUS 0x00400000 /* Secondary bus rest, hot rest, 1ms */ |
||
4534 | +/* Others are read only */ |
||
4535 | +enum { |
||
4536 | + PCIE_INTRBCTRL_INT_NON = 0, |
||
4537 | + PCIE_INTRBCTRL_INTA, |
||
4538 | + PCIE_INTRBCTRL_INTB, |
||
4539 | + PCIE_INTRBCTRL_INTC, |
||
4540 | + PCIE_INTRBCTRL_INTD, |
||
4541 | +}; |
||
4542 | + |
||
4543 | +#define PCIE_PM_CAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x40) |
||
4544 | + |
||
4545 | +/* Power Management Control and Status Register */ |
||
4546 | +#define PCIE_PM_CSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x44) |
||
4547 | + |
||
4548 | +#define PCIE_PM_CSR_POWER_STATE 0x00000003 /* Power State */ |
||
4549 | +#define PCIE_PM_CSR_POWER_STATE_S 0 |
||
4550 | +#define PCIE_PM_CSR_SW_RST 0x00000008 /* Soft Reset Enabled */ |
||
4551 | +#define PCIE_PM_CSR_PME_ENABLE 0x00000100 /* PME Enable */ |
||
4552 | +#define PCIE_PM_CSR_PME_STATUS 0x00008000 /* PME status */ |
||
4553 | + |
||
4554 | +/* MSI Capability Register for EP */ |
||
4555 | +#define PCIE_MCAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x50) |
||
4556 | + |
||
4557 | +#define PCIE_MCAPR_MSI_CAP_ID 0x000000FF /* MSI Capability ID */ |
||
4558 | +#define PCIE_MCAPR_MSI_CAP_ID_S 0 |
||
4559 | +#define PCIE_MCAPR_MSI_NEXT_CAP_PTR 0x0000FF00 /* Next Capability Pointer */ |
||
4560 | +#define PCIE_MCAPR_MSI_NEXT_CAP_PTR_S 8 |
||
4561 | +#define PCIE_MCAPR_MSI_ENABLE 0x00010000 /* MSI Enable */ |
||
4562 | +#define PCIE_MCAPR_MULTI_MSG_CAP 0x000E0000 /* Multiple Message Capable */ |
||
4563 | +#define PCIE_MCAPR_MULTI_MSG_CAP_S 17 |
||
4564 | +#define PCIE_MCAPR_MULTI_MSG_ENABLE 0x00700000 /* Multiple Message Enable */ |
||
4565 | +#define PCIE_MCAPR_MULTI_MSG_ENABLE_S 20 |
||
4566 | +#define PCIE_MCAPR_ADDR64_CAP 0X00800000 /* 64-bit Address Capable */ |
||
4567 | + |
||
4568 | +/* MSI Message Address Register */ |
||
4569 | +#define PCIE_MA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x54) |
||
4570 | + |
||
4571 | +#define PCIE_MA_ADDR_MASK 0xFFFFFFFC /* Message Address */ |
||
4572 | + |
||
4573 | +/* MSI Message Upper Address Register */ |
||
4574 | +#define PCIE_MUA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x58) |
||
4575 | + |
||
4576 | +/* MSI Message Data Register */ |
||
4577 | +#define PCIE_MD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x5C) |
||
4578 | + |
||
4579 | +#define PCIE_MD_DATA 0x0000FFFF /* Message Data */ |
||
4580 | +#define PCIE_MD_DATA_S 0 |
||
4581 | + |
||
4582 | +/* PCI Express Capability Register */ |
||
4583 | +#define PCIE_XCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70) |
||
4584 | + |
||
4585 | +#define PCIE_XCAP_ID 0x000000FF /* PCI Express Capability ID */ |
||
4586 | +#define PCIE_XCAP_ID_S 0 |
||
4587 | +#define PCIE_XCAP_NEXT_CAP 0x0000FF00 /* Next Capability Pointer */ |
||
4588 | +#define PCIE_XCAP_NEXT_CAP_S 8 |
||
4589 | +#define PCIE_XCAP_VER 0x000F0000 /* PCI Express Capability Version */ |
||
4590 | +#define PCIE_XCAP_VER_S 16 |
||
4591 | +#define PCIE_XCAP_DEV_PORT_TYPE 0x00F00000 /* Device Port Type */ |
||
4592 | +#define PCIE_XCAP_DEV_PORT_TYPE_S 20 |
||
4593 | +#define PCIE_XCAP_SLOT_IMPLEMENTED 0x01000000 /* Slot Implemented */ |
||
4594 | +#define PCIE_XCAP_MSG_INT_NUM 0x3E000000 /* Interrupt Message Number */ |
||
4595 | +#define PCIE_XCAP_MSG_INT_NUM_S 25 |
||
4596 | + |
||
4597 | +/* Device Capability Register */ |
||
4598 | +#define PCIE_DCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74) |
||
4599 | + |
||
4600 | +#define PCIE_DCAP_MAX_PAYLOAD_SIZE 0x00000007 /* Max Payload size */ |
||
4601 | +#define PCIE_DCAP_MAX_PAYLOAD_SIZE_S 0 |
||
4602 | +#define PCIE_DCAP_PHANTOM_FUNC 0x00000018 /* Phanton Function, not supported */ |
||
4603 | +#define PCIE_DCAP_PHANTOM_FUNC_S 3 |
||
4604 | +#define PCIE_DCAP_EXT_TAG 0x00000020 /* Extended Tag Field */ |
||
4605 | +#define PCIE_DCAP_EP_L0S_LATENCY 0x000001C0 /* EP L0s latency only */ |
||
4606 | +#define PCIE_DCAP_EP_L0S_LATENCY_S 6 |
||
4607 | +#define PCIE_DCAP_EP_L1_LATENCY 0x00000E00 /* EP L1 latency only */ |
||
4608 | +#define PCIE_DCAP_EP_L1_LATENCY_S 9 |
||
4609 | +#define PCIE_DCAP_ROLE_BASE_ERR_REPORT 0x00008000 /* Role Based ERR */ |
||
4610 | + |
||
4611 | +/* Maximum payload size supported */ |
||
4612 | +enum { |
||
4613 | + PCIE_MAX_PAYLOAD_128 = 0, |
||
4614 | + PCIE_MAX_PAYLOAD_256, |
||
4615 | + PCIE_MAX_PAYLOAD_512, |
||
4616 | + PCIE_MAX_PAYLOAD_1024, |
||
4617 | + PCIE_MAX_PAYLOAD_2048, |
||
4618 | + PCIE_MAX_PAYLOAD_4096, |
||
4619 | +}; |
||
4620 | + |
||
4621 | +/* Device Control and Status Register */ |
||
4622 | +#define PCIE_DCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x78) |
||
4623 | + |
||
4624 | +#define PCIE_DCTLSTS_CORRECTABLE_ERR_EN 0x00000001 /* COR-ERR */ |
||
4625 | +#define PCIE_DCTLSTS_NONFATAL_ERR_EN 0x00000002 /* Non-fatal ERR */ |
||
4626 | +#define PCIE_DCTLSTS_FATAL_ERR_EN 0x00000004 /* Fatal ERR */ |
||
4627 | +#define PCIE_DCTLSYS_UR_REQ_EN 0x00000008 /* UR ERR */ |
||
4628 | +#define PCIE_DCTLSTS_RELAXED_ORDERING_EN 0x00000010 /* Enable relaxing ordering */ |
||
4629 | +#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE 0x000000E0 /* Max payload mask */ |
||
4630 | +#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE_S 5 |
||
4631 | +#define PCIE_DCTLSTS_EXT_TAG_EN 0x00000100 /* Extended tag field */ |
||
4632 | +#define PCIE_DCTLSTS_PHANTOM_FUNC_EN 0x00000200 /* Phantom Function Enable */ |
||
4633 | +#define PCIE_DCTLSTS_AUX_PM_EN 0x00000400 /* AUX Power PM Enable */ |
||
4634 | +#define PCIE_DCTLSTS_NO_SNOOP_EN 0x00000800 /* Enable no snoop, except root port*/ |
||
4635 | +#define PCIE_DCTLSTS_MAX_READ_SIZE 0x00007000 /* Max Read Request size*/ |
||
4636 | +#define PCIE_DCTLSTS_MAX_READ_SIZE_S 12 |
||
4637 | +#define PCIE_DCTLSTS_CORRECTABLE_ERR 0x00010000 /* COR-ERR Detected */ |
||
4638 | +#define PCIE_DCTLSTS_NONFATAL_ERR 0x00020000 /* Non-Fatal ERR Detected */ |
||
4639 | +#define PCIE_DCTLSTS_FATAL_ER 0x00040000 /* Fatal ERR Detected */ |
||
4640 | +#define PCIE_DCTLSTS_UNSUPPORTED_REQ 0x00080000 /* UR Detected */ |
||
4641 | +#define PCIE_DCTLSTS_AUX_POWER 0x00100000 /* Aux Power Detected */ |
||
4642 | +#define PCIE_DCTLSTS_TRANSACT_PENDING 0x00200000 /* Transaction pending */ |
||
4643 | + |
||
4644 | +#define PCIE_DCTLSTS_ERR_EN (PCIE_DCTLSTS_CORRECTABLE_ERR_EN | \ |
||
4645 | + PCIE_DCTLSTS_NONFATAL_ERR_EN | PCIE_DCTLSTS_FATAL_ERR_EN | \ |
||
4646 | + PCIE_DCTLSYS_UR_REQ_EN) |
||
4647 | + |
||
4648 | +/* Link Capability Register */ |
||
4649 | +#define PCIE_LCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7C) |
||
4650 | +#define PCIE_LCAP_MAX_LINK_SPEED 0x0000000F /* Max link speed, 0x1 by default */ |
||
4651 | +#define PCIE_LCAP_MAX_LINK_SPEED_S 0 |
||
4652 | +#define PCIE_LCAP_MAX_LENGTH_WIDTH 0x000003F0 /* Maxium Length Width */ |
||
4653 | +#define PCIE_LCAP_MAX_LENGTH_WIDTH_S 4 |
||
4654 | +#define PCIE_LCAP_ASPM_LEVEL 0x00000C00 /* Active State Link PM Support */ |
||
4655 | +#define PCIE_LCAP_ASPM_LEVEL_S 10 |
||
4656 | +#define PCIE_LCAP_L0S_EIXT_LATENCY 0x00007000 /* L0s Exit Latency */ |
||
4657 | +#define PCIE_LCAP_L0S_EIXT_LATENCY_S 12 |
||
4658 | +#define PCIE_LCAP_L1_EXIT_LATENCY 0x00038000 /* L1 Exit Latency */ |
||
4659 | +#define PCIE_LCAP_L1_EXIT_LATENCY_S 15 |
||
4660 | +#define PCIE_LCAP_CLK_PM 0x00040000 /* Clock Power Management */ |
||
4661 | +#define PCIE_LCAP_SDER 0x00080000 /* Surprise Down Error Reporting */ |
||
4662 | +#define PCIE_LCAP_DLL_ACTIVE_REPROT 0x00100000 /* Data Link Layer Active Reporting Capable */ |
||
4663 | +#define PCIE_LCAP_PORT_NUM 0xFF0000000 /* Port number */ |
||
4664 | +#define PCIE_LCAP_PORT_NUM_S 24 |
||
4665 | + |
||
4666 | +/* Maximum Length width definition */ |
||
4667 | +#define PCIE_MAX_LENGTH_WIDTH_RES 0x00 |
||
4668 | +#define PCIE_MAX_LENGTH_WIDTH_X1 0x01 /* Default */ |
||
4669 | +#define PCIE_MAX_LENGTH_WIDTH_X2 0x02 |
||
4670 | +#define PCIE_MAX_LENGTH_WIDTH_X4 0x04 |
||
4671 | +#define PCIE_MAX_LENGTH_WIDTH_X8 0x08 |
||
4672 | +#define PCIE_MAX_LENGTH_WIDTH_X12 0x0C |
||
4673 | +#define PCIE_MAX_LENGTH_WIDTH_X16 0x10 |
||
4674 | +#define PCIE_MAX_LENGTH_WIDTH_X32 0x20 |
||
4675 | + |
||
4676 | +/* Active State Link PM definition */ |
||
4677 | +enum { |
||
4678 | + PCIE_ASPM_RES0 = 0, |
||
4679 | + PCIE_ASPM_L0S_ENTRY_SUPPORT, /* L0s */ |
||
4680 | + PCIE_ASPM_RES1, |
||
4681 | + PCIE_ASPM_L0S_L1_ENTRY_SUPPORT, /* L0s and L1, default */ |
||
4682 | +}; |
||
4683 | + |
||
4684 | +/* L0s Exit Latency definition */ |
||
4685 | +enum { |
||
4686 | + PCIE_L0S_EIXT_LATENCY_L64NS = 0, /* < 64 ns */ |
||
4687 | + PCIE_L0S_EIXT_LATENCY_B64A128, /* > 64 ns < 128 ns */ |
||
4688 | + PCIE_L0S_EIXT_LATENCY_B128A256, /* > 128 ns < 256 ns */ |
||
4689 | + PCIE_L0S_EIXT_LATENCY_B256A512, /* > 256 ns < 512 ns */ |
||
4690 | + PCIE_L0S_EIXT_LATENCY_B512TO1U, /* > 512 ns < 1 us */ |
||
4691 | + PCIE_L0S_EIXT_LATENCY_B1A2U, /* > 1 us < 2 us */ |
||
4692 | + PCIE_L0S_EIXT_LATENCY_B2A4U, /* > 2 us < 4 us */ |
||
4693 | + PCIE_L0S_EIXT_LATENCY_M4US, /* > 4 us */ |
||
4694 | +}; |
||
4695 | + |
||
4696 | +/* L1 Exit Latency definition */ |
||
4697 | +enum { |
||
4698 | + PCIE_L1_EXIT_LATENCY_L1US = 0, /* < 1 us */ |
||
4699 | + PCIE_L1_EXIT_LATENCY_B1A2, /* > 1 us < 2 us */ |
||
4700 | + PCIE_L1_EXIT_LATENCY_B2A4, /* > 2 us < 4 us */ |
||
4701 | + PCIE_L1_EXIT_LATENCY_B4A8, /* > 4 us < 8 us */ |
||
4702 | + PCIE_L1_EXIT_LATENCY_B8A16, /* > 8 us < 16 us */ |
||
4703 | + PCIE_L1_EXIT_LATENCY_B16A32, /* > 16 us < 32 us */ |
||
4704 | + PCIE_L1_EXIT_LATENCY_B32A64, /* > 32 us < 64 us */ |
||
4705 | + PCIE_L1_EXIT_LATENCY_M64US, /* > 64 us */ |
||
4706 | +}; |
||
4707 | + |
||
4708 | +/* Link Control and Status Register */ |
||
4709 | +#define PCIE_LCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x80) |
||
4710 | +#define PCIE_LCTLSTS_ASPM_ENABLE 0x00000003 /* Active State Link PM Control */ |
||
4711 | +#define PCIE_LCTLSTS_ASPM_ENABLE_S 0 |
||
4712 | +#define PCIE_LCTLSTS_RCB128 0x00000008 /* Read Completion Boundary 128*/ |
||
4713 | +#define PCIE_LCTLSTS_LINK_DISABLE 0x00000010 /* Link Disable */ |
||
4714 | +#define PCIE_LCTLSTS_RETRIAN_LINK 0x00000020 /* Retrain Link */ |
||
4715 | +#define PCIE_LCTLSTS_COM_CLK_CFG 0x00000040 /* Common Clock Configuration */ |
||
4716 | +#define PCIE_LCTLSTS_EXT_SYNC 0x00000080 /* Extended Synch */ |
||
4717 | +#define PCIE_LCTLSTS_CLK_PM_EN 0x00000100 /* Enable Clock Powerm Management */ |
||
4718 | +#define PCIE_LCTLSTS_LINK_SPEED 0x000F0000 /* Link Speed */ |
||
4719 | +#define PCIE_LCTLSTS_LINK_SPEED_S 16 |
||
4720 | +#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH 0x03F00000 /* Negotiated Link Width */ |
||
4721 | +#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH_S 20 |
||
4722 | +#define PCIE_LCTLSTS_RETRAIN_PENDING 0x08000000 /* Link training is ongoing */ |
||
4723 | +#define PCIE_LCTLSTS_SLOT_CLK_CFG 0x10000000 /* Slot Clock Configuration */ |
||
4724 | +#define PCIE_LCTLSTS_DLL_ACTIVE 0x20000000 /* Data Link Layer Active */ |
||
4725 | + |
||
4726 | +/* Slot Capabilities Register */ |
||
4727 | +#define PCIE_SLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x84) |
||
4728 | + |
||
4729 | +/* Slot Capabilities */ |
||
4730 | +#define PCIE_SLCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x88) |
||
4731 | + |
||
4732 | +/* Root Control and Capability Register */ |
||
4733 | +#define PCIE_RCTLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x8C) |
||
4734 | +#define PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR 0x00000001 /* #SERR on COR-ERR */ |
||
4735 | +#define PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR 0x00000002 /* #SERR on Non-Fatal ERR */ |
||
4736 | +#define PCIE_RCTLCAP_SERR_ON_FATAL_ERR 0x00000004 /* #SERR on Fatal ERR */ |
||
4737 | +#define PCIE_RCTLCAP_PME_INT_EN 0x00000008 /* PME Interrupt Enable */ |
||
4738 | +#define PCIE_RCTLCAP_SERR_ENABLE (PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR | \ |
||
4739 | + PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR | PCIE_RCTLCAP_SERR_ON_FATAL_ERR) |
||
4740 | +/* Root Status Register */ |
||
4741 | +#define PCIE_RSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x90) |
||
4742 | +#define PCIE_RSTS_PME_REQ_ID 0x0000FFFF /* PME Request ID */ |
||
4743 | +#define PCIE_RSTS_PME_REQ_ID_S 0 |
||
4744 | +#define PCIE_RSTS_PME_STATUS 0x00010000 /* PME Status */ |
||
4745 | +#define PCIE_RSTS_PME_PENDING 0x00020000 /* PME Pending */ |
||
4746 | + |
||
4747 | +/* PCI Express Enhanced Capability Header */ |
||
4748 | +#define PCIE_ENHANCED_CAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x100) |
||
4749 | +#define PCIE_ENHANCED_CAP_ID 0x0000FFFF /* PCI Express Extended Capability ID */ |
||
4750 | +#define PCIE_ENHANCED_CAP_ID_S 0 |
||
4751 | +#define PCIE_ENHANCED_CAP_VER 0x000F0000 /* Capability Version */ |
||
4752 | +#define PCIE_ENHANCED_CAP_VER_S 16 |
||
4753 | +#define PCIE_ENHANCED_CAP_NEXT_OFFSET 0xFFF00000 /* Next Capability Offset */ |
||
4754 | +#define PCIE_ENHANCED_CAP_NEXT_OFFSET_S 20 |
||
4755 | + |
||
4756 | +/* Uncorrectable Error Status Register */ |
||
4757 | +#define PCIE_UES_R(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x104) |
||
4758 | +#define PCIE_DATA_LINK_PROTOCOL_ERR 0x00000010 /* Data Link Protocol Error Status */ |
||
4759 | +#define PCIE_SURPRISE_DOWN_ERROR 0x00000020 /* Surprise Down Error Status */ |
||
4760 | +#define PCIE_POISONED_TLP 0x00001000 /* Poisoned TLP Status */ |
||
4761 | +#define PCIE_FC_PROTOCOL_ERR 0x00002000 /* Flow Control Protocol Error Status */ |
||
4762 | +#define PCIE_COMPLETION_TIMEOUT 0x00004000 /* Completion Timeout Status */ |
||
4763 | +#define PCIE_COMPLETOR_ABORT 0x00008000 /* Completer Abort Error */ |
||
4764 | +#define PCIE_UNEXPECTED_COMPLETION 0x00010000 /* Unexpected Completion Status */ |
||
4765 | +#define PCIE_RECEIVER_OVERFLOW 0x00020000 /* Receive Overflow Status */ |
||
4766 | +#define PCIE_MALFORNED_TLP 0x00040000 /* Malformed TLP Stauts */ |
||
4767 | +#define PCIE_ECRC_ERR 0x00080000 /* ECRC Error Stauts */ |
||
4768 | +#define PCIE_UR_REQ 0x00100000 /* Unsupported Request Error Status */ |
||
4769 | +#define PCIE_ALL_UNCORRECTABLE_ERR (PCIE_DATA_LINK_PROTOCOL_ERR | PCIE_SURPRISE_DOWN_ERROR | \ |
||
4770 | + PCIE_POISONED_TLP | PCIE_FC_PROTOCOL_ERR | PCIE_COMPLETION_TIMEOUT | \ |
||
4771 | + PCIE_COMPLETOR_ABORT | PCIE_UNEXPECTED_COMPLETION | PCIE_RECEIVER_OVERFLOW |\ |
||
4772 | + PCIE_MALFORNED_TLP | PCIE_ECRC_ERR | PCIE_UR_REQ) |
||
4773 | + |
||
4774 | +/* Uncorrectable Error Mask Register, Mask means no report */ |
||
4775 | +#define PCIE_UEMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x108) |
||
4776 | + |
||
4777 | +/* Uncorrectable Error Severity Register */ |
||
4778 | +#define PCIE_UESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10C) |
||
4779 | + |
||
4780 | +/* Correctable Error Status Register */ |
||
4781 | +#define PCIE_CESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x110) |
||
4782 | +#define PCIE_RX_ERR 0x00000001 /* Receive Error Status */ |
||
4783 | +#define PCIE_BAD_TLP 0x00000040 /* Bad TLP Status */ |
||
4784 | +#define PCIE_BAD_DLLP 0x00000080 /* Bad DLLP Status */ |
||
4785 | +#define PCIE_REPLAY_NUM_ROLLOVER 0x00000100 /* Replay Number Rollover Status */ |
||
4786 | +#define PCIE_REPLAY_TIMER_TIMEOUT_ERR 0x00001000 /* Reply Timer Timeout Status */ |
||
4787 | +#define PCIE_ADVISORY_NONFTAL_ERR 0x00002000 /* Advisory Non-Fatal Error Status */ |
||
4788 | +#define PCIE_CORRECTABLE_ERR (PCIE_RX_ERR | PCIE_BAD_TLP | PCIE_BAD_DLLP | PCIE_REPLAY_NUM_ROLLOVER |\ |
||
4789 | + PCIE_REPLAY_TIMER_TIMEOUT_ERR | PCIE_ADVISORY_NONFTAL_ERR) |
||
4790 | + |
||
4791 | +/* Correctable Error Mask Register */ |
||
4792 | +#define PCIE_CEMR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x114) |
||
4793 | + |
||
4794 | +/* Advanced Error Capabilities and Control Register */ |
||
4795 | +#define PCIE_AECCR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x118) |
||
4796 | +#define PCIE_AECCR_FIRST_ERR_PTR 0x0000001F /* First Error Pointer */ |
||
4797 | +#define PCIE_AECCR_FIRST_ERR_PTR_S 0 |
||
4798 | +#define PCIE_AECCR_ECRC_GEN_CAP 0x00000020 /* ECRC Generation Capable */ |
||
4799 | +#define PCIE_AECCR_ECRC_GEN_EN 0x00000040 /* ECRC Generation Enable */ |
||
4800 | +#define PCIE_AECCR_ECRC_CHECK_CAP 0x00000080 /* ECRC Check Capable */ |
||
4801 | +#define PCIE_AECCR_ECRC_CHECK_EN 0x00000100 /* ECRC Check Enable */ |
||
4802 | + |
||
4803 | +/* Header Log Register 1 */ |
||
4804 | +#define PCIE_HLR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x11C) |
||
4805 | + |
||
4806 | +/* Header Log Register 2 */ |
||
4807 | +#define PCIE_HLR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x120) |
||
4808 | + |
||
4809 | +/* Header Log Register 3 */ |
||
4810 | +#define PCIE_HLR3(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x124) |
||
4811 | + |
||
4812 | +/* Header Log Register 4 */ |
||
4813 | +#define PCIE_HLR4(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x128) |
||
4814 | + |
||
4815 | +/* Root Error Command Register */ |
||
4816 | +#define PCIE_RECR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x12C) |
||
4817 | +#define PCIE_RECR_CORRECTABLE_ERR_REPORT_EN 0x00000001 /* COR-ERR */ |
||
4818 | +#define PCIE_RECR_NONFATAL_ERR_REPORT_EN 0x00000002 /* Non-Fatal ERR */ |
||
4819 | +#define PCIE_RECR_FATAL_ERR_REPORT_EN 0x00000004 /* Fatal ERR */ |
||
4820 | +#define PCIE_RECR_ERR_REPORT_EN (PCIE_RECR_CORRECTABLE_ERR_REPORT_EN | \ |
||
4821 | + PCIE_RECR_NONFATAL_ERR_REPORT_EN | PCIE_RECR_FATAL_ERR_REPORT_EN) |
||
4822 | + |
||
4823 | +/* Root Error Status Register */ |
||
4824 | +#define PCIE_RESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x130) |
||
4825 | +#define PCIE_RESR_CORRECTABLE_ERR 0x00000001 /* COR-ERR Receveid */ |
||
4826 | +#define PCIE_RESR_MULTI_CORRECTABLE_ERR 0x00000002 /* Multiple COR-ERR Received */ |
||
4827 | +#define PCIE_RESR_FATAL_NOFATAL_ERR 0x00000004 /* ERR Fatal/Non-Fatal Received */ |
||
4828 | +#define PCIE_RESR_MULTI_FATAL_NOFATAL_ERR 0x00000008 /* Multiple ERR Fatal/Non-Fatal Received */ |
||
4829 | +#define PCIE_RESR_FIRST_UNCORRECTABLE_FATAL_ERR 0x00000010 /* First UN-COR Fatal */ |
||
4830 | +#define PCIR_RESR_NON_FATAL_ERR 0x00000020 /* Non-Fatal Error Message Received */ |
||
4831 | +#define PCIE_RESR_FATAL_ERR 0x00000040 /* Fatal Message Received */ |
||
4832 | +#define PCIE_RESR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ |
||
4833 | +#define PCIE_RESR_AER_INT_MSG_NUM_S 27 |
||
4834 | + |
||
4835 | +/* Error Source Indentification Register */ |
||
4836 | +#define PCIE_ESIR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x134) |
||
4837 | +#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID 0x0000FFFF |
||
4838 | +#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID_S 0 |
||
4839 | +#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID 0xFFFF0000 |
||
4840 | +#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID_S 16 |
||
4841 | + |
||
4842 | +/* VC Enhanced Capability Header */ |
||
4843 | +#define PCIE_VC_ECH(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x140) |
||
4844 | + |
||
4845 | +/* Port VC Capability Register */ |
||
4846 | +#define PCIE_PVC1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x144) |
||
4847 | +#define PCIE_PVC1_EXT_VC_CNT 0x00000007 /* Extended VC Count */ |
||
4848 | +#define PCIE_PVC1_EXT_VC_CNT_S 0 |
||
4849 | +#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT 0x00000070 /* Low Priority Extended VC Count */ |
||
4850 | +#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT_S 4 |
||
4851 | +#define PCIE_PVC1_REF_CLK 0x00000300 /* Reference Clock */ |
||
4852 | +#define PCIE_PVC1_REF_CLK_S 8 |
||
4853 | +#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE 0x00000C00 /* Port Arbitration Table Entry Size */ |
||
4854 | +#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE_S 10 |
||
4855 | + |
||
4856 | +/* Extended Virtual Channel Count Defintion */ |
||
4857 | +#define PCIE_EXT_VC_CNT_MIN 0 |
||
4858 | +#define PCIE_EXT_VC_CNT_MAX 7 |
||
4859 | + |
||
4860 | +/* Port Arbitration Table Entry Size Definition */ |
||
4861 | +enum { |
||
4862 | + PCIE_PORT_ARB_TAB_ENTRY_SIZE_S1BIT = 0, |
||
4863 | + PCIE_PORT_ARB_TAB_ENTRY_SIZE_S2BIT, |
||
4864 | + PCIE_PORT_ARB_TAB_ENTRY_SIZE_S4BIT, |
||
4865 | + PCIE_PORT_ARB_TAB_ENTRY_SIZE_S8BIT, |
||
4866 | +}; |
||
4867 | + |
||
4868 | +/* Port VC Capability Register 2 */ |
||
4869 | +#define PCIE_PVC2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x148) |
||
4870 | +#define PCIE_PVC2_VC_ARB_16P_FIXED_WRR 0x00000001 /* HW Fixed arbitration, 16 phase WRR */ |
||
4871 | +#define PCIE_PVC2_VC_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ |
||
4872 | +#define PCIE_PVC2_VC_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ |
||
4873 | +#define PCIE_PVC2_VC_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ |
||
4874 | +#define PCIE_PVC2_VC_ARB_WRR 0x0000000F |
||
4875 | +#define PCIE_PVC2_VC_ARB_TAB_OFFSET 0xFF000000 /* VC arbitration table offset, not support */ |
||
4876 | +#define PCIE_PVC2_VC_ARB_TAB_OFFSET_S 24 |
||
4877 | + |
||
4878 | +/* Port VC Control and Status Register */ |
||
4879 | +#define PCIE_PVCCRSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14C) |
||
4880 | +#define PCIE_PVCCRSR_LOAD_VC_ARB_TAB 0x00000001 /* Load VC Arbitration Table */ |
||
4881 | +#define PCIE_PVCCRSR_VC_ARB_SEL 0x0000000E /* VC Arbitration Select */ |
||
4882 | +#define PCIE_PVCCRSR_VC_ARB_SEL_S 1 |
||
4883 | +#define PCIE_PVCCRSR_VC_ARB_TAB_STATUS 0x00010000 /* Arbitration Status */ |
||
4884 | + |
||
4885 | +/* VC0 Resource Capability Register */ |
||
4886 | +#define PCIE_VC0_RC(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x150) |
||
4887 | +#define PCIE_VC0_RC_PORT_ARB_HW_FIXED 0x00000001 /* HW Fixed arbitration */ |
||
4888 | +#define PCIE_VC0_RC_PORT_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ |
||
4889 | +#define PCIE_VC0_RC_PORT_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ |
||
4890 | +#define PCIE_VC0_RC_PORT_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ |
||
4891 | +#define PCIE_VC0_RC_PORT_ARB_TM_128P_WRR 0x00000010 /* Time-based 128 phase WRR */ |
||
4892 | +#define PCIE_VC0_RC_PORT_ARB_TM_256P_WRR 0x00000020 /* Time-based 256 phase WRR */ |
||
4893 | +#define PCIE_VC0_RC_PORT_ARB (PCIE_VC0_RC_PORT_ARB_HW_FIXED | PCIE_VC0_RC_PORT_ARB_32P_WRR |\ |
||
4894 | + PCIE_VC0_RC_PORT_ARB_64P_WRR | PCIE_VC0_RC_PORT_ARB_128P_WRR | \ |
||
4895 | + PCIE_VC0_RC_PORT_ARB_TM_128P_WRR | PCIE_VC0_RC_PORT_ARB_TM_256P_WRR) |
||
4896 | + |
||
4897 | +#define PCIE_VC0_RC_REJECT_SNOOP 0x00008000 /* Reject Snoop Transactioin */ |
||
4898 | +#define PCIE_VC0_RC_MAX_TIMESLOTS 0x007F0000 /* Maximum time Slots */ |
||
4899 | +#define PCIE_VC0_RC_MAX_TIMESLOTS_S 16 |
||
4900 | +#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET 0xFF000000 /* Port Arbitration Table Offset */ |
||
4901 | +#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET_S 24 |
||
4902 | + |
||
4903 | +/* VC0 Resource Control Register */ |
||
4904 | +#define PCIE_VC0_RC0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x154) |
||
4905 | +#define PCIE_VC0_RC0_TVM0 0x00000001 /* TC0 and VC0 */ |
||
4906 | +#define PCIE_VC0_RC0_TVM1 0x00000002 /* TC1 and VC1 */ |
||
4907 | +#define PCIE_VC0_RC0_TVM2 0x00000004 /* TC2 and VC2 */ |
||
4908 | +#define PCIE_VC0_RC0_TVM3 0x00000008 /* TC3 and VC3 */ |
||
4909 | +#define PCIE_VC0_RC0_TVM4 0x00000010 /* TC4 and VC4 */ |
||
4910 | +#define PCIE_VC0_RC0_TVM5 0x00000020 /* TC5 and VC5 */ |
||
4911 | +#define PCIE_VC0_RC0_TVM6 0x00000040 /* TC6 and VC6 */ |
||
4912 | +#define PCIE_VC0_RC0_TVM7 0x00000080 /* TC7 and VC7 */ |
||
4913 | +#define PCIE_VC0_RC0_TC_VC 0x000000FF /* TC/VC mask */ |
||
4914 | + |
||
4915 | +#define PCIE_VC0_RC0_LOAD_PORT_ARB_TAB 0x00010000 /* Load Port Arbitration Table */ |
||
4916 | +#define PCIE_VC0_RC0_PORT_ARB_SEL 0x000E0000 /* Port Arbitration Select */ |
||
4917 | +#define PCIE_VC0_RC0_PORT_ARB_SEL_S 17 |
||
4918 | +#define PCIE_VC0_RC0_VC_ID 0x07000000 /* VC ID */ |
||
4919 | +#define PCIE_VC0_RC0_VC_ID_S 24 |
||
4920 | +#define PCIE_VC0_RC0_VC_EN 0x80000000 /* VC Enable */ |
||
4921 | + |
||
4922 | +/* VC0 Resource Status Register */ |
||
4923 | +#define PCIE_VC0_RSR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x158) |
||
4924 | +#define PCIE_VC0_RSR0_PORT_ARB_TAB_STATUS 0x00010000 /* Port Arbitration Table Status,not used */ |
||
4925 | +#define PCIE_VC0_RSR0_VC_NEG_PENDING 0x00020000 /* VC Negotiation Pending */ |
||
4926 | + |
||
4927 | +/* Ack Latency Timer and Replay Timer Register */ |
||
4928 | +#define PCIE_ALTRT(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x700) |
||
4929 | +#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT 0x0000FFFF /* Round Trip Latency Time Limit */ |
||
4930 | +#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT_S 0 |
||
4931 | +#define PCIE_ALTRT_REPLAY_TIME_LIMIT 0xFFFF0000 /* Replay Time Limit */ |
||
4932 | +#define PCIE_ALTRT_REPLAY_TIME_LIMIT_S 16 |
||
4933 | + |
||
4934 | +/* Other Message Register */ |
||
4935 | +#define PCIE_OMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x704) |
||
4936 | + |
||
4937 | +/* Port Force Link Register */ |
||
4938 | +#define PCIE_PFLR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x708) |
||
4939 | +#define PCIE_PFLR_LINK_NUM 0x000000FF /* Link Number */ |
||
4940 | +#define PCIE_PFLR_LINK_NUM_S 0 |
||
4941 | +#define PCIE_PFLR_FORCE_LINK 0x00008000 /* Force link */ |
||
4942 | +#define PCIE_PFLR_LINK_STATE 0x003F0000 /* Link State */ |
||
4943 | +#define PCIE_PFLR_LINK_STATE_S 16 |
||
4944 | +#define PCIE_PFLR_LOW_POWER_ENTRY_CNT 0xFF000000 /* Low Power Entrance Count, only for EP */ |
||
4945 | +#define PCIE_PFLR_LOW_POWER_ENTRY_CNT_S 24 |
||
4946 | + |
||
4947 | +/* Ack Frequency Register */ |
||
4948 | +#define PCIE_AFR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70C) |
||
4949 | +#define PCIE_AFR_AF 0x000000FF /* Ack Frequency */ |
||
4950 | +#define PCIE_AFR_AF_S 0 |
||
4951 | +#define PCIE_AFR_FTS_NUM 0x0000FF00 /* The number of Fast Training Sequence from L0S to L0 */ |
||
4952 | +#define PCIE_AFR_FTS_NUM_S 8 |
||
4953 | +#define PCIE_AFR_COM_FTS_NUM 0x00FF0000 /* N_FTS; when common clock is used*/ |
||
4954 | +#define PCIE_AFR_COM_FTS_NUM_S 16 |
||
4955 | +#define PCIE_AFR_L0S_ENTRY_LATENCY 0x07000000 /* L0s Entrance Latency */ |
||
4956 | +#define PCIE_AFR_L0S_ENTRY_LATENCY_S 24 |
||
4957 | +#define PCIE_AFR_L1_ENTRY_LATENCY 0x38000000 /* L1 Entrance Latency */ |
||
4958 | +#define PCIE_AFR_L1_ENTRY_LATENCY_S 27 |
||
4959 | +#define PCIE_AFR_FTS_NUM_DEFAULT 32 |
||
4960 | +#define PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT 7 |
||
4961 | +#define PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT 5 |
||
4962 | + |
||
4963 | +/* Port Link Control Register */ |
||
4964 | +#define PCIE_PLCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x710) |
||
4965 | +#define PCIE_PLCR_OTHER_MSG_REQ 0x00000001 /* Other Message Request */ |
||
4966 | +#define PCIE_PLCR_SCRAMBLE_DISABLE 0x00000002 /* Scramble Disable */ |
||
4967 | +#define PCIE_PLCR_LOOPBACK_EN 0x00000004 /* Loopback Enable */ |
||
4968 | +#define PCIE_PLCR_LTSSM_HOT_RST 0x00000008 /* Force LTSSM to the hot reset */ |
||
4969 | +#define PCIE_PLCR_DLL_LINK_EN 0x00000020 /* Enable Link initialization */ |
||
4970 | +#define PCIE_PLCR_FAST_LINK_SIM_EN 0x00000080 /* Sets all internal timers to fast mode for simulation purposes */ |
||
4971 | +#define PCIE_PLCR_LINK_MODE 0x003F0000 /* Link Mode Enable Mask */ |
||
4972 | +#define PCIE_PLCR_LINK_MODE_S 16 |
||
4973 | +#define PCIE_PLCR_CORRUPTED_CRC_EN 0x02000000 /* Enabled Corrupt CRC */ |
||
4974 | + |
||
4975 | +/* Lane Skew Register */ |
||
4976 | +#define PCIE_LSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x714) |
||
4977 | +#define PCIE_LSR_LANE_SKEW_NUM 0x00FFFFFF /* Insert Lane Skew for Transmit, not applicable */ |
||
4978 | +#define PCIE_LSR_LANE_SKEW_NUM_S 0 |
||
4979 | +#define PCIE_LSR_FC_DISABLE 0x01000000 /* Disable of Flow Control */ |
||
4980 | +#define PCIE_LSR_ACKNAK_DISABLE 0x02000000 /* Disable of Ack/Nak */ |
||
4981 | +#define PCIE_LSR_LANE_DESKEW_DISABLE 0x80000000 /* Disable of Lane-to-Lane Skew */ |
||
4982 | + |
||
4983 | +/* Symbol Number Register */ |
||
4984 | +#define PCIE_SNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x718) |
||
4985 | +#define PCIE_SNR_TS 0x0000000F /* Number of TS Symbol */ |
||
4986 | +#define PCIE_SNR_TS_S 0 |
||
4987 | +#define PCIE_SNR_SKP 0x00000700 /* Number of SKP Symbol */ |
||
4988 | +#define PCIE_SNR_SKP_S 8 |
||
4989 | +#define PCIE_SNR_REPLAY_TIMER 0x0007C000 /* Timer Modifier for Replay Timer */ |
||
4990 | +#define PCIE_SNR_REPLAY_TIMER_S 14 |
||
4991 | +#define PCIE_SNR_ACKNAK_LATENCY_TIMER 0x00F80000 /* Timer Modifier for Ack/Nak Latency Timer */ |
||
4992 | +#define PCIE_SNR_ACKNAK_LATENCY_TIMER_S 19 |
||
4993 | +#define PCIE_SNR_FC_TIMER 0x1F000000 /* Timer Modifier for Flow Control Watchdog Timer */ |
||
4994 | +#define PCIE_SNR_FC_TIMER_S 28 |
||
4995 | + |
||
4996 | +/* Symbol Timer Register and Filter Mask Register 1 */ |
||
4997 | +#define PCIE_STRFMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x71C) |
||
4998 | +#define PCIE_STRFMR_SKP_INTERVAL 0x000007FF /* SKP lnterval Value */ |
||
4999 | +#define PCIE_STRFMR_SKP_INTERVAL_S 0 |
||
5000 | +#define PCIE_STRFMR_FC_WDT_DISABLE 0x00008000 /* Disable of FC Watchdog Timer */ |
||
5001 | +#define PCIE_STRFMR_TLP_FUNC_MISMATCH_OK 0x00010000 /* Mask Function Mismatch Filtering for Incoming Requests */ |
||
5002 | +#define PCIE_STRFMR_POISONED_TLP_OK 0x00020000 /* Mask Poisoned TLP Filtering */ |
||
5003 | +#define PCIE_STRFMR_BAR_MATCH_OK 0x00040000 /* Mask BAR Match Filtering */ |
||
5004 | +#define PCIE_STRFMR_TYPE1_CFG_REQ_OK 0x00080000 /* Mask Type 1 Configuration Request Filtering */ |
||
5005 | +#define PCIE_STRFMR_LOCKED_REQ_OK 0x00100000 /* Mask Locked Request Filtering */ |
||
5006 | +#define PCIE_STRFMR_CPL_TAG_ERR_RULES_OK 0x00200000 /* Mask Tag Error Rules for Received Completions */ |
||
5007 | +#define PCIE_STRFMR_CPL_REQUESTOR_ID_MISMATCH_OK 0x00400000 /* Mask Requester ID Mismatch Error for Received Completions */ |
||
5008 | +#define PCIE_STRFMR_CPL_FUNC_MISMATCH_OK 0x00800000 /* Mask Function Mismatch Error for Received Completions */ |
||
5009 | +#define PCIE_STRFMR_CPL_TC_MISMATCH_OK 0x01000000 /* Mask Traffic Class Mismatch Error for Received Completions */ |
||
5010 | +#define PCIE_STRFMR_CPL_ATTR_MISMATCH_OK 0x02000000 /* Mask Attribute Mismatch Error for Received Completions */ |
||
5011 | +#define PCIE_STRFMR_CPL_LENGTH_MISMATCH_OK 0x04000000 /* Mask Length Mismatch Error for Received Completions */ |
||
5012 | +#define PCIE_STRFMR_TLP_ECRC_ERR_OK 0x08000000 /* Mask ECRC Error Filtering */ |
||
5013 | +#define PCIE_STRFMR_CPL_TLP_ECRC_OK 0x10000000 /* Mask ECRC Error Filtering for Completions */ |
||
5014 | +#define PCIE_STRFMR_RX_TLP_MSG_NO_DROP 0x20000000 /* Send Message TLPs */ |
||
5015 | +#define PCIE_STRFMR_RX_IO_TRANS_ENABLE 0x40000000 /* Mask Filtering of received I/O Requests */ |
||
5016 | +#define PCIE_STRFMR_RX_CFG_TRANS_ENABLE 0x80000000 /* Mask Filtering of Received Configuration Requests */ |
||
5017 | + |
||
5018 | +#define PCIE_DEF_SKP_INTERVAL 700 /* 1180 ~1538 , 125MHz * 2, 250MHz * 1 */ |
||
5019 | + |
||
5020 | +/* Filter Masker Register 2 */ |
||
5021 | +#define PCIE_FMR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x720) |
||
5022 | +#define PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1 0x00000001 /* Mask RADM Filtering and Error Handling Rules */ |
||
5023 | +#define PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 0x00000002 /* Mask RADM Filtering and Error Handling Rules */ |
||
5024 | + |
||
5025 | +/* Debug Register 0 */ |
||
5026 | +#define PCIE_DBR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x728) |
||
5027 | + |
||
5028 | +/* Debug Register 1 */ |
||
5029 | +#define PCIE_DBR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x72C) |
||
5030 | + |
||
5031 | +/* Transmit Posted FC Credit Status Register */ |
||
5032 | +#define PCIE_TPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x730) |
||
5033 | +#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS 0x00000FFF /* Transmit Posted Data FC Credits */ |
||
5034 | +#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS_S 0 |
||
5035 | +#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS 0x000FF000 /* Transmit Posted Header FC Credits */ |
||
5036 | +#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS_S 12 |
||
5037 | + |
||
5038 | +/* Transmit Non-Posted FC Credit Status */ |
||
5039 | +#define PCIE_TNPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x734) |
||
5040 | +#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS 0x00000FFF /* Transmit Non-Posted Data FC Credits */ |
||
5041 | +#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS_S 0 |
||
5042 | +#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS 0x000FF000 /* Transmit Non-Posted Header FC Credits */ |
||
5043 | +#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS_S 12 |
||
5044 | + |
||
5045 | +/* Transmit Complete FC Credit Status Register */ |
||
5046 | +#define PCIE_TCFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x738) |
||
5047 | +#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS 0x00000FFF /* Transmit Completion Data FC Credits */ |
||
5048 | +#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS_S 0 |
||
5049 | +#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS 0x000FF000 /* Transmit Completion Header FC Credits */ |
||
5050 | +#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS_S 12 |
||
5051 | + |
||
5052 | +/* Queue Status Register */ |
||
5053 | +#define PCIE_QSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x73C) |
||
5054 | +#define PCIE_QSR_WAIT_UPDATE_FC_DLL 0x00000001 /* Received TLP FC Credits Not Returned */ |
||
5055 | +#define PCIE_QSR_TX_RETRY_BUF_NOT_EMPTY 0x00000002 /* Transmit Retry Buffer Not Empty */ |
||
5056 | +#define PCIE_QSR_RX_QUEUE_NOT_EMPTY 0x00000004 /* Received Queue Not Empty */ |
||
5057 | + |
||
5058 | +/* VC Transmit Arbitration Register 1 */ |
||
5059 | +#define PCIE_VCTAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x740) |
||
5060 | +#define PCIE_VCTAR1_WRR_WEIGHT_VC0 0x000000FF /* WRR Weight for VC0 */ |
||
5061 | +#define PCIE_VCTAR1_WRR_WEIGHT_VC1 0x0000FF00 /* WRR Weight for VC1 */ |
||
5062 | +#define PCIE_VCTAR1_WRR_WEIGHT_VC2 0x00FF0000 /* WRR Weight for VC2 */ |
||
5063 | +#define PCIE_VCTAR1_WRR_WEIGHT_VC3 0xFF000000 /* WRR Weight for VC3 */ |
||
5064 | + |
||
5065 | +/* VC Transmit Arbitration Register 2 */ |
||
5066 | +#define PCIE_VCTAR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x744) |
||
5067 | +#define PCIE_VCTAR2_WRR_WEIGHT_VC4 0x000000FF /* WRR Weight for VC4 */ |
||
5068 | +#define PCIE_VCTAR2_WRR_WEIGHT_VC5 0x0000FF00 /* WRR Weight for VC5 */ |
||
5069 | +#define PCIE_VCTAR2_WRR_WEIGHT_VC6 0x00FF0000 /* WRR Weight for VC6 */ |
||
5070 | +#define PCIE_VCTAR2_WRR_WEIGHT_VC7 0xFF000000 /* WRR Weight for VC7 */ |
||
5071 | + |
||
5072 | +/* VC0 Posted Receive Queue Control Register */ |
||
5073 | +#define PCIE_VC0_PRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x748) |
||
5074 | +#define PCIE_VC0_PRQCR_P_DATA_CREDITS 0x00000FFF /* VC0 Posted Data Credits */ |
||
5075 | +#define PCIE_VC0_PRQCR_P_DATA_CREDITS_S 0 |
||
5076 | +#define PCIE_VC0_PRQCR_P_HDR_CREDITS 0x000FF000 /* VC0 Posted Header Credits */ |
||
5077 | +#define PCIE_VC0_PRQCR_P_HDR_CREDITS_S 12 |
||
5078 | +#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE 0x00E00000 /* VC0 Posted TLP Queue Mode */ |
||
5079 | +#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE_S 20 |
||
5080 | +#define PCIE_VC0_PRQCR_TLP_RELAX_ORDER 0x40000000 /* TLP Type Ordering for VC0 */ |
||
5081 | +#define PCIE_VC0_PRQCR_VC_STRICT_ORDER 0x80000000 /* VC0 Ordering for Receive Queues */ |
||
5082 | + |
||
5083 | +/* VC0 Non-Posted Receive Queue Control */ |
||
5084 | +#define PCIE_VC0_NPRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74C) |
||
5085 | +#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS 0x00000FFF /* VC0 Non-Posted Data Credits */ |
||
5086 | +#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS_S 0 |
||
5087 | +#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS 0x000FF000 /* VC0 Non-Posted Header Credits */ |
||
5088 | +#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS_S 12 |
||
5089 | +#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE 0x00E00000 /* VC0 Non-Posted TLP Queue Mode */ |
||
5090 | +#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE_S 20 |
||
5091 | + |
||
5092 | +/* VC0 Completion Receive Queue Control */ |
||
5093 | +#define PCIE_VC0_CRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x750) |
||
5094 | +#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS 0x00000FFF /* VC0 Completion TLP Queue Mode */ |
||
5095 | +#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS_S 0 |
||
5096 | +#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS 0x000FF000 /* VC0 Completion Header Credits */ |
||
5097 | +#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS_S 12 |
||
5098 | +#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE 0x00E00000 /* VC0 Completion Data Credits */ |
||
5099 | +#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE_S 21 |
||
5100 | + |
||
5101 | +/* Applicable to the above three registers */ |
||
5102 | +enum { |
||
5103 | + PCIE_VC0_TLP_QUEUE_MODE_STORE_FORWARD = 1, |
||
5104 | + PCIE_VC0_TLP_QUEUE_MODE_CUT_THROUGH = 2, |
||
5105 | + PCIE_VC0_TLP_QUEUE_MODE_BYPASS = 4, |
||
5106 | +}; |
||
5107 | + |
||
5108 | +/* VC0 Posted Buffer Depth Register */ |
||
5109 | +#define PCIE_VC0_PBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7A8) |
||
5110 | +#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Posted Data Queue Depth */ |
||
5111 | +#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES_S 0 |
||
5112 | +#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Posted Header Queue Depth */ |
||
5113 | +#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES_S 16 |
||
5114 | + |
||
5115 | +/* VC0 Non-Posted Buffer Depth Register */ |
||
5116 | +#define PCIE_VC0_NPBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7AC) |
||
5117 | +#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Non-Posted Data Queue Depth */ |
||
5118 | +#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES_S 0 |
||
5119 | +#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Non-Posted Header Queue Depth */ |
||
5120 | +#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES_S 16 |
||
5121 | + |
||
5122 | +/* VC0 Completion Buffer Depth Register */ |
||
5123 | +#define PCIE_VC0_CBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7B0) |
||
5124 | +#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES 0x00003FFF /* C0 Completion Data Queue Depth */ |
||
5125 | +#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES_S 0 |
||
5126 | +#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Completion Header Queue Depth */ |
||
5127 | +#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES_S 16 |
||
5128 | + |
||
5129 | +/* PHY Status Register, all zeros in VR9 */ |
||
5130 | +#define PCIE_PHYSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x810) |
||
5131 | + |
||
5132 | +/* PHY Control Register, all zeros in VR9 */ |
||
5133 | +#define PCIE_PHYCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x814) |
||
5134 | + |
||
5135 | +/* |
||
5136 | + * PCIe PDI PHY register definition, suppose all the following |
||
5137 | + * stuff is confidential. |
||
5138 | + * XXX, detailed bit definition |
||
5139 | + */ |
||
5140 | +#define PCIE_PHY_PLL_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x22 << 1)) |
||
5141 | +#define PCIE_PHY_PLL_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x23 << 1)) |
||
5142 | +#define PCIE_PHY_PLL_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x24 << 1)) |
||
5143 | +#define PCIE_PHY_PLL_CTRL4(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x25 << 1)) |
||
5144 | +#define PCIE_PHY_PLL_CTRL5(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x26 << 1)) |
||
5145 | +#define PCIE_PHY_PLL_CTRL6(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x27 << 1)) |
||
5146 | +#define PCIE_PHY_PLL_CTRL7(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x28 << 1)) |
||
5147 | +#define PCIE_PHY_PLL_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x29 << 1)) |
||
5148 | +#define PCIE_PHY_PLL_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2A << 1)) |
||
5149 | +#define PCIE_PHY_PLL_A_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2B << 1)) |
||
5150 | +#define PCIE_PHY_PLL_STATUS(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2C << 1)) |
||
5151 | + |
||
5152 | +#define PCIE_PHY_TX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x30 << 1)) |
||
5153 | +#define PCIE_PHY_TX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x31 << 1)) |
||
5154 | +#define PCIE_PHY_TX1_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x32 << 1)) |
||
5155 | +#define PCIE_PHY_TX1_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x33 << 1)) |
||
5156 | +#define PCIE_PHY_TX1_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x34 << 1)) |
||
5157 | +#define PCIE_PHY_TX1_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x35 << 1)) |
||
5158 | +#define PCIE_PHY_TX1_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x36 << 1)) |
||
5159 | +#define PCIE_PHY_TX1_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x37 << 1)) |
||
5160 | + |
||
5161 | +#define PCIE_PHY_TX2_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x38 << 1)) |
||
5162 | +#define PCIE_PHY_TX2_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x39 << 1)) |
||
5163 | +#define PCIE_PHY_TX2_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3B << 1)) |
||
5164 | +#define PCIE_PHY_TX2_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3C << 1)) |
||
5165 | +#define PCIE_PHY_TX2_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3D << 1)) |
||
5166 | +#define PCIE_PHY_TX2_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3E << 1)) |
||
5167 | +#define PCIE_PHY_TX2_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3F << 1)) |
||
5168 | + |
||
5169 | +#define PCIE_PHY_RX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x50 << 1)) |
||
5170 | +#define PCIE_PHY_RX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x51 << 1)) |
||
5171 | +#define PCIE_PHY_RX1_CDR(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x52 << 1)) |
||
5172 | +#define PCIE_PHY_RX1_EI(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x53 << 1)) |
||
5173 | +#define PCIE_PHY_RX1_A_CTRL(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x55 << 1)) |
||
5174 | + |
||
5175 | +/* Interrupt related stuff */ |
||
5176 | +#define PCIE_LEGACY_DISABLE 0 |
||
5177 | +#define PCIE_LEGACY_INTA 1 |
||
5178 | +#define PCIE_LEGACY_INTB 2 |
||
5179 | +#define PCIE_LEGACY_INTC 3 |
||
5180 | +#define PCIE_LEGACY_INTD 4 |
||
5181 | +#define PCIE_LEGACY_INT_MAX PCIE_LEGACY_INTD |
||
5182 | + |
||
5183 | +#define PCIE_IRQ_LOCK(lock) do { \ |
||
5184 | + unsigned long flags; \ |
||
5185 | + spin_lock_irqsave(&(lock), flags); |
||
5186 | +#define PCIE_IRQ_UNLOCK(lock) \ |
||
5187 | + spin_unlock_irqrestore(&(lock), flags); \ |
||
5188 | +} while (0) |
||
5189 | + |
||
5190 | +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) |
||
5191 | +#define IRQF_SHARED SA_SHIRQ |
||
5192 | +#endif |
||
5193 | + |
||
5194 | +#define PCIE_MSG_MSI 0x00000001 |
||
5195 | +#define PCIE_MSG_ISR 0x00000002 |
||
5196 | +#define PCIE_MSG_FIXUP 0x00000004 |
||
5197 | +#define PCIE_MSG_READ_CFG 0x00000008 |
||
5198 | +#define PCIE_MSG_WRITE_CFG 0x00000010 |
||
5199 | +#define PCIE_MSG_CFG (PCIE_MSG_READ_CFG | PCIE_MSG_WRITE_CFG) |
||
5200 | +#define PCIE_MSG_REG 0x00000020 |
||
5201 | +#define PCIE_MSG_INIT 0x00000040 |
||
5202 | +#define PCIE_MSG_ERR 0x00000080 |
||
5203 | +#define PCIE_MSG_PHY 0x00000100 |
||
5204 | +#define PCIE_MSG_ANY 0x000001ff |
||
5205 | + |
||
5206 | +#define IFX_PCIE_PORT0 0 |
||
5207 | +#define IFX_PCIE_PORT1 1 |
||
5208 | + |
||
5209 | +#ifdef CONFIG_IFX_PCIE_2ND_CORE |
||
5210 | +#define IFX_PCIE_CORE_NR 2 |
||
5211 | +#else |
||
5212 | +#define IFX_PCIE_CORE_NR 1 |
||
5213 | +#endif |
||
5214 | + |
||
5215 | +//#define IFX_PCIE_ERROR_INT |
||
5216 | + |
||
5217 | +//#define IFX_PCIE_DBG |
||
5218 | + |
||
5219 | +#if defined(IFX_PCIE_DBG) |
||
5220 | +#define IFX_PCIE_PRINT(_m, _fmt, args...) do { \ |
||
5221 | + if (g_pcie_debug_flag & (_m)) { \ |
||
5222 | + ifx_pcie_debug((_fmt), ##args); \ |
||
5223 | + } \ |
||
5224 | +} while (0) |
||
5225 | + |
||
5226 | +#define INLINE |
||
5227 | +#else |
||
5228 | +#define IFX_PCIE_PRINT(_m, _fmt, args...) \ |
||
5229 | + do {} while(0) |
||
5230 | +#define INLINE inline |
||
5231 | +#endif |
||
5232 | + |
||
5233 | +struct ifx_pci_controller { |
||
5234 | + struct pci_controller pcic; |
||
5235 | + |
||
5236 | + /* RC specific, per host bus information */ |
||
5237 | + u32 port; /* Port index, 0 -- 1st core, 1 -- 2nd core */ |
||
5238 | +}; |
||
5239 | + |
||
5240 | +typedef struct ifx_pcie_ir_irq { |
||
5241 | + const unsigned int irq; |
||
5242 | + const char name[16]; |
||
5243 | +}ifx_pcie_ir_irq_t; |
||
5244 | + |
||
5245 | +typedef struct ifx_pcie_legacy_irq{ |
||
5246 | + const u32 irq_bit; |
||
5247 | + const int irq; |
||
5248 | +}ifx_pcie_legacy_irq_t; |
||
5249 | + |
||
5250 | +typedef struct ifx_pcie_irq { |
||
5251 | + ifx_pcie_ir_irq_t ir_irq; |
||
5252 | + ifx_pcie_legacy_irq_t legacy_irq[PCIE_LEGACY_INT_MAX]; |
||
5253 | +}ifx_pcie_irq_t; |
||
5254 | + |
||
5255 | +extern u32 g_pcie_debug_flag; |
||
5256 | +extern void ifx_pcie_debug(const char *fmt, ...); |
||
5257 | +extern void pcie_phy_clock_mode_setup(int pcie_port); |
||
5258 | +extern void pcie_msi_pic_init(int pcie_port); |
||
5259 | +extern u32 ifx_pcie_bus_enum_read_hack(int where, u32 value); |
||
5260 | +extern u32 ifx_pcie_bus_enum_write_hack(int where, u32 value); |
||
5261 | + |
||
5262 | + |
||
5263 | +#include <linux/types.h> |
||
5264 | +#include <linux/delay.h> |
||
5265 | +#include <linux/gpio.h> |
||
5266 | +#include <linux/clk.h> |
||
5267 | + |
||
5268 | +#include <lantiq_soc.h> |
||
5269 | + |
||
5270 | +#define IFX_PCIE_GPIO_RESET 38 |
||
5271 | +#define IFX_REG_R32 ltq_r32 |
||
5272 | +#define IFX_REG_W32 ltq_w32 |
||
5273 | +#define CONFIG_IFX_PCIE_HW_SWAP |
||
5274 | +#define IFX_RCU_AHB_ENDIAN ((volatile u32*)(IFX_RCU + 0x004C)) |
||
5275 | +#define IFX_RCU_RST_REQ ((volatile u32*)(IFX_RCU + 0x0010)) |
||
5276 | +#define IFX_RCU_AHB_BE_PCIE_PDI 0x00000080 /* Configure PCIE PDI module in big endian*/ |
||
5277 | + |
||
5278 | +#define IFX_RCU (KSEG1 | 0x1F203000) |
||
5279 | +#define IFX_RCU_AHB_BE_PCIE_M 0x00000001 /* Configure AHB master port that connects to PCIe RC in big endian */ |
||
5280 | +#define IFX_RCU_AHB_BE_PCIE_S 0x00000010 /* Configure AHB slave port that connects to PCIe RC in little endian */ |
||
5281 | +#define IFX_RCU_AHB_BE_XBAR_M 0x00000002 /* Configure AHB master port that connects to XBAR in big endian */ |
||
5282 | +#define CONFIG_IFX_PCIE_PHY_36MHZ_MODE |
||
5283 | + |
||
5284 | +#define IFX_PMU1_MODULE_PCIE_PHY (0) |
||
5285 | +#define IFX_PMU1_MODULE_PCIE_CTRL (1) |
||
5286 | +#define IFX_PMU1_MODULE_PDI (4) |
||
5287 | +#define IFX_PMU1_MODULE_MSI (5) |
||
5288 | + |
||
5289 | +#define IFX_PMU_MODULE_PCIE_L0_CLK (31) |
||
5290 | + |
||
5291 | + |
||
5292 | +static inline void pcie_ep_gpio_rst_init(int pcie_port) |
||
5293 | +{ |
||
5294 | +} |
||
5295 | + |
||
5296 | +static inline void pcie_ahb_pmu_setup(void) |
||
5297 | +{ |
||
5298 | + struct clk *clk; |
||
5299 | + clk = clk_get_sys("ltq_pcie", "ahb"); |
||
5300 | + clk_enable(clk); |
||
5301 | + //ltq_pmu_enable(PMU_AHBM | PMU_AHBS); |
||
5302 | +} |
||
5303 | + |
||
5304 | +static inline void pcie_rcu_endian_setup(int pcie_port) |
||
5305 | +{ |
||
5306 | + u32 reg; |
||
5307 | + |
||
5308 | + reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); |
||
5309 | +#ifdef CONFIG_IFX_PCIE_HW_SWAP |
||
5310 | + reg |= IFX_RCU_AHB_BE_PCIE_M; |
||
5311 | + reg |= IFX_RCU_AHB_BE_PCIE_S; |
||
5312 | + reg &= ~IFX_RCU_AHB_BE_XBAR_M; |
||
5313 | +#else |
||
5314 | + reg |= IFX_RCU_AHB_BE_PCIE_M; |
||
5315 | + reg &= ~IFX_RCU_AHB_BE_PCIE_S; |
||
5316 | + reg &= ~IFX_RCU_AHB_BE_XBAR_M; |
||
5317 | +#endif /* CONFIG_IFX_PCIE_HW_SWAP */ |
||
5318 | + IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); |
||
5319 | + IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN)); |
||
5320 | +} |
||
5321 | + |
||
5322 | +static inline void pcie_phy_pmu_enable(int pcie_port) |
||
5323 | +{ |
||
5324 | + struct clk *clk; |
||
5325 | + clk = clk_get_sys("ltq_pcie", "phy"); |
||
5326 | + clk_enable(clk); |
||
5327 | + //ltq_pmu1_enable(1<<IFX_PMU1_MODULE_PCIE_PHY); |
||
5328 | +} |
||
5329 | + |
||
5330 | +static inline void pcie_phy_pmu_disable(int pcie_port) |
||
5331 | +{ |
||
5332 | + struct clk *clk; |
||
5333 | + clk = clk_get_sys("ltq_pcie", "phy"); |
||
5334 | + clk_disable(clk); |
||
5335 | + //ltq_pmu1_disable(1<<IFX_PMU1_MODULE_PCIE_PHY); |
||
5336 | +} |
||
5337 | + |
||
5338 | +static inline void pcie_pdi_big_endian(int pcie_port) |
||
5339 | +{ |
||
5340 | + u32 reg; |
||
5341 | + |
||
5342 | + /* SRAM2PDI endianness control. */ |
||
5343 | + reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); |
||
5344 | + /* Config AHB->PCIe and PDI endianness */ |
||
5345 | + reg |= IFX_RCU_AHB_BE_PCIE_PDI; |
||
5346 | + IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); |
||
5347 | +} |
||
5348 | + |
||
5349 | +static inline void pcie_pdi_pmu_enable(int pcie_port) |
||
5350 | +{ |
||
5351 | + struct clk *clk; |
||
5352 | + clk = clk_get_sys("ltq_pcie", "pdi"); |
||
5353 | + clk_enable(clk); |
||
5354 | + //ltq_pmu1_enable(1<<IFX_PMU1_MODULE_PDI); |
||
5355 | +} |
||
5356 | + |
||
5357 | +static inline void pcie_core_rst_assert(int pcie_port) |
||
5358 | +{ |
||
5359 | + u32 reg; |
||
5360 | + |
||
5361 | + reg = IFX_REG_R32(IFX_RCU_RST_REQ); |
||
5362 | + |
||
5363 | + /* Reset PCIe PHY & Core, bit 22, bit 26 may be affected if write it directly */ |
||
5364 | + reg |= 0x00400000; |
||
5365 | + IFX_REG_W32(reg, IFX_RCU_RST_REQ); |
||
5366 | +} |
||
5367 | + |
||
5368 | +static inline void pcie_core_rst_deassert(int pcie_port) |
||
5369 | +{ |
||
5370 | + u32 reg; |
||
5371 | + |
||
5372 | + /* Make sure one micro-second delay */ |
||
5373 | + udelay(1); |
||
5374 | + |
||
5375 | + /* Reset PCIe PHY & Core, bit 22 */ |
||
5376 | + reg = IFX_REG_R32(IFX_RCU_RST_REQ); |
||
5377 | + reg &= ~0x00400000; |
||
5378 | + IFX_REG_W32(reg, IFX_RCU_RST_REQ); |
||
5379 | +} |
||
5380 | + |
||
5381 | +static inline void pcie_phy_rst_assert(int pcie_port) |
||
5382 | +{ |
||
5383 | + u32 reg; |
||
5384 | + |
||
5385 | + reg = IFX_REG_R32(IFX_RCU_RST_REQ); |
||
5386 | + reg |= 0x00001000; /* Bit 12 */ |
||
5387 | + IFX_REG_W32(reg, IFX_RCU_RST_REQ); |
||
5388 | +} |
||
5389 | + |
||
5390 | +static inline void pcie_phy_rst_deassert(int pcie_port) |
||
5391 | +{ |
||
5392 | + u32 reg; |
||
5393 | + |
||
5394 | + /* Make sure one micro-second delay */ |
||
5395 | + udelay(1); |
||
5396 | + |
||
5397 | + reg = IFX_REG_R32(IFX_RCU_RST_REQ); |
||
5398 | + reg &= ~0x00001000; /* Bit 12 */ |
||
5399 | + IFX_REG_W32(reg, IFX_RCU_RST_REQ); |
||
5400 | +} |
||
5401 | + |
||
5402 | +static inline void pcie_device_rst_assert(int pcie_port) |
||
5403 | +{ |
||
5404 | + gpio_set_value(IFX_PCIE_GPIO_RESET, 0); |
||
5405 | + // ifx_gpio_output_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); |
||
5406 | +} |
||
5407 | + |
||
5408 | +static inline void pcie_device_rst_deassert(int pcie_port) |
||
5409 | +{ |
||
5410 | + mdelay(100); |
||
5411 | + gpio_set_value(IFX_PCIE_GPIO_RESET, 1); |
||
5412 | +// ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); |
||
5413 | +} |
||
5414 | + |
||
5415 | +static inline void pcie_core_pmu_setup(int pcie_port) |
||
5416 | +{ |
||
5417 | + struct clk *clk; |
||
5418 | + clk = clk_get_sys("ltq_pcie", "ctl"); |
||
5419 | + clk_enable(clk); |
||
5420 | + clk = clk_get_sys("ltq_pcie", "bus"); |
||
5421 | + clk_enable(clk); |
||
5422 | + |
||
5423 | + //ltq_pmu1_enable(1 << IFX_PMU1_MODULE_PCIE_CTRL); |
||
5424 | + //ltq_pmu_enable(1 << IFX_PMU_MODULE_PCIE_L0_CLK); |
||
5425 | +} |
||
5426 | + |
||
5427 | +static inline void pcie_msi_init(int pcie_port) |
||
5428 | +{ |
||
5429 | + struct clk *clk; |
||
5430 | + pcie_msi_pic_init(pcie_port); |
||
5431 | + clk = clk_get_sys("ltq_pcie", "msi"); |
||
5432 | + clk_enable(clk); |
||
5433 | + //ltq_pmu1_enable(1 << IFX_PMU1_MODULE_MSI); |
||
5434 | +} |
||
5435 | + |
||
5436 | +static inline u32 |
||
5437 | +ifx_pcie_bus_nr_deduct(u32 bus_number, int pcie_port) |
||
5438 | +{ |
||
5439 | + u32 tbus_number = bus_number; |
||
5440 | + |
||
5441 | +#ifdef CONFIG_PCI_LANTIQ |
||
5442 | + if (pcibios_host_nr() > 1) { |
||
5443 | + tbus_number -= pcibios_1st_host_bus_nr(); |
||
5444 | + } |
||
5445 | +#endif /* CONFIG_PCI_LANTIQ */ |
||
5446 | + return tbus_number; |
||
5447 | +} |
||
5448 | + |
||
5449 | +static inline u32 |
||
5450 | +ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read) |
||
5451 | +{ |
||
5452 | + struct pci_dev *pdev; |
||
5453 | + u32 tvalue = value; |
||
5454 | + |
||
5455 | + /* Sanity check */ |
||
5456 | + pdev = pci_get_slot(bus, devfn); |
||
5457 | + if (pdev == NULL) { |
||
5458 | + return tvalue; |
||
5459 | + } |
||
5460 | + |
||
5461 | + /* Only care about PCI bridge */ |
||
5462 | + if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) { |
||
5463 | + return tvalue; |
||
5464 | + } |
||
5465 | + |
||
5466 | + if (read) { /* Read hack */ |
||
5467 | + #ifdef CONFIG_PCI_LANTIQ |
||
5468 | + if (pcibios_host_nr() > 1) { |
||
5469 | + tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue); |
||
5470 | + } |
||
5471 | + #endif /* CONFIG_PCI_LANTIQ */ |
||
5472 | + } |
||
5473 | + else { /* Write hack */ |
||
5474 | + #ifdef CONFIG_PCI_LANTIQ |
||
5475 | + if (pcibios_host_nr() > 1) { |
||
5476 | + tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue); |
||
5477 | + } |
||
5478 | + #endif |
||
5479 | + } |
||
5480 | + return tvalue; |
||
5481 | +} |
||
5482 | + |
||
5483 | +#endif /* IFXMIPS_PCIE_VR9_H */ |
||
5484 | + |
||
5485 | --- a/drivers/pci/pcie/aer/Kconfig |
||
5486 | +++ b/drivers/pci/pcie/aer/Kconfig |
||
5487 | @@ -19,6 +19,7 @@ config PCIEAER |
||
5488 | config PCIE_ECRC |
||
5489 | bool "PCI Express ECRC settings control" |
||
5490 | depends on PCIEAER |
||
5491 | + default n |
||
5492 | help |
||
5493 | Used to override firmware/bios settings for PCI Express ECRC |
||
5494 | (transaction layer end-to-end CRC checking). |
||
5495 | --- a/include/linux/pci.h |
||
5496 | +++ b/include/linux/pci.h |
||
3 | office | 5497 | @@ -1300,6 +1300,8 @@ void pci_walk_bus(struct pci_bus *top, i |
1 | office | 5498 | void *userdata); |
5499 | int pci_cfg_space_size(struct pci_dev *dev); |
||
5500 | unsigned char pci_bus_max_busnr(struct pci_bus *bus); |
||
5501 | +int pcibios_host_nr(void); |
||
5502 | +int pcibios_1st_host_bus_nr(void); |
||
5503 | void pci_setup_bridge(struct pci_bus *bus); |
||
5504 | resource_size_t pcibios_window_alignment(struct pci_bus *bus, |
||
5505 | unsigned long type); |
||
5506 | --- a/include/linux/pci_ids.h |
||
5507 | +++ b/include/linux/pci_ids.h |
||
5508 | @@ -1061,6 +1061,12 @@ |
||
5509 | #define PCI_DEVICE_ID_SGI_LITHIUM 0x1002 |
||
5510 | #define PCI_DEVICE_ID_SGI_IOC4 0x100a |
||
5511 | |||
5512 | +#define PCI_VENDOR_ID_INFINEON 0x15D1 |
||
5513 | +#define PCI_DEVICE_ID_INFINEON_DANUBE 0x000F |
||
5514 | +#define PCI_DEVICE_ID_INFINEON_PCIE 0x0011 |
||
5515 | +#define PCI_VENDOR_ID_LANTIQ 0x1BEF |
||
5516 | +#define PCI_DEVICE_ID_LANTIQ_PCIE 0x0011 |
||
5517 | + |
||
5518 | #define PCI_VENDOR_ID_WINBOND 0x10ad |
||
5519 | #define PCI_DEVICE_ID_WINBOND_82C105 0x0105 |
||
5520 | #define PCI_DEVICE_ID_WINBOND_83C553 0x0565 |