OpenWrt – Blame information for rev 3
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Rev | Author | Line No. | Line |
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1 | office | 1 | /* |
2 | * ar8216.h: AR8216 switch driver |
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3 | * |
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4 | * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name> |
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5 | * |
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6 | * This program is free software; you can redistribute it and/or |
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7 | * modify it under the terms of the GNU General Public License |
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8 | * as published by the Free Software Foundation; either version 2 |
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9 | * of the License, or (at your option) any later version. |
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10 | * |
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11 | * This program is distributed in the hope that it will be useful, |
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12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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14 | * GNU General Public License for more details. |
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15 | */ |
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16 | |||
17 | #ifndef __AR8216_H |
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18 | #define __AR8216_H |
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19 | |||
20 | #define BITS(_s, _n) (((1UL << (_n)) - 1) << _s) |
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21 | |||
22 | #define AR8XXX_CAP_GIGE BIT(0) |
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23 | #define AR8XXX_CAP_MIB_COUNTERS BIT(1) |
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24 | |||
25 | #define AR8XXX_NUM_PHYS 5 |
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26 | #define AR8216_PORT_CPU 0 |
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27 | #define AR8216_NUM_PORTS 6 |
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28 | #define AR8216_NUM_VLANS 16 |
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29 | #define AR8316_NUM_VLANS 4096 |
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30 | |||
31 | /* size of the vlan table */ |
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32 | #define AR8X16_MAX_VLANS 128 |
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33 | #define AR8X16_PROBE_RETRIES 10 |
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34 | #define AR8X16_MAX_PORTS 8 |
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35 | |||
36 | #define AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS 7 |
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37 | #define AR8XXX_DEFAULT_ARL_AGE_TIME 300 |
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38 | |||
39 | /* Atheros specific MII registers */ |
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40 | #define MII_ATH_MMD_ADDR 0x0d |
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41 | #define MII_ATH_MMD_DATA 0x0e |
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42 | #define MII_ATH_DBG_ADDR 0x1d |
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43 | #define MII_ATH_DBG_DATA 0x1e |
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44 | |||
45 | #define AR8216_REG_CTRL 0x0000 |
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46 | #define AR8216_CTRL_REVISION BITS(0, 8) |
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47 | #define AR8216_CTRL_REVISION_S 0 |
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48 | #define AR8216_CTRL_VERSION BITS(8, 8) |
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49 | #define AR8216_CTRL_VERSION_S 8 |
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50 | #define AR8216_CTRL_RESET BIT(31) |
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51 | |||
52 | #define AR8216_REG_FLOOD_MASK 0x002C |
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53 | #define AR8216_FM_UNI_DEST_PORTS BITS(0, 6) |
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54 | #define AR8216_FM_MULTI_DEST_PORTS BITS(16, 6) |
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55 | #define AR8236_FM_CPU_BROADCAST_EN BIT(26) |
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56 | #define AR8236_FM_CPU_BCAST_FWD_EN BIT(25) |
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57 | |||
58 | #define AR8216_REG_GLOBAL_CTRL 0x0030 |
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59 | #define AR8216_GCTRL_MTU BITS(0, 11) |
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60 | #define AR8236_GCTRL_MTU BITS(0, 14) |
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61 | #define AR8316_GCTRL_MTU BITS(0, 14) |
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62 | |||
63 | #define AR8216_REG_VTU 0x0040 |
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64 | #define AR8216_VTU_OP BITS(0, 3) |
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65 | #define AR8216_VTU_OP_NOOP 0x0 |
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66 | #define AR8216_VTU_OP_FLUSH 0x1 |
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67 | #define AR8216_VTU_OP_LOAD 0x2 |
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68 | #define AR8216_VTU_OP_PURGE 0x3 |
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69 | #define AR8216_VTU_OP_REMOVE_PORT 0x4 |
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70 | #define AR8216_VTU_ACTIVE BIT(3) |
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71 | #define AR8216_VTU_FULL BIT(4) |
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72 | #define AR8216_VTU_PORT BITS(8, 4) |
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73 | #define AR8216_VTU_PORT_S 8 |
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74 | #define AR8216_VTU_VID BITS(16, 12) |
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75 | #define AR8216_VTU_VID_S 16 |
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76 | #define AR8216_VTU_PRIO BITS(28, 3) |
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77 | #define AR8216_VTU_PRIO_S 28 |
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78 | #define AR8216_VTU_PRIO_EN BIT(31) |
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79 | |||
80 | #define AR8216_REG_VTU_DATA 0x0044 |
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81 | #define AR8216_VTUDATA_MEMBER BITS(0, 10) |
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82 | #define AR8236_VTUDATA_MEMBER BITS(0, 7) |
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83 | #define AR8216_VTUDATA_VALID BIT(11) |
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84 | |||
85 | #define AR8216_REG_ATU_FUNC0 0x0050 |
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86 | #define AR8216_ATU_OP BITS(0, 3) |
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87 | #define AR8216_ATU_OP_NOOP 0x0 |
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88 | #define AR8216_ATU_OP_FLUSH 0x1 |
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89 | #define AR8216_ATU_OP_LOAD 0x2 |
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90 | #define AR8216_ATU_OP_PURGE 0x3 |
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91 | #define AR8216_ATU_OP_FLUSH_UNLOCKED 0x4 |
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92 | #define AR8216_ATU_OP_FLUSH_PORT 0x5 |
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93 | #define AR8216_ATU_OP_GET_NEXT 0x6 |
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94 | #define AR8216_ATU_ACTIVE BIT(3) |
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95 | #define AR8216_ATU_PORT_NUM BITS(8, 4) |
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96 | #define AR8216_ATU_PORT_NUM_S 8 |
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97 | #define AR8216_ATU_FULL_VIO BIT(12) |
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98 | #define AR8216_ATU_ADDR5 BITS(16, 8) |
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99 | #define AR8216_ATU_ADDR5_S 16 |
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100 | #define AR8216_ATU_ADDR4 BITS(24, 8) |
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101 | #define AR8216_ATU_ADDR4_S 24 |
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102 | |||
103 | #define AR8216_REG_ATU_FUNC1 0x0054 |
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104 | #define AR8216_ATU_ADDR3 BITS(0, 8) |
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105 | #define AR8216_ATU_ADDR3_S 0 |
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106 | #define AR8216_ATU_ADDR2 BITS(8, 8) |
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107 | #define AR8216_ATU_ADDR2_S 8 |
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108 | #define AR8216_ATU_ADDR1 BITS(16, 8) |
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109 | #define AR8216_ATU_ADDR1_S 16 |
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110 | #define AR8216_ATU_ADDR0 BITS(24, 8) |
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111 | #define AR8216_ATU_ADDR0_S 24 |
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112 | |||
113 | #define AR8216_REG_ATU_FUNC2 0x0058 |
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114 | #define AR8216_ATU_PORTS BITS(0, 6) |
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115 | #define AR8216_ATU_PORT0 BIT(0) |
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116 | #define AR8216_ATU_PORT1 BIT(1) |
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117 | #define AR8216_ATU_PORT2 BIT(2) |
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118 | #define AR8216_ATU_PORT3 BIT(3) |
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119 | #define AR8216_ATU_PORT4 BIT(4) |
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120 | #define AR8216_ATU_PORT5 BIT(5) |
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121 | #define AR8216_ATU_STATUS BITS(16, 4) |
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122 | #define AR8216_ATU_STATUS_S 16 |
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123 | |||
124 | #define AR8216_REG_ATU_CTRL 0x005C |
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125 | #define AR8216_ATU_CTRL_AGE_EN BIT(17) |
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126 | #define AR8216_ATU_CTRL_AGE_TIME BITS(0, 16) |
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127 | #define AR8216_ATU_CTRL_AGE_TIME_S 0 |
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128 | #define AR8236_ATU_CTRL_RES BIT(20) |
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129 | |||
130 | #define AR8216_REG_MIB_FUNC 0x0080 |
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131 | #define AR8216_MIB_TIMER BITS(0, 16) |
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132 | #define AR8216_MIB_AT_HALF_EN BIT(16) |
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133 | #define AR8216_MIB_BUSY BIT(17) |
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134 | #define AR8216_MIB_FUNC BITS(24, 3) |
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135 | #define AR8216_MIB_FUNC_S 24 |
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136 | #define AR8216_MIB_FUNC_NO_OP 0x0 |
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137 | #define AR8216_MIB_FUNC_FLUSH 0x1 |
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138 | #define AR8216_MIB_FUNC_CAPTURE 0x3 |
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139 | #define AR8236_MIB_EN BIT(30) |
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140 | |||
141 | #define AR8216_REG_GLOBAL_CPUPORT 0x0078 |
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142 | #define AR8216_GLOBAL_CPUPORT_MIRROR_PORT BITS(4, 4) |
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143 | #define AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S 4 |
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144 | |||
145 | #define AR8216_PORT_OFFSET(_i) (0x0100 * (_i + 1)) |
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146 | #define AR8216_REG_PORT_STATUS(_i) (AR8216_PORT_OFFSET(_i) + 0x0000) |
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147 | #define AR8216_PORT_STATUS_SPEED BITS(0,2) |
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148 | #define AR8216_PORT_STATUS_SPEED_S 0 |
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149 | #define AR8216_PORT_STATUS_TXMAC BIT(2) |
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150 | #define AR8216_PORT_STATUS_RXMAC BIT(3) |
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151 | #define AR8216_PORT_STATUS_TXFLOW BIT(4) |
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152 | #define AR8216_PORT_STATUS_RXFLOW BIT(5) |
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153 | #define AR8216_PORT_STATUS_DUPLEX BIT(6) |
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154 | #define AR8216_PORT_STATUS_LINK_UP BIT(8) |
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155 | #define AR8216_PORT_STATUS_LINK_AUTO BIT(9) |
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156 | #define AR8216_PORT_STATUS_LINK_PAUSE BIT(10) |
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157 | #define AR8216_PORT_STATUS_FLOW_CONTROL BIT(12) |
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158 | |||
159 | #define AR8216_REG_PORT_CTRL(_i) (AR8216_PORT_OFFSET(_i) + 0x0004) |
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160 | |||
161 | /* port forwarding state */ |
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162 | #define AR8216_PORT_CTRL_STATE BITS(0, 3) |
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163 | #define AR8216_PORT_CTRL_STATE_S 0 |
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164 | |||
165 | #define AR8216_PORT_CTRL_LEARN_LOCK BIT(7) |
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166 | |||
167 | /* egress 802.1q mode */ |
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168 | #define AR8216_PORT_CTRL_VLAN_MODE BITS(8, 2) |
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169 | #define AR8216_PORT_CTRL_VLAN_MODE_S 8 |
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170 | |||
171 | #define AR8216_PORT_CTRL_IGMP_SNOOP BIT(10) |
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172 | #define AR8216_PORT_CTRL_HEADER BIT(11) |
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173 | #define AR8216_PORT_CTRL_MAC_LOOP BIT(12) |
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174 | #define AR8216_PORT_CTRL_SINGLE_VLAN BIT(13) |
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175 | #define AR8216_PORT_CTRL_LEARN BIT(14) |
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176 | #define AR8216_PORT_CTRL_MIRROR_TX BIT(16) |
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177 | #define AR8216_PORT_CTRL_MIRROR_RX BIT(17) |
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178 | |||
179 | #define AR8216_REG_PORT_VLAN(_i) (AR8216_PORT_OFFSET(_i) + 0x0008) |
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180 | |||
181 | #define AR8216_PORT_VLAN_DEFAULT_ID BITS(0, 12) |
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182 | #define AR8216_PORT_VLAN_DEFAULT_ID_S 0 |
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183 | |||
184 | #define AR8216_PORT_VLAN_DEST_PORTS BITS(16, 9) |
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185 | #define AR8216_PORT_VLAN_DEST_PORTS_S 16 |
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186 | |||
187 | /* bit0 added to the priority field of egress frames */ |
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188 | #define AR8216_PORT_VLAN_TX_PRIO BIT(27) |
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189 | |||
190 | /* port default priority */ |
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191 | #define AR8216_PORT_VLAN_PRIORITY BITS(28, 2) |
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192 | #define AR8216_PORT_VLAN_PRIORITY_S 28 |
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193 | |||
194 | /* ingress 802.1q mode */ |
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195 | #define AR8216_PORT_VLAN_MODE BITS(30, 2) |
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196 | #define AR8216_PORT_VLAN_MODE_S 30 |
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197 | |||
198 | #define AR8216_REG_PORT_RATE(_i) (AR8216_PORT_OFFSET(_i) + 0x000c) |
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199 | #define AR8216_REG_PORT_PRIO(_i) (AR8216_PORT_OFFSET(_i) + 0x0010) |
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200 | |||
201 | #define AR8216_STATS_RXBROAD 0x00 |
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202 | #define AR8216_STATS_RXPAUSE 0x04 |
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203 | #define AR8216_STATS_RXMULTI 0x08 |
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204 | #define AR8216_STATS_RXFCSERR 0x0c |
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205 | #define AR8216_STATS_RXALIGNERR 0x10 |
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206 | #define AR8216_STATS_RXRUNT 0x14 |
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207 | #define AR8216_STATS_RXFRAGMENT 0x18 |
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208 | #define AR8216_STATS_RX64BYTE 0x1c |
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209 | #define AR8216_STATS_RX128BYTE 0x20 |
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210 | #define AR8216_STATS_RX256BYTE 0x24 |
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211 | #define AR8216_STATS_RX512BYTE 0x28 |
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212 | #define AR8216_STATS_RX1024BYTE 0x2c |
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213 | #define AR8216_STATS_RXMAXBYTE 0x30 |
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214 | #define AR8216_STATS_RXTOOLONG 0x34 |
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215 | #define AR8216_STATS_RXGOODBYTE 0x38 |
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216 | #define AR8216_STATS_RXBADBYTE 0x40 |
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217 | #define AR8216_STATS_RXOVERFLOW 0x48 |
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218 | #define AR8216_STATS_FILTERED 0x4c |
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219 | #define AR8216_STATS_TXBROAD 0x50 |
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220 | #define AR8216_STATS_TXPAUSE 0x54 |
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221 | #define AR8216_STATS_TXMULTI 0x58 |
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222 | #define AR8216_STATS_TXUNDERRUN 0x5c |
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223 | #define AR8216_STATS_TX64BYTE 0x60 |
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224 | #define AR8216_STATS_TX128BYTE 0x64 |
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225 | #define AR8216_STATS_TX256BYTE 0x68 |
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226 | #define AR8216_STATS_TX512BYTE 0x6c |
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227 | #define AR8216_STATS_TX1024BYTE 0x70 |
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228 | #define AR8216_STATS_TXMAXBYTE 0x74 |
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229 | #define AR8216_STATS_TXOVERSIZE 0x78 |
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230 | #define AR8216_STATS_TXBYTE 0x7c |
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231 | #define AR8216_STATS_TXCOLLISION 0x84 |
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232 | #define AR8216_STATS_TXABORTCOL 0x88 |
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233 | #define AR8216_STATS_TXMULTICOL 0x8c |
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234 | #define AR8216_STATS_TXSINGLECOL 0x90 |
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235 | #define AR8216_STATS_TXEXCDEFER 0x94 |
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236 | #define AR8216_STATS_TXDEFER 0x98 |
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237 | #define AR8216_STATS_TXLATECOL 0x9c |
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238 | |||
239 | #define AR8236_REG_PORT_VLAN(_i) (AR8216_PORT_OFFSET((_i)) + 0x0008) |
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240 | #define AR8236_PORT_VLAN_DEFAULT_ID BITS(16, 12) |
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241 | #define AR8236_PORT_VLAN_DEFAULT_ID_S 16 |
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242 | #define AR8236_PORT_VLAN_PRIORITY BITS(29, 3) |
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243 | #define AR8236_PORT_VLAN_PRIORITY_S 28 |
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244 | |||
245 | #define AR8236_REG_PORT_VLAN2(_i) (AR8216_PORT_OFFSET((_i)) + 0x000c) |
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246 | #define AR8236_PORT_VLAN2_MEMBER BITS(16, 7) |
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247 | #define AR8236_PORT_VLAN2_MEMBER_S 16 |
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248 | #define AR8236_PORT_VLAN2_TX_PRIO BIT(23) |
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249 | #define AR8236_PORT_VLAN2_VLAN_MODE BITS(30, 2) |
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250 | #define AR8236_PORT_VLAN2_VLAN_MODE_S 30 |
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251 | |||
252 | #define AR8236_STATS_RXBROAD 0x00 |
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253 | #define AR8236_STATS_RXPAUSE 0x04 |
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254 | #define AR8236_STATS_RXMULTI 0x08 |
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255 | #define AR8236_STATS_RXFCSERR 0x0c |
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256 | #define AR8236_STATS_RXALIGNERR 0x10 |
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257 | #define AR8236_STATS_RXRUNT 0x14 |
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258 | #define AR8236_STATS_RXFRAGMENT 0x18 |
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259 | #define AR8236_STATS_RX64BYTE 0x1c |
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260 | #define AR8236_STATS_RX128BYTE 0x20 |
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261 | #define AR8236_STATS_RX256BYTE 0x24 |
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262 | #define AR8236_STATS_RX512BYTE 0x28 |
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263 | #define AR8236_STATS_RX1024BYTE 0x2c |
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264 | #define AR8236_STATS_RX1518BYTE 0x30 |
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265 | #define AR8236_STATS_RXMAXBYTE 0x34 |
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266 | #define AR8236_STATS_RXTOOLONG 0x38 |
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267 | #define AR8236_STATS_RXGOODBYTE 0x3c |
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268 | #define AR8236_STATS_RXBADBYTE 0x44 |
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269 | #define AR8236_STATS_RXOVERFLOW 0x4c |
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270 | #define AR8236_STATS_FILTERED 0x50 |
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271 | #define AR8236_STATS_TXBROAD 0x54 |
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272 | #define AR8236_STATS_TXPAUSE 0x58 |
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273 | #define AR8236_STATS_TXMULTI 0x5c |
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274 | #define AR8236_STATS_TXUNDERRUN 0x60 |
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275 | #define AR8236_STATS_TX64BYTE 0x64 |
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276 | #define AR8236_STATS_TX128BYTE 0x68 |
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277 | #define AR8236_STATS_TX256BYTE 0x6c |
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278 | #define AR8236_STATS_TX512BYTE 0x70 |
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279 | #define AR8236_STATS_TX1024BYTE 0x74 |
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280 | #define AR8236_STATS_TX1518BYTE 0x78 |
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281 | #define AR8236_STATS_TXMAXBYTE 0x7c |
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282 | #define AR8236_STATS_TXOVERSIZE 0x80 |
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283 | #define AR8236_STATS_TXBYTE 0x84 |
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284 | #define AR8236_STATS_TXCOLLISION 0x8c |
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285 | #define AR8236_STATS_TXABORTCOL 0x90 |
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286 | #define AR8236_STATS_TXMULTICOL 0x94 |
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287 | #define AR8236_STATS_TXSINGLECOL 0x98 |
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288 | #define AR8236_STATS_TXEXCDEFER 0x9c |
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289 | #define AR8236_STATS_TXDEFER 0xa0 |
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290 | #define AR8236_STATS_TXLATECOL 0xa4 |
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291 | |||
292 | #define AR8316_REG_POSTRIP 0x0008 |
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293 | #define AR8316_POSTRIP_MAC0_GMII_EN BIT(0) |
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294 | #define AR8316_POSTRIP_MAC0_RGMII_EN BIT(1) |
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295 | #define AR8316_POSTRIP_PHY4_GMII_EN BIT(2) |
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296 | #define AR8316_POSTRIP_PHY4_RGMII_EN BIT(3) |
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297 | #define AR8316_POSTRIP_MAC0_MAC_MODE BIT(4) |
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298 | #define AR8316_POSTRIP_RTL_MODE BIT(5) |
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299 | #define AR8316_POSTRIP_RGMII_RXCLK_DELAY_EN BIT(6) |
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300 | #define AR8316_POSTRIP_RGMII_TXCLK_DELAY_EN BIT(7) |
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301 | #define AR8316_POSTRIP_SERDES_EN BIT(8) |
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302 | #define AR8316_POSTRIP_SEL_ANA_RST BIT(9) |
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303 | #define AR8316_POSTRIP_GATE_25M_EN BIT(10) |
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304 | #define AR8316_POSTRIP_SEL_CLK25M BIT(11) |
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305 | #define AR8316_POSTRIP_HIB_PULSE_HW BIT(12) |
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306 | #define AR8316_POSTRIP_DBG_MODE_I BIT(13) |
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307 | #define AR8316_POSTRIP_MAC5_MAC_MODE BIT(14) |
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308 | #define AR8316_POSTRIP_MAC5_PHY_MODE BIT(15) |
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309 | #define AR8316_POSTRIP_POWER_DOWN_HW BIT(16) |
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310 | #define AR8316_POSTRIP_LPW_STATE_EN BIT(17) |
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311 | #define AR8316_POSTRIP_MAN_EN BIT(18) |
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312 | #define AR8316_POSTRIP_PHY_PLL_ON BIT(19) |
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313 | #define AR8316_POSTRIP_LPW_EXIT BIT(20) |
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314 | #define AR8316_POSTRIP_TXDELAY_S0 BIT(21) |
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315 | #define AR8316_POSTRIP_TXDELAY_S1 BIT(22) |
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316 | #define AR8316_POSTRIP_RXDELAY_S0 BIT(23) |
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317 | #define AR8316_POSTRIP_LED_OPEN_EN BIT(24) |
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318 | #define AR8316_POSTRIP_SPI_EN BIT(25) |
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319 | #define AR8316_POSTRIP_RXDELAY_S1 BIT(26) |
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320 | #define AR8316_POSTRIP_POWER_ON_SEL BIT(31) |
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321 | |||
322 | /* port speed */ |
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323 | enum { |
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324 | AR8216_PORT_SPEED_10M = 0, |
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325 | AR8216_PORT_SPEED_100M = 1, |
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326 | AR8216_PORT_SPEED_1000M = 2, |
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327 | AR8216_PORT_SPEED_ERR = 3, |
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328 | }; |
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329 | |||
330 | /* ingress 802.1q mode */ |
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331 | enum { |
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332 | AR8216_IN_PORT_ONLY = 0, |
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333 | AR8216_IN_PORT_FALLBACK = 1, |
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334 | AR8216_IN_VLAN_ONLY = 2, |
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335 | AR8216_IN_SECURE = 3 |
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336 | }; |
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337 | |||
338 | /* egress 802.1q mode */ |
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339 | enum { |
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340 | AR8216_OUT_KEEP = 0, |
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341 | AR8216_OUT_STRIP_VLAN = 1, |
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342 | AR8216_OUT_ADD_VLAN = 2 |
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343 | }; |
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344 | |||
345 | /* port forwarding state */ |
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346 | enum { |
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347 | AR8216_PORT_STATE_DISABLED = 0, |
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348 | AR8216_PORT_STATE_BLOCK = 1, |
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349 | AR8216_PORT_STATE_LISTEN = 2, |
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350 | AR8216_PORT_STATE_LEARN = 3, |
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351 | AR8216_PORT_STATE_FORWARD = 4 |
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352 | }; |
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353 | |||
354 | enum { |
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355 | AR8XXX_VER_AR8216 = 0x01, |
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356 | AR8XXX_VER_AR8236 = 0x03, |
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357 | AR8XXX_VER_AR8316 = 0x10, |
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358 | AR8XXX_VER_AR8327 = 0x12, |
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359 | AR8XXX_VER_AR8337 = 0x13, |
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360 | }; |
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361 | |||
362 | #define AR8XXX_NUM_ARL_RECORDS 100 |
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363 | |||
364 | enum arl_op { |
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365 | AR8XXX_ARL_INITIALIZE, |
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366 | AR8XXX_ARL_GET_NEXT |
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367 | }; |
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368 | |||
369 | struct arl_entry { |
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3 | office | 370 | u8 port; |
1 | office | 371 | u8 mac[6]; |
372 | }; |
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373 | |||
374 | struct ar8xxx_priv; |
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375 | |||
376 | struct ar8xxx_mib_desc { |
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377 | unsigned int size; |
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378 | unsigned int offset; |
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379 | const char *name; |
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380 | }; |
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381 | |||
382 | struct ar8xxx_chip { |
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383 | unsigned long caps; |
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384 | bool config_at_probe; |
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385 | bool mii_lo_first; |
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386 | |||
387 | /* parameters to calculate REG_PORT_STATS_BASE */ |
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388 | unsigned reg_port_stats_start; |
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389 | unsigned reg_port_stats_length; |
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390 | |||
391 | unsigned reg_arl_ctrl; |
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392 | |||
393 | int (*hw_init)(struct ar8xxx_priv *priv); |
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394 | void (*cleanup)(struct ar8xxx_priv *priv); |
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395 | |||
396 | const char *name; |
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397 | int vlans; |
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398 | int ports; |
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399 | const struct switch_dev_ops *swops; |
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400 | |||
401 | void (*init_globals)(struct ar8xxx_priv *priv); |
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402 | void (*init_port)(struct ar8xxx_priv *priv, int port); |
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403 | void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 members); |
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404 | u32 (*read_port_status)(struct ar8xxx_priv *priv, int port); |
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405 | u32 (*read_port_eee_status)(struct ar8xxx_priv *priv, int port); |
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406 | int (*atu_flush)(struct ar8xxx_priv *priv); |
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407 | int (*atu_flush_port)(struct ar8xxx_priv *priv, int port); |
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408 | void (*vtu_flush)(struct ar8xxx_priv *priv); |
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409 | void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask); |
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410 | void (*phy_fixup)(struct ar8xxx_priv *priv, int phy); |
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411 | void (*set_mirror_regs)(struct ar8xxx_priv *priv); |
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412 | void (*get_arl_entry)(struct ar8xxx_priv *priv, struct arl_entry *a, |
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413 | u32 *status, enum arl_op op); |
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414 | int (*sw_hw_apply)(struct switch_dev *dev); |
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415 | |||
416 | const struct ar8xxx_mib_desc *mib_decs; |
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417 | unsigned num_mibs; |
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418 | unsigned mib_func; |
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419 | }; |
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420 | |||
421 | struct ar8xxx_priv { |
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422 | struct switch_dev dev; |
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423 | struct mii_bus *mii_bus; |
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424 | struct phy_device *phy; |
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425 | |||
426 | int (*get_port_link)(unsigned port); |
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427 | |||
428 | const struct net_device_ops *ndo_old; |
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429 | struct net_device_ops ndo; |
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430 | struct mutex reg_mutex; |
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431 | u8 chip_ver; |
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432 | u8 chip_rev; |
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433 | const struct ar8xxx_chip *chip; |
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434 | void *chip_data; |
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435 | bool initialized; |
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436 | bool port4_phy; |
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437 | char buf[2048]; |
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438 | struct arl_entry arl_table[AR8XXX_NUM_ARL_RECORDS]; |
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439 | char arl_buf[AR8XXX_NUM_ARL_RECORDS * 32 + 256]; |
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440 | bool link_up[AR8X16_MAX_PORTS]; |
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441 | |||
442 | bool init; |
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443 | |||
444 | struct mutex mib_lock; |
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445 | struct delayed_work mib_work; |
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446 | int mib_next_port; |
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447 | u64 *mib_stats; |
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448 | |||
449 | struct list_head list; |
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450 | unsigned int use_count; |
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451 | |||
452 | /* all fields below are cleared on reset */ |
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453 | bool vlan; |
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454 | u16 vlan_id[AR8X16_MAX_VLANS]; |
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455 | u8 vlan_table[AR8X16_MAX_VLANS]; |
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456 | u8 vlan_tagged; |
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457 | u16 pvid[AR8X16_MAX_PORTS]; |
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458 | int arl_age_time; |
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459 | |||
460 | /* mirroring */ |
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461 | bool mirror_rx; |
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462 | bool mirror_tx; |
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463 | int source_port; |
||
464 | int monitor_port; |
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465 | u8 port_vlan_prio[AR8X16_MAX_PORTS]; |
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466 | }; |
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467 | |||
468 | u32 |
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469 | ar8xxx_mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum); |
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470 | void |
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471 | ar8xxx_mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val); |
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472 | u32 |
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473 | ar8xxx_read(struct ar8xxx_priv *priv, int reg); |
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474 | void |
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475 | ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val); |
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476 | u32 |
||
477 | ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val); |
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478 | |||
479 | void |
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480 | ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr, |
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481 | u16 dbg_addr, u16 dbg_data); |
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482 | void |
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483 | ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg, u16 data); |
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484 | u16 |
||
485 | ar8xxx_phy_mmd_read(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg); |
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486 | void |
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487 | ar8xxx_phy_init(struct ar8xxx_priv *priv); |
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488 | int |
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489 | ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr, |
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490 | struct switch_val *val); |
||
491 | int |
||
492 | ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr, |
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493 | struct switch_val *val); |
||
494 | int |
||
495 | ar8xxx_sw_set_reset_mibs(struct switch_dev *dev, |
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496 | const struct switch_attr *attr, |
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497 | struct switch_val *val); |
||
498 | int |
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499 | ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev, |
||
500 | const struct switch_attr *attr, |
||
501 | struct switch_val *val); |
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502 | int |
||
503 | ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev, |
||
504 | const struct switch_attr *attr, |
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505 | struct switch_val *val); |
||
506 | int |
||
507 | ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev, |
||
508 | const struct switch_attr *attr, |
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509 | struct switch_val *val); |
||
510 | int |
||
511 | ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev, |
||
512 | const struct switch_attr *attr, |
||
513 | struct switch_val *val); |
||
514 | int |
||
515 | ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev, |
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516 | const struct switch_attr *attr, |
||
517 | struct switch_val *val); |
||
518 | int |
||
519 | ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev, |
||
520 | const struct switch_attr *attr, |
||
521 | struct switch_val *val); |
||
522 | int |
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523 | ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev, |
||
524 | const struct switch_attr *attr, |
||
525 | struct switch_val *val); |
||
526 | int |
||
527 | ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev, |
||
528 | const struct switch_attr *attr, |
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529 | struct switch_val *val); |
||
530 | int |
||
531 | ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan); |
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532 | int |
||
533 | ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan); |
||
534 | int |
||
535 | ar8xxx_sw_hw_apply(struct switch_dev *dev); |
||
536 | int |
||
537 | ar8xxx_sw_reset_switch(struct switch_dev *dev); |
||
538 | int |
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539 | ar8xxx_sw_get_port_link(struct switch_dev *dev, int port, |
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540 | struct switch_port_link *link); |
||
541 | int |
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542 | ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev, |
||
543 | const struct switch_attr *attr, |
||
544 | struct switch_val *val); |
||
545 | int |
||
546 | ar8xxx_sw_get_port_mib(struct switch_dev *dev, |
||
547 | const struct switch_attr *attr, |
||
548 | struct switch_val *val); |
||
549 | int |
||
550 | ar8xxx_sw_get_arl_age_time(struct switch_dev *dev, |
||
551 | const struct switch_attr *attr, |
||
552 | struct switch_val *val); |
||
553 | int |
||
554 | ar8xxx_sw_set_arl_age_time(struct switch_dev *dev, |
||
555 | const struct switch_attr *attr, |
||
556 | struct switch_val *val); |
||
557 | int |
||
558 | ar8xxx_sw_get_arl_table(struct switch_dev *dev, |
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559 | const struct switch_attr *attr, |
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560 | struct switch_val *val); |
||
561 | int |
||
562 | ar8xxx_sw_set_flush_arl_table(struct switch_dev *dev, |
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563 | const struct switch_attr *attr, |
||
564 | struct switch_val *val); |
||
565 | int |
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566 | ar8xxx_sw_set_flush_port_arl_table(struct switch_dev *dev, |
||
567 | const struct switch_attr *attr, |
||
568 | struct switch_val *val); |
||
569 | int |
||
570 | ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val); |
||
571 | |||
572 | static inline struct ar8xxx_priv * |
||
573 | swdev_to_ar8xxx(struct switch_dev *swdev) |
||
574 | { |
||
575 | return container_of(swdev, struct ar8xxx_priv, dev); |
||
576 | } |
||
577 | |||
578 | static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv) |
||
579 | { |
||
580 | return priv->chip->caps & AR8XXX_CAP_GIGE; |
||
581 | } |
||
582 | |||
583 | static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv) |
||
584 | { |
||
585 | return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS; |
||
586 | } |
||
587 | |||
588 | static inline bool chip_is_ar8216(struct ar8xxx_priv *priv) |
||
589 | { |
||
590 | return priv->chip_ver == AR8XXX_VER_AR8216; |
||
591 | } |
||
592 | |||
593 | static inline bool chip_is_ar8236(struct ar8xxx_priv *priv) |
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594 | { |
||
595 | return priv->chip_ver == AR8XXX_VER_AR8236; |
||
596 | } |
||
597 | |||
598 | static inline bool chip_is_ar8316(struct ar8xxx_priv *priv) |
||
599 | { |
||
600 | return priv->chip_ver == AR8XXX_VER_AR8316; |
||
601 | } |
||
602 | |||
603 | static inline bool chip_is_ar8327(struct ar8xxx_priv *priv) |
||
604 | { |
||
605 | return priv->chip_ver == AR8XXX_VER_AR8327; |
||
606 | } |
||
607 | |||
608 | static inline bool chip_is_ar8337(struct ar8xxx_priv *priv) |
||
609 | { |
||
610 | return priv->chip_ver == AR8XXX_VER_AR8337; |
||
611 | } |
||
612 | |||
613 | static inline void |
||
614 | ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val) |
||
615 | { |
||
616 | ar8xxx_rmw(priv, reg, 0, val); |
||
617 | } |
||
618 | |||
619 | static inline void |
||
620 | ar8xxx_reg_clear(struct ar8xxx_priv *priv, int reg, u32 val) |
||
621 | { |
||
622 | ar8xxx_rmw(priv, reg, val, 0); |
||
623 | } |
||
624 | |||
625 | static inline void |
||
626 | split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page) |
||
627 | { |
||
628 | regaddr >>= 1; |
||
629 | *r1 = regaddr & 0x1e; |
||
630 | |||
631 | regaddr >>= 5; |
||
632 | *r2 = regaddr & 0x7; |
||
633 | |||
634 | regaddr >>= 3; |
||
635 | *page = regaddr & 0x1ff; |
||
636 | } |
||
637 | |||
638 | static inline void |
||
639 | wait_for_page_switch(void) |
||
640 | { |
||
641 | udelay(5); |
||
642 | } |
||
643 | |||
644 | #endif |