OpenWrt – Blame information for rev 3
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Rev | Author | Line No. | Line |
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1 | office | 1 | --- a/arch/arm/mach-cns3xxx/core.c |
2 | +++ b/arch/arm/mach-cns3xxx/core.c |
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3 | @@ -138,6 +138,7 @@ static int cns3xxx_set_oneshot(struct cl |
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4 | |||
5 | /* period set, and timer enabled in 'next_event' hook */ |
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6 | ctrl |= (1 << 2) | (1 << 9); |
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7 | + writel(0, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); |
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8 | writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); |
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9 | return 0; |
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10 | } |
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11 | @@ -148,7 +149,7 @@ static int cns3xxx_set_periodic(struct c |
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12 | int pclk = cns3xxx_cpu_clock() / 8; |
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13 | int reload; |
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14 | |||
15 | - reload = pclk * 20 / (3 * HZ) * 0x25000; |
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16 | + reload = pclk * 1000000 / HZ; |
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17 | writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); |
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18 | ctrl |= (1 << 0) | (1 << 2) | (1 << 9); |
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19 | writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); |
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3 | office | 20 | @@ -175,7 +176,7 @@ static struct clock_event_device cns3xxx |
1 | office | 21 | .set_state_oneshot = cns3xxx_set_oneshot, |
22 | .tick_resume = cns3xxx_shutdown, |
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23 | .set_next_event = cns3xxx_timer_set_next_event, |
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24 | - .rating = 350, |
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25 | + .rating = 300, |
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3 | office | 26 | .cpumask = cpu_all_mask, |
1 | office | 27 | }; |
28 | |||
29 | @@ -220,6 +221,32 @@ static void __init cns3xxx_init_twd(void |
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30 | twd_local_timer_register(&cns3xx_twd_local_timer); |
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31 | } |
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32 | |||
33 | +static u64 cns3xxx_get_cycles(struct clocksource *cs) |
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34 | +{ |
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35 | + u64 val; |
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36 | + |
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37 | + val = readl(cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET); |
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38 | + val &= 0xffff; |
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39 | + |
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40 | + return ((val << 32) | readl(cns3xxx_tmr1 + TIMER_FREERUN_OFFSET)); |
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41 | +} |
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42 | + |
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43 | +static struct clocksource clocksource_cns3xxx = { |
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44 | + .name = "freerun", |
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45 | + .rating = 200, |
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46 | + .read = cns3xxx_get_cycles, |
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47 | + .mask = CLOCKSOURCE_MASK(48), |
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48 | + .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
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49 | +}; |
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50 | + |
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51 | +static void __init cns3xxx_clocksource_init(void) |
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52 | +{ |
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53 | + /* Reset the FreeRunning counter */ |
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54 | + writel((1 << 16), cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET); |
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55 | + |
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56 | + clocksource_register_khz(&clocksource_cns3xxx, 100); |
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57 | +} |
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58 | + |
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59 | /* |
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60 | * Set up the clock source and clock events devices |
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61 | */ |
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62 | @@ -237,13 +264,12 @@ static void __init __cns3xxx_timer_init( |
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63 | /* stop free running timer3 */ |
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64 | writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET); |
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65 | |||
66 | - /* timer1 */ |
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67 | - writel(0x5C800, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET); |
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68 | - writel(0x5C800, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); |
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69 | - |
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70 | writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V1_OFFSET); |
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71 | writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V2_OFFSET); |
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72 | |||
73 | + val = (cns3xxx_cpu_clock() >> 3) * 1000000 / HZ; |
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74 | + writel(val, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET); |
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75 | + |
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76 | /* mask irq, non-mask timer1 overflow */ |
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77 | irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); |
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78 | irq_mask &= ~(1 << 2); |
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79 | @@ -255,23 +281,9 @@ static void __init __cns3xxx_timer_init( |
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80 | val |= (1 << 9); |
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81 | writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); |
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82 | |||
83 | - /* timer2 */ |
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84 | - writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V1_OFFSET); |
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85 | - writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V2_OFFSET); |
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86 | - |
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87 | - /* mask irq */ |
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88 | - irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); |
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89 | - irq_mask |= ((1 << 3) | (1 << 4) | (1 << 5)); |
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90 | - writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); |
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91 | - |
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92 | - /* down counter */ |
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93 | - val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); |
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94 | - val |= (1 << 10); |
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95 | - writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); |
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96 | - |
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97 | - /* Make irqs happen for the system timer */ |
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98 | setup_irq(timer_irq, &cns3xxx_timer_irq); |
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99 | |||
100 | + cns3xxx_clocksource_init(); |
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101 | cns3xxx_clockevents_init(timer_irq); |
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102 | cns3xxx_init_twd(); |
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103 | } |