OpenWrt – Blame information for rev 3
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Rev | Author | Line No. | Line |
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1 | office | 1 | /* |
2 | * Atheros AR71xx built-in ethernet mac driver |
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3 | * |
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4 | * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> |
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5 | * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> |
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6 | * |
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7 | * Based on Atheros' AG7100 driver |
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8 | * |
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9 | * This program is free software; you can redistribute it and/or modify it |
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10 | * under the terms of the GNU General Public License version 2 as published |
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11 | * by the Free Software Foundation. |
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12 | */ |
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13 | |||
14 | #include "ag71xx.h" |
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15 | |||
16 | #define AG71XX_DEFAULT_MSG_ENABLE \ |
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17 | (NETIF_MSG_DRV \ |
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18 | | NETIF_MSG_PROBE \ |
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19 | | NETIF_MSG_LINK \ |
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20 | | NETIF_MSG_TIMER \ |
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21 | | NETIF_MSG_IFDOWN \ |
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22 | | NETIF_MSG_IFUP \ |
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23 | | NETIF_MSG_RX_ERR \ |
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24 | | NETIF_MSG_TX_ERR) |
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25 | |||
26 | static int ag71xx_msg_level = -1; |
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27 | |||
28 | module_param_named(msg_level, ag71xx_msg_level, int, 0); |
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29 | MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); |
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30 | |||
31 | #define ETH_SWITCH_HEADER_LEN 2 |
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32 | |||
33 | static int ag71xx_tx_packets(struct ag71xx *ag, bool flush); |
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34 | |||
35 | static inline unsigned int ag71xx_max_frame_len(unsigned int mtu) |
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36 | { |
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37 | return ETH_SWITCH_HEADER_LEN + ETH_HLEN + VLAN_HLEN + mtu + ETH_FCS_LEN; |
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38 | } |
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39 | |||
40 | static void ag71xx_dump_dma_regs(struct ag71xx *ag) |
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41 | { |
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42 | DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n", |
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43 | ag->dev->name, |
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44 | ag71xx_rr(ag, AG71XX_REG_TX_CTRL), |
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45 | ag71xx_rr(ag, AG71XX_REG_TX_DESC), |
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46 | ag71xx_rr(ag, AG71XX_REG_TX_STATUS)); |
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47 | |||
48 | DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n", |
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49 | ag->dev->name, |
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50 | ag71xx_rr(ag, AG71XX_REG_RX_CTRL), |
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51 | ag71xx_rr(ag, AG71XX_REG_RX_DESC), |
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52 | ag71xx_rr(ag, AG71XX_REG_RX_STATUS)); |
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53 | } |
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54 | |||
55 | static void ag71xx_dump_regs(struct ag71xx *ag) |
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56 | { |
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57 | DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n", |
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58 | ag->dev->name, |
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59 | ag71xx_rr(ag, AG71XX_REG_MAC_CFG1), |
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60 | ag71xx_rr(ag, AG71XX_REG_MAC_CFG2), |
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61 | ag71xx_rr(ag, AG71XX_REG_MAC_IPG), |
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62 | ag71xx_rr(ag, AG71XX_REG_MAC_HDX), |
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63 | ag71xx_rr(ag, AG71XX_REG_MAC_MFL)); |
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64 | DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n", |
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65 | ag->dev->name, |
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66 | ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL), |
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67 | ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1), |
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68 | ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2)); |
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69 | DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n", |
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70 | ag->dev->name, |
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71 | ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0), |
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72 | ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1), |
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73 | ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2)); |
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74 | DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n", |
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75 | ag->dev->name, |
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76 | ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3), |
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77 | ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4), |
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78 | ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5)); |
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79 | } |
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80 | |||
81 | static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr) |
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82 | { |
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83 | DBG("%s: %s intr=%08x %s%s%s%s%s%s\n", |
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84 | ag->dev->name, label, intr, |
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85 | (intr & AG71XX_INT_TX_PS) ? "TXPS " : "", |
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86 | (intr & AG71XX_INT_TX_UR) ? "TXUR " : "", |
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87 | (intr & AG71XX_INT_TX_BE) ? "TXBE " : "", |
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88 | (intr & AG71XX_INT_RX_PR) ? "RXPR " : "", |
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89 | (intr & AG71XX_INT_RX_OF) ? "RXOF " : "", |
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90 | (intr & AG71XX_INT_RX_BE) ? "RXBE " : ""); |
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91 | } |
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92 | |||
93 | static void ag71xx_ring_tx_clean(struct ag71xx *ag) |
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94 | { |
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95 | struct ag71xx_ring *ring = &ag->tx_ring; |
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96 | struct net_device *dev = ag->dev; |
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97 | int ring_mask = BIT(ring->order) - 1; |
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98 | u32 bytes_compl = 0, pkts_compl = 0; |
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99 | |||
100 | while (ring->curr != ring->dirty) { |
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101 | struct ag71xx_desc *desc; |
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102 | u32 i = ring->dirty & ring_mask; |
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103 | |||
104 | desc = ag71xx_ring_desc(ring, i); |
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105 | if (!ag71xx_desc_empty(desc)) { |
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106 | desc->ctrl = 0; |
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107 | dev->stats.tx_errors++; |
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108 | } |
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109 | |||
110 | if (ring->buf[i].skb) { |
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111 | bytes_compl += ring->buf[i].len; |
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112 | pkts_compl++; |
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113 | dev_kfree_skb_any(ring->buf[i].skb); |
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114 | } |
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115 | ring->buf[i].skb = NULL; |
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116 | ring->dirty++; |
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117 | } |
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118 | |||
119 | /* flush descriptors */ |
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120 | wmb(); |
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121 | |||
122 | netdev_completed_queue(dev, pkts_compl, bytes_compl); |
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123 | } |
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124 | |||
125 | static void ag71xx_ring_tx_init(struct ag71xx *ag) |
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126 | { |
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127 | struct ag71xx_ring *ring = &ag->tx_ring; |
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128 | int ring_size = BIT(ring->order); |
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129 | int ring_mask = ring_size - 1; |
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130 | int i; |
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131 | |||
132 | for (i = 0; i < ring_size; i++) { |
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133 | struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i); |
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134 | |||
135 | desc->next = (u32) (ring->descs_dma + |
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136 | AG71XX_DESC_SIZE * ((i + 1) & ring_mask)); |
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137 | |||
138 | desc->ctrl = DESC_EMPTY; |
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139 | ring->buf[i].skb = NULL; |
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140 | } |
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141 | |||
142 | /* flush descriptors */ |
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143 | wmb(); |
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144 | |||
145 | ring->curr = 0; |
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146 | ring->dirty = 0; |
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147 | netdev_reset_queue(ag->dev); |
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148 | } |
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149 | |||
150 | static void ag71xx_ring_rx_clean(struct ag71xx *ag) |
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151 | { |
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152 | struct ag71xx_ring *ring = &ag->rx_ring; |
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153 | int ring_size = BIT(ring->order); |
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154 | int i; |
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155 | |||
156 | if (!ring->buf) |
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157 | return; |
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158 | |||
159 | for (i = 0; i < ring_size; i++) |
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160 | if (ring->buf[i].rx_buf) { |
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161 | dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr, |
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162 | ag->rx_buf_size, DMA_FROM_DEVICE); |
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163 | skb_free_frag(ring->buf[i].rx_buf); |
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164 | } |
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165 | } |
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166 | |||
167 | static int ag71xx_buffer_offset(struct ag71xx *ag) |
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168 | { |
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169 | int offset = NET_SKB_PAD; |
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170 | |||
171 | /* |
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172 | * On AR71xx/AR91xx packets must be 4-byte aligned. |
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173 | * |
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174 | * When using builtin AR8216 support, hardware adds a 2-byte header, |
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175 | * so we don't need any extra alignment in that case. |
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176 | */ |
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177 | if (!ag71xx_get_pdata(ag)->is_ar724x || ag71xx_has_ar8216(ag)) |
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178 | return offset; |
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179 | |||
180 | return offset + NET_IP_ALIGN; |
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181 | } |
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182 | |||
183 | static int ag71xx_buffer_size(struct ag71xx *ag) |
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184 | { |
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185 | return ag->rx_buf_size + |
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186 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); |
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187 | } |
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188 | |||
189 | static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf, |
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190 | int offset, |
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191 | void *(*alloc)(unsigned int size)) |
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192 | { |
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193 | struct ag71xx_ring *ring = &ag->rx_ring; |
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194 | struct ag71xx_desc *desc = ag71xx_ring_desc(ring, buf - &ring->buf[0]); |
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195 | void *data; |
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196 | |||
197 | data = alloc(ag71xx_buffer_size(ag)); |
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198 | if (!data) |
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199 | return false; |
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200 | |||
201 | buf->rx_buf = data; |
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202 | buf->dma_addr = dma_map_single(&ag->dev->dev, data, ag->rx_buf_size, |
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203 | DMA_FROM_DEVICE); |
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204 | desc->data = (u32) buf->dma_addr + offset; |
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205 | return true; |
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206 | } |
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207 | |||
208 | static int ag71xx_ring_rx_init(struct ag71xx *ag) |
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209 | { |
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210 | struct ag71xx_ring *ring = &ag->rx_ring; |
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211 | int ring_size = BIT(ring->order); |
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212 | int ring_mask = BIT(ring->order) - 1; |
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213 | unsigned int i; |
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214 | int ret; |
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215 | int offset = ag71xx_buffer_offset(ag); |
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216 | |||
217 | ret = 0; |
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218 | for (i = 0; i < ring_size; i++) { |
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219 | struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i); |
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220 | |||
221 | desc->next = (u32) (ring->descs_dma + |
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222 | AG71XX_DESC_SIZE * ((i + 1) & ring_mask)); |
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223 | |||
224 | DBG("ag71xx: RX desc at %p, next is %08x\n", |
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225 | desc, desc->next); |
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226 | } |
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227 | |||
228 | for (i = 0; i < ring_size; i++) { |
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229 | struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i); |
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230 | |||
231 | if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], offset, |
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232 | netdev_alloc_frag)) { |
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233 | ret = -ENOMEM; |
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234 | break; |
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235 | } |
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236 | |||
237 | desc->ctrl = DESC_EMPTY; |
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238 | } |
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239 | |||
240 | /* flush descriptors */ |
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241 | wmb(); |
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242 | |||
243 | ring->curr = 0; |
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244 | ring->dirty = 0; |
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245 | |||
246 | return ret; |
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247 | } |
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248 | |||
249 | static int ag71xx_ring_rx_refill(struct ag71xx *ag) |
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250 | { |
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251 | struct ag71xx_ring *ring = &ag->rx_ring; |
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252 | int ring_mask = BIT(ring->order) - 1; |
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253 | unsigned int count; |
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254 | int offset = ag71xx_buffer_offset(ag); |
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255 | |||
256 | count = 0; |
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257 | for (; ring->curr - ring->dirty > 0; ring->dirty++) { |
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258 | struct ag71xx_desc *desc; |
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259 | unsigned int i; |
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260 | |||
261 | i = ring->dirty & ring_mask; |
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262 | desc = ag71xx_ring_desc(ring, i); |
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263 | |||
264 | if (!ring->buf[i].rx_buf && |
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265 | !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset, |
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266 | napi_alloc_frag)) |
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267 | break; |
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268 | |||
269 | desc->ctrl = DESC_EMPTY; |
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270 | count++; |
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271 | } |
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272 | |||
273 | /* flush descriptors */ |
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274 | wmb(); |
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275 | |||
276 | DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count); |
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277 | |||
278 | return count; |
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279 | } |
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280 | |||
281 | static int ag71xx_rings_init(struct ag71xx *ag) |
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282 | { |
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283 | struct ag71xx_ring *tx = &ag->tx_ring; |
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284 | struct ag71xx_ring *rx = &ag->rx_ring; |
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285 | int ring_size = BIT(tx->order) + BIT(rx->order); |
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286 | int tx_size = BIT(tx->order); |
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287 | |||
288 | tx->buf = kzalloc(ring_size * sizeof(*tx->buf), GFP_KERNEL); |
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289 | if (!tx->buf) |
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290 | return -ENOMEM; |
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291 | |||
292 | tx->descs_cpu = dma_alloc_coherent(NULL, ring_size * AG71XX_DESC_SIZE, |
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293 | &tx->descs_dma, GFP_ATOMIC); |
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294 | if (!tx->descs_cpu) { |
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295 | kfree(tx->buf); |
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296 | tx->buf = NULL; |
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297 | return -ENOMEM; |
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298 | } |
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299 | |||
300 | rx->buf = &tx->buf[BIT(tx->order)]; |
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301 | rx->descs_cpu = ((void *)tx->descs_cpu) + tx_size * AG71XX_DESC_SIZE; |
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302 | rx->descs_dma = tx->descs_dma + tx_size * AG71XX_DESC_SIZE; |
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303 | |||
304 | ag71xx_ring_tx_init(ag); |
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305 | return ag71xx_ring_rx_init(ag); |
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306 | } |
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307 | |||
308 | static void ag71xx_rings_free(struct ag71xx *ag) |
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309 | { |
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310 | struct ag71xx_ring *tx = &ag->tx_ring; |
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311 | struct ag71xx_ring *rx = &ag->rx_ring; |
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312 | int ring_size = BIT(tx->order) + BIT(rx->order); |
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313 | |||
314 | if (tx->descs_cpu) |
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315 | dma_free_coherent(NULL, ring_size * AG71XX_DESC_SIZE, |
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316 | tx->descs_cpu, tx->descs_dma); |
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317 | |||
318 | kfree(tx->buf); |
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319 | |||
320 | tx->descs_cpu = NULL; |
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321 | rx->descs_cpu = NULL; |
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322 | tx->buf = NULL; |
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323 | rx->buf = NULL; |
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324 | } |
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325 | |||
326 | static void ag71xx_rings_cleanup(struct ag71xx *ag) |
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327 | { |
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328 | ag71xx_ring_rx_clean(ag); |
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329 | ag71xx_ring_tx_clean(ag); |
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330 | ag71xx_rings_free(ag); |
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331 | |||
332 | netdev_reset_queue(ag->dev); |
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333 | } |
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334 | |||
335 | static unsigned char *ag71xx_speed_str(struct ag71xx *ag) |
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336 | { |
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337 | switch (ag->speed) { |
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338 | case SPEED_1000: |
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339 | return "1000"; |
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340 | case SPEED_100: |
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341 | return "100"; |
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342 | case SPEED_10: |
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343 | return "10"; |
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344 | } |
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345 | |||
346 | return "?"; |
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347 | } |
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348 | |||
349 | static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac) |
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350 | { |
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351 | u32 t; |
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352 | |||
353 | t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16) |
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354 | | (((u32) mac[3]) << 8) | ((u32) mac[2]); |
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355 | |||
356 | ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t); |
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357 | |||
358 | t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16); |
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359 | ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t); |
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360 | } |
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361 | |||
362 | static void ag71xx_dma_reset(struct ag71xx *ag) |
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363 | { |
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364 | u32 val; |
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365 | int i; |
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366 | |||
367 | ag71xx_dump_dma_regs(ag); |
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368 | |||
369 | /* stop RX and TX */ |
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370 | ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0); |
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371 | ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0); |
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372 | |||
373 | /* |
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374 | * give the hardware some time to really stop all rx/tx activity |
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375 | * clearing the descriptors too early causes random memory corruption |
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376 | */ |
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377 | mdelay(1); |
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378 | |||
379 | /* clear descriptor addresses */ |
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380 | ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma); |
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381 | ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma); |
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382 | |||
383 | /* clear pending RX/TX interrupts */ |
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384 | for (i = 0; i < 256; i++) { |
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385 | ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR); |
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386 | ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS); |
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387 | } |
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388 | |||
389 | /* clear pending errors */ |
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390 | ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF); |
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391 | ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR); |
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392 | |||
393 | val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS); |
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394 | if (val) |
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395 | pr_alert("%s: unable to clear DMA Rx status: %08x\n", |
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396 | ag->dev->name, val); |
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397 | |||
398 | val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS); |
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399 | |||
400 | /* mask out reserved bits */ |
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401 | val &= ~0xff000000; |
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402 | |||
403 | if (val) |
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404 | pr_alert("%s: unable to clear DMA Tx status: %08x\n", |
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405 | ag->dev->name, val); |
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406 | |||
407 | ag71xx_dump_dma_regs(ag); |
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408 | } |
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409 | |||
410 | #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \ |
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411 | MAC_CFG1_SRX | MAC_CFG1_STX) |
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412 | |||
413 | #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT) |
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414 | |||
415 | #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \ |
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416 | FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \ |
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417 | FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \ |
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418 | FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \ |
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419 | FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \ |
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420 | FIFO_CFG4_VT) |
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421 | |||
422 | #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \ |
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423 | FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \ |
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424 | FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \ |
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425 | FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \ |
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426 | FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \ |
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427 | FIFO_CFG5_17 | FIFO_CFG5_SF) |
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428 | |||
429 | static void ag71xx_hw_stop(struct ag71xx *ag) |
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430 | { |
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431 | /* disable all interrupts and stop the rx/tx engine */ |
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432 | ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0); |
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433 | ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0); |
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434 | ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0); |
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435 | } |
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436 | |||
437 | static void ag71xx_hw_setup(struct ag71xx *ag) |
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438 | { |
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439 | struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); |
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440 | u32 init = MAC_CFG1_INIT; |
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441 | |||
442 | /* setup MAC configuration registers */ |
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443 | if (pdata->use_flow_control) |
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444 | init |= MAC_CFG1_TFC | MAC_CFG1_RFC; |
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445 | ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, init); |
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446 | |||
447 | ag71xx_sb(ag, AG71XX_REG_MAC_CFG2, |
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448 | MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK); |
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449 | |||
450 | /* setup max frame length to zero */ |
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451 | ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0); |
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452 | |||
453 | /* setup FIFO configuration registers */ |
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454 | ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT); |
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455 | if (pdata->is_ar724x) { |
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456 | ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0010ffff); |
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457 | ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x015500aa); |
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458 | } else { |
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459 | ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000); |
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460 | ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff); |
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461 | } |
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462 | ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT); |
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463 | ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT); |
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464 | } |
||
465 | |||
466 | static void ag71xx_hw_init(struct ag71xx *ag) |
||
467 | { |
||
468 | struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); |
||
469 | u32 reset_mask = pdata->reset_bit; |
||
470 | |||
471 | ag71xx_hw_stop(ag); |
||
472 | |||
473 | if (pdata->is_ar724x) { |
||
474 | u32 reset_phy = reset_mask; |
||
475 | |||
476 | reset_phy &= AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY; |
||
477 | reset_mask &= ~(AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY); |
||
478 | |||
479 | ath79_device_reset_set(reset_phy); |
||
480 | msleep(50); |
||
481 | ath79_device_reset_clear(reset_phy); |
||
482 | msleep(200); |
||
483 | } |
||
484 | |||
485 | ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR); |
||
486 | udelay(20); |
||
487 | |||
488 | ath79_device_reset_set(reset_mask); |
||
489 | msleep(100); |
||
490 | ath79_device_reset_clear(reset_mask); |
||
491 | msleep(200); |
||
492 | |||
493 | ag71xx_hw_setup(ag); |
||
494 | |||
495 | ag71xx_dma_reset(ag); |
||
496 | } |
||
497 | |||
498 | static void ag71xx_fast_reset(struct ag71xx *ag) |
||
499 | { |
||
500 | struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); |
||
501 | struct net_device *dev = ag->dev; |
||
502 | u32 reset_mask = pdata->reset_bit; |
||
503 | u32 rx_ds; |
||
504 | u32 mii_reg; |
||
505 | |||
506 | reset_mask &= AR71XX_RESET_GE0_MAC | AR71XX_RESET_GE1_MAC; |
||
507 | |||
508 | ag71xx_hw_stop(ag); |
||
509 | wmb(); |
||
510 | |||
511 | mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG); |
||
512 | rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC); |
||
513 | |||
514 | ag71xx_tx_packets(ag, true); |
||
515 | |||
516 | ath79_device_reset_set(reset_mask); |
||
517 | udelay(10); |
||
518 | ath79_device_reset_clear(reset_mask); |
||
519 | udelay(10); |
||
520 | |||
521 | ag71xx_dma_reset(ag); |
||
522 | ag71xx_hw_setup(ag); |
||
523 | ag->tx_ring.curr = 0; |
||
524 | ag->tx_ring.dirty = 0; |
||
525 | netdev_reset_queue(ag->dev); |
||
526 | |||
527 | /* setup max frame length */ |
||
528 | ag71xx_wr(ag, AG71XX_REG_MAC_MFL, |
||
529 | ag71xx_max_frame_len(ag->dev->mtu)); |
||
530 | |||
531 | ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds); |
||
532 | ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma); |
||
533 | ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg); |
||
534 | |||
535 | ag71xx_hw_set_macaddr(ag, dev->dev_addr); |
||
536 | } |
||
537 | |||
538 | static void ag71xx_hw_start(struct ag71xx *ag) |
||
539 | { |
||
540 | /* start RX engine */ |
||
541 | ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE); |
||
542 | |||
543 | /* enable interrupts */ |
||
544 | ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT); |
||
545 | |||
546 | netif_wake_queue(ag->dev); |
||
547 | } |
||
548 | |||
549 | static void |
||
550 | __ag71xx_link_adjust(struct ag71xx *ag, bool update) |
||
551 | { |
||
552 | struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); |
||
553 | u32 cfg2; |
||
554 | u32 ifctl; |
||
555 | u32 fifo5; |
||
556 | u32 fifo3; |
||
557 | |||
558 | if (!ag->link && update) { |
||
559 | ag71xx_hw_stop(ag); |
||
560 | netif_carrier_off(ag->dev); |
||
561 | if (netif_msg_link(ag)) |
||
562 | pr_info("%s: link down\n", ag->dev->name); |
||
563 | return; |
||
564 | } |
||
565 | |||
566 | if (pdata->is_ar724x) |
||
567 | ag71xx_fast_reset(ag); |
||
568 | |||
569 | cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2); |
||
570 | cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX); |
||
571 | cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0; |
||
572 | |||
573 | ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL); |
||
574 | ifctl &= ~(MAC_IFCTL_SPEED); |
||
575 | |||
576 | fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5); |
||
577 | fifo5 &= ~FIFO_CFG5_BM; |
||
578 | |||
579 | switch (ag->speed) { |
||
580 | case SPEED_1000: |
||
581 | cfg2 |= MAC_CFG2_IF_1000; |
||
582 | fifo5 |= FIFO_CFG5_BM; |
||
583 | break; |
||
584 | case SPEED_100: |
||
585 | cfg2 |= MAC_CFG2_IF_10_100; |
||
586 | ifctl |= MAC_IFCTL_SPEED; |
||
587 | break; |
||
588 | case SPEED_10: |
||
589 | cfg2 |= MAC_CFG2_IF_10_100; |
||
590 | break; |
||
591 | default: |
||
592 | BUG(); |
||
593 | return; |
||
594 | } |
||
595 | |||
596 | if (pdata->is_ar91xx) |
||
597 | fifo3 = 0x00780fff; |
||
598 | else if (pdata->is_ar724x) |
||
599 | fifo3 = 0x01f00140; |
||
600 | else |
||
601 | fifo3 = 0x008001ff; |
||
602 | |||
603 | if (ag->tx_ring.desc_split) { |
||
604 | fifo3 &= 0xffff; |
||
605 | fifo3 |= ((2048 - ag->tx_ring.desc_split) / 4) << 16; |
||
606 | } |
||
607 | |||
608 | ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, fifo3); |
||
609 | |||
610 | if (update && pdata->set_speed) |
||
611 | pdata->set_speed(ag->speed); |
||
612 | |||
613 | ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2); |
||
614 | ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5); |
||
615 | ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl); |
||
616 | |||
617 | if (pdata->disable_inline_checksum_engine) { |
||
618 | /* |
||
619 | * The rx ring buffer can stall on small packets on QCA953x and |
||
620 | * QCA956x. Disabling the inline checksum engine fixes the stall. |
||
621 | * The wr, rr functions cannot be used since this hidden register |
||
622 | * is outside of the normal ag71xx register block. |
||
623 | */ |
||
624 | void __iomem *dam = ioremap_nocache(0xb90001bc, 0x4); |
||
625 | if (dam) { |
||
626 | __raw_writel(__raw_readl(dam) & ~BIT(27), dam); |
||
627 | (void)__raw_readl(dam); |
||
628 | iounmap(dam); |
||
629 | } |
||
630 | } |
||
631 | |||
632 | ag71xx_hw_start(ag); |
||
633 | |||
634 | netif_carrier_on(ag->dev); |
||
635 | if (update && netif_msg_link(ag)) |
||
636 | pr_info("%s: link up (%sMbps/%s duplex)\n", |
||
637 | ag->dev->name, |
||
638 | ag71xx_speed_str(ag), |
||
639 | (DUPLEX_FULL == ag->duplex) ? "Full" : "Half"); |
||
640 | |||
3 | office | 641 | DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n", |
642 | ag->dev->name, |
||
643 | ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0), |
||
644 | ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1), |
||
645 | ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2)); |
||
646 | |||
647 | DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n", |
||
648 | ag->dev->name, |
||
649 | ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3), |
||
650 | ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4), |
||
651 | ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5)); |
||
652 | |||
653 | DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x\n", |
||
654 | ag->dev->name, |
||
655 | ag71xx_rr(ag, AG71XX_REG_MAC_CFG2), |
||
656 | ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL)); |
||
1 | office | 657 | } |
658 | |||
659 | void ag71xx_link_adjust(struct ag71xx *ag) |
||
660 | { |
||
661 | __ag71xx_link_adjust(ag, true); |
||
662 | } |
||
663 | |||
664 | static int ag71xx_hw_enable(struct ag71xx *ag) |
||
665 | { |
||
666 | int ret; |
||
667 | |||
668 | ret = ag71xx_rings_init(ag); |
||
669 | if (ret) |
||
670 | return ret; |
||
671 | |||
672 | napi_enable(&ag->napi); |
||
673 | ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma); |
||
674 | ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma); |
||
675 | netif_start_queue(ag->dev); |
||
676 | |||
677 | return 0; |
||
678 | } |
||
679 | |||
680 | static void ag71xx_hw_disable(struct ag71xx *ag) |
||
681 | { |
||
682 | unsigned long flags; |
||
683 | |||
684 | spin_lock_irqsave(&ag->lock, flags); |
||
685 | |||
686 | netif_stop_queue(ag->dev); |
||
687 | |||
688 | ag71xx_hw_stop(ag); |
||
689 | ag71xx_dma_reset(ag); |
||
690 | |||
691 | napi_disable(&ag->napi); |
||
692 | del_timer_sync(&ag->oom_timer); |
||
693 | |||
694 | spin_unlock_irqrestore(&ag->lock, flags); |
||
695 | |||
696 | ag71xx_rings_cleanup(ag); |
||
697 | } |
||
698 | |||
699 | static int ag71xx_open(struct net_device *dev) |
||
700 | { |
||
701 | struct ag71xx *ag = netdev_priv(dev); |
||
702 | unsigned int max_frame_len; |
||
703 | int ret; |
||
704 | |||
705 | netif_carrier_off(dev); |
||
706 | max_frame_len = ag71xx_max_frame_len(dev->mtu); |
||
707 | ag->rx_buf_size = SKB_DATA_ALIGN(max_frame_len + NET_SKB_PAD + NET_IP_ALIGN); |
||
708 | |||
709 | /* setup max frame length */ |
||
710 | ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len); |
||
711 | ag71xx_hw_set_macaddr(ag, dev->dev_addr); |
||
712 | |||
713 | ret = ag71xx_hw_enable(ag); |
||
714 | if (ret) |
||
715 | goto err; |
||
716 | |||
717 | ag71xx_phy_start(ag); |
||
718 | |||
719 | return 0; |
||
720 | |||
721 | err: |
||
722 | ag71xx_rings_cleanup(ag); |
||
723 | return ret; |
||
724 | } |
||
725 | |||
726 | static int ag71xx_stop(struct net_device *dev) |
||
727 | { |
||
728 | struct ag71xx *ag = netdev_priv(dev); |
||
729 | |||
730 | netif_carrier_off(dev); |
||
731 | ag71xx_phy_stop(ag); |
||
732 | ag71xx_hw_disable(ag); |
||
733 | |||
734 | return 0; |
||
735 | } |
||
736 | |||
737 | static int ag71xx_fill_dma_desc(struct ag71xx_ring *ring, u32 addr, int len) |
||
738 | { |
||
739 | int i; |
||
740 | struct ag71xx_desc *desc; |
||
741 | int ring_mask = BIT(ring->order) - 1; |
||
742 | int ndesc = 0; |
||
743 | int split = ring->desc_split; |
||
744 | |||
745 | if (!split) |
||
746 | split = len; |
||
747 | |||
748 | while (len > 0) { |
||
749 | unsigned int cur_len = len; |
||
750 | |||
751 | i = (ring->curr + ndesc) & ring_mask; |
||
752 | desc = ag71xx_ring_desc(ring, i); |
||
753 | |||
754 | if (!ag71xx_desc_empty(desc)) |
||
755 | return -1; |
||
756 | |||
757 | if (cur_len > split) { |
||
758 | cur_len = split; |
||
759 | |||
760 | /* |
||
761 | * TX will hang if DMA transfers <= 4 bytes, |
||
762 | * make sure next segment is more than 4 bytes long. |
||
763 | */ |
||
764 | if (len <= split + 4) |
||
765 | cur_len -= 4; |
||
766 | } |
||
767 | |||
768 | desc->data = addr; |
||
769 | addr += cur_len; |
||
770 | len -= cur_len; |
||
771 | |||
772 | if (len > 0) |
||
773 | cur_len |= DESC_MORE; |
||
774 | |||
775 | /* prevent early tx attempt of this descriptor */ |
||
776 | if (!ndesc) |
||
777 | cur_len |= DESC_EMPTY; |
||
778 | |||
779 | desc->ctrl = cur_len; |
||
780 | ndesc++; |
||
781 | } |
||
782 | |||
783 | return ndesc; |
||
784 | } |
||
785 | |||
786 | static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb, |
||
787 | struct net_device *dev) |
||
788 | { |
||
789 | struct ag71xx *ag = netdev_priv(dev); |
||
790 | struct ag71xx_ring *ring = &ag->tx_ring; |
||
791 | int ring_mask = BIT(ring->order) - 1; |
||
792 | int ring_size = BIT(ring->order); |
||
793 | struct ag71xx_desc *desc; |
||
794 | dma_addr_t dma_addr; |
||
795 | int i, n, ring_min; |
||
796 | |||
797 | if (ag71xx_has_ar8216(ag)) |
||
798 | ag71xx_add_ar8216_header(ag, skb); |
||
799 | |||
800 | if (skb->len <= 4) { |
||
801 | DBG("%s: packet len is too small\n", ag->dev->name); |
||
802 | goto err_drop; |
||
803 | } |
||
804 | |||
805 | dma_addr = dma_map_single(&dev->dev, skb->data, skb->len, |
||
806 | DMA_TO_DEVICE); |
||
807 | |||
808 | i = ring->curr & ring_mask; |
||
809 | desc = ag71xx_ring_desc(ring, i); |
||
810 | |||
811 | /* setup descriptor fields */ |
||
812 | n = ag71xx_fill_dma_desc(ring, (u32) dma_addr, skb->len & ag->desc_pktlen_mask); |
||
813 | if (n < 0) |
||
814 | goto err_drop_unmap; |
||
815 | |||
816 | i = (ring->curr + n - 1) & ring_mask; |
||
817 | ring->buf[i].len = skb->len; |
||
818 | ring->buf[i].skb = skb; |
||
819 | |||
820 | netdev_sent_queue(dev, skb->len); |
||
821 | |||
822 | skb_tx_timestamp(skb); |
||
823 | |||
824 | desc->ctrl &= ~DESC_EMPTY; |
||
825 | ring->curr += n; |
||
826 | |||
827 | /* flush descriptor */ |
||
828 | wmb(); |
||
829 | |||
830 | ring_min = 2; |
||
831 | if (ring->desc_split) |
||
832 | ring_min *= AG71XX_TX_RING_DS_PER_PKT; |
||
833 | |||
834 | if (ring->curr - ring->dirty >= ring_size - ring_min) { |
||
835 | DBG("%s: tx queue full\n", dev->name); |
||
836 | netif_stop_queue(dev); |
||
837 | } |
||
838 | |||
839 | DBG("%s: packet injected into TX queue\n", ag->dev->name); |
||
840 | |||
841 | /* enable TX engine */ |
||
842 | ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE); |
||
843 | |||
844 | return NETDEV_TX_OK; |
||
845 | |||
846 | err_drop_unmap: |
||
847 | dma_unmap_single(&dev->dev, dma_addr, skb->len, DMA_TO_DEVICE); |
||
848 | |||
849 | err_drop: |
||
850 | dev->stats.tx_dropped++; |
||
851 | |||
852 | dev_kfree_skb(skb); |
||
853 | return NETDEV_TX_OK; |
||
854 | } |
||
855 | |||
856 | static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
||
857 | { |
||
858 | struct ag71xx *ag = netdev_priv(dev); |
||
859 | int ret; |
||
860 | |||
861 | switch (cmd) { |
||
862 | case SIOCETHTOOL: |
||
863 | if (ag->phy_dev == NULL) |
||
864 | break; |
||
865 | |||
866 | spin_lock_irq(&ag->lock); |
||
867 | ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data); |
||
868 | spin_unlock_irq(&ag->lock); |
||
869 | return ret; |
||
870 | |||
871 | case SIOCSIFHWADDR: |
||
872 | if (copy_from_user |
||
873 | (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr))) |
||
874 | return -EFAULT; |
||
875 | return 0; |
||
876 | |||
877 | case SIOCGIFHWADDR: |
||
878 | if (copy_to_user |
||
879 | (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr))) |
||
880 | return -EFAULT; |
||
881 | return 0; |
||
882 | |||
883 | case SIOCGMIIPHY: |
||
884 | case SIOCGMIIREG: |
||
885 | case SIOCSMIIREG: |
||
886 | if (ag->phy_dev == NULL) |
||
887 | break; |
||
888 | |||
889 | return phy_mii_ioctl(ag->phy_dev, ifr, cmd); |
||
890 | |||
891 | default: |
||
892 | break; |
||
893 | } |
||
894 | |||
895 | return -EOPNOTSUPP; |
||
896 | } |
||
897 | |||
898 | static void ag71xx_oom_timer_handler(unsigned long data) |
||
899 | { |
||
900 | struct net_device *dev = (struct net_device *) data; |
||
901 | struct ag71xx *ag = netdev_priv(dev); |
||
902 | |||
903 | napi_schedule(&ag->napi); |
||
904 | } |
||
905 | |||
906 | static void ag71xx_tx_timeout(struct net_device *dev) |
||
907 | { |
||
908 | struct ag71xx *ag = netdev_priv(dev); |
||
909 | |||
910 | if (netif_msg_tx_err(ag)) |
||
911 | pr_info("%s: tx timeout\n", ag->dev->name); |
||
912 | |||
913 | schedule_delayed_work(&ag->restart_work, 1); |
||
914 | } |
||
915 | |||
916 | static void ag71xx_restart_work_func(struct work_struct *work) |
||
917 | { |
||
918 | struct ag71xx *ag = container_of(work, struct ag71xx, restart_work.work); |
||
919 | |||
920 | rtnl_lock(); |
||
921 | ag71xx_hw_disable(ag); |
||
922 | ag71xx_hw_enable(ag); |
||
923 | if (ag->link) |
||
924 | __ag71xx_link_adjust(ag, false); |
||
925 | rtnl_unlock(); |
||
926 | } |
||
927 | |||
928 | static bool ag71xx_check_dma_stuck(struct ag71xx *ag) |
||
929 | { |
||
930 | unsigned long timestamp; |
||
931 | u32 rx_sm, tx_sm, rx_fd; |
||
932 | |||
933 | timestamp = netdev_get_tx_queue(ag->dev, 0)->trans_start; |
||
934 | if (likely(time_before(jiffies, timestamp + HZ/10))) |
||
935 | return false; |
||
936 | |||
937 | if (!netif_carrier_ok(ag->dev)) |
||
938 | return false; |
||
939 | |||
940 | rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM); |
||
941 | if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6) |
||
942 | return true; |
||
943 | |||
944 | tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM); |
||
945 | rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH); |
||
946 | if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) && |
||
947 | ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0) |
||
948 | return true; |
||
949 | |||
950 | return false; |
||
951 | } |
||
952 | |||
953 | static int ag71xx_tx_packets(struct ag71xx *ag, bool flush) |
||
954 | { |
||
955 | struct ag71xx_ring *ring = &ag->tx_ring; |
||
956 | struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); |
||
957 | bool dma_stuck = false; |
||
958 | int ring_mask = BIT(ring->order) - 1; |
||
959 | int ring_size = BIT(ring->order); |
||
960 | int sent = 0; |
||
961 | int bytes_compl = 0; |
||
962 | int n = 0; |
||
963 | |||
964 | DBG("%s: processing TX ring\n", ag->dev->name); |
||
965 | |||
966 | while (ring->dirty + n != ring->curr) { |
||
967 | unsigned int i = (ring->dirty + n) & ring_mask; |
||
968 | struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i); |
||
969 | struct sk_buff *skb = ring->buf[i].skb; |
||
970 | |||
971 | if (!flush && !ag71xx_desc_empty(desc)) { |
||
972 | if (pdata->is_ar724x && |
||
973 | ag71xx_check_dma_stuck(ag)) { |
||
974 | schedule_delayed_work(&ag->restart_work, HZ / 2); |
||
975 | dma_stuck = true; |
||
976 | } |
||
977 | break; |
||
978 | } |
||
979 | |||
980 | if (flush) |
||
981 | desc->ctrl |= DESC_EMPTY; |
||
982 | |||
983 | n++; |
||
984 | if (!skb) |
||
985 | continue; |
||
986 | |||
987 | dev_kfree_skb_any(skb); |
||
988 | ring->buf[i].skb = NULL; |
||
989 | |||
990 | bytes_compl += ring->buf[i].len; |
||
991 | |||
992 | sent++; |
||
993 | ring->dirty += n; |
||
994 | |||
995 | while (n > 0) { |
||
996 | ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS); |
||
997 | n--; |
||
998 | } |
||
999 | } |
||
1000 | |||
1001 | DBG("%s: %d packets sent out\n", ag->dev->name, sent); |
||
1002 | |||
1003 | if (!sent) |
||
1004 | return 0; |
||
1005 | |||
1006 | ag->dev->stats.tx_bytes += bytes_compl; |
||
1007 | ag->dev->stats.tx_packets += sent; |
||
1008 | |||
1009 | netdev_completed_queue(ag->dev, sent, bytes_compl); |
||
1010 | if ((ring->curr - ring->dirty) < (ring_size * 3) / 4) |
||
1011 | netif_wake_queue(ag->dev); |
||
1012 | |||
1013 | if (!dma_stuck) |
||
1014 | cancel_delayed_work(&ag->restart_work); |
||
1015 | |||
1016 | return sent; |
||
1017 | } |
||
1018 | |||
1019 | static int ag71xx_rx_packets(struct ag71xx *ag, int limit) |
||
1020 | { |
||
1021 | struct net_device *dev = ag->dev; |
||
1022 | struct ag71xx_ring *ring = &ag->rx_ring; |
||
1023 | int offset = ag71xx_buffer_offset(ag); |
||
1024 | unsigned int pktlen_mask = ag->desc_pktlen_mask; |
||
1025 | int ring_mask = BIT(ring->order) - 1; |
||
1026 | int ring_size = BIT(ring->order); |
||
1027 | struct sk_buff_head queue; |
||
1028 | struct sk_buff *skb; |
||
1029 | int done = 0; |
||
1030 | |||
1031 | DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n", |
||
1032 | dev->name, limit, ring->curr, ring->dirty); |
||
1033 | |||
1034 | skb_queue_head_init(&queue); |
||
1035 | |||
1036 | while (done < limit) { |
||
1037 | unsigned int i = ring->curr & ring_mask; |
||
1038 | struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i); |
||
1039 | int pktlen; |
||
1040 | int err = 0; |
||
1041 | |||
1042 | if (ag71xx_desc_empty(desc)) |
||
1043 | break; |
||
1044 | |||
1045 | if ((ring->dirty + ring_size) == ring->curr) { |
||
1046 | ag71xx_assert(0); |
||
1047 | break; |
||
1048 | } |
||
1049 | |||
1050 | ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR); |
||
1051 | |||
1052 | pktlen = desc->ctrl & pktlen_mask; |
||
1053 | pktlen -= ETH_FCS_LEN; |
||
1054 | |||
1055 | dma_unmap_single(&dev->dev, ring->buf[i].dma_addr, |
||
1056 | ag->rx_buf_size, DMA_FROM_DEVICE); |
||
1057 | |||
1058 | dev->stats.rx_packets++; |
||
1059 | dev->stats.rx_bytes += pktlen; |
||
1060 | |||
1061 | skb = build_skb(ring->buf[i].rx_buf, ag71xx_buffer_size(ag)); |
||
1062 | if (!skb) { |
||
1063 | skb_free_frag(ring->buf[i].rx_buf); |
||
1064 | goto next; |
||
1065 | } |
||
1066 | |||
1067 | skb_reserve(skb, offset); |
||
1068 | skb_put(skb, pktlen); |
||
1069 | |||
1070 | if (ag71xx_has_ar8216(ag)) |
||
1071 | err = ag71xx_remove_ar8216_header(ag, skb, pktlen); |
||
1072 | |||
1073 | if (err) { |
||
1074 | dev->stats.rx_dropped++; |
||
1075 | kfree_skb(skb); |
||
1076 | } else { |
||
1077 | skb->dev = dev; |
||
1078 | skb->ip_summed = CHECKSUM_NONE; |
||
1079 | __skb_queue_tail(&queue, skb); |
||
1080 | } |
||
1081 | |||
1082 | next: |
||
1083 | ring->buf[i].rx_buf = NULL; |
||
1084 | done++; |
||
1085 | |||
1086 | ring->curr++; |
||
1087 | } |
||
1088 | |||
1089 | ag71xx_ring_rx_refill(ag); |
||
1090 | |||
1091 | while ((skb = __skb_dequeue(&queue)) != NULL) { |
||
1092 | skb->protocol = eth_type_trans(skb, dev); |
||
1093 | netif_receive_skb(skb); |
||
1094 | } |
||
1095 | |||
1096 | DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n", |
||
1097 | dev->name, ring->curr, ring->dirty, done); |
||
1098 | |||
1099 | return done; |
||
1100 | } |
||
1101 | |||
1102 | static int ag71xx_poll(struct napi_struct *napi, int limit) |
||
1103 | { |
||
1104 | struct ag71xx *ag = container_of(napi, struct ag71xx, napi); |
||
1105 | struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); |
||
1106 | struct net_device *dev = ag->dev; |
||
1107 | struct ag71xx_ring *rx_ring = &ag->rx_ring; |
||
1108 | int rx_ring_size = BIT(rx_ring->order); |
||
1109 | unsigned long flags; |
||
1110 | u32 status; |
||
1111 | int tx_done; |
||
1112 | int rx_done; |
||
1113 | |||
1114 | pdata->ddr_flush(); |
||
1115 | tx_done = ag71xx_tx_packets(ag, false); |
||
1116 | |||
1117 | DBG("%s: processing RX ring\n", dev->name); |
||
1118 | rx_done = ag71xx_rx_packets(ag, limit); |
||
1119 | |||
1120 | ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done); |
||
1121 | |||
1122 | if (rx_ring->buf[rx_ring->dirty % rx_ring_size].rx_buf == NULL) |
||
1123 | goto oom; |
||
1124 | |||
1125 | status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS); |
||
1126 | if (unlikely(status & RX_STATUS_OF)) { |
||
1127 | ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF); |
||
1128 | dev->stats.rx_fifo_errors++; |
||
1129 | |||
1130 | /* restart RX */ |
||
1131 | ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE); |
||
1132 | } |
||
1133 | |||
1134 | if (rx_done < limit) { |
||
1135 | if (status & RX_STATUS_PR) |
||
1136 | goto more; |
||
1137 | |||
1138 | status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS); |
||
1139 | if (status & TX_STATUS_PS) |
||
1140 | goto more; |
||
1141 | |||
1142 | DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n", |
||
1143 | dev->name, rx_done, tx_done, limit); |
||
1144 | |||
1145 | napi_complete(napi); |
||
1146 | |||
1147 | /* enable interrupts */ |
||
1148 | spin_lock_irqsave(&ag->lock, flags); |
||
1149 | ag71xx_int_enable(ag, AG71XX_INT_POLL); |
||
1150 | spin_unlock_irqrestore(&ag->lock, flags); |
||
1151 | return rx_done; |
||
1152 | } |
||
1153 | |||
1154 | more: |
||
1155 | DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n", |
||
1156 | dev->name, rx_done, tx_done, limit); |
||
1157 | return limit; |
||
1158 | |||
1159 | oom: |
||
1160 | if (netif_msg_rx_err(ag)) |
||
1161 | pr_info("%s: out of memory\n", dev->name); |
||
1162 | |||
1163 | mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL); |
||
1164 | napi_complete(napi); |
||
1165 | return 0; |
||
1166 | } |
||
1167 | |||
1168 | static irqreturn_t ag71xx_interrupt(int irq, void *dev_id) |
||
1169 | { |
||
1170 | struct net_device *dev = dev_id; |
||
1171 | struct ag71xx *ag = netdev_priv(dev); |
||
1172 | u32 status; |
||
1173 | |||
1174 | status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS); |
||
1175 | ag71xx_dump_intr(ag, "raw", status); |
||
1176 | |||
1177 | if (unlikely(!status)) |
||
1178 | return IRQ_NONE; |
||
1179 | |||
1180 | if (unlikely(status & AG71XX_INT_ERR)) { |
||
1181 | if (status & AG71XX_INT_TX_BE) { |
||
1182 | ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE); |
||
1183 | dev_err(&dev->dev, "TX BUS error\n"); |
||
1184 | } |
||
1185 | if (status & AG71XX_INT_RX_BE) { |
||
1186 | ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE); |
||
1187 | dev_err(&dev->dev, "RX BUS error\n"); |
||
1188 | } |
||
1189 | } |
||
1190 | |||
1191 | if (likely(status & AG71XX_INT_POLL)) { |
||
1192 | ag71xx_int_disable(ag, AG71XX_INT_POLL); |
||
1193 | DBG("%s: enable polling mode\n", dev->name); |
||
1194 | napi_schedule(&ag->napi); |
||
1195 | } |
||
1196 | |||
1197 | ag71xx_debugfs_update_int_stats(ag, status); |
||
1198 | |||
1199 | return IRQ_HANDLED; |
||
1200 | } |
||
1201 | |||
1202 | #ifdef CONFIG_NET_POLL_CONTROLLER |
||
1203 | /* |
||
1204 | * Polling 'interrupt' - used by things like netconsole to send skbs |
||
1205 | * without having to re-enable interrupts. It's not called while |
||
1206 | * the interrupt routine is executing. |
||
1207 | */ |
||
1208 | static void ag71xx_netpoll(struct net_device *dev) |
||
1209 | { |
||
1210 | disable_irq(dev->irq); |
||
1211 | ag71xx_interrupt(dev->irq, dev); |
||
1212 | enable_irq(dev->irq); |
||
1213 | } |
||
1214 | #endif |
||
1215 | |||
1216 | static int ag71xx_change_mtu(struct net_device *dev, int new_mtu) |
||
1217 | { |
||
1218 | struct ag71xx *ag = netdev_priv(dev); |
||
1219 | unsigned int max_frame_len; |
||
1220 | |||
1221 | max_frame_len = ag71xx_max_frame_len(new_mtu); |
||
1222 | if (new_mtu < 68 || max_frame_len > ag->max_frame_len) |
||
1223 | return -EINVAL; |
||
1224 | |||
1225 | if (netif_running(dev)) |
||
1226 | return -EBUSY; |
||
1227 | |||
1228 | dev->mtu = new_mtu; |
||
1229 | return 0; |
||
1230 | } |
||
1231 | |||
1232 | static const struct net_device_ops ag71xx_netdev_ops = { |
||
1233 | .ndo_open = ag71xx_open, |
||
1234 | .ndo_stop = ag71xx_stop, |
||
1235 | .ndo_start_xmit = ag71xx_hard_start_xmit, |
||
1236 | .ndo_do_ioctl = ag71xx_do_ioctl, |
||
1237 | .ndo_tx_timeout = ag71xx_tx_timeout, |
||
1238 | .ndo_change_mtu = ag71xx_change_mtu, |
||
1239 | .ndo_set_mac_address = eth_mac_addr, |
||
1240 | .ndo_validate_addr = eth_validate_addr, |
||
1241 | #ifdef CONFIG_NET_POLL_CONTROLLER |
||
1242 | .ndo_poll_controller = ag71xx_netpoll, |
||
1243 | #endif |
||
1244 | }; |
||
1245 | |||
1246 | static const char *ag71xx_get_phy_if_mode_name(phy_interface_t mode) |
||
1247 | { |
||
1248 | switch (mode) { |
||
1249 | case PHY_INTERFACE_MODE_MII: |
||
1250 | return "MII"; |
||
1251 | case PHY_INTERFACE_MODE_GMII: |
||
1252 | return "GMII"; |
||
1253 | case PHY_INTERFACE_MODE_RMII: |
||
1254 | return "RMII"; |
||
1255 | case PHY_INTERFACE_MODE_RGMII: |
||
1256 | return "RGMII"; |
||
1257 | case PHY_INTERFACE_MODE_SGMII: |
||
1258 | return "SGMII"; |
||
1259 | default: |
||
1260 | break; |
||
1261 | } |
||
1262 | |||
1263 | return "unknown"; |
||
1264 | } |
||
1265 | |||
1266 | |||
1267 | static int ag71xx_probe(struct platform_device *pdev) |
||
1268 | { |
||
1269 | struct net_device *dev; |
||
1270 | struct resource *res; |
||
1271 | struct ag71xx *ag; |
||
1272 | struct ag71xx_platform_data *pdata; |
||
1273 | int tx_size, err; |
||
1274 | |||
1275 | pdata = pdev->dev.platform_data; |
||
1276 | if (!pdata) { |
||
1277 | dev_err(&pdev->dev, "no platform data specified\n"); |
||
1278 | err = -ENXIO; |
||
1279 | goto err_out; |
||
1280 | } |
||
1281 | |||
1282 | if (pdata->mii_bus_dev == NULL && pdata->phy_mask) { |
||
1283 | dev_err(&pdev->dev, "no MII bus device specified\n"); |
||
1284 | err = -EINVAL; |
||
1285 | goto err_out; |
||
1286 | } |
||
1287 | |||
1288 | dev = alloc_etherdev(sizeof(*ag)); |
||
1289 | if (!dev) { |
||
1290 | dev_err(&pdev->dev, "alloc_etherdev failed\n"); |
||
1291 | err = -ENOMEM; |
||
1292 | goto err_out; |
||
1293 | } |
||
1294 | |||
1295 | if (!pdata->max_frame_len || !pdata->desc_pktlen_mask) |
||
1296 | return -EINVAL; |
||
1297 | |||
1298 | SET_NETDEV_DEV(dev, &pdev->dev); |
||
1299 | |||
1300 | ag = netdev_priv(dev); |
||
1301 | ag->pdev = pdev; |
||
1302 | ag->dev = dev; |
||
1303 | ag->msg_enable = netif_msg_init(ag71xx_msg_level, |
||
1304 | AG71XX_DEFAULT_MSG_ENABLE); |
||
1305 | spin_lock_init(&ag->lock); |
||
1306 | |||
1307 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base"); |
||
1308 | if (!res) { |
||
1309 | dev_err(&pdev->dev, "no mac_base resource found\n"); |
||
1310 | err = -ENXIO; |
||
1311 | goto err_out; |
||
1312 | } |
||
1313 | |||
1314 | ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1); |
||
1315 | if (!ag->mac_base) { |
||
1316 | dev_err(&pdev->dev, "unable to ioremap mac_base\n"); |
||
1317 | err = -ENOMEM; |
||
1318 | goto err_free_dev; |
||
1319 | } |
||
1320 | |||
1321 | dev->irq = platform_get_irq(pdev, 0); |
||
1322 | err = request_irq(dev->irq, ag71xx_interrupt, |
||
1323 | 0x0, |
||
1324 | dev->name, dev); |
||
1325 | if (err) { |
||
1326 | dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq); |
||
1327 | goto err_unmap_base; |
||
1328 | } |
||
1329 | |||
1330 | dev->base_addr = (unsigned long)ag->mac_base; |
||
1331 | dev->netdev_ops = &ag71xx_netdev_ops; |
||
1332 | dev->ethtool_ops = &ag71xx_ethtool_ops; |
||
1333 | |||
1334 | INIT_DELAYED_WORK(&ag->restart_work, ag71xx_restart_work_func); |
||
1335 | |||
1336 | init_timer(&ag->oom_timer); |
||
1337 | ag->oom_timer.data = (unsigned long) dev; |
||
1338 | ag->oom_timer.function = ag71xx_oom_timer_handler; |
||
1339 | |||
1340 | tx_size = AG71XX_TX_RING_SIZE_DEFAULT; |
||
1341 | ag->rx_ring.order = ag71xx_ring_size_order(AG71XX_RX_RING_SIZE_DEFAULT); |
||
1342 | |||
1343 | ag->max_frame_len = pdata->max_frame_len; |
||
1344 | ag->desc_pktlen_mask = pdata->desc_pktlen_mask; |
||
1345 | |||
1346 | if (!pdata->is_ar724x && !pdata->is_ar91xx) { |
||
1347 | ag->tx_ring.desc_split = AG71XX_TX_RING_SPLIT; |
||
1348 | tx_size *= AG71XX_TX_RING_DS_PER_PKT; |
||
1349 | } |
||
1350 | ag->tx_ring.order = ag71xx_ring_size_order(tx_size); |
||
1351 | |||
1352 | ag->stop_desc = dma_alloc_coherent(NULL, |
||
1353 | sizeof(struct ag71xx_desc), &ag->stop_desc_dma, GFP_KERNEL); |
||
1354 | |||
1355 | if (!ag->stop_desc) |
||
1356 | goto err_free_irq; |
||
1357 | |||
1358 | ag->stop_desc->data = 0; |
||
1359 | ag->stop_desc->ctrl = 0; |
||
1360 | ag->stop_desc->next = (u32) ag->stop_desc_dma; |
||
1361 | |||
1362 | memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN); |
||
1363 | |||
1364 | netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT); |
||
1365 | |||
1366 | ag71xx_dump_regs(ag); |
||
1367 | |||
1368 | ag71xx_hw_init(ag); |
||
1369 | |||
1370 | ag71xx_dump_regs(ag); |
||
1371 | |||
1372 | err = ag71xx_phy_connect(ag); |
||
1373 | if (err) |
||
1374 | goto err_free_desc; |
||
1375 | |||
1376 | err = ag71xx_debugfs_init(ag); |
||
1377 | if (err) |
||
1378 | goto err_phy_disconnect; |
||
1379 | |||
1380 | platform_set_drvdata(pdev, dev); |
||
1381 | |||
1382 | err = register_netdev(dev); |
||
1383 | if (err) { |
||
1384 | dev_err(&pdev->dev, "unable to register net device\n"); |
||
1385 | goto err_debugfs_exit; |
||
1386 | } |
||
1387 | |||
1388 | pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d, mode:%s\n", |
||
1389 | dev->name, dev->base_addr, dev->irq, |
||
1390 | ag71xx_get_phy_if_mode_name(pdata->phy_if_mode)); |
||
1391 | |||
1392 | return 0; |
||
1393 | |||
1394 | err_debugfs_exit: |
||
1395 | ag71xx_debugfs_exit(ag); |
||
1396 | err_phy_disconnect: |
||
1397 | ag71xx_phy_disconnect(ag); |
||
1398 | err_free_desc: |
||
1399 | dma_free_coherent(NULL, sizeof(struct ag71xx_desc), ag->stop_desc, |
||
1400 | ag->stop_desc_dma); |
||
1401 | err_free_irq: |
||
1402 | free_irq(dev->irq, dev); |
||
1403 | err_unmap_base: |
||
1404 | iounmap(ag->mac_base); |
||
1405 | err_free_dev: |
||
1406 | kfree(dev); |
||
1407 | err_out: |
||
1408 | platform_set_drvdata(pdev, NULL); |
||
1409 | return err; |
||
1410 | } |
||
1411 | |||
1412 | static int ag71xx_remove(struct platform_device *pdev) |
||
1413 | { |
||
1414 | struct net_device *dev = platform_get_drvdata(pdev); |
||
1415 | |||
1416 | if (dev) { |
||
1417 | struct ag71xx *ag = netdev_priv(dev); |
||
1418 | |||
1419 | ag71xx_debugfs_exit(ag); |
||
1420 | ag71xx_phy_disconnect(ag); |
||
1421 | unregister_netdev(dev); |
||
1422 | free_irq(dev->irq, dev); |
||
1423 | iounmap(ag->mac_base); |
||
1424 | kfree(dev); |
||
1425 | platform_set_drvdata(pdev, NULL); |
||
1426 | } |
||
1427 | |||
1428 | return 0; |
||
1429 | } |
||
1430 | |||
1431 | static struct platform_driver ag71xx_driver = { |
||
1432 | .probe = ag71xx_probe, |
||
1433 | .remove = ag71xx_remove, |
||
1434 | .driver = { |
||
1435 | .name = AG71XX_DRV_NAME, |
||
1436 | } |
||
1437 | }; |
||
1438 | |||
1439 | static int __init ag71xx_module_init(void) |
||
1440 | { |
||
1441 | int ret; |
||
1442 | |||
1443 | ret = ag71xx_debugfs_root_init(); |
||
1444 | if (ret) |
||
1445 | goto err_out; |
||
1446 | |||
1447 | ret = ag71xx_mdio_driver_init(); |
||
1448 | if (ret) |
||
1449 | goto err_debugfs_exit; |
||
1450 | |||
1451 | ret = platform_driver_register(&ag71xx_driver); |
||
1452 | if (ret) |
||
1453 | goto err_mdio_exit; |
||
1454 | |||
1455 | return 0; |
||
1456 | |||
1457 | err_mdio_exit: |
||
1458 | ag71xx_mdio_driver_exit(); |
||
1459 | err_debugfs_exit: |
||
1460 | ag71xx_debugfs_root_exit(); |
||
1461 | err_out: |
||
1462 | return ret; |
||
1463 | } |
||
1464 | |||
1465 | static void __exit ag71xx_module_exit(void) |
||
1466 | { |
||
1467 | platform_driver_unregister(&ag71xx_driver); |
||
1468 | ag71xx_mdio_driver_exit(); |
||
1469 | ag71xx_debugfs_root_exit(); |
||
1470 | } |
||
1471 | |||
1472 | module_init(ag71xx_module_init); |
||
1473 | module_exit(ag71xx_module_exit); |
||
1474 | |||
1475 | MODULE_VERSION(AG71XX_DRV_VERSION); |
||
1476 | MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>"); |
||
1477 | MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>"); |
||
1478 | MODULE_LICENSE("GPL v2"); |
||
1479 | MODULE_ALIAS("platform:" AG71XX_DRV_NAME); |