OpenWrt – Blame information for rev 3
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Rev | Author | Line No. | Line |
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1 | office | 1 | /* |
2 | * Support for YunCore SR3200 and XD3200 boards |
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3 | * |
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4 | * Copyright (C) 2016 Piotr Dymacz <pepe2k@gmail.com> |
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5 | * |
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6 | * This program is free software; you can redistribute it and/or modify it |
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7 | * under the terms of the GNU General Public License version 2 as published |
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8 | * by the Free Software Foundation. |
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9 | */ |
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10 | |||
11 | #include <linux/phy.h> |
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12 | #include <linux/gpio.h> |
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13 | #include <linux/ar8216_platform.h> |
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14 | #include <linux/platform_device.h> |
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15 | |||
16 | #include <asm/mach-ath79/ath79.h> |
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17 | #include <asm/mach-ath79/ar71xx_regs.h> |
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18 | |||
19 | #include "common.h" |
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20 | #include "dev-ap9x-pci.h" |
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21 | #include "dev-eth.h" |
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22 | #include "dev-gpio-buttons.h" |
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23 | #include "dev-leds-gpio.h" |
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24 | #include "dev-m25p80.h" |
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25 | #include "dev-usb.h" |
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26 | #include "dev-wmac.h" |
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27 | #include "machtypes.h" |
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28 | |||
29 | #define SR3200_XD3200_GPIO_LED_SYSTEM 1 |
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30 | #define SR3200_XD3200_GPIO_LED_WLAN2G 19 |
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31 | |||
32 | #define SR3200_XD3200_GPIO_BTN_RESET 2 |
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33 | |||
34 | #define SR3200_XD3200_KEYS_POLL_INTERVAL 20 |
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35 | #define SR3200_XD3200_KEYS_DEBOUNCE_INTERVAL \ |
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36 | (3 * SR3200_XD3200_KEYS_POLL_INTERVAL) |
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37 | |||
38 | static struct gpio_led xd3200_leds_gpio[] __initdata = { |
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39 | { |
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40 | .name = "xd3200:green:system", |
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41 | .gpio = SR3200_XD3200_GPIO_LED_SYSTEM, |
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42 | .active_low = 1, |
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43 | }, |
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44 | { |
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45 | .name = "xd3200:blue:wlan2g", |
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46 | .gpio = SR3200_XD3200_GPIO_LED_WLAN2G, |
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47 | .active_low = 1, |
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48 | }, |
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49 | }; |
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50 | |||
51 | static struct gpio_led sr3200_leds_gpio[] __initdata = { |
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52 | { |
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53 | .name = "sr3200:green:system", |
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54 | .gpio = SR3200_XD3200_GPIO_LED_SYSTEM, |
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55 | .active_low = 1, |
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56 | }, |
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57 | { |
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58 | .name = "sr3200:green:wlan2g", |
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59 | .gpio = SR3200_XD3200_GPIO_LED_WLAN2G, |
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60 | .active_low = 1, |
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61 | }, |
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62 | }; |
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63 | |||
64 | static struct gpio_keys_button sr3200_xd3200_gpio_keys[] __initdata = { |
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65 | { |
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66 | .desc = "reset", |
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67 | .type = EV_KEY, |
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68 | .code = KEY_RESTART, |
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69 | .debounce_interval = SR3200_XD3200_KEYS_DEBOUNCE_INTERVAL, |
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70 | .gpio = SR3200_XD3200_GPIO_BTN_RESET, |
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71 | .active_low = 1, |
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72 | }, |
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73 | }; |
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74 | |||
75 | static const struct ar8327_led_info sr3200_leds_qca833x[] = { |
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76 | AR8327_LED_INFO(PHY0_0, HW, "sr3200:green:lan1"), |
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77 | AR8327_LED_INFO(PHY1_0, HW, "sr3200:green:lan2"), |
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78 | AR8327_LED_INFO(PHY2_0, HW, "sr3200:green:lan3"), |
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79 | AR8327_LED_INFO(PHY3_0, HW, "sr3200:green:lan4"), |
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80 | AR8327_LED_INFO(PHY4_0, HW, "sr3200:green:wan"), |
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81 | }; |
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82 | |||
83 | static const struct ar8327_led_info xd3200_leds_qca833x[] = { |
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84 | AR8327_LED_INFO(PHY1_0, HW, "xd3200:green:lan"), |
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85 | AR8327_LED_INFO(PHY2_0, HW, "xd3200:green:wan"), |
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86 | }; |
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87 | |||
88 | /* Blink rate: 1 Gbps -> 8 hz, 100 Mbs -> 4 Hz, 10 Mbps -> 2 Hz */ |
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89 | static struct ar8327_led_cfg sr3200_xd3200_qca833x_led_cfg = { |
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90 | .led_ctrl0 = 0xcf37cf37, |
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91 | .led_ctrl1 = 0xcf37cf37, |
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92 | .led_ctrl2 = 0xcf37cf37, |
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93 | .led_ctrl3 = 0x0, |
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94 | .open_drain = true, |
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95 | }; |
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96 | |||
97 | static struct ar8327_pad_cfg sr3200_xd3200_qca833x_pad0_cfg = { |
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98 | .mode = AR8327_PAD_MAC_SGMII, |
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99 | .sgmii_delay_en = true, |
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100 | }; |
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101 | |||
102 | static struct ar8327_platform_data sr3200_xd3200_qca833x_data = { |
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103 | .pad0_cfg = &sr3200_xd3200_qca833x_pad0_cfg, |
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104 | .port0_cfg = { |
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105 | .force_link = 1, |
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106 | .speed = AR8327_PORT_SPEED_1000, |
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107 | .duplex = 1, |
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108 | .txpause = 1, |
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109 | .rxpause = 1, |
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110 | }, |
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111 | .led_cfg = &sr3200_xd3200_qca833x_led_cfg, |
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112 | }; |
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113 | |||
114 | static struct mdio_board_info sr3200_xd3200_mdio0_info[] = { |
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115 | { |
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116 | .bus_id = "ag71xx-mdio.0", |
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3 | office | 117 | .phy_addr = 0, |
1 | office | 118 | .platform_data = &sr3200_xd3200_qca833x_data, |
119 | }, |
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120 | }; |
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121 | |||
122 | static void __init sr3200_xd3200_common_setup(void) |
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123 | { |
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124 | u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000); |
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125 | |||
126 | ath79_register_m25p80(NULL); |
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127 | |||
128 | ath79_register_mdio(0, 0x0); |
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129 | mdiobus_register_board_info(sr3200_xd3200_mdio0_info, |
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130 | ARRAY_SIZE(sr3200_xd3200_mdio0_info)); |
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131 | |||
132 | /* GMAC0 is connected to QCA8334/QCA8337N switch */ |
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133 | ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; |
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134 | ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; |
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135 | ath79_eth0_data.phy_mask = BIT(0); |
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136 | ath79_eth0_data.speed = SPEED_1000; |
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137 | ath79_eth0_data.duplex = DUPLEX_FULL; |
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138 | |||
139 | ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0); |
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140 | ath79_register_eth(0); |
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141 | |||
142 | ath79_register_wmac(mac + 0x1000, NULL); |
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143 | |||
144 | ap91_pci_init(mac + 0x5000, NULL); |
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145 | |||
146 | ath79_gpio_direction_select(SR3200_XD3200_GPIO_LED_SYSTEM, true); |
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147 | ath79_gpio_direction_select(SR3200_XD3200_GPIO_LED_WLAN2G, true); |
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148 | |||
149 | /* Mute LEDs on boot */ |
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150 | gpio_set_value(SR3200_XD3200_GPIO_LED_SYSTEM, 1); |
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151 | gpio_set_value(SR3200_XD3200_GPIO_LED_WLAN2G, 1); |
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152 | |||
153 | ath79_gpio_output_select(SR3200_XD3200_GPIO_LED_SYSTEM, 0); |
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154 | ath79_gpio_output_select(SR3200_XD3200_GPIO_LED_WLAN2G, 0); |
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155 | |||
156 | ath79_register_gpio_keys_polled(-1, SR3200_XD3200_KEYS_POLL_INTERVAL, |
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157 | ARRAY_SIZE(sr3200_xd3200_gpio_keys), |
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158 | sr3200_xd3200_gpio_keys); |
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159 | } |
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160 | |||
161 | static void __init sr3200_setup(void) |
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162 | { |
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163 | sr3200_xd3200_qca833x_data.leds = sr3200_leds_qca833x; |
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164 | sr3200_xd3200_qca833x_data.num_leds = ARRAY_SIZE(sr3200_leds_qca833x); |
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165 | |||
166 | sr3200_xd3200_common_setup(); |
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167 | |||
168 | ath79_register_leds_gpio(-1, ARRAY_SIZE(sr3200_leds_gpio), |
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169 | sr3200_leds_gpio); |
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170 | |||
171 | ath79_register_usb(); |
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172 | } |
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173 | |||
174 | MIPS_MACHINE(ATH79_MACH_SR3200, "SR3200", "YunCore SR3200", sr3200_setup); |
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175 | |||
176 | static void __init xd3200_setup(void) |
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177 | { |
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178 | sr3200_xd3200_qca833x_data.leds = xd3200_leds_qca833x; |
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179 | sr3200_xd3200_qca833x_data.num_leds = ARRAY_SIZE(xd3200_leds_qca833x); |
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180 | |||
181 | sr3200_xd3200_common_setup(); |
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182 | |||
183 | ath79_register_leds_gpio(-1, ARRAY_SIZE(xd3200_leds_gpio), |
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184 | xd3200_leds_gpio); |
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185 | } |
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186 | |||
187 | MIPS_MACHINE(ATH79_MACH_XD3200, "XD3200", "YunCore XD3200", xd3200_setup); |