OpenWrt – Blame information for rev 3
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Rev | Author | Line No. | Line |
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1 | office | 1 | /* |
2 | * EnGenius ESR900 board support |
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3 | * |
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4 | * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org> |
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5 | * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> |
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6 | * |
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7 | * This program is free software; you can redistribute it and/or modify it |
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8 | * under the terms of the GNU General Public License version 2 as published |
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9 | * by the Free Software Foundation. |
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10 | */ |
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11 | |||
12 | #define pr_fmt(fmt) "esr900: " fmt |
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13 | |||
14 | #include <linux/platform_device.h> |
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15 | #include <linux/ar8216_platform.h> |
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16 | |||
17 | #include <asm/mach-ath79/ar71xx_regs.h> |
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18 | |||
19 | #include "common.h" |
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20 | #include "pci.h" |
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21 | #include "dev-ap9x-pci.h" |
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22 | #include "dev-gpio-buttons.h" |
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23 | #include "dev-eth.h" |
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24 | #include "dev-leds-gpio.h" |
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25 | #include "dev-m25p80.h" |
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26 | #include "dev-usb.h" |
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27 | #include "dev-wmac.h" |
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28 | #include "machtypes.h" |
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29 | #include "nvram.h" |
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30 | |||
31 | #define ESR900_GPIO_LED_POWER 2 |
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32 | #define ESR900_GPIO_LED_WLAN_2G 13 |
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33 | #define ESR900_GPIO_LED_WPS_BLUE 19 |
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34 | #define ESR900_GPIO_LED_WPS_AMBER 22 |
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35 | #define ESR900_GPIO_LED_WLAN_5G 23 |
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36 | |||
37 | #define ESR900_GPIO_BTN_WPS 16 |
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38 | #define ESR900_GPIO_BTN_RESET 17 |
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39 | |||
40 | #define ESR900_KEYS_POLL_INTERVAL 20 /* msecs */ |
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41 | #define ESR900_KEYS_DEBOUNCE_INTERVAL (3 * ESR900_KEYS_POLL_INTERVAL) |
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42 | |||
43 | #define ESR900_CALDATA_ADDR 0x1fff0000 |
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44 | #define ESR900_WMAC_CALDATA_OFFSET 0x1000 |
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45 | #define ESR900_PCIE_CALDATA_OFFSET 0x5000 |
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46 | |||
47 | #define ESR900_CONFIG_ADDR 0x1f030000 |
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48 | #define ESR900_CONFIG_SIZE 0x10000 |
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49 | |||
50 | #define ESR900_LAN_PHYMASK BIT(0) |
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51 | #define ESR900_WAN_PHYMASK BIT(5) |
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52 | #define ESR900_MDIO_MASK (~(ESR900_LAN_PHYMASK | ESR900_WAN_PHYMASK)) |
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53 | |||
54 | static struct gpio_led esr900_leds_gpio[] __initdata = { |
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55 | { |
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56 | .name = "engenius:amber:power", |
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57 | .gpio = ESR900_GPIO_LED_POWER, |
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58 | .active_low = 1, |
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59 | }, |
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60 | { |
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61 | .name = "engenius:blue:wlan-2g", |
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62 | .gpio = ESR900_GPIO_LED_WLAN_2G, |
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63 | .active_low = 1, |
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64 | }, |
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65 | { |
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66 | .name = "engenius:blue:wps", |
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67 | .gpio = ESR900_GPIO_LED_WPS_BLUE, |
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68 | .active_low = 1, |
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69 | }, |
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70 | { |
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71 | .name = "engenius:amber:wps", |
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72 | .gpio = ESR900_GPIO_LED_WPS_AMBER, |
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73 | .active_low = 1, |
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74 | }, |
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75 | { |
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76 | .name = "engenius:blue:wlan-5g", |
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77 | .gpio = ESR900_GPIO_LED_WLAN_5G, |
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78 | .active_low = 1, |
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79 | } |
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80 | }; |
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81 | |||
82 | static struct gpio_keys_button esr900_gpio_keys[] __initdata = { |
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83 | { |
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84 | .desc = "WPS button", |
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85 | .type = EV_KEY, |
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86 | .code = KEY_WPS_BUTTON, |
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87 | .debounce_interval = ESR900_KEYS_DEBOUNCE_INTERVAL, |
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88 | .gpio = ESR900_GPIO_BTN_WPS, |
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89 | .active_low = 1, |
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90 | }, |
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91 | { |
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92 | .desc = "Reset button", |
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93 | .type = EV_KEY, |
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94 | .code = KEY_RESTART, |
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95 | .debounce_interval = ESR900_KEYS_DEBOUNCE_INTERVAL, |
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96 | .gpio = ESR900_GPIO_BTN_RESET, |
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97 | .active_low = 1, |
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98 | }, |
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99 | }; |
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100 | |||
101 | static struct ar8327_pad_cfg esr900_ar8327_pad0_cfg = { |
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102 | /* GMAC0 of the AR8337 switch is connected to GMAC0 via RGMII */ |
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103 | .mode = AR8327_PAD_MAC_RGMII, |
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104 | .txclk_delay_en = true, |
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105 | .rxclk_delay_en = true, |
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106 | .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, |
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107 | .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, |
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108 | }; |
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109 | |||
110 | static struct ar8327_pad_cfg esr900_ar8327_pad6_cfg = { |
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111 | /* GMAC6 of the AR8337 switch is connected to GMAC1 via SGMII */ |
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112 | .mode = AR8327_PAD_MAC_SGMII, |
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113 | .rxclk_delay_en = true, |
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114 | .rxclk_delay_sel = AR8327_CLK_DELAY_SEL0, |
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115 | }; |
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116 | |||
117 | static struct ar8327_platform_data esr900_ar8327_data = { |
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118 | .pad0_cfg = &esr900_ar8327_pad0_cfg, |
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119 | .pad6_cfg = &esr900_ar8327_pad6_cfg, |
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120 | .port0_cfg = { |
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121 | .force_link = 1, |
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122 | .speed = AR8327_PORT_SPEED_1000, |
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123 | .duplex = 1, |
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124 | .txpause = 1, |
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125 | .rxpause = 1, |
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126 | }, |
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127 | .port6_cfg = { |
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128 | .force_link = 1, |
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129 | .speed = AR8327_PORT_SPEED_1000, |
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130 | .duplex = 1, |
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131 | .txpause = 1, |
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132 | .rxpause = 1, |
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133 | }, |
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134 | }; |
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135 | |||
136 | static struct mdio_board_info esr900_mdio0_info[] = { |
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137 | { |
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138 | .bus_id = "ag71xx-mdio.0", |
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3 | office | 139 | .phy_addr = 0, |
1 | office | 140 | .platform_data = &esr900_ar8327_data, |
141 | }, |
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142 | }; |
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143 | |||
144 | static void __init esr900_setup(void) |
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145 | { |
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146 | const char *config = (char *) KSEG1ADDR(ESR900_CONFIG_ADDR); |
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147 | u8 *art = (u8 *) KSEG1ADDR(ESR900_CALDATA_ADDR); |
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148 | u8 lan_mac[ETH_ALEN]; |
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149 | u8 wlan0_mac[ETH_ALEN]; |
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150 | u8 wlan1_mac[ETH_ALEN]; |
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151 | |||
152 | if (ath79_nvram_parse_mac_addr(config, ESR900_CONFIG_SIZE, |
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153 | "ethaddr=", lan_mac) == 0) { |
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154 | ath79_init_local_mac(ath79_eth0_data.mac_addr, lan_mac); |
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155 | ath79_init_mac(wlan0_mac, lan_mac, 0); |
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156 | ath79_init_mac(wlan1_mac, lan_mac, 1); |
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157 | } else { |
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158 | pr_err("could not find ethaddr in u-boot environment\n"); |
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159 | } |
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160 | |||
161 | ath79_register_m25p80(NULL); |
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162 | |||
163 | ath79_register_leds_gpio(-1, ARRAY_SIZE(esr900_leds_gpio), |
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164 | esr900_leds_gpio); |
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165 | ath79_register_gpio_keys_polled(-1, ESR900_KEYS_POLL_INTERVAL, |
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166 | ARRAY_SIZE(esr900_gpio_keys), |
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167 | esr900_gpio_keys); |
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168 | |||
169 | ath79_register_usb(); |
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170 | |||
171 | ath79_register_wmac(art + ESR900_WMAC_CALDATA_OFFSET, wlan0_mac); |
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172 | |||
173 | ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); |
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174 | |||
175 | ath79_register_mdio(0, 0x0); |
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176 | |||
177 | mdiobus_register_board_info(esr900_mdio0_info, |
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178 | ARRAY_SIZE(esr900_mdio0_info)); |
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179 | |||
180 | /* GMAC0 is connected to the RMGII interface */ |
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181 | ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; |
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182 | ath79_eth0_data.phy_mask = ESR900_LAN_PHYMASK; |
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183 | ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; |
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184 | |||
185 | ath79_eth0_pll_data.pll_1000 = 0xa6000000; |
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186 | ath79_register_eth(0); |
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187 | |||
188 | /* GMAC1 is connected to the SGMII interface */ |
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189 | ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; |
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190 | ath79_eth1_data.speed = SPEED_1000; |
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191 | ath79_eth1_data.duplex = DUPLEX_FULL; |
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192 | |||
193 | ath79_eth1_pll_data.pll_1000 = 0x03000101; |
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194 | ath79_register_eth(1); |
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195 | |||
196 | ap91_pci_init(art + ESR900_PCIE_CALDATA_OFFSET, wlan1_mac); |
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197 | } |
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198 | |||
199 | MIPS_MACHINE(ATH79_MACH_ESR900, "ESR900", "EnGenius ESR900", esr900_setup); |
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200 |