OpenWrt – Blame information for rev 3
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1 | office | 1 | /* |
2 | * TP-LINK Archer C5/C7/TL-WDR4900 v2 board support |
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3 | * |
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4 | * Copyright (c) 2013 Gabor Juhos <juhosg@openwrt.org> |
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5 | * Copyright (c) 2014 施康成 <tenninjas@tenninjas.ca> |
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6 | * Copyright (c) 2014 Imre Kaloz <kaloz@openwrt.org> |
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7 | * |
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8 | * Based on the Qualcomm Atheros AP135/AP136 reference board support code |
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9 | * Copyright (c) 2012 Qualcomm Atheros |
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10 | * |
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11 | * Permission to use, copy, modify, and/or distribute this software for any |
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12 | * purpose with or without fee is hereby granted, provided that the above |
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13 | * copyright notice and this permission notice appear in all copies. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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16 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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17 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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18 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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19 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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20 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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21 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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22 | * |
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23 | */ |
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24 | |||
25 | #include <linux/pci.h> |
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26 | #include <linux/phy.h> |
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27 | #include <linux/gpio.h> |
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28 | #include <linux/platform_device.h> |
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29 | #include <linux/ath9k_platform.h> |
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30 | #include <linux/ar8216_platform.h> |
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31 | |||
32 | #include <asm/mach-ath79/ar71xx_regs.h> |
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33 | |||
34 | #include "common.h" |
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35 | #include "dev-ap9x-pci.h" |
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36 | #include "dev-eth.h" |
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37 | #include "dev-gpio-buttons.h" |
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38 | #include "dev-leds-gpio.h" |
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39 | #include "dev-m25p80.h" |
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40 | #include "dev-spi.h" |
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41 | #include "dev-usb.h" |
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42 | #include "dev-wmac.h" |
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43 | #include "machtypes.h" |
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44 | #include "pci.h" |
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45 | |||
46 | #define ARCHER_C7_GPIO_LED_WLAN2G 12 |
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47 | #define ARCHER_C7_GPIO_LED_SYSTEM 14 |
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48 | #define ARCHER_C7_GPIO_LED_QSS 15 |
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49 | #define ARCHER_C7_GPIO_LED_WLAN5G 17 |
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50 | #define ARCHER_C7_GPIO_LED_USB1 18 |
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51 | #define ARCHER_C7_GPIO_LED_USB2 19 |
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52 | |||
53 | #define ARCHER_C7_GPIO_BTN_RFKILL 13 |
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54 | #define ARCHER_C7_V2_GPIO_BTN_RFKILL 23 |
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55 | #define ARCHER_C7_GPIO_BTN_RESET 16 |
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56 | |||
57 | #define ARCHER_C7_GPIO_USB1_POWER 22 |
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58 | #define ARCHER_C7_GPIO_USB2_POWER 21 |
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59 | |||
60 | #define ARCHER_C7_KEYS_POLL_INTERVAL 20 /* msecs */ |
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61 | #define ARCHER_C7_KEYS_DEBOUNCE_INTERVAL (3 * ARCHER_C7_KEYS_POLL_INTERVAL) |
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62 | |||
63 | #define ARCHER_C7_WMAC_CALDATA_OFFSET 0x1000 |
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64 | #define ARCHER_C7_PCIE_CALDATA_OFFSET 0x5000 |
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65 | |||
66 | static const char *archer_c7_part_probes[] = { |
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67 | "tp-link", |
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68 | NULL, |
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69 | }; |
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70 | |||
71 | static struct flash_platform_data archer_c7_flash_data = { |
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72 | .part_probes = archer_c7_part_probes, |
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73 | }; |
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74 | |||
75 | static struct gpio_led archer_c7_leds_gpio[] __initdata = { |
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76 | { |
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77 | .name = "tp-link:blue:qss", |
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78 | .gpio = ARCHER_C7_GPIO_LED_QSS, |
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79 | .active_low = 1, |
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80 | }, |
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81 | { |
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82 | .name = "tp-link:blue:system", |
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83 | .gpio = ARCHER_C7_GPIO_LED_SYSTEM, |
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84 | .active_low = 1, |
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85 | }, |
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86 | { |
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87 | .name = "tp-link:blue:wlan2g", |
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88 | .gpio = ARCHER_C7_GPIO_LED_WLAN2G, |
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89 | .active_low = 1, |
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90 | }, |
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91 | { |
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92 | .name = "tp-link:blue:wlan5g", |
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93 | .gpio = ARCHER_C7_GPIO_LED_WLAN5G, |
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94 | .active_low = 1, |
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95 | }, |
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96 | { |
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97 | .name = "tp-link:green:usb1", |
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98 | .gpio = ARCHER_C7_GPIO_LED_USB1, |
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99 | .active_low = 1, |
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100 | }, |
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101 | { |
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102 | .name = "tp-link:green:usb2", |
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103 | .gpio = ARCHER_C7_GPIO_LED_USB2, |
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104 | .active_low = 1, |
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105 | }, |
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106 | }; |
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107 | |||
108 | static struct gpio_keys_button archer_c7_gpio_keys[] __initdata = { |
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109 | { |
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110 | .desc = "Reset button", |
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111 | .type = EV_KEY, |
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112 | .code = KEY_WPS_BUTTON, |
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113 | .debounce_interval = ARCHER_C7_KEYS_DEBOUNCE_INTERVAL, |
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114 | .gpio = ARCHER_C7_GPIO_BTN_RESET, |
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115 | .active_low = 1, |
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116 | }, |
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117 | { |
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118 | .desc = "RFKILL switch", |
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119 | .type = EV_SW, |
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120 | .code = KEY_RFKILL, |
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121 | .debounce_interval = ARCHER_C7_KEYS_DEBOUNCE_INTERVAL, |
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122 | .gpio = ARCHER_C7_GPIO_BTN_RFKILL, |
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123 | }, |
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124 | }; |
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125 | |||
126 | static struct gpio_keys_button archer_c7_v2_gpio_keys[] __initdata = { |
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127 | { |
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128 | .desc = "Reset button", |
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129 | .type = EV_KEY, |
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130 | .code = KEY_WPS_BUTTON, |
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131 | .debounce_interval = ARCHER_C7_KEYS_DEBOUNCE_INTERVAL, |
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132 | .gpio = ARCHER_C7_GPIO_BTN_RESET, |
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133 | .active_low = 1, |
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134 | }, |
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135 | { |
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136 | .desc = "RFKILL switch", |
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137 | .type = EV_SW, |
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138 | .code = KEY_RFKILL, |
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139 | .debounce_interval = ARCHER_C7_KEYS_DEBOUNCE_INTERVAL, |
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140 | .gpio = ARCHER_C7_V2_GPIO_BTN_RFKILL, |
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141 | }, |
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142 | }; |
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143 | |||
144 | static const struct ar8327_led_info archer_c7_leds_ar8327[] = { |
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145 | AR8327_LED_INFO(PHY0_0, HW, "tp-link:blue:wan"), |
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146 | AR8327_LED_INFO(PHY1_0, HW, "tp-link:blue:lan1"), |
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147 | AR8327_LED_INFO(PHY2_0, HW, "tp-link:blue:lan2"), |
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148 | AR8327_LED_INFO(PHY3_0, HW, "tp-link:blue:lan3"), |
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149 | AR8327_LED_INFO(PHY4_0, HW, "tp-link:blue:lan4"), |
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150 | }; |
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151 | |||
152 | /* GMAC0 of the AR8327 switch is connected to the QCA9558 SoC via SGMII */ |
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153 | static struct ar8327_pad_cfg archer_c7_ar8327_pad0_cfg = { |
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154 | .mode = AR8327_PAD_MAC_SGMII, |
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155 | .sgmii_delay_en = true, |
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156 | }; |
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157 | |||
158 | /* GMAC6 of the AR8327 switch is connected to the QCA9558 SoC via RGMII */ |
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159 | static struct ar8327_pad_cfg archer_c7_ar8327_pad6_cfg = { |
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160 | .mode = AR8327_PAD_MAC_RGMII, |
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161 | .txclk_delay_en = true, |
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162 | .rxclk_delay_en = true, |
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163 | .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, |
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164 | .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, |
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165 | }; |
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166 | |||
167 | static struct ar8327_led_cfg archer_c7_ar8327_led_cfg = { |
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168 | .led_ctrl0 = 0xc737c737, |
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169 | .led_ctrl1 = 0x00000000, |
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170 | .led_ctrl2 = 0x00000000, |
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171 | .led_ctrl3 = 0x0030c300, |
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172 | .open_drain = false, |
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173 | }; |
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174 | |||
175 | static struct ar8327_platform_data archer_c7_ar8327_data = { |
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176 | .pad0_cfg = &archer_c7_ar8327_pad0_cfg, |
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177 | .pad6_cfg = &archer_c7_ar8327_pad6_cfg, |
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178 | .port0_cfg = { |
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179 | .force_link = 1, |
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180 | .speed = AR8327_PORT_SPEED_1000, |
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181 | .duplex = 1, |
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182 | .txpause = 1, |
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183 | .rxpause = 1, |
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184 | }, |
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185 | .port6_cfg = { |
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186 | .force_link = 1, |
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187 | .speed = AR8327_PORT_SPEED_1000, |
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188 | .duplex = 1, |
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189 | .txpause = 1, |
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190 | .rxpause = 1, |
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191 | }, |
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192 | .led_cfg = &archer_c7_ar8327_led_cfg, |
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193 | .num_leds = ARRAY_SIZE(archer_c7_leds_ar8327), |
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194 | .leds = archer_c7_leds_ar8327, |
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195 | }; |
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196 | |||
197 | static struct mdio_board_info archer_c7_mdio0_info[] = { |
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198 | { |
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199 | .bus_id = "ag71xx-mdio.0", |
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3 | office | 200 | .phy_addr = 0, |
1 | office | 201 | .platform_data = &archer_c7_ar8327_data, |
202 | }, |
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203 | }; |
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204 | |||
205 | static void __init common_setup(bool pcie_slot) |
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206 | { |
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207 | u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); |
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208 | u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); |
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209 | u8 tmpmac[ETH_ALEN]; |
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210 | |||
211 | ath79_register_m25p80(&archer_c7_flash_data); |
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212 | ath79_register_leds_gpio(-1, ARRAY_SIZE(archer_c7_leds_gpio), |
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213 | archer_c7_leds_gpio); |
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214 | |||
215 | ath79_init_mac(tmpmac, mac, -1); |
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216 | ath79_register_wmac(art + ARCHER_C7_WMAC_CALDATA_OFFSET, tmpmac); |
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217 | |||
218 | if (pcie_slot) { |
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219 | ath79_register_pci(); |
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220 | } else { |
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221 | ath79_init_mac(tmpmac, mac, -1); |
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222 | ap9x_pci_setup_wmac_led_pin(0, 0); |
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223 | ap91_pci_init(art + ARCHER_C7_PCIE_CALDATA_OFFSET, tmpmac); |
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224 | } |
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225 | |||
226 | mdiobus_register_board_info(archer_c7_mdio0_info, |
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227 | ARRAY_SIZE(archer_c7_mdio0_info)); |
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228 | ath79_register_mdio(0, 0x0); |
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229 | |||
230 | ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); |
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231 | |||
232 | /* GMAC0 is connected to the RMGII interface */ |
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233 | ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; |
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234 | ath79_eth0_data.phy_mask = BIT(0); |
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235 | ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; |
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236 | ath79_eth0_pll_data.pll_1000 = 0x56000000; |
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237 | |||
238 | ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); |
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239 | ath79_register_eth(0); |
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240 | |||
241 | /* GMAC1 is connected to the SGMII interface */ |
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242 | ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; |
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243 | ath79_eth1_data.speed = SPEED_1000; |
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244 | ath79_eth1_data.duplex = DUPLEX_FULL; |
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245 | ath79_eth1_pll_data.pll_1000 = 0x03000101; |
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246 | |||
247 | ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); |
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248 | ath79_register_eth(1); |
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249 | |||
250 | gpio_request_one(ARCHER_C7_GPIO_USB1_POWER, |
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251 | GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, |
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252 | "USB1 power"); |
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253 | gpio_request_one(ARCHER_C7_GPIO_USB2_POWER, |
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254 | GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, |
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255 | "USB2 power"); |
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256 | ath79_register_usb(); |
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257 | } |
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258 | |||
259 | static void __init archer_c5_setup(void) |
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260 | { |
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261 | ath79_register_gpio_keys_polled(-1, ARCHER_C7_KEYS_POLL_INTERVAL, |
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262 | ARRAY_SIZE(archer_c7_gpio_keys), |
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263 | archer_c7_gpio_keys); |
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264 | common_setup(true); |
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265 | } |
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266 | |||
267 | MIPS_MACHINE(ATH79_MACH_ARCHER_C5, "ARCHER-C5", "TP-LINK Archer C5", |
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268 | archer_c5_setup); |
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269 | |||
270 | static void __init archer_c7_setup(void) |
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271 | { |
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272 | ath79_register_gpio_keys_polled(-1, ARCHER_C7_KEYS_POLL_INTERVAL, |
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273 | ARRAY_SIZE(archer_c7_gpio_keys), |
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274 | archer_c7_gpio_keys); |
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275 | common_setup(true); |
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276 | } |
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277 | |||
278 | MIPS_MACHINE(ATH79_MACH_ARCHER_C7, "ARCHER-C7", "TP-LINK Archer C7", |
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279 | archer_c7_setup); |
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280 | |||
281 | static void __init archer_c7_v2_setup(void) |
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282 | { |
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283 | ath79_register_gpio_keys_polled(-1, ARCHER_C7_KEYS_POLL_INTERVAL, |
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284 | ARRAY_SIZE(archer_c7_v2_gpio_keys), |
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285 | archer_c7_v2_gpio_keys); |
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286 | common_setup(true); |
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287 | } |
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288 | |||
289 | MIPS_MACHINE(ATH79_MACH_ARCHER_C7_V2, "ARCHER-C7-V2", "TP-LINK Archer C7", |
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290 | archer_c7_v2_setup); |
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291 | |||
292 | static void __init tl_wdr4900_v2_setup(void) |
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293 | { |
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294 | ath79_register_gpio_keys_polled(-1, ARCHER_C7_KEYS_POLL_INTERVAL, |
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295 | ARRAY_SIZE(archer_c7_gpio_keys), |
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296 | archer_c7_gpio_keys); |
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297 | common_setup(false); |
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298 | } |
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299 | |||
300 | MIPS_MACHINE(ATH79_MACH_TL_WDR4900_V2, "TL-WDR4900-v2", "TP-LINK TL-WDR4900 v2", |
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301 | tl_wdr4900_v2_setup) |
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302 |