OpenWrt – Blame information for rev 3
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Rev | Author | Line No. | Line |
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1 | office | 1 | /* |
2 | * Atheros AP132 reference board support |
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3 | * |
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4 | * Copyright (c) 2012 Qualcomm Atheros |
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5 | * Copyright (c) 2012 Gabor Juhos <juhosg@openwrt.org> |
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6 | * Copyright (c) 2013 Embedded Wireless GmbH <info@embeddedwireless.de> |
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7 | * |
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8 | * Permission to use, copy, modify, and/or distribute this software for any |
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9 | * purpose with or without fee is hereby granted, provided that the above |
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10 | * copyright notice and this permission notice appear in all copies. |
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11 | * |
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12 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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13 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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14 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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15 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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16 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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17 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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18 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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19 | * |
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20 | */ |
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21 | |||
22 | #include <linux/platform_device.h> |
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23 | #include <linux/ar8216_platform.h> |
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24 | |||
25 | #include <asm/mach-ath79/ar71xx_regs.h> |
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26 | |||
27 | #include "common.h" |
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28 | #include "dev-ap9x-pci.h" |
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29 | #include "dev-gpio-buttons.h" |
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30 | #include "dev-eth.h" |
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31 | #include "dev-leds-gpio.h" |
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32 | #include "dev-m25p80.h" |
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33 | #include "dev-usb.h" |
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34 | #include "dev-wmac.h" |
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35 | #include "machtypes.h" |
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36 | |||
37 | #define AP132_GPIO_LED_USB 4 |
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38 | #define AP132_GPIO_LED_WLAN_5G 12 |
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39 | #define AP132_GPIO_LED_WLAN_2G 13 |
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40 | #define AP132_GPIO_LED_STATUS_RED 14 |
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41 | #define AP132_GPIO_LED_WPS_RED 15 |
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42 | |||
43 | #define AP132_GPIO_BTN_WPS 16 |
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44 | |||
45 | #define AP132_KEYS_POLL_INTERVAL 20 /* msecs */ |
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46 | #define AP132_KEYS_DEBOUNCE_INTERVAL (3 * AP132_KEYS_POLL_INTERVAL) |
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47 | |||
48 | #define AP132_MAC0_OFFSET 0 |
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49 | #define AP132_WMAC_CALDATA_OFFSET 0x1000 |
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50 | |||
51 | static struct gpio_led ap132_leds_gpio[] __initdata = { |
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52 | { |
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53 | .name = "ap132:red:status", |
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54 | .gpio = AP132_GPIO_LED_STATUS_RED, |
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55 | .active_low = 1, |
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56 | }, |
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57 | { |
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58 | .name = "ap132:red:wps", |
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59 | .gpio = AP132_GPIO_LED_WPS_RED, |
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60 | .active_low = 1, |
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61 | }, |
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62 | { |
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63 | .name = "ap132:red:wlan-2g", |
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64 | .gpio = AP132_GPIO_LED_WLAN_2G, |
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65 | .active_low = 1, |
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66 | }, |
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67 | { |
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68 | .name = "ap132:red:usb", |
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69 | .gpio = AP132_GPIO_LED_USB, |
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70 | .active_low = 1, |
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71 | } |
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72 | }; |
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73 | |||
74 | static struct gpio_keys_button ap132_gpio_keys[] __initdata = { |
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75 | { |
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76 | .desc = "WPS button", |
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77 | .type = EV_KEY, |
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78 | .code = KEY_WPS_BUTTON, |
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79 | .debounce_interval = AP132_KEYS_DEBOUNCE_INTERVAL, |
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80 | .gpio = AP132_GPIO_BTN_WPS, |
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81 | .active_low = 1, |
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82 | }, |
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83 | }; |
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84 | |||
85 | static struct ar8327_pad_cfg ap132_ar8327_pad0_cfg; |
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86 | |||
87 | static struct ar8327_platform_data ap132_ar8327_data = { |
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88 | .pad0_cfg = &ap132_ar8327_pad0_cfg, |
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89 | .port0_cfg = { |
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90 | .force_link = 1, |
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91 | .speed = AR8327_PORT_SPEED_1000, |
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92 | .duplex = 1, |
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93 | .txpause = 1, |
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94 | .rxpause = 1, |
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95 | }, |
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96 | }; |
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97 | |||
98 | static struct mdio_board_info ap132_mdio1_info[] = { |
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99 | { |
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100 | .bus_id = "ag71xx-mdio.1", |
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3 | office | 101 | .phy_addr = 0, |
1 | office | 102 | .platform_data = &ap132_ar8327_data, |
103 | }, |
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104 | }; |
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105 | |||
106 | static void __init ap132_mdio_setup(void) |
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107 | { |
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108 | void __iomem *base; |
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109 | u32 t; |
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110 | |||
111 | #define GPIO_IN_ENABLE3_ADDRESS 0x0050 |
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112 | #define GPIO_IN_ENABLE3_MII_GE1_MDI_MASK 0x00ff0000 |
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113 | #define GPIO_IN_ENABLE3_MII_GE1_MDI_LSB 16 |
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114 | #define GPIO_IN_ENABLE3_MII_GE1_MDI_SET(x) (((x) << GPIO_IN_ENABLE3_MII_GE1_MDI_LSB) & GPIO_IN_ENABLE3_MII_GE1_MDI_MASK) |
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115 | #define GPIO_OUT_FUNCTION4_ADDRESS 0x003c |
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116 | #define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_MASK 0xff000000 |
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117 | #define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_LSB 24 |
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118 | #define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_SET(x) (((x) << GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_LSB) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_MASK) |
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119 | #define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK 0x0000ff00 |
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120 | #define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_LSB 8 |
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121 | #define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_SET(x) (((x) << GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_LSB) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK) |
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122 | |||
123 | base = ioremap(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE); |
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124 | |||
125 | t = __raw_readl(base + GPIO_IN_ENABLE3_ADDRESS); |
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126 | t &= ~GPIO_IN_ENABLE3_MII_GE1_MDI_MASK; |
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127 | t |= GPIO_IN_ENABLE3_MII_GE1_MDI_SET(19); |
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128 | __raw_writel(t, base + GPIO_IN_ENABLE3_ADDRESS); |
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129 | |||
130 | |||
131 | __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << 19), base + AR71XX_GPIO_REG_OE); |
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132 | |||
133 | __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << 17), base + AR71XX_GPIO_REG_OE); |
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134 | |||
135 | |||
136 | t = __raw_readl(base + GPIO_OUT_FUNCTION4_ADDRESS); |
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137 | t &= ~(GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_MASK | GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK); |
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138 | t |= GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_SET(0x20) | GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_SET(0x21); |
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139 | __raw_writel(t, base + GPIO_OUT_FUNCTION4_ADDRESS); |
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140 | |||
141 | iounmap(base); |
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142 | |||
143 | } |
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144 | |||
145 | static void __init ap132_setup(void) |
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146 | { |
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147 | u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); |
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148 | |||
149 | ath79_register_m25p80(NULL); |
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150 | |||
151 | ath79_register_leds_gpio(-1, ARRAY_SIZE(ap132_leds_gpio), |
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152 | ap132_leds_gpio); |
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153 | ath79_register_gpio_keys_polled(-1, AP132_KEYS_POLL_INTERVAL, |
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154 | ARRAY_SIZE(ap132_gpio_keys), |
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155 | ap132_gpio_keys); |
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156 | |||
157 | ath79_register_usb(); |
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158 | |||
159 | ath79_register_wmac(art + AP132_WMAC_CALDATA_OFFSET, NULL); |
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160 | |||
161 | /* GMAC0 of the AR8327 switch is connected to GMAC1 via SGMII */ |
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162 | ap132_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_SGMII; |
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163 | ap132_ar8327_pad0_cfg.sgmii_delay_en = true; |
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164 | |||
165 | ath79_eth1_pll_data.pll_1000 = 0x03000101; |
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166 | |||
167 | ap132_mdio_setup(); |
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168 | |||
169 | ath79_register_mdio(1, 0x0); |
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170 | |||
171 | ath79_init_mac(ath79_eth1_data.mac_addr, art + AP132_MAC0_OFFSET, 0); |
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172 | |||
173 | mdiobus_register_board_info(ap132_mdio1_info, |
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174 | ARRAY_SIZE(ap132_mdio1_info)); |
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175 | |||
176 | /* GMAC1 is connected to the SGMII interface */ |
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177 | ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; |
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178 | ath79_eth1_data.speed = SPEED_1000; |
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179 | ath79_eth1_data.duplex = DUPLEX_FULL; |
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180 | ath79_eth1_data.phy_mask = BIT(0); |
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181 | ath79_eth1_data.mii_bus_dev = &ath79_mdio1_device.dev; |
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182 | |||
183 | ath79_register_eth(1); |
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184 | } |
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185 | |||
186 | MIPS_MACHINE(ATH79_MACH_AP132, "AP132", |
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187 | "Atheros AP132 reference board", |
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188 | ap132_setup); |
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189 |