OpenWrt – Blame information for rev 3
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1 | office | 1 | /****************************************************************************** |
2 | ** |
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3 | ** FILE NAME : ifxmips_atm_core.c |
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4 | ** PROJECT : UEIP |
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5 | ** MODULES : ATM |
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6 | ** |
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7 | ** DATE : 7 Jul 2009 |
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8 | ** AUTHOR : Xu Liang |
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9 | ** DESCRIPTION : ATM driver common source file (core functions) |
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10 | ** COPYRIGHT : Copyright (c) 2006 |
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11 | ** Infineon Technologies AG |
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12 | ** Am Campeon 1-12, 85579 Neubiberg, Germany |
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13 | ** |
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14 | ** This program is free software; you can redistribute it and/or modify |
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15 | ** it under the terms of the GNU General Public License as published by |
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16 | ** the Free Software Foundation; either version 2 of the License, or |
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17 | ** (at your option) any later version. |
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18 | ** |
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19 | ** HISTORY |
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20 | ** $Date $Author $Comment |
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21 | ** 07 JUL 2009 Xu Liang Init Version |
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22 | ** |
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23 | ** Copyright 2017 Alexander Couzens <lynxis@fe80.eu> |
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24 | *******************************************************************************/ |
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25 | |||
26 | #define IFX_ATM_VER_MAJOR 1 |
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27 | #define IFX_ATM_VER_MID 0 |
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28 | #define IFX_ATM_VER_MINOR 26 |
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29 | |||
30 | #include <linux/kernel.h> |
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31 | #include <linux/module.h> |
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32 | #include <linux/version.h> |
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33 | #include <linux/types.h> |
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34 | #include <linux/errno.h> |
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35 | #include <linux/proc_fs.h> |
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36 | #include <linux/init.h> |
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37 | #include <linux/ioctl.h> |
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38 | #include <linux/atmdev.h> |
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39 | #include <linux/platform_device.h> |
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40 | #include <linux/of_device.h> |
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41 | #include <linux/atm.h> |
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42 | #include <linux/clk.h> |
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43 | #include <linux/interrupt.h> |
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44 | #ifdef CONFIG_XFRM |
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45 | #include <net/xfrm.h> |
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46 | #endif |
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47 | |||
48 | #include <lantiq_soc.h> |
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49 | |||
50 | #include "ifxmips_atm_core.h" |
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51 | |||
52 | #define MODULE_PARM_ARRAY(a, b) module_param_array(a, int, NULL, 0) |
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53 | #define MODULE_PARM(a, b) module_param(a, int, 0) |
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54 | |||
55 | /*! |
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56 | \brief QSB cell delay variation due to concurrency |
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57 | */ |
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58 | static int qsb_tau = 1; /* QSB cell delay variation due to concurrency */ |
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59 | /*! |
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60 | \brief QSB scheduler burst length |
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61 | */ |
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62 | static int qsb_srvm = 0x0F; /* QSB scheduler burst length */ |
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63 | /*! |
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64 | \brief QSB time step, all legal values are 1, 2, 4 |
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65 | */ |
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66 | static int qsb_tstep = 4 ; /* QSB time step, all legal values are 1, 2, 4 */ |
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67 | |||
68 | /*! |
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69 | \brief Write descriptor delay |
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70 | */ |
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71 | static int write_descriptor_delay = 0x20; /* Write descriptor delay */ |
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72 | |||
73 | /*! |
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74 | \brief AAL5 padding byte ('~') |
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75 | */ |
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76 | static int aal5_fill_pattern = 0x007E; /* AAL5 padding byte ('~') */ |
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77 | /*! |
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78 | \brief Max frame size for RX |
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79 | */ |
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80 | static int aal5r_max_packet_size = 0x0700; /* Max frame size for RX */ |
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81 | /*! |
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82 | \brief Min frame size for RX |
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83 | */ |
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84 | static int aal5r_min_packet_size = 0x0000; /* Min frame size for RX */ |
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85 | /*! |
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86 | \brief Max frame size for TX |
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87 | */ |
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88 | static int aal5s_max_packet_size = 0x0700; /* Max frame size for TX */ |
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89 | /*! |
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90 | \brief Min frame size for TX |
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91 | */ |
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92 | static int aal5s_min_packet_size = 0x0000; /* Min frame size for TX */ |
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93 | /*! |
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94 | \brief Drop error packet in RX path |
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95 | */ |
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96 | static int aal5r_drop_error_packet = 1; /* Drop error packet in RX path */ |
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97 | |||
98 | /*! |
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99 | \brief Number of descriptors per DMA RX channel |
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100 | */ |
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101 | static int dma_rx_descriptor_length = 128; /* Number of descriptors per DMA RX channel */ |
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102 | /*! |
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103 | \brief Number of descriptors per DMA TX channel |
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104 | */ |
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105 | static int dma_tx_descriptor_length = 64; /* Number of descriptors per DMA TX channel */ |
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106 | /*! |
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107 | \brief PPE core clock cycles between descriptor write and effectiveness in external RAM |
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108 | */ |
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109 | static int dma_rx_clp1_descriptor_threshold = 38; |
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110 | /*@}*/ |
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111 | |||
112 | MODULE_PARM(qsb_tau, "i"); |
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113 | MODULE_PARM_DESC(qsb_tau, "Cell delay variation. Value must be > 0"); |
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114 | MODULE_PARM(qsb_srvm, "i"); |
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115 | MODULE_PARM_DESC(qsb_srvm, "Maximum burst size"); |
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116 | MODULE_PARM(qsb_tstep, "i"); |
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117 | MODULE_PARM_DESC(qsb_tstep, "n*32 cycles per sbs cycles n=1,2,4"); |
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118 | |||
119 | MODULE_PARM(write_descriptor_delay, "i"); |
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120 | MODULE_PARM_DESC(write_descriptor_delay, "PPE core clock cycles between descriptor write and effectiveness in external RAM"); |
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121 | |||
122 | MODULE_PARM(aal5_fill_pattern, "i"); |
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123 | MODULE_PARM_DESC(aal5_fill_pattern, "Filling pattern (PAD) for AAL5 frames"); |
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124 | MODULE_PARM(aal5r_max_packet_size, "i"); |
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125 | MODULE_PARM_DESC(aal5r_max_packet_size, "Max packet size in byte for downstream AAL5 frames"); |
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126 | MODULE_PARM(aal5r_min_packet_size, "i"); |
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127 | MODULE_PARM_DESC(aal5r_min_packet_size, "Min packet size in byte for downstream AAL5 frames"); |
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128 | MODULE_PARM(aal5s_max_packet_size, "i"); |
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129 | MODULE_PARM_DESC(aal5s_max_packet_size, "Max packet size in byte for upstream AAL5 frames"); |
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130 | MODULE_PARM(aal5s_min_packet_size, "i"); |
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131 | MODULE_PARM_DESC(aal5s_min_packet_size, "Min packet size in byte for upstream AAL5 frames"); |
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132 | MODULE_PARM(aal5r_drop_error_packet, "i"); |
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133 | MODULE_PARM_DESC(aal5r_drop_error_packet, "Non-zero value to drop error packet for downstream"); |
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134 | |||
135 | MODULE_PARM(dma_rx_descriptor_length, "i"); |
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136 | MODULE_PARM_DESC(dma_rx_descriptor_length, "Number of descriptor assigned to DMA RX channel (>16)"); |
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137 | MODULE_PARM(dma_tx_descriptor_length, "i"); |
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138 | MODULE_PARM_DESC(dma_tx_descriptor_length, "Number of descriptor assigned to DMA TX channel (>16)"); |
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139 | MODULE_PARM(dma_rx_clp1_descriptor_threshold, "i"); |
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140 | MODULE_PARM_DESC(dma_rx_clp1_descriptor_threshold, "Descriptor threshold for cells with cell loss priority 1"); |
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141 | |||
142 | |||
143 | |||
144 | /* |
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145 | * #################################### |
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146 | * Definition |
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147 | * #################################### |
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148 | */ |
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149 | |||
150 | #ifdef CONFIG_AMAZON_SE |
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151 | #define ENABLE_LESS_CACHE_INV 1 |
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152 | #define LESS_CACHE_INV_LEN 96 |
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153 | #endif |
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154 | |||
155 | #define DUMP_SKB_LEN ~0 |
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156 | |||
157 | |||
158 | |||
159 | /* |
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160 | * #################################### |
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161 | * Declaration |
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162 | * #################################### |
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163 | */ |
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164 | |||
165 | /* |
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166 | * Network Operations |
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167 | */ |
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168 | static int ppe_ioctl(struct atm_dev *, unsigned int, void *); |
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169 | static int ppe_open(struct atm_vcc *); |
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170 | static void ppe_close(struct atm_vcc *); |
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171 | static int ppe_send(struct atm_vcc *, struct sk_buff *); |
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172 | static int ppe_send_oam(struct atm_vcc *, void *, int); |
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173 | static int ppe_change_qos(struct atm_vcc *, struct atm_qos *, int); |
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174 | |||
175 | /* |
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176 | * ADSL LED |
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177 | */ |
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178 | static inline void adsl_led_flash(void); |
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179 | |||
180 | /* |
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181 | * 64-bit operation used by MIB calculation |
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182 | */ |
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183 | static inline void u64_add_u32(ppe_u64_t, unsigned int, ppe_u64_t *); |
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184 | |||
185 | /* |
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186 | * buffer manage functions |
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187 | */ |
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188 | static inline struct sk_buff* alloc_skb_rx(void); |
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189 | static inline struct sk_buff* alloc_skb_tx(unsigned int); |
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3 | office | 190 | struct sk_buff* atm_alloc_tx(struct atm_vcc *, unsigned int); |
1 | office | 191 | static inline void atm_free_tx_skb_vcc(struct sk_buff *, struct atm_vcc *); |
192 | static inline struct sk_buff *get_skb_rx_pointer(unsigned int); |
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193 | static inline int get_tx_desc(unsigned int); |
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194 | |||
195 | /* |
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196 | * mailbox handler and signal function |
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197 | */ |
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198 | static inline void mailbox_oam_rx_handler(void); |
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199 | static inline void mailbox_aal_rx_handler(void); |
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200 | static irqreturn_t mailbox_irq_handler(int, void *); |
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201 | static inline void mailbox_signal(unsigned int, int); |
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202 | static void do_ppe_tasklet(unsigned long); |
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203 | DECLARE_TASKLET(g_dma_tasklet, do_ppe_tasklet, 0); |
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204 | |||
205 | /* |
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206 | * QSB & HTU setting functions |
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207 | */ |
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208 | static void set_qsb(struct atm_vcc *, struct atm_qos *, unsigned int); |
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209 | static void qsb_global_set(void); |
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210 | static inline void set_htu_entry(unsigned int, unsigned int, unsigned int, int, int); |
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211 | static inline void clear_htu_entry(unsigned int); |
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212 | static void validate_oam_htu_entry(void); |
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213 | static void invalidate_oam_htu_entry(void); |
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214 | |||
215 | /* |
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216 | * look up for connection ID |
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217 | */ |
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218 | static inline int find_vpi(unsigned int); |
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219 | static inline int find_vpivci(unsigned int, unsigned int); |
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220 | static inline int find_vcc(struct atm_vcc *); |
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221 | |||
222 | static inline int ifx_atm_version(const struct ltq_atm_ops *ops, char *); |
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223 | |||
224 | /* |
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225 | * Init & clean-up functions |
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226 | */ |
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227 | static inline void check_parameters(void); |
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228 | static inline int init_priv_data(void); |
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229 | static inline void clear_priv_data(void); |
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230 | static inline void init_rx_tables(void); |
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231 | static inline void init_tx_tables(void); |
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232 | |||
233 | /* |
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234 | * Exteranl Function |
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235 | */ |
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236 | #if defined(CONFIG_IFX_OAM) || defined(CONFIG_IFX_OAM_MODULE) |
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237 | extern void ifx_push_oam(unsigned char *); |
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238 | #else |
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239 | static inline void ifx_push_oam(unsigned char *dummy) {} |
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240 | #endif |
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241 | |||
242 | #if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE) |
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243 | extern int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr); |
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244 | extern int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *); |
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245 | |||
246 | extern int (*ifx_mei_atm_showtime_exit)(void); |
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247 | extern int ifx_mei_atm_led_blink(void); |
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248 | #else |
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249 | static inline int ifx_mei_atm_led_blink(void) { return 0; } |
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250 | static inline int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr) |
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251 | { |
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252 | if ( is_showtime != NULL ) |
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253 | *is_showtime = 0; |
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254 | return 0; |
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255 | } |
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256 | int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *) = NULL; |
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257 | EXPORT_SYMBOL(ifx_mei_atm_showtime_enter); |
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258 | |||
259 | int (*ifx_mei_atm_showtime_exit)(void) = NULL; |
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260 | EXPORT_SYMBOL(ifx_mei_atm_showtime_exit); |
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261 | |||
262 | #endif |
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263 | |||
3 | office | 264 | static struct sk_buff* (*ifx_atm_alloc_tx)(struct atm_vcc *, unsigned int) = NULL; |
265 | |||
1 | office | 266 | static struct atm_priv_data g_atm_priv_data; |
267 | |||
268 | static struct atmdev_ops g_ifx_atm_ops = { |
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269 | .open = ppe_open, |
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270 | .close = ppe_close, |
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271 | .ioctl = ppe_ioctl, |
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272 | .send = ppe_send, |
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273 | .send_oam = ppe_send_oam, |
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274 | .change_qos = ppe_change_qos, |
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275 | .owner = THIS_MODULE, |
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276 | }; |
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277 | |||
278 | static int g_showtime = 0; |
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279 | static void *g_xdata_addr = NULL; |
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280 | |||
281 | static int ppe_ioctl(struct atm_dev *dev, unsigned int cmd, void *arg) |
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282 | { |
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283 | int ret = 0; |
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284 | atm_cell_ifEntry_t mib_cell; |
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285 | atm_aal5_ifEntry_t mib_aal5; |
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286 | atm_aal5_vcc_x_t mib_vcc; |
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287 | unsigned int value; |
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288 | int conn; |
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289 | |||
290 | if ( _IOC_TYPE(cmd) != PPE_ATM_IOC_MAGIC |
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291 | || _IOC_NR(cmd) >= PPE_ATM_IOC_MAXNR ) |
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292 | return -ENOTTY; |
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293 | |||
294 | if ( _IOC_DIR(cmd) & _IOC_READ ) |
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295 | ret = !access_ok(VERIFY_WRITE, arg, _IOC_SIZE(cmd)); |
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296 | else if ( _IOC_DIR(cmd) & _IOC_WRITE ) |
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297 | ret = !access_ok(VERIFY_READ, arg, _IOC_SIZE(cmd)); |
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298 | if ( ret ) |
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299 | return -EFAULT; |
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300 | |||
301 | switch (cmd) { |
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302 | case PPE_ATM_MIB_CELL: /* cell level MIB */ |
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303 | /* These MIB should be read at ARC side, now put zero only. */ |
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304 | mib_cell.ifHCInOctets_h = 0; |
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305 | mib_cell.ifHCInOctets_l = 0; |
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306 | mib_cell.ifHCOutOctets_h = 0; |
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307 | mib_cell.ifHCOutOctets_l = 0; |
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308 | mib_cell.ifInErrors = 0; |
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309 | mib_cell.ifInUnknownProtos = WAN_MIB_TABLE->wrx_drophtu_cell; |
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310 | mib_cell.ifOutErrors = 0; |
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311 | |||
312 | ret = sizeof(mib_cell) - copy_to_user(arg, &mib_cell, sizeof(mib_cell)); |
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313 | break; |
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314 | |||
315 | case PPE_ATM_MIB_AAL5: /* AAL5 MIB */ |
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316 | value = WAN_MIB_TABLE->wrx_total_byte; |
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317 | u64_add_u32(g_atm_priv_data.wrx_total_byte, value - g_atm_priv_data.prev_wrx_total_byte, &g_atm_priv_data.wrx_total_byte); |
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318 | g_atm_priv_data.prev_wrx_total_byte = value; |
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319 | mib_aal5.ifHCInOctets_h = g_atm_priv_data.wrx_total_byte.h; |
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320 | mib_aal5.ifHCInOctets_l = g_atm_priv_data.wrx_total_byte.l; |
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321 | |||
322 | value = WAN_MIB_TABLE->wtx_total_byte; |
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323 | u64_add_u32(g_atm_priv_data.wtx_total_byte, value - g_atm_priv_data.prev_wtx_total_byte, &g_atm_priv_data.wtx_total_byte); |
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324 | g_atm_priv_data.prev_wtx_total_byte = value; |
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325 | mib_aal5.ifHCOutOctets_h = g_atm_priv_data.wtx_total_byte.h; |
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326 | mib_aal5.ifHCOutOctets_l = g_atm_priv_data.wtx_total_byte.l; |
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327 | |||
328 | mib_aal5.ifInUcastPkts = g_atm_priv_data.wrx_pdu; |
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329 | mib_aal5.ifOutUcastPkts = WAN_MIB_TABLE->wtx_total_pdu; |
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330 | mib_aal5.ifInErrors = WAN_MIB_TABLE->wrx_err_pdu; |
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331 | mib_aal5.ifInDiscards = WAN_MIB_TABLE->wrx_dropdes_pdu + g_atm_priv_data.wrx_drop_pdu; |
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332 | mib_aal5.ifOutErros = g_atm_priv_data.wtx_err_pdu; |
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333 | mib_aal5.ifOutDiscards = g_atm_priv_data.wtx_drop_pdu; |
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334 | |||
335 | ret = sizeof(mib_aal5) - copy_to_user(arg, &mib_aal5, sizeof(mib_aal5)); |
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336 | break; |
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337 | |||
338 | case PPE_ATM_MIB_VCC: /* VCC related MIB */ |
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339 | copy_from_user(&mib_vcc, arg, sizeof(mib_vcc)); |
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340 | conn = find_vpivci(mib_vcc.vpi, mib_vcc.vci); |
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341 | if (conn >= 0) { |
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342 | mib_vcc.mib_vcc.aal5VccCrcErrors = g_atm_priv_data.conn[conn].aal5_vcc_crc_err; |
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343 | mib_vcc.mib_vcc.aal5VccOverSizedSDUs = g_atm_priv_data.conn[conn].aal5_vcc_oversize_sdu; |
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344 | mib_vcc.mib_vcc.aal5VccSarTimeOuts = 0; /* no timer support */ |
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345 | ret = sizeof(mib_vcc) - copy_to_user(arg, &mib_vcc, sizeof(mib_vcc)); |
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346 | } else |
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347 | ret = -EINVAL; |
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348 | break; |
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349 | |||
350 | default: |
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351 | ret = -ENOIOCTLCMD; |
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352 | } |
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353 | |||
354 | return ret; |
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355 | } |
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356 | |||
357 | static int ppe_open(struct atm_vcc *vcc) |
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358 | { |
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359 | int ret; |
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360 | short vpi = vcc->vpi; |
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361 | int vci = vcc->vci; |
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362 | struct port *port = &g_atm_priv_data.port[(int)vcc->dev->dev_data]; |
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363 | int conn; |
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364 | int f_enable_irq = 0; |
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365 | |||
366 | if ( vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0 ) |
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367 | return -EPROTONOSUPPORT; |
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368 | |||
369 | #if !defined(DISABLE_QOS_WORKAROUND) || !DISABLE_QOS_WORKAROUND |
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370 | /* check bandwidth */ |
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371 | if ( (vcc->qos.txtp.traffic_class == ATM_CBR && vcc->qos.txtp.max_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate)) |
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372 | || (vcc->qos.txtp.traffic_class == ATM_VBR_RT && vcc->qos.txtp.max_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate)) |
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373 | #if 0 |
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374 | || (vcc->qos.txtp.traffic_class == ATM_VBR_NRT && vcc->qos.txtp.scr > (port->tx_max_cell_rate - port->tx_current_cell_rate)) |
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375 | #endif |
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376 | || (vcc->qos.txtp.traffic_class == ATM_UBR_PLUS && vcc->qos.txtp.min_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate)) ) |
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377 | { |
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378 | ret = -EINVAL; |
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379 | goto PPE_OPEN_EXIT; |
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380 | } |
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381 | #endif |
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382 | |||
383 | /* check existing vpi,vci */ |
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384 | conn = find_vpivci(vpi, vci); |
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385 | if ( conn >= 0 ) { |
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386 | ret = -EADDRINUSE; |
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387 | goto PPE_OPEN_EXIT; |
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388 | } |
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389 | |||
390 | /* check whether it need to enable irq */ |
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391 | if ( g_atm_priv_data.conn_table == 0 ) |
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392 | f_enable_irq = 1; |
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393 | |||
394 | /* allocate connection */ |
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395 | for ( conn = 0; conn < MAX_PVC_NUMBER; conn++ ) { |
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396 | if ( test_and_set_bit(conn, &g_atm_priv_data.conn_table) == 0 ) { |
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397 | g_atm_priv_data.conn[conn].vcc = vcc; |
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398 | break; |
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399 | } |
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400 | } |
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401 | if ( conn == MAX_PVC_NUMBER ) { |
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402 | ret = -EINVAL; |
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403 | goto PPE_OPEN_EXIT; |
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404 | } |
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405 | |||
406 | /* reserve bandwidth */ |
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407 | switch ( vcc->qos.txtp.traffic_class ) { |
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408 | case ATM_CBR: |
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409 | case ATM_VBR_RT: |
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410 | port->tx_current_cell_rate += vcc->qos.txtp.max_pcr; |
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411 | break; |
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412 | case ATM_VBR_NRT: |
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413 | #if 0 |
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414 | port->tx_current_cell_rate += vcc->qos.txtp.scr; |
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415 | #endif |
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416 | break; |
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417 | case ATM_UBR_PLUS: |
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418 | port->tx_current_cell_rate += vcc->qos.txtp.min_pcr; |
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419 | break; |
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420 | } |
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421 | |||
422 | /* set qsb */ |
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423 | set_qsb(vcc, &vcc->qos, conn); |
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424 | |||
425 | /* update atm_vcc structure */ |
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426 | vcc->itf = (int)vcc->dev->dev_data; |
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427 | vcc->vpi = vpi; |
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428 | vcc->vci = vci; |
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429 | set_bit(ATM_VF_READY, &vcc->flags); |
||
430 | |||
431 | /* enable irq */ |
||
432 | if ( f_enable_irq ) { |
||
3 | office | 433 | ifx_atm_alloc_tx = atm_alloc_tx; |
434 | |||
1 | office | 435 | *MBOX_IGU1_ISRC = (1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM); |
436 | *MBOX_IGU1_IER = (1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM); |
||
437 | |||
438 | enable_irq(PPE_MAILBOX_IGU1_INT); |
||
439 | } |
||
440 | |||
441 | /* set port */ |
||
442 | WTX_QUEUE_CONFIG(conn + FIRST_QSB_QID)->sbid = (int)vcc->dev->dev_data; |
||
443 | |||
444 | /* set htu entry */ |
||
445 | set_htu_entry(vpi, vci, conn, vcc->qos.aal == ATM_AAL5 ? 1 : 0, 0); |
||
446 | |||
447 | *MBOX_IGU1_ISRC |= (1 << (conn + FIRST_QSB_QID + 16)); |
||
448 | *MBOX_IGU1_IER |= (1 << (conn + FIRST_QSB_QID + 16)); |
||
449 | |||
450 | ret = 0; |
||
451 | |||
452 | PPE_OPEN_EXIT: |
||
453 | return ret; |
||
454 | } |
||
455 | |||
456 | static void ppe_close(struct atm_vcc *vcc) |
||
457 | { |
||
458 | int conn; |
||
459 | struct port *port; |
||
460 | struct connection *connection; |
||
461 | if ( vcc == NULL ) |
||
462 | return; |
||
463 | |||
464 | /* get connection id */ |
||
465 | conn = find_vcc(vcc); |
||
466 | if ( conn < 0 ) { |
||
467 | pr_err("can't find vcc\n"); |
||
468 | goto PPE_CLOSE_EXIT; |
||
469 | } |
||
470 | connection = &g_atm_priv_data.conn[conn]; |
||
471 | port = &g_atm_priv_data.port[connection->port]; |
||
472 | |||
473 | /* clear htu */ |
||
474 | clear_htu_entry(conn); |
||
475 | |||
476 | /* release connection */ |
||
477 | connection->vcc = NULL; |
||
478 | connection->aal5_vcc_crc_err = 0; |
||
479 | connection->aal5_vcc_oversize_sdu = 0; |
||
480 | clear_bit(conn, &g_atm_priv_data.conn_table); |
||
481 | |||
482 | /* disable irq */ |
||
3 | office | 483 | if ( g_atm_priv_data.conn_table == 0 ) { |
1 | office | 484 | disable_irq(PPE_MAILBOX_IGU1_INT); |
3 | office | 485 | ifx_atm_alloc_tx = NULL; |
486 | } |
||
1 | office | 487 | |
488 | /* release bandwidth */ |
||
489 | switch ( vcc->qos.txtp.traffic_class ) |
||
490 | { |
||
491 | case ATM_CBR: |
||
492 | case ATM_VBR_RT: |
||
493 | port->tx_current_cell_rate -= vcc->qos.txtp.max_pcr; |
||
494 | break; |
||
495 | case ATM_VBR_NRT: |
||
496 | #if 0 |
||
497 | port->tx_current_cell_rate -= vcc->qos.txtp.scr; |
||
498 | #endif |
||
499 | break; |
||
500 | case ATM_UBR_PLUS: |
||
501 | port->tx_current_cell_rate -= vcc->qos.txtp.min_pcr; |
||
502 | break; |
||
503 | } |
||
504 | |||
505 | /* wait for incoming packets to be processed by upper layers */ |
||
506 | tasklet_unlock_wait(&g_dma_tasklet); |
||
507 | |||
508 | PPE_CLOSE_EXIT: |
||
509 | return; |
||
510 | } |
||
511 | |||
512 | static int ppe_send(struct atm_vcc *vcc, struct sk_buff *skb) |
||
513 | { |
||
514 | int ret; |
||
515 | int conn; |
||
516 | int desc_base; |
||
517 | int byteoff; |
||
518 | int required; |
||
519 | /* the len of the data without offset and header */ |
||
520 | int datalen; |
||
521 | unsigned long flags; |
||
522 | struct tx_descriptor reg_desc = {0}; |
||
523 | struct tx_inband_header *header; |
||
524 | |||
525 | if ( vcc == NULL || skb == NULL ) |
||
526 | return -EINVAL; |
||
527 | |||
528 | |||
529 | conn = find_vcc(vcc); |
||
530 | if ( conn < 0 ) { |
||
531 | ret = -EINVAL; |
||
532 | goto FIND_VCC_FAIL; |
||
533 | } |
||
534 | |||
535 | if ( !g_showtime ) { |
||
536 | pr_debug("not in showtime\n"); |
||
537 | ret = -EIO; |
||
538 | goto PPE_SEND_FAIL; |
||
539 | } |
||
540 | |||
541 | byteoff = (unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1); |
||
542 | required = sizeof(*header) + byteoff; |
||
543 | if (!skb_clone_writable(skb, required)) { |
||
544 | int expand_by = 0; |
||
545 | int ret; |
||
546 | |||
547 | if (skb_headroom(skb) < required) |
||
548 | expand_by = required - skb_headroom(skb); |
||
549 | |||
550 | ret = pskb_expand_head(skb, expand_by, 0, GFP_ATOMIC); |
||
551 | if (ret) { |
||
552 | printk("pskb_expand_head failed.\n"); |
||
553 | atm_free_tx_skb_vcc(skb, vcc); |
||
554 | return ret; |
||
555 | } |
||
556 | } |
||
557 | |||
558 | datalen = skb->len; |
||
559 | header = (void *)skb_push(skb, byteoff + TX_INBAND_HEADER_LENGTH); |
||
560 | |||
561 | |||
562 | if ( vcc->qos.aal == ATM_AAL5 ) { |
||
563 | /* setup inband trailer */ |
||
564 | header->uu = 0; |
||
565 | header->cpi = 0; |
||
566 | header->pad = aal5_fill_pattern; |
||
567 | header->res1 = 0; |
||
568 | |||
569 | /* setup cell header */ |
||
570 | header->clp = (vcc->atm_options & ATM_ATMOPT_CLP) ? 1 : 0; |
||
571 | header->pti = ATM_PTI_US0; |
||
572 | header->vci = vcc->vci; |
||
573 | header->vpi = vcc->vpi; |
||
574 | header->gfc = 0; |
||
575 | |||
576 | /* setup descriptor */ |
||
577 | reg_desc.dataptr = (unsigned int)skb->data >> 2; |
||
578 | reg_desc.datalen = datalen; |
||
579 | reg_desc.byteoff = byteoff; |
||
580 | reg_desc.iscell = 0; |
||
581 | } else { |
||
582 | reg_desc.dataptr = (unsigned int)skb->data >> 2; |
||
583 | reg_desc.datalen = skb->len; |
||
584 | reg_desc.byteoff = byteoff; |
||
585 | reg_desc.iscell = 1; |
||
586 | } |
||
587 | |||
588 | reg_desc.own = 1; |
||
589 | reg_desc.c = 1; |
||
590 | reg_desc.sop = reg_desc.eop = 1; |
||
591 | |||
592 | spin_lock_irqsave(&g_atm_priv_data.conn[conn].lock, flags); |
||
593 | desc_base = get_tx_desc(conn); |
||
594 | if ( desc_base < 0 ) { |
||
595 | spin_unlock_irqrestore(&g_atm_priv_data.conn[conn].lock, flags); |
||
596 | pr_debug("ALLOC_TX_CONNECTION_FAIL\n"); |
||
597 | ret = -EIO; |
||
598 | goto PPE_SEND_FAIL; |
||
599 | } |
||
600 | /* update descriptor send pointer */ |
||
601 | if ( g_atm_priv_data.conn[conn].tx_skb[desc_base] != NULL ) |
||
602 | dev_kfree_skb_any(g_atm_priv_data.conn[conn].tx_skb[desc_base]); |
||
603 | g_atm_priv_data.conn[conn].tx_skb[desc_base] = skb; |
||
604 | |||
605 | spin_unlock_irqrestore(&g_atm_priv_data.conn[conn].lock, flags); |
||
606 | |||
607 | if ( vcc->stats ) |
||
608 | atomic_inc(&vcc->stats->tx); |
||
609 | if ( vcc->qos.aal == ATM_AAL5 ) |
||
610 | g_atm_priv_data.wtx_pdu++; |
||
611 | /* write discriptor to memory and write back cache */ |
||
612 | g_atm_priv_data.conn[conn].tx_desc[desc_base] = reg_desc; |
||
613 | dma_cache_wback((unsigned long)skb->data, skb->len); |
||
614 | |||
615 | mailbox_signal(conn, 1); |
||
616 | |||
617 | adsl_led_flash(); |
||
618 | |||
619 | return 0; |
||
620 | |||
621 | FIND_VCC_FAIL: |
||
622 | pr_err("FIND_VCC_FAIL\n"); |
||
623 | g_atm_priv_data.wtx_err_pdu++; |
||
624 | dev_kfree_skb_any(skb); |
||
625 | return ret; |
||
626 | |||
627 | PPE_SEND_FAIL: |
||
628 | if ( vcc->qos.aal == ATM_AAL5 ) |
||
629 | g_atm_priv_data.wtx_drop_pdu++; |
||
630 | if ( vcc->stats ) |
||
631 | atomic_inc(&vcc->stats->tx_err); |
||
632 | dev_kfree_skb_any(skb); |
||
633 | return ret; |
||
634 | } |
||
635 | |||
636 | /* operation and maintainance */ |
||
637 | static int ppe_send_oam(struct atm_vcc *vcc, void *cell, int flags) |
||
638 | { |
||
639 | int conn; |
||
640 | struct uni_cell_header *uni_cell_header = (struct uni_cell_header *)cell; |
||
641 | int desc_base; |
||
642 | struct sk_buff *skb; |
||
643 | struct tx_descriptor reg_desc = {0}; |
||
644 | |||
645 | if ( ((uni_cell_header->pti == ATM_PTI_SEGF5 || uni_cell_header->pti == ATM_PTI_E2EF5) |
||
646 | && find_vpivci(uni_cell_header->vpi, uni_cell_header->vci) < 0) |
||
647 | || ((uni_cell_header->vci == 0x03 || uni_cell_header->vci == 0x04) |
||
648 | && find_vpi(uni_cell_header->vpi) < 0) ) |
||
649 | { |
||
650 | g_atm_priv_data.wtx_err_oam++; |
||
651 | return -EINVAL; |
||
652 | } |
||
653 | |||
654 | if ( !g_showtime ) { |
||
655 | pr_err("not in showtime\n"); |
||
656 | g_atm_priv_data.wtx_drop_oam++; |
||
657 | return -EIO; |
||
658 | } |
||
659 | |||
660 | conn = find_vcc(vcc); |
||
661 | if ( conn < 0 ) { |
||
662 | pr_err("FIND_VCC_FAIL\n"); |
||
663 | g_atm_priv_data.wtx_drop_oam++; |
||
664 | return -EINVAL; |
||
665 | } |
||
666 | |||
667 | skb = alloc_skb_tx(CELL_SIZE); |
||
668 | if ( skb == NULL ) { |
||
669 | pr_err("ALLOC_SKB_TX_FAIL\n"); |
||
670 | g_atm_priv_data.wtx_drop_oam++; |
||
671 | return -ENOMEM; |
||
672 | } |
||
673 | skb_put(skb, CELL_SIZE); |
||
674 | memcpy(skb->data, cell, CELL_SIZE); |
||
675 | |||
676 | reg_desc.dataptr = (unsigned int)skb->data >> 2; |
||
677 | reg_desc.datalen = CELL_SIZE; |
||
678 | reg_desc.byteoff = 0; |
||
679 | reg_desc.iscell = 1; |
||
680 | |||
681 | reg_desc.own = 1; |
||
682 | reg_desc.c = 1; |
||
683 | reg_desc.sop = reg_desc.eop = 1; |
||
684 | |||
685 | desc_base = get_tx_desc(conn); |
||
686 | if ( desc_base < 0 ) { |
||
687 | dev_kfree_skb_any(skb); |
||
688 | pr_err("ALLOC_TX_CONNECTION_FAIL\n"); |
||
689 | g_atm_priv_data.wtx_drop_oam++; |
||
690 | return -EIO; |
||
691 | } |
||
692 | |||
693 | if ( vcc->stats ) |
||
694 | atomic_inc(&vcc->stats->tx); |
||
695 | |||
696 | /* update descriptor send pointer */ |
||
697 | if ( g_atm_priv_data.conn[conn].tx_skb[desc_base] != NULL ) |
||
698 | dev_kfree_skb_any(g_atm_priv_data.conn[conn].tx_skb[desc_base]); |
||
699 | g_atm_priv_data.conn[conn].tx_skb[desc_base] = skb; |
||
700 | |||
701 | /* write discriptor to memory and write back cache */ |
||
702 | g_atm_priv_data.conn[conn].tx_desc[desc_base] = reg_desc; |
||
703 | dma_cache_wback((unsigned long)skb->data, CELL_SIZE); |
||
704 | |||
705 | mailbox_signal(conn, 1); |
||
706 | |||
707 | g_atm_priv_data.wtx_oam++; |
||
708 | adsl_led_flash(); |
||
709 | |||
710 | return 0; |
||
711 | } |
||
712 | |||
713 | static int ppe_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags) |
||
714 | { |
||
715 | int conn; |
||
716 | |||
717 | if ( vcc == NULL || qos == NULL ) |
||
718 | return -EINVAL; |
||
719 | |||
720 | conn = find_vcc(vcc); |
||
721 | if ( conn < 0 ) |
||
722 | return -EINVAL; |
||
723 | |||
724 | set_qsb(vcc, qos, conn); |
||
725 | |||
726 | return 0; |
||
727 | } |
||
728 | |||
729 | static inline void adsl_led_flash(void) |
||
730 | { |
||
731 | ifx_mei_atm_led_blink(); |
||
732 | } |
||
733 | |||
734 | /* |
||
735 | * Description: |
||
736 | * Add a 32-bit value to 64-bit value, and put result in a 64-bit variable. |
||
737 | * Input: |
||
738 | * opt1 --- ppe_u64_t, first operand, a 64-bit unsigned integer value |
||
739 | * opt2 --- unsigned int, second operand, a 32-bit unsigned integer value |
||
740 | * ret --- ppe_u64_t, pointer to a variable to hold result |
||
741 | * Output: |
||
742 | * none |
||
743 | */ |
||
744 | static inline void u64_add_u32(ppe_u64_t opt1, unsigned int opt2, ppe_u64_t *ret) |
||
745 | { |
||
746 | ret->l = opt1.l + opt2; |
||
747 | if ( ret->l < opt1.l || ret->l < opt2 ) |
||
748 | ret->h++; |
||
749 | } |
||
750 | |||
751 | static inline struct sk_buff* alloc_skb_rx(void) |
||
752 | { |
||
753 | struct sk_buff *skb; |
||
754 | |||
755 | skb = dev_alloc_skb(RX_DMA_CH_AAL_BUF_SIZE + DATA_BUFFER_ALIGNMENT); |
||
756 | if ( skb != NULL ) { |
||
757 | /* must be burst length alignment */ |
||
758 | if ( ((unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1)) != 0 ) |
||
759 | skb_reserve(skb, ~((unsigned int)skb->data + (DATA_BUFFER_ALIGNMENT - 1)) & (DATA_BUFFER_ALIGNMENT - 1)); |
||
760 | /* pub skb in reserved area "skb->data - 4" */ |
||
761 | *((struct sk_buff **)skb->data - 1) = skb; |
||
762 | /* write back and invalidate cache */ |
||
763 | dma_cache_wback_inv((unsigned long)skb->data - sizeof(skb), sizeof(skb)); |
||
764 | /* invalidate cache */ |
||
765 | #if defined(ENABLE_LESS_CACHE_INV) && ENABLE_LESS_CACHE_INV |
||
766 | dma_cache_inv((unsigned long)skb->data, LESS_CACHE_INV_LEN); |
||
767 | #else |
||
768 | dma_cache_inv((unsigned long)skb->data, RX_DMA_CH_AAL_BUF_SIZE); |
||
769 | #endif |
||
770 | } |
||
771 | return skb; |
||
772 | } |
||
773 | |||
774 | static inline struct sk_buff* alloc_skb_tx(unsigned int size) |
||
775 | { |
||
776 | struct sk_buff *skb; |
||
777 | |||
778 | /* allocate memory including header and padding */ |
||
779 | size += TX_INBAND_HEADER_LENGTH + MAX_TX_PACKET_ALIGN_BYTES + MAX_TX_PACKET_PADDING_BYTES; |
||
780 | size &= ~(DATA_BUFFER_ALIGNMENT - 1); |
||
781 | skb = dev_alloc_skb(size + DATA_BUFFER_ALIGNMENT); |
||
782 | /* must be burst length alignment */ |
||
783 | if ( skb != NULL ) |
||
784 | skb_reserve(skb, (~((unsigned int)skb->data + (DATA_BUFFER_ALIGNMENT - 1)) & (DATA_BUFFER_ALIGNMENT - 1)) + TX_INBAND_HEADER_LENGTH); |
||
785 | return skb; |
||
786 | } |
||
787 | |||
3 | office | 788 | struct sk_buff* atm_alloc_tx(struct atm_vcc *vcc, unsigned int size) |
789 | { |
||
790 | int conn; |
||
791 | struct sk_buff *skb; |
||
792 | |||
793 | /* oversize packet */ |
||
794 | if ( size > aal5s_max_packet_size ) { |
||
795 | pr_err("atm_alloc_tx: oversize packet\n"); |
||
796 | return NULL; |
||
797 | } |
||
798 | /* send buffer overflow */ |
||
799 | if ( sk_wmem_alloc_get(sk_atm(vcc)) && !atm_may_send(vcc, size) ) { |
||
800 | pr_err("atm_alloc_tx: send buffer overflow\n"); |
||
801 | return NULL; |
||
802 | } |
||
803 | conn = find_vcc(vcc); |
||
804 | if ( conn < 0 ) { |
||
805 | pr_err("atm_alloc_tx: unknown VCC\n"); |
||
806 | return NULL; |
||
807 | } |
||
808 | |||
809 | skb = dev_alloc_skb(size); |
||
810 | if ( skb == NULL ) { |
||
811 | pr_err("atm_alloc_tx: sk buffer is used up\n"); |
||
812 | return NULL; |
||
813 | } |
||
814 | |||
815 | #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,13,0)) |
||
816 | refcount_add(skb->truesize, &sk_atm(vcc)->sk_wmem_alloc); |
||
817 | #else |
||
818 | atomic_add(skb->truesize, &sk_atm(vcc)->sk_wmem_alloc); |
||
819 | #endif |
||
820 | |||
821 | return skb; |
||
822 | } |
||
823 | |||
1 | office | 824 | static inline void atm_free_tx_skb_vcc(struct sk_buff *skb, struct atm_vcc *vcc) |
825 | { |
||
826 | if ( vcc->pop != NULL ) |
||
827 | vcc->pop(vcc, skb); |
||
828 | else |
||
829 | dev_kfree_skb_any(skb); |
||
830 | } |
||
831 | |||
832 | static inline struct sk_buff *get_skb_rx_pointer(unsigned int dataptr) |
||
833 | { |
||
834 | unsigned int skb_dataptr; |
||
835 | struct sk_buff *skb; |
||
836 | |||
837 | skb_dataptr = ((dataptr - 1) << 2) | KSEG1; |
||
838 | skb = *(struct sk_buff **)skb_dataptr; |
||
839 | |||
840 | ASSERT((unsigned int)skb >= KSEG0, "invalid skb - skb = %#08x, dataptr = %#08x", (unsigned int)skb, dataptr); |
||
841 | ASSERT(((unsigned int)skb->data | KSEG1) == ((dataptr << 2) | KSEG1), "invalid skb - skb = %#08x, skb->data = %#08x, dataptr = %#08x", (unsigned int)skb, (unsigned int)skb->data, dataptr); |
||
842 | |||
843 | return skb; |
||
844 | } |
||
845 | |||
846 | static inline int get_tx_desc(unsigned int conn) |
||
847 | { |
||
848 | int desc_base = -1; |
||
849 | struct connection *p_conn = &g_atm_priv_data.conn[conn]; |
||
850 | |||
851 | if ( p_conn->tx_desc[p_conn->tx_desc_pos].own == 0 ) { |
||
852 | desc_base = p_conn->tx_desc_pos; |
||
853 | if ( ++(p_conn->tx_desc_pos) == dma_tx_descriptor_length ) |
||
854 | p_conn->tx_desc_pos = 0; |
||
855 | } |
||
856 | |||
857 | return desc_base; |
||
858 | } |
||
859 | |||
860 | static void free_tx_ring(unsigned int queue) |
||
861 | { |
||
862 | unsigned long flags; |
||
863 | int i; |
||
864 | struct connection *conn = &g_atm_priv_data.conn[queue]; |
||
865 | struct sk_buff *skb; |
||
866 | |||
867 | if (!conn) |
||
868 | return; |
||
869 | |||
870 | spin_lock_irqsave(&conn->lock, flags); |
||
871 | |||
872 | for (i = 0; i < dma_tx_descriptor_length; i++) { |
||
873 | if (conn->tx_desc[i].own == 0 && conn->tx_skb[i] != NULL) { |
||
874 | skb = conn->tx_skb[i]; |
||
875 | conn->tx_skb[i] = NULL; |
||
876 | atm_free_tx_skb_vcc(skb, ATM_SKB(skb)->vcc); |
||
877 | } |
||
878 | } |
||
879 | spin_unlock_irqrestore(&conn->lock, flags); |
||
880 | } |
||
881 | |||
882 | static void mailbox_tx_handler(unsigned int queue_bitmap) |
||
883 | { |
||
884 | int i; |
||
885 | int bit; |
||
886 | |||
887 | /* only get valid queues */ |
||
888 | queue_bitmap &= g_atm_priv_data.conn_table; |
||
889 | |||
890 | for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) { |
||
891 | if (queue_bitmap & bit) |
||
892 | free_tx_ring(i); |
||
893 | } |
||
894 | } |
||
895 | |||
896 | static inline void mailbox_oam_rx_handler(void) |
||
897 | { |
||
898 | unsigned int vlddes = WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_OAM)->vlddes; |
||
899 | struct rx_descriptor reg_desc; |
||
900 | struct uni_cell_header *header; |
||
901 | int conn; |
||
902 | struct atm_vcc *vcc; |
||
903 | unsigned int i; |
||
904 | |||
905 | for ( i = 0; i < vlddes; i++ ) { |
||
906 | unsigned int loop_count = 0; |
||
907 | |||
908 | do { |
||
909 | reg_desc = g_atm_priv_data.oam_desc[g_atm_priv_data.oam_desc_pos]; |
||
910 | if ( ++loop_count == 1000 ) |
||
911 | break; |
||
912 | } while ( reg_desc.own || !reg_desc.c ); // keep test OWN and C bit until data is ready |
||
913 | ASSERT(loop_count == 1, "loop_count = %u, own = %d, c = %d, oam_desc_pos = %u", loop_count, (int)reg_desc.own, (int)reg_desc.c, g_atm_priv_data.oam_desc_pos); |
||
914 | |||
915 | header = (struct uni_cell_header *)&g_atm_priv_data.oam_buf[g_atm_priv_data.oam_desc_pos * RX_DMA_CH_OAM_BUF_SIZE]; |
||
916 | |||
917 | if ( header->pti == ATM_PTI_SEGF5 || header->pti == ATM_PTI_E2EF5 ) |
||
918 | conn = find_vpivci(header->vpi, header->vci); |
||
919 | else if ( header->vci == 0x03 || header->vci == 0x04 ) |
||
920 | conn = find_vpi(header->vpi); |
||
921 | else |
||
922 | conn = -1; |
||
923 | |||
924 | if ( conn >= 0 && g_atm_priv_data.conn[conn].vcc != NULL ) { |
||
925 | vcc = g_atm_priv_data.conn[conn].vcc; |
||
926 | |||
927 | if ( vcc->push_oam != NULL ) |
||
928 | vcc->push_oam(vcc, header); |
||
929 | else |
||
930 | ifx_push_oam((unsigned char *)header); |
||
931 | |||
932 | g_atm_priv_data.wrx_oam++; |
||
933 | |||
934 | adsl_led_flash(); |
||
935 | } else |
||
936 | g_atm_priv_data.wrx_drop_oam++; |
||
937 | |||
938 | reg_desc.byteoff = 0; |
||
939 | reg_desc.datalen = RX_DMA_CH_OAM_BUF_SIZE; |
||
940 | reg_desc.own = 1; |
||
941 | reg_desc.c = 0; |
||
942 | |||
943 | g_atm_priv_data.oam_desc[g_atm_priv_data.oam_desc_pos] = reg_desc; |
||
944 | if ( ++g_atm_priv_data.oam_desc_pos == RX_DMA_CH_OAM_DESC_LEN ) |
||
945 | g_atm_priv_data.oam_desc_pos = 0; |
||
946 | |||
947 | dma_cache_inv((unsigned long)header, CELL_SIZE); |
||
948 | mailbox_signal(RX_DMA_CH_OAM, 0); |
||
949 | } |
||
950 | } |
||
951 | |||
952 | static inline void mailbox_aal_rx_handler(void) |
||
953 | { |
||
954 | unsigned int vlddes = WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_AAL)->vlddes; |
||
955 | struct rx_descriptor reg_desc; |
||
956 | int conn; |
||
957 | struct atm_vcc *vcc; |
||
958 | struct sk_buff *skb, *new_skb; |
||
959 | struct rx_inband_trailer *trailer; |
||
960 | unsigned int i; |
||
961 | |||
962 | for ( i = 0; i < vlddes; i++ ) { |
||
963 | unsigned int loop_count = 0; |
||
964 | |||
965 | do { |
||
966 | reg_desc = g_atm_priv_data.aal_desc[g_atm_priv_data.aal_desc_pos]; |
||
967 | if ( ++loop_count == 1000 ) |
||
968 | break; |
||
969 | } while ( reg_desc.own || !reg_desc.c ); // keep test OWN and C bit until data is ready |
||
970 | ASSERT(loop_count == 1, "loop_count = %u, own = %d, c = %d, aal_desc_pos = %u", loop_count, (int)reg_desc.own, (int)reg_desc.c, g_atm_priv_data.aal_desc_pos); |
||
971 | |||
972 | conn = reg_desc.id; |
||
973 | |||
974 | if ( g_atm_priv_data.conn[conn].vcc != NULL ) { |
||
975 | vcc = g_atm_priv_data.conn[conn].vcc; |
||
976 | |||
977 | skb = get_skb_rx_pointer(reg_desc.dataptr); |
||
978 | |||
979 | if ( reg_desc.err ) { |
||
980 | if ( vcc->qos.aal == ATM_AAL5 ) { |
||
981 | trailer = (struct rx_inband_trailer *)((unsigned int)skb->data + ((reg_desc.byteoff + reg_desc.datalen + MAX_RX_PACKET_PADDING_BYTES) & ~MAX_RX_PACKET_PADDING_BYTES)); |
||
982 | if ( trailer->stw_crc ) |
||
983 | g_atm_priv_data.conn[conn].aal5_vcc_crc_err++; |
||
984 | if ( trailer->stw_ovz ) |
||
985 | g_atm_priv_data.conn[conn].aal5_vcc_oversize_sdu++; |
||
986 | g_atm_priv_data.wrx_drop_pdu++; |
||
987 | } |
||
988 | if ( vcc->stats ) { |
||
989 | atomic_inc(&vcc->stats->rx_drop); |
||
990 | atomic_inc(&vcc->stats->rx_err); |
||
991 | } |
||
992 | reg_desc.err = 0; |
||
993 | } else if ( atm_charge(vcc, skb->truesize) ) { |
||
994 | new_skb = alloc_skb_rx(); |
||
995 | if ( new_skb != NULL ) { |
||
996 | #if defined(ENABLE_LESS_CACHE_INV) && ENABLE_LESS_CACHE_INV |
||
997 | if ( reg_desc.byteoff + reg_desc.datalen > LESS_CACHE_INV_LEN ) |
||
998 | dma_cache_inv((unsigned long)skb->data + LESS_CACHE_INV_LEN, reg_desc.byteoff + reg_desc.datalen - LESS_CACHE_INV_LEN); |
||
999 | #endif |
||
1000 | |||
1001 | skb_reserve(skb, reg_desc.byteoff); |
||
1002 | skb_put(skb, reg_desc.datalen); |
||
1003 | ATM_SKB(skb)->vcc = vcc; |
||
1004 | |||
1005 | vcc->push(vcc, skb); |
||
1006 | |||
1007 | if ( vcc->qos.aal == ATM_AAL5 ) |
||
1008 | g_atm_priv_data.wrx_pdu++; |
||
1009 | if ( vcc->stats ) |
||
1010 | atomic_inc(&vcc->stats->rx); |
||
1011 | adsl_led_flash(); |
||
1012 | |||
1013 | reg_desc.dataptr = (unsigned int)new_skb->data >> 2; |
||
1014 | } else { |
||
1015 | atm_return(vcc, skb->truesize); |
||
1016 | if ( vcc->qos.aal == ATM_AAL5 ) |
||
1017 | g_atm_priv_data.wrx_drop_pdu++; |
||
1018 | if ( vcc->stats ) |
||
1019 | atomic_inc(&vcc->stats->rx_drop); |
||
1020 | } |
||
1021 | } else { |
||
1022 | if ( vcc->qos.aal == ATM_AAL5 ) |
||
1023 | g_atm_priv_data.wrx_drop_pdu++; |
||
1024 | if ( vcc->stats ) |
||
1025 | atomic_inc(&vcc->stats->rx_drop); |
||
1026 | } |
||
1027 | } else { |
||
1028 | g_atm_priv_data.wrx_drop_pdu++; |
||
1029 | } |
||
1030 | |||
1031 | reg_desc.byteoff = 0; |
||
1032 | reg_desc.datalen = RX_DMA_CH_AAL_BUF_SIZE; |
||
1033 | reg_desc.own = 1; |
||
1034 | reg_desc.c = 0; |
||
1035 | |||
1036 | g_atm_priv_data.aal_desc[g_atm_priv_data.aal_desc_pos] = reg_desc; |
||
1037 | if ( ++g_atm_priv_data.aal_desc_pos == dma_rx_descriptor_length ) |
||
1038 | g_atm_priv_data.aal_desc_pos = 0; |
||
1039 | |||
1040 | mailbox_signal(RX_DMA_CH_AAL, 0); |
||
1041 | } |
||
1042 | } |
||
1043 | |||
1044 | static void do_ppe_tasklet(unsigned long data) |
||
1045 | { |
||
1046 | unsigned int irqs = *MBOX_IGU1_ISR; |
||
1047 | *MBOX_IGU1_ISRC = *MBOX_IGU1_ISR; |
||
1048 | |||
1049 | if (irqs & (1 << RX_DMA_CH_AAL)) |
||
1050 | mailbox_aal_rx_handler(); |
||
1051 | if (irqs & (1 << RX_DMA_CH_OAM)) |
||
1052 | mailbox_oam_rx_handler(); |
||
1053 | |||
1054 | /* any valid tx irqs */ |
||
1055 | if ((irqs >> (FIRST_QSB_QID + 16)) & g_atm_priv_data.conn_table) |
||
1056 | mailbox_tx_handler(irqs >> (FIRST_QSB_QID + 16)); |
||
1057 | |||
1058 | if ((*MBOX_IGU1_ISR & ((1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM))) != 0) |
||
1059 | tasklet_schedule(&g_dma_tasklet); |
||
1060 | else if (*MBOX_IGU1_ISR >> (FIRST_QSB_QID + 16)) /* TX queue */ |
||
1061 | tasklet_schedule(&g_dma_tasklet); |
||
1062 | else |
||
1063 | enable_irq(PPE_MAILBOX_IGU1_INT); |
||
1064 | } |
||
1065 | |||
1066 | static irqreturn_t mailbox_irq_handler(int irq, void *dev_id) |
||
1067 | { |
||
1068 | if ( !*MBOX_IGU1_ISR ) |
||
1069 | return IRQ_HANDLED; |
||
1070 | |||
1071 | disable_irq_nosync(PPE_MAILBOX_IGU1_INT); |
||
1072 | tasklet_schedule(&g_dma_tasklet); |
||
1073 | |||
1074 | return IRQ_HANDLED; |
||
1075 | } |
||
1076 | |||
1077 | static inline void mailbox_signal(unsigned int queue, int is_tx) |
||
1078 | { |
||
1079 | int count = 1000; |
||
1080 | |||
1081 | if ( is_tx ) { |
||
1082 | while ( MBOX_IGU3_ISR_ISR(queue + FIRST_QSB_QID + 16) && count > 0 ) |
||
1083 | count--; |
||
1084 | *MBOX_IGU3_ISRS = MBOX_IGU3_ISRS_SET(queue + FIRST_QSB_QID + 16); |
||
1085 | } else { |
||
1086 | while ( MBOX_IGU3_ISR_ISR(queue) && count > 0 ) |
||
1087 | count--; |
||
1088 | *MBOX_IGU3_ISRS = MBOX_IGU3_ISRS_SET(queue); |
||
1089 | } |
||
1090 | |||
1091 | ASSERT(count > 0, "queue = %u, is_tx = %d, MBOX_IGU3_ISR = 0x%08x", queue, is_tx, IFX_REG_R32(MBOX_IGU3_ISR)); |
||
1092 | } |
||
1093 | |||
1094 | static void set_qsb(struct atm_vcc *vcc, struct atm_qos *qos, unsigned int queue) |
||
1095 | { |
||
1096 | struct clk *fpi_clk = clk_get_fpi(); |
||
1097 | unsigned int qsb_clk = clk_get_rate(fpi_clk); |
||
1098 | unsigned int qsb_qid = queue + FIRST_QSB_QID; |
||
1099 | union qsb_queue_parameter_table qsb_queue_parameter_table = {{0}}; |
||
1100 | union qsb_queue_vbr_parameter_table qsb_queue_vbr_parameter_table = {{0}}; |
||
1101 | unsigned int tmp; |
||
1102 | |||
1103 | |||
1104 | /* |
||
1105 | * Peak Cell Rate (PCR) Limiter |
||
1106 | */ |
||
1107 | if ( qos->txtp.max_pcr == 0 ) |
||
1108 | qsb_queue_parameter_table.bit.tp = 0; /* disable PCR limiter */ |
||
1109 | else { |
||
1110 | /* peak cell rate would be slightly lower than requested [maximum_rate / pcr = (qsb_clock / 8) * (time_step / 4) / pcr] */ |
||
1111 | tmp = ((qsb_clk * qsb_tstep) >> 5) / qos->txtp.max_pcr + 1; |
||
1112 | /* check if overflow takes place */ |
||
1113 | qsb_queue_parameter_table.bit.tp = tmp > QSB_TP_TS_MAX ? QSB_TP_TS_MAX : tmp; |
||
1114 | } |
||
1115 | |||
1116 | #if !defined(DISABLE_QOS_WORKAROUND) || !DISABLE_QOS_WORKAROUND |
||
1117 | // A funny issue. Create two PVCs, one UBR and one UBR with max_pcr. |
||
1118 | // Send packets to these two PVCs at same time, it trigger strange behavior. |
||
1119 | // In A1, RAM from 0x80000000 to 0x0x8007FFFF was corrupted with fixed pattern 0x00000000 0x40000000. |
||
1120 | // In A4, PPE firmware keep emiting unknown cell and do not respond to driver. |
||
1121 | // To work around, create UBR always with max_pcr. |
||
1122 | // If user want to create UBR without max_pcr, we give a default one larger than line-rate. |
||
1123 | if ( qos->txtp.traffic_class == ATM_UBR && qsb_queue_parameter_table.bit.tp == 0 ) { |
||
1124 | int port = g_atm_priv_data.conn[queue].port; |
||
1125 | unsigned int max_pcr = g_atm_priv_data.port[port].tx_max_cell_rate + 1000; |
||
1126 | |||
1127 | tmp = ((qsb_clk * qsb_tstep) >> 5) / max_pcr + 1; |
||
1128 | if ( tmp > QSB_TP_TS_MAX ) |
||
1129 | tmp = QSB_TP_TS_MAX; |
||
1130 | else if ( tmp < 1 ) |
||
1131 | tmp = 1; |
||
1132 | qsb_queue_parameter_table.bit.tp = tmp; |
||
1133 | } |
||
1134 | #endif |
||
1135 | |||
1136 | /* |
||
1137 | * Weighted Fair Queueing Factor (WFQF) |
||
1138 | */ |
||
1139 | switch ( qos->txtp.traffic_class ) { |
||
1140 | case ATM_CBR: |
||
1141 | case ATM_VBR_RT: |
||
1142 | /* real time queue gets weighted fair queueing bypass */ |
||
1143 | qsb_queue_parameter_table.bit.wfqf = 0; |
||
1144 | break; |
||
1145 | case ATM_VBR_NRT: |
||
1146 | case ATM_UBR_PLUS: |
||
1147 | /* WFQF calculation here is based on virtual cell rates, to reduce granularity for high rates */ |
||
1148 | /* WFQF is maximum cell rate / garenteed cell rate */ |
||
1149 | /* wfqf = qsb_minimum_cell_rate * QSB_WFQ_NONUBR_MAX / requested_minimum_peak_cell_rate */ |
||
1150 | if ( qos->txtp.min_pcr == 0 ) |
||
1151 | qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_NONUBR_MAX; |
||
1152 | else { |
||
1153 | tmp = QSB_GCR_MIN * QSB_WFQ_NONUBR_MAX / qos->txtp.min_pcr; |
||
1154 | if ( tmp == 0 ) |
||
1155 | qsb_queue_parameter_table.bit.wfqf = 1; |
||
1156 | else if ( tmp > QSB_WFQ_NONUBR_MAX ) |
||
1157 | qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_NONUBR_MAX; |
||
1158 | else |
||
1159 | qsb_queue_parameter_table.bit.wfqf = tmp; |
||
1160 | } |
||
1161 | break; |
||
1162 | default: |
||
1163 | case ATM_UBR: |
||
1164 | qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_UBR_BYPASS; |
||
1165 | } |
||
1166 | |||
1167 | /* |
||
1168 | * Sustained Cell Rate (SCR) Leaky Bucket Shaper VBR.0/VBR.1 |
||
1169 | */ |
||
1170 | if ( qos->txtp.traffic_class == ATM_VBR_RT || qos->txtp.traffic_class == ATM_VBR_NRT ) { |
||
1171 | #if 0 |
||
1172 | if ( qos->txtp.scr == 0 ) { |
||
1173 | #endif |
||
1174 | /* disable shaper */ |
||
1175 | qsb_queue_vbr_parameter_table.bit.taus = 0; |
||
1176 | qsb_queue_vbr_parameter_table.bit.ts = 0; |
||
1177 | #if 0 |
||
1178 | } else { |
||
1179 | /* Cell Loss Priority (CLP) */ |
||
1180 | if ( (vcc->atm_options & ATM_ATMOPT_CLP) ) |
||
1181 | /* CLP1 */ |
||
1182 | qsb_queue_parameter_table.bit.vbr = 1; |
||
1183 | else |
||
1184 | /* CLP0 */ |
||
1185 | qsb_queue_parameter_table.bit.vbr = 0; |
||
1186 | /* Rate Shaper Parameter (TS) and Burst Tolerance Parameter for SCR (tauS) */ |
||
1187 | tmp = ((qsb_clk * qsb_tstep) >> 5) / qos->txtp.scr + 1; |
||
1188 | qsb_queue_vbr_parameter_table.bit.ts = tmp > QSB_TP_TS_MAX ? QSB_TP_TS_MAX : tmp; |
||
1189 | tmp = (qos->txtp.mbs - 1) * (qsb_queue_vbr_parameter_table.bit.ts - qsb_queue_parameter_table.bit.tp) / 64; |
||
1190 | if ( tmp == 0 ) |
||
1191 | qsb_queue_vbr_parameter_table.bit.taus = 1; |
||
1192 | else if ( tmp > QSB_TAUS_MAX ) |
||
1193 | qsb_queue_vbr_parameter_table.bit.taus = QSB_TAUS_MAX; |
||
1194 | else |
||
1195 | qsb_queue_vbr_parameter_table.bit.taus = tmp; |
||
1196 | } |
||
1197 | #endif |
||
1198 | } else { |
||
1199 | qsb_queue_vbr_parameter_table.bit.taus = 0; |
||
1200 | qsb_queue_vbr_parameter_table.bit.ts = 0; |
||
1201 | } |
||
1202 | |||
1203 | /* Queue Parameter Table (QPT) */ |
||
1204 | *QSB_RTM = QSB_RTM_DM_SET(QSB_QPT_SET_MASK); |
||
1205 | *QSB_RTD = QSB_RTD_TTV_SET(qsb_queue_parameter_table.dword); |
||
1206 | *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_QPT) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(qsb_qid); |
||
1207 | /* Queue VBR Paramter Table (QVPT) */ |
||
1208 | *QSB_RTM = QSB_RTM_DM_SET(QSB_QVPT_SET_MASK); |
||
1209 | *QSB_RTD = QSB_RTD_TTV_SET(qsb_queue_vbr_parameter_table.dword); |
||
1210 | *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_VBR) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(qsb_qid); |
||
1211 | |||
1212 | } |
||
1213 | |||
1214 | static void qsb_global_set(void) |
||
1215 | { |
||
1216 | struct clk *fpi_clk = clk_get_fpi(); |
||
1217 | unsigned int qsb_clk = clk_get_rate(fpi_clk); |
||
1218 | int i; |
||
1219 | unsigned int tmp1, tmp2, tmp3; |
||
1220 | |||
1221 | *QSB_ICDV = QSB_ICDV_TAU_SET(qsb_tau); |
||
1222 | *QSB_SBL = QSB_SBL_SBL_SET(qsb_srvm); |
||
1223 | *QSB_CFG = QSB_CFG_TSTEPC_SET(qsb_tstep >> 1); |
||
1224 | |||
1225 | /* |
||
1226 | * set SCT and SPT per port |
||
1227 | */ |
||
1228 | for ( i = 0; i < ATM_PORT_NUMBER; i++ ) { |
||
1229 | if ( g_atm_priv_data.port[i].tx_max_cell_rate != 0 ) { |
||
1230 | tmp1 = ((qsb_clk * qsb_tstep) >> 1) / g_atm_priv_data.port[i].tx_max_cell_rate; |
||
1231 | tmp2 = tmp1 >> 6; /* integer value of Tsb */ |
||
1232 | tmp3 = (tmp1 & ((1 << 6) - 1)) + 1; /* fractional part of Tsb */ |
||
1233 | /* carry over to integer part (?) */ |
||
1234 | if ( tmp3 == (1 << 6) ) { |
||
1235 | tmp3 = 0; |
||
1236 | tmp2++; |
||
1237 | } |
||
1238 | if ( tmp2 == 0 ) |
||
1239 | tmp2 = tmp3 = 1; |
||
1240 | /* 1. set mask */ |
||
1241 | /* 2. write value to data transfer register */ |
||
1242 | /* 3. start the tranfer */ |
||
1243 | /* SCT (FracRate) */ |
||
1244 | *QSB_RTM = QSB_RTM_DM_SET(QSB_SET_SCT_MASK); |
||
1245 | *QSB_RTD = QSB_RTD_TTV_SET(tmp3); |
||
1246 | *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | |
||
1247 | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_SCT) | |
||
1248 | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | |
||
1249 | QSB_RAMAC_TESEL_SET(i & 0x01); |
||
1250 | /* SPT (SBV + PN + IntRage) */ |
||
1251 | *QSB_RTM = QSB_RTM_DM_SET(QSB_SET_SPT_MASK); |
||
1252 | *QSB_RTD = QSB_RTD_TTV_SET(QSB_SPT_SBV_VALID | QSB_SPT_PN_SET(i & 0x01) | QSB_SPT_INTRATE_SET(tmp2)); |
||
1253 | *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | |
||
1254 | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_SPT) | |
||
1255 | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | |
||
1256 | QSB_RAMAC_TESEL_SET(i & 0x01); |
||
1257 | } |
||
1258 | } |
||
1259 | } |
||
1260 | |||
1261 | static inline void set_htu_entry(unsigned int vpi, unsigned int vci, unsigned int queue, int aal5, int is_retx) |
||
1262 | { |
||
1263 | struct htu_entry htu_entry = { |
||
1264 | res1: 0x00, |
||
1265 | clp: is_retx ? 0x01 : 0x00, |
||
1266 | pid: g_atm_priv_data.conn[queue].port & 0x01, |
||
1267 | vpi: vpi, |
||
1268 | vci: vci, |
||
1269 | pti: 0x00, |
||
1270 | vld: 0x01}; |
||
1271 | |||
1272 | struct htu_mask htu_mask = { |
||
1273 | set: 0x01, |
||
1274 | clp: 0x01, |
||
1275 | pid_mask: 0x02, |
||
1276 | vpi_mask: 0x00, |
||
1277 | vci_mask: 0x0000, |
||
1278 | pti_mask: 0x03, // 0xx, user data |
||
1279 | clear: 0x00}; |
||
1280 | |||
1281 | struct htu_result htu_result = { |
||
1282 | res1: 0x00, |
||
1283 | cellid: queue, |
||
1284 | res2: 0x00, |
||
1285 | type: aal5 ? 0x00 : 0x01, |
||
1286 | ven: 0x01, |
||
1287 | res3: 0x00, |
||
1288 | qid: queue}; |
||
1289 | |||
1290 | *HTU_RESULT(queue + OAM_HTU_ENTRY_NUMBER) = htu_result; |
||
1291 | *HTU_MASK(queue + OAM_HTU_ENTRY_NUMBER) = htu_mask; |
||
1292 | *HTU_ENTRY(queue + OAM_HTU_ENTRY_NUMBER) = htu_entry; |
||
1293 | } |
||
1294 | |||
1295 | static inline void clear_htu_entry(unsigned int queue) |
||
1296 | { |
||
1297 | HTU_ENTRY(queue + OAM_HTU_ENTRY_NUMBER)->vld = 0; |
||
1298 | } |
||
1299 | |||
1300 | static void validate_oam_htu_entry(void) |
||
1301 | { |
||
1302 | HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY)->vld = 1; |
||
1303 | HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY)->vld = 1; |
||
1304 | HTU_ENTRY(OAM_F5_HTU_ENTRY)->vld = 1; |
||
1305 | } |
||
1306 | |||
1307 | static void invalidate_oam_htu_entry(void) |
||
1308 | { |
||
1309 | HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY)->vld = 0; |
||
1310 | HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY)->vld = 0; |
||
1311 | HTU_ENTRY(OAM_F5_HTU_ENTRY)->vld = 0; |
||
1312 | } |
||
1313 | |||
1314 | static inline int find_vpi(unsigned int vpi) |
||
1315 | { |
||
1316 | int i; |
||
1317 | unsigned int bit; |
||
1318 | |||
1319 | for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) { |
||
1320 | if ( (g_atm_priv_data.conn_table & bit) != 0 |
||
1321 | && g_atm_priv_data.conn[i].vcc != NULL |
||
1322 | && vpi == g_atm_priv_data.conn[i].vcc->vpi ) |
||
1323 | return i; |
||
1324 | } |
||
1325 | |||
1326 | return -1; |
||
1327 | } |
||
1328 | |||
1329 | static inline int find_vpivci(unsigned int vpi, unsigned int vci) |
||
1330 | { |
||
1331 | int i; |
||
1332 | unsigned int bit; |
||
1333 | |||
1334 | for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) { |
||
1335 | if ( (g_atm_priv_data.conn_table & bit) != 0 |
||
1336 | && g_atm_priv_data.conn[i].vcc != NULL |
||
1337 | && vpi == g_atm_priv_data.conn[i].vcc->vpi |
||
1338 | && vci == g_atm_priv_data.conn[i].vcc->vci ) |
||
1339 | return i; |
||
1340 | } |
||
1341 | |||
1342 | return -1; |
||
1343 | } |
||
1344 | |||
1345 | static inline int find_vcc(struct atm_vcc *vcc) |
||
1346 | { |
||
1347 | int i; |
||
1348 | unsigned int bit; |
||
1349 | |||
1350 | for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) { |
||
1351 | if ( (g_atm_priv_data.conn_table & bit) != 0 |
||
1352 | && g_atm_priv_data.conn[i].vcc == vcc ) |
||
1353 | return i; |
||
1354 | } |
||
1355 | |||
1356 | return -1; |
||
1357 | } |
||
1358 | |||
1359 | static inline int ifx_atm_version(const struct ltq_atm_ops *ops, char *buf) |
||
1360 | { |
||
1361 | int len = 0; |
||
1362 | unsigned int major, minor; |
||
1363 | |||
1364 | ops->fw_ver(&major, &minor); |
||
1365 | |||
1366 | len += sprintf(buf + len, "ATM%d.%d.%d", IFX_ATM_VER_MAJOR, IFX_ATM_VER_MID, IFX_ATM_VER_MINOR); |
||
1367 | len += sprintf(buf + len, " ATM (A1) firmware version %d.%d\n", major, minor); |
||
1368 | |||
1369 | return len; |
||
1370 | } |
||
1371 | |||
1372 | static inline void check_parameters(void) |
||
1373 | { |
||
1374 | /* Please refer to Amazon spec 15.4 for setting these values. */ |
||
1375 | if ( qsb_tau < 1 ) |
||
1376 | qsb_tau = 1; |
||
1377 | if ( qsb_tstep < 1 ) |
||
1378 | qsb_tstep = 1; |
||
1379 | else if ( qsb_tstep > 4 ) |
||
1380 | qsb_tstep = 4; |
||
1381 | else if ( qsb_tstep == 3 ) |
||
1382 | qsb_tstep = 2; |
||
1383 | |||
1384 | /* There is a delay between PPE write descriptor and descriptor is */ |
||
1385 | /* really stored in memory. Host also has this delay when writing */ |
||
1386 | /* descriptor. So PPE will use this value to determine if the write */ |
||
1387 | /* operation makes effect. */ |
||
1388 | if ( write_descriptor_delay < 0 ) |
||
1389 | write_descriptor_delay = 0; |
||
1390 | |||
1391 | if ( aal5_fill_pattern < 0 ) |
||
1392 | aal5_fill_pattern = 0; |
||
1393 | else |
||
1394 | aal5_fill_pattern &= 0xFF; |
||
1395 | |||
1396 | /* Because of the limitation of length field in descriptors, the packet */ |
||
1397 | /* size could not be larger than 64K minus overhead size. */ |
||
1398 | if ( aal5r_max_packet_size < 0 ) |
||
1399 | aal5r_max_packet_size = 0; |
||
1400 | else if ( aal5r_max_packet_size >= 65535 - MAX_RX_FRAME_EXTRA_BYTES ) |
||
1401 | aal5r_max_packet_size = 65535 - MAX_RX_FRAME_EXTRA_BYTES; |
||
1402 | if ( aal5r_min_packet_size < 0 ) |
||
1403 | aal5r_min_packet_size = 0; |
||
1404 | else if ( aal5r_min_packet_size > aal5r_max_packet_size ) |
||
1405 | aal5r_min_packet_size = aal5r_max_packet_size; |
||
1406 | if ( aal5s_max_packet_size < 0 ) |
||
1407 | aal5s_max_packet_size = 0; |
||
1408 | else if ( aal5s_max_packet_size >= 65535 - MAX_TX_FRAME_EXTRA_BYTES ) |
||
1409 | aal5s_max_packet_size = 65535 - MAX_TX_FRAME_EXTRA_BYTES; |
||
1410 | if ( aal5s_min_packet_size < 0 ) |
||
1411 | aal5s_min_packet_size = 0; |
||
1412 | else if ( aal5s_min_packet_size > aal5s_max_packet_size ) |
||
1413 | aal5s_min_packet_size = aal5s_max_packet_size; |
||
1414 | |||
1415 | if ( dma_rx_descriptor_length < 2 ) |
||
1416 | dma_rx_descriptor_length = 2; |
||
1417 | if ( dma_tx_descriptor_length < 2 ) |
||
1418 | dma_tx_descriptor_length = 2; |
||
1419 | if ( dma_rx_clp1_descriptor_threshold < 0 ) |
||
1420 | dma_rx_clp1_descriptor_threshold = 0; |
||
1421 | else if ( dma_rx_clp1_descriptor_threshold > dma_rx_descriptor_length ) |
||
1422 | dma_rx_clp1_descriptor_threshold = dma_rx_descriptor_length; |
||
1423 | |||
1424 | if ( dma_tx_descriptor_length < 2 ) |
||
1425 | dma_tx_descriptor_length = 2; |
||
1426 | } |
||
1427 | |||
1428 | static inline int init_priv_data(void) |
||
1429 | { |
||
1430 | void *p; |
||
1431 | int i; |
||
1432 | struct rx_descriptor rx_desc = {0}; |
||
1433 | struct sk_buff *skb; |
||
1434 | volatile struct tx_descriptor *p_tx_desc; |
||
1435 | struct sk_buff **ppskb; |
||
1436 | |||
1437 | // clear atm private data structure |
||
1438 | memset(&g_atm_priv_data, 0, sizeof(g_atm_priv_data)); |
||
1439 | |||
1440 | // allocate memory for RX (AAL) descriptors |
||
1441 | p = kzalloc(dma_rx_descriptor_length * sizeof(struct rx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL); |
||
1442 | if ( p == NULL ) |
||
1443 | return -1; |
||
1444 | dma_cache_wback_inv((unsigned long)p, dma_rx_descriptor_length * sizeof(struct rx_descriptor) + DESC_ALIGNMENT); |
||
1445 | g_atm_priv_data.aal_desc_base = p; |
||
1446 | p = (void *)((((unsigned int)p + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1); |
||
1447 | g_atm_priv_data.aal_desc = (volatile struct rx_descriptor *)p; |
||
1448 | |||
1449 | // allocate memory for RX (OAM) descriptors |
||
1450 | p = kzalloc(RX_DMA_CH_OAM_DESC_LEN * sizeof(struct rx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL); |
||
1451 | if ( p == NULL ) |
||
1452 | return -1; |
||
1453 | dma_cache_wback_inv((unsigned long)p, RX_DMA_CH_OAM_DESC_LEN * sizeof(struct rx_descriptor) + DESC_ALIGNMENT); |
||
1454 | g_atm_priv_data.oam_desc_base = p; |
||
1455 | p = (void *)((((unsigned int)p + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1); |
||
1456 | g_atm_priv_data.oam_desc = (volatile struct rx_descriptor *)p; |
||
1457 | |||
1458 | // allocate memory for RX (OAM) buffer |
||
1459 | p = kzalloc(RX_DMA_CH_OAM_DESC_LEN * RX_DMA_CH_OAM_BUF_SIZE + DATA_BUFFER_ALIGNMENT, GFP_KERNEL); |
||
1460 | if ( p == NULL ) |
||
1461 | return -1; |
||
1462 | dma_cache_wback_inv((unsigned long)p, RX_DMA_CH_OAM_DESC_LEN * RX_DMA_CH_OAM_BUF_SIZE + DATA_BUFFER_ALIGNMENT); |
||
1463 | g_atm_priv_data.oam_buf_base = p; |
||
1464 | p = (void *)(((unsigned int)p + DATA_BUFFER_ALIGNMENT - 1) & ~(DATA_BUFFER_ALIGNMENT - 1)); |
||
1465 | g_atm_priv_data.oam_buf = p; |
||
1466 | |||
1467 | // allocate memory for TX descriptors |
||
1468 | p = kzalloc(MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct tx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL); |
||
1469 | if ( p == NULL ) |
||
1470 | return -1; |
||
1471 | dma_cache_wback_inv((unsigned long)p, MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct tx_descriptor) + DESC_ALIGNMENT); |
||
1472 | g_atm_priv_data.tx_desc_base = p; |
||
1473 | |||
1474 | // allocate memory for TX skb pointers |
||
1475 | p = kzalloc(MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct sk_buff *) + 4, GFP_KERNEL); |
||
1476 | if ( p == NULL ) |
||
1477 | return -1; |
||
1478 | dma_cache_wback_inv((unsigned long)p, MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct sk_buff *) + 4); |
||
1479 | g_atm_priv_data.tx_skb_base = p; |
||
1480 | |||
1481 | // setup RX (AAL) descriptors |
||
1482 | rx_desc.own = 1; |
||
1483 | rx_desc.c = 0; |
||
1484 | rx_desc.sop = 1; |
||
1485 | rx_desc.eop = 1; |
||
1486 | rx_desc.byteoff = 0; |
||
1487 | rx_desc.id = 0; |
||
1488 | rx_desc.err = 0; |
||
1489 | rx_desc.datalen = RX_DMA_CH_AAL_BUF_SIZE; |
||
1490 | for ( i = 0; i < dma_rx_descriptor_length; i++ ) { |
||
1491 | skb = alloc_skb_rx(); |
||
1492 | if ( skb == NULL ) |
||
1493 | return -1; |
||
1494 | rx_desc.dataptr = ((unsigned int)skb->data >> 2) & 0x0FFFFFFF; |
||
1495 | g_atm_priv_data.aal_desc[i] = rx_desc; |
||
1496 | } |
||
1497 | |||
1498 | // setup RX (OAM) descriptors |
||
1499 | p = (void *)((unsigned int)g_atm_priv_data.oam_buf | KSEG1); |
||
1500 | rx_desc.own = 1; |
||
1501 | rx_desc.c = 0; |
||
1502 | rx_desc.sop = 1; |
||
1503 | rx_desc.eop = 1; |
||
1504 | rx_desc.byteoff = 0; |
||
1505 | rx_desc.id = 0; |
||
1506 | rx_desc.err = 0; |
||
1507 | rx_desc.datalen = RX_DMA_CH_OAM_BUF_SIZE; |
||
1508 | for ( i = 0; i < RX_DMA_CH_OAM_DESC_LEN; i++ ) { |
||
1509 | rx_desc.dataptr = ((unsigned int)p >> 2) & 0x0FFFFFFF; |
||
1510 | g_atm_priv_data.oam_desc[i] = rx_desc; |
||
1511 | p = (void *)((unsigned int)p + RX_DMA_CH_OAM_BUF_SIZE); |
||
1512 | } |
||
1513 | |||
1514 | // setup TX descriptors and skb pointers |
||
1515 | p_tx_desc = (volatile struct tx_descriptor *)((((unsigned int)g_atm_priv_data.tx_desc_base + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1); |
||
1516 | ppskb = (struct sk_buff **)(((unsigned int)g_atm_priv_data.tx_skb_base + 3) & ~3); |
||
1517 | for ( i = 0; i < MAX_PVC_NUMBER; i++ ) { |
||
1518 | spin_lock_init(&g_atm_priv_data.conn[i].lock); |
||
1519 | g_atm_priv_data.conn[i].tx_desc = &p_tx_desc[i * dma_tx_descriptor_length]; |
||
1520 | g_atm_priv_data.conn[i].tx_skb = &ppskb[i * dma_tx_descriptor_length]; |
||
1521 | } |
||
1522 | |||
1523 | for ( i = 0; i < ATM_PORT_NUMBER; i++ ) |
||
1524 | g_atm_priv_data.port[i].tx_max_cell_rate = DEFAULT_TX_LINK_RATE; |
||
1525 | |||
1526 | return 0; |
||
1527 | } |
||
1528 | |||
1529 | static inline void clear_priv_data(void) |
||
1530 | { |
||
1531 | int i, j; |
||
1532 | struct sk_buff *skb; |
||
1533 | |||
1534 | for ( i = 0; i < MAX_PVC_NUMBER; i++ ) { |
||
1535 | if ( g_atm_priv_data.conn[i].tx_skb != NULL ) { |
||
1536 | for ( j = 0; j < dma_tx_descriptor_length; j++ ) |
||
1537 | if ( g_atm_priv_data.conn[i].tx_skb[j] != NULL ) |
||
1538 | dev_kfree_skb_any(g_atm_priv_data.conn[i].tx_skb[j]); |
||
1539 | } |
||
1540 | } |
||
1541 | |||
1542 | if ( g_atm_priv_data.tx_skb_base != NULL ) |
||
1543 | kfree(g_atm_priv_data.tx_skb_base); |
||
1544 | |||
1545 | if ( g_atm_priv_data.tx_desc_base != NULL ) |
||
1546 | kfree(g_atm_priv_data.tx_desc_base); |
||
1547 | |||
1548 | if ( g_atm_priv_data.oam_buf_base != NULL ) |
||
1549 | kfree(g_atm_priv_data.oam_buf_base); |
||
1550 | |||
1551 | if ( g_atm_priv_data.oam_desc_base != NULL ) |
||
1552 | kfree(g_atm_priv_data.oam_desc_base); |
||
1553 | |||
1554 | if ( g_atm_priv_data.aal_desc_base != NULL ) { |
||
1555 | for ( i = 0; i < dma_rx_descriptor_length; i++ ) { |
||
1556 | if ( g_atm_priv_data.aal_desc[i].sop || g_atm_priv_data.aal_desc[i].eop ) { // descriptor initialized |
||
1557 | skb = get_skb_rx_pointer(g_atm_priv_data.aal_desc[i].dataptr); |
||
1558 | dev_kfree_skb_any(skb); |
||
1559 | } |
||
1560 | } |
||
1561 | kfree(g_atm_priv_data.aal_desc_base); |
||
1562 | } |
||
1563 | } |
||
1564 | |||
1565 | static inline void init_rx_tables(void) |
||
1566 | { |
||
1567 | int i; |
||
1568 | struct wrx_queue_config wrx_queue_config = {0}; |
||
1569 | struct wrx_dma_channel_config wrx_dma_channel_config = {0}; |
||
1570 | struct htu_entry htu_entry = {0}; |
||
1571 | struct htu_result htu_result = {0}; |
||
1572 | struct htu_mask htu_mask = { |
||
1573 | set: 0x01, |
||
1574 | clp: 0x01, |
||
1575 | pid_mask: 0x00, |
||
1576 | vpi_mask: 0x00, |
||
1577 | vci_mask: 0x00, |
||
1578 | pti_mask: 0x00, |
||
1579 | clear: 0x00 |
||
1580 | }; |
||
1581 | |||
1582 | /* |
||
1583 | * General Registers |
||
1584 | */ |
||
1585 | *CFG_WRX_HTUTS = MAX_PVC_NUMBER + OAM_HTU_ENTRY_NUMBER; |
||
1586 | #ifndef CONFIG_AMAZON_SE |
||
1587 | *CFG_WRX_QNUM = MAX_QUEUE_NUMBER; |
||
1588 | #endif |
||
1589 | *CFG_WRX_DCHNUM = RX_DMA_CH_TOTAL; |
||
1590 | *WRX_DMACH_ON = (1 << RX_DMA_CH_TOTAL) - 1; |
||
1591 | *WRX_HUNT_BITTH = DEFAULT_RX_HUNT_BITTH; |
||
1592 | |||
1593 | /* |
||
1594 | * WRX Queue Configuration Table |
||
1595 | */ |
||
1596 | wrx_queue_config.uumask = 0xFF; |
||
1597 | wrx_queue_config.cpimask = 0xFF; |
||
1598 | wrx_queue_config.uuexp = 0; |
||
1599 | wrx_queue_config.cpiexp = 0; |
||
1600 | wrx_queue_config.mfs = aal5r_max_packet_size; |
||
1601 | wrx_queue_config.oversize = aal5r_max_packet_size; |
||
1602 | wrx_queue_config.undersize = aal5r_min_packet_size; |
||
1603 | wrx_queue_config.errdp = aal5r_drop_error_packet; |
||
1604 | wrx_queue_config.dmach = RX_DMA_CH_AAL; |
||
1605 | for ( i = 0; i < MAX_QUEUE_NUMBER; i++ ) |
||
1606 | *WRX_QUEUE_CONFIG(i) = wrx_queue_config; |
||
1607 | WRX_QUEUE_CONFIG(OAM_RX_QUEUE)->dmach = RX_DMA_CH_OAM; |
||
1608 | |||
1609 | /* |
||
1610 | * WRX DMA Channel Configuration Table |
||
1611 | */ |
||
1612 | wrx_dma_channel_config.chrl = 0; |
||
1613 | wrx_dma_channel_config.clp1th = dma_rx_clp1_descriptor_threshold; |
||
1614 | wrx_dma_channel_config.mode = 0; |
||
1615 | wrx_dma_channel_config.rlcfg = 0; |
||
1616 | |||
1617 | wrx_dma_channel_config.deslen = RX_DMA_CH_OAM_DESC_LEN; |
||
1618 | wrx_dma_channel_config.desba = ((unsigned int)g_atm_priv_data.oam_desc >> 2) & 0x0FFFFFFF; |
||
1619 | *WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_OAM) = wrx_dma_channel_config; |
||
1620 | |||
1621 | wrx_dma_channel_config.deslen = dma_rx_descriptor_length; |
||
1622 | wrx_dma_channel_config.desba = ((unsigned int)g_atm_priv_data.aal_desc >> 2) & 0x0FFFFFFF; |
||
1623 | *WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_AAL) = wrx_dma_channel_config; |
||
1624 | |||
1625 | /* |
||
1626 | * HTU Tables |
||
1627 | */ |
||
1628 | for (i = 0; i < MAX_PVC_NUMBER; i++) { |
||
1629 | htu_result.qid = (unsigned int)i; |
||
1630 | |||
1631 | *HTU_ENTRY(i + OAM_HTU_ENTRY_NUMBER) = htu_entry; |
||
1632 | *HTU_MASK(i + OAM_HTU_ENTRY_NUMBER) = htu_mask; |
||
1633 | *HTU_RESULT(i + OAM_HTU_ENTRY_NUMBER) = htu_result; |
||
1634 | } |
||
1635 | |||
1636 | /* OAM HTU Entry */ |
||
1637 | htu_entry.vci = 0x03; |
||
1638 | htu_mask.pid_mask = 0x03; |
||
1639 | htu_mask.vpi_mask = 0xFF; |
||
1640 | htu_mask.vci_mask = 0x0000; |
||
1641 | htu_mask.pti_mask = 0x07; |
||
1642 | htu_result.cellid = OAM_RX_QUEUE; |
||
1643 | htu_result.type = 1; |
||
1644 | htu_result.ven = 1; |
||
1645 | htu_result.qid = OAM_RX_QUEUE; |
||
1646 | *HTU_RESULT(OAM_F4_SEG_HTU_ENTRY) = htu_result; |
||
1647 | *HTU_MASK(OAM_F4_SEG_HTU_ENTRY) = htu_mask; |
||
1648 | *HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY) = htu_entry; |
||
1649 | htu_entry.vci = 0x04; |
||
1650 | htu_result.cellid = OAM_RX_QUEUE; |
||
1651 | htu_result.type = 1; |
||
1652 | htu_result.ven = 1; |
||
1653 | htu_result.qid = OAM_RX_QUEUE; |
||
1654 | *HTU_RESULT(OAM_F4_TOT_HTU_ENTRY) = htu_result; |
||
1655 | *HTU_MASK(OAM_F4_TOT_HTU_ENTRY) = htu_mask; |
||
1656 | *HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY) = htu_entry; |
||
1657 | htu_entry.vci = 0x00; |
||
1658 | htu_entry.pti = 0x04; |
||
1659 | htu_mask.vci_mask = 0xFFFF; |
||
1660 | htu_mask.pti_mask = 0x01; |
||
1661 | htu_result.cellid = OAM_RX_QUEUE; |
||
1662 | htu_result.type = 1; |
||
1663 | htu_result.ven = 1; |
||
1664 | htu_result.qid = OAM_RX_QUEUE; |
||
1665 | *HTU_RESULT(OAM_F5_HTU_ENTRY) = htu_result; |
||
1666 | *HTU_MASK(OAM_F5_HTU_ENTRY) = htu_mask; |
||
1667 | *HTU_ENTRY(OAM_F5_HTU_ENTRY) = htu_entry; |
||
1668 | } |
||
1669 | |||
1670 | static inline void init_tx_tables(void) |
||
1671 | { |
||
1672 | int i; |
||
1673 | struct wtx_queue_config wtx_queue_config = {0}; |
||
1674 | struct wtx_dma_channel_config wtx_dma_channel_config = {0}; |
||
1675 | struct wtx_port_config wtx_port_config = { |
||
1676 | res1: 0, |
||
1677 | qid: 0, |
||
1678 | qsben: 1 |
||
1679 | }; |
||
1680 | |||
1681 | /* |
||
1682 | * General Registers |
||
1683 | */ |
||
1684 | *CFG_WTX_DCHNUM = MAX_TX_DMA_CHANNEL_NUMBER; |
||
1685 | *WTX_DMACH_ON = ((1 << MAX_TX_DMA_CHANNEL_NUMBER) - 1) ^ ((1 << FIRST_QSB_QID) - 1); |
||
1686 | *CFG_WRDES_DELAY = write_descriptor_delay; |
||
1687 | |||
1688 | /* |
||
1689 | * WTX Port Configuration Table |
||
1690 | */ |
||
1691 | for ( i = 0; i < ATM_PORT_NUMBER; i++ ) |
||
1692 | *WTX_PORT_CONFIG(i) = wtx_port_config; |
||
1693 | |||
1694 | /* |
||
1695 | * WTX Queue Configuration Table |
||
1696 | */ |
||
1697 | wtx_queue_config.qsben = 1; |
||
1698 | wtx_queue_config.sbid = 0; |
||
1699 | for ( i = 0; i < MAX_TX_DMA_CHANNEL_NUMBER; i++ ) { |
||
1700 | wtx_queue_config.qsb_vcid = i; |
||
1701 | *WTX_QUEUE_CONFIG(i) = wtx_queue_config; |
||
1702 | } |
||
1703 | |||
1704 | /* |
||
1705 | * WTX DMA Channel Configuration Table |
||
1706 | */ |
||
1707 | wtx_dma_channel_config.mode = 0; |
||
1708 | wtx_dma_channel_config.deslen = 0; |
||
1709 | wtx_dma_channel_config.desba = 0; |
||
1710 | for ( i = 0; i < FIRST_QSB_QID; i++ ) |
||
1711 | *WTX_DMA_CHANNEL_CONFIG(i) = wtx_dma_channel_config; |
||
1712 | /* normal connection */ |
||
1713 | wtx_dma_channel_config.deslen = dma_tx_descriptor_length; |
||
1714 | for ( ; i < MAX_TX_DMA_CHANNEL_NUMBER ; i++ ) { |
||
1715 | wtx_dma_channel_config.desba = ((unsigned int)g_atm_priv_data.conn[i - FIRST_QSB_QID].tx_desc >> 2) & 0x0FFFFFFF; |
||
1716 | *WTX_DMA_CHANNEL_CONFIG(i) = wtx_dma_channel_config; |
||
1717 | } |
||
1718 | } |
||
1719 | |||
1720 | static int atm_showtime_enter(struct port_cell_info *port_cell, void *xdata_addr) |
||
1721 | { |
||
1722 | int i, j, port_num; |
||
1723 | |||
1724 | ASSERT(port_cell != NULL, "port_cell is NULL"); |
||
1725 | ASSERT(xdata_addr != NULL, "xdata_addr is NULL"); |
||
1726 | |||
1727 | for ( j = 0; j < ATM_PORT_NUMBER && j < port_cell->port_num; j++ ) |
||
1728 | if ( port_cell->tx_link_rate[j] > 0 ) |
||
1729 | break; |
||
1730 | for ( i = 0; i < ATM_PORT_NUMBER && i < port_cell->port_num; i++ ) |
||
1731 | g_atm_priv_data.port[i].tx_max_cell_rate = |
||
1732 | port_cell->tx_link_rate[i] > 0 ? port_cell->tx_link_rate[i] : port_cell->tx_link_rate[j]; |
||
1733 | |||
1734 | qsb_global_set(); |
||
1735 | |||
1736 | for ( i = 0; i < MAX_PVC_NUMBER; i++ ) |
||
1737 | if ( g_atm_priv_data.conn[i].vcc != NULL ) |
||
1738 | set_qsb(g_atm_priv_data.conn[i].vcc, &g_atm_priv_data.conn[i].vcc->qos, i); |
||
1739 | |||
1740 | // TODO: ReTX set xdata_addr |
||
1741 | g_xdata_addr = xdata_addr; |
||
1742 | |||
1743 | g_showtime = 1; |
||
1744 | |||
1745 | for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ ) |
||
1746 | atm_dev_signal_change(g_atm_priv_data.port[port_num].dev, ATM_PHY_SIG_FOUND); |
||
1747 | |||
1748 | #if defined(CONFIG_VR9) |
||
1749 | IFX_REG_W32(0x0F, UTP_CFG); |
||
1750 | #endif |
||
1751 | |||
1752 | printk("enter showtime, cell rate: 0 - %d, 1 - %d, xdata addr: 0x%08x\n", |
||
1753 | g_atm_priv_data.port[0].tx_max_cell_rate, |
||
1754 | g_atm_priv_data.port[1].tx_max_cell_rate, |
||
1755 | (unsigned int)g_xdata_addr); |
||
1756 | |||
1757 | return 0; |
||
1758 | } |
||
1759 | |||
1760 | static int atm_showtime_exit(void) |
||
1761 | { |
||
1762 | int port_num; |
||
1763 | |||
1764 | if ( !g_showtime ) |
||
1765 | return -1; |
||
1766 | |||
1767 | #if defined(CONFIG_VR9) |
||
1768 | IFX_REG_W32(0x00, UTP_CFG); |
||
1769 | #endif |
||
1770 | |||
1771 | for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ ) |
||
1772 | atm_dev_signal_change(g_atm_priv_data.port[port_num].dev, ATM_PHY_SIG_LOST); |
||
1773 | |||
1774 | g_showtime = 0; |
||
1775 | g_xdata_addr = NULL; |
||
1776 | printk("leave showtime\n"); |
||
1777 | return 0; |
||
1778 | } |
||
1779 | |||
1780 | extern struct ltq_atm_ops ar9_ops; |
||
1781 | extern struct ltq_atm_ops vr9_ops; |
||
1782 | extern struct ltq_atm_ops danube_ops; |
||
1783 | extern struct ltq_atm_ops ase_ops; |
||
1784 | |||
1785 | static const struct of_device_id ltq_atm_match[] = { |
||
1786 | #ifdef CONFIG_DANUBE |
||
1787 | { .compatible = "lantiq,ppe-danube", .data = &danube_ops }, |
||
1788 | #elif defined CONFIG_AMAZON_SE |
||
1789 | { .compatible = "lantiq,ppe-ase", .data = &ase_ops }, |
||
1790 | #elif defined CONFIG_AR9 |
||
1791 | { .compatible = "lantiq,ppe-arx100", .data = &ar9_ops }, |
||
1792 | #elif defined CONFIG_VR9 |
||
1793 | { .compatible = "lantiq,ppe-xrx200", .data = &vr9_ops }, |
||
1794 | #endif |
||
1795 | {}, |
||
1796 | }; |
||
1797 | MODULE_DEVICE_TABLE(of, ltq_atm_match); |
||
1798 | |||
1799 | static int ltq_atm_probe(struct platform_device *pdev) |
||
1800 | { |
||
1801 | const struct of_device_id *match; |
||
1802 | struct ltq_atm_ops *ops = NULL; |
||
1803 | int ret; |
||
1804 | int port_num; |
||
1805 | struct port_cell_info port_cell = {0}; |
||
1806 | char ver_str[256]; |
||
1807 | |||
1808 | match = of_match_device(ltq_atm_match, &pdev->dev); |
||
1809 | if (!match) { |
||
1810 | dev_err(&pdev->dev, "failed to find matching device\n"); |
||
1811 | return -ENOENT; |
||
1812 | } |
||
1813 | ops = (struct ltq_atm_ops *) match->data; |
||
1814 | |||
1815 | check_parameters(); |
||
1816 | |||
1817 | ret = init_priv_data(); |
||
1818 | if ( ret != 0 ) { |
||
1819 | pr_err("INIT_PRIV_DATA_FAIL\n"); |
||
1820 | goto INIT_PRIV_DATA_FAIL; |
||
1821 | } |
||
1822 | |||
1823 | ops->init(); |
||
1824 | init_rx_tables(); |
||
1825 | init_tx_tables(); |
||
1826 | |||
1827 | /* create devices */ |
||
1828 | for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ ) { |
||
1829 | g_atm_priv_data.port[port_num].dev = atm_dev_register("ifxmips_atm", NULL, &g_ifx_atm_ops, -1, NULL); |
||
1830 | if ( !g_atm_priv_data.port[port_num].dev ) { |
||
1831 | pr_err("failed to register atm device %d!\n", port_num); |
||
1832 | ret = -EIO; |
||
1833 | goto ATM_DEV_REGISTER_FAIL; |
||
1834 | } else { |
||
1835 | g_atm_priv_data.port[port_num].dev->ci_range.vpi_bits = 8; |
||
1836 | g_atm_priv_data.port[port_num].dev->ci_range.vci_bits = 16; |
||
1837 | g_atm_priv_data.port[port_num].dev->link_rate = g_atm_priv_data.port[port_num].tx_max_cell_rate; |
||
1838 | g_atm_priv_data.port[port_num].dev->dev_data = (void*)port_num; |
||
1839 | |||
1840 | #if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE) |
||
1841 | atm_dev_signal_change(g_atm_priv_data.port[port_num].dev, ATM_PHY_SIG_LOST); |
||
1842 | #endif |
||
1843 | } |
||
1844 | } |
||
1845 | |||
1846 | /* register interrupt handler */ |
||
1847 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(4,1,0) |
||
1848 | ret = request_irq(PPE_MAILBOX_IGU1_INT, mailbox_irq_handler, 0, "atm_mailbox_isr", &g_atm_priv_data); |
||
1849 | #else |
||
1850 | ret = request_irq(PPE_MAILBOX_IGU1_INT, mailbox_irq_handler, IRQF_DISABLED, "atm_mailbox_isr", &g_atm_priv_data); |
||
1851 | #endif |
||
1852 | if ( ret ) { |
||
1853 | if ( ret == -EBUSY ) { |
||
1854 | pr_err("IRQ may be occupied by other driver, please reconfig to disable it.\n"); |
||
1855 | } else { |
||
1856 | pr_err("request_irq fail irq:%d\n", PPE_MAILBOX_IGU1_INT); |
||
1857 | } |
||
1858 | goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL; |
||
1859 | } |
||
1860 | disable_irq(PPE_MAILBOX_IGU1_INT); |
||
1861 | |||
1862 | |||
1863 | ret = ops->start(0); |
||
1864 | if ( ret ) { |
||
1865 | pr_err("ifx_pp32_start fail!\n"); |
||
1866 | goto PP32_START_FAIL; |
||
1867 | } |
||
1868 | |||
1869 | port_cell.port_num = ATM_PORT_NUMBER; |
||
1870 | ifx_mei_atm_showtime_check(&g_showtime, &port_cell, &g_xdata_addr); |
||
1871 | if ( g_showtime ) { |
||
1872 | atm_showtime_enter(&port_cell, &g_xdata_addr); |
||
1873 | } else { |
||
1874 | qsb_global_set(); |
||
1875 | } |
||
1876 | |||
1877 | validate_oam_htu_entry(); |
||
1878 | |||
1879 | ifx_mei_atm_showtime_enter = atm_showtime_enter; |
||
1880 | ifx_mei_atm_showtime_exit = atm_showtime_exit; |
||
1881 | |||
1882 | ifx_atm_version(ops, ver_str); |
||
1883 | printk(KERN_INFO "%s", ver_str); |
||
1884 | platform_set_drvdata(pdev, ops); |
||
1885 | printk("ifxmips_atm: ATM init succeed\n"); |
||
1886 | |||
1887 | return 0; |
||
1888 | |||
1889 | PP32_START_FAIL: |
||
1890 | free_irq(PPE_MAILBOX_IGU1_INT, &g_atm_priv_data); |
||
1891 | REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL: |
||
1892 | ATM_DEV_REGISTER_FAIL: |
||
1893 | while ( port_num-- > 0 ) |
||
1894 | atm_dev_deregister(g_atm_priv_data.port[port_num].dev); |
||
1895 | INIT_PRIV_DATA_FAIL: |
||
1896 | clear_priv_data(); |
||
1897 | printk("ifxmips_atm: ATM init failed\n"); |
||
1898 | return ret; |
||
1899 | } |
||
1900 | |||
1901 | static int ltq_atm_remove(struct platform_device *pdev) |
||
1902 | { |
||
1903 | int port_num; |
||
1904 | struct ltq_atm_ops *ops = platform_get_drvdata(pdev); |
||
1905 | |||
1906 | ifx_mei_atm_showtime_enter = NULL; |
||
1907 | ifx_mei_atm_showtime_exit = NULL; |
||
1908 | |||
1909 | invalidate_oam_htu_entry(); |
||
1910 | |||
1911 | ops->stop(0); |
||
1912 | |||
1913 | free_irq(PPE_MAILBOX_IGU1_INT, &g_atm_priv_data); |
||
1914 | |||
1915 | for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ ) |
||
1916 | atm_dev_deregister(g_atm_priv_data.port[port_num].dev); |
||
1917 | |||
1918 | ops->shutdown(); |
||
1919 | |||
1920 | clear_priv_data(); |
||
1921 | |||
1922 | return 0; |
||
1923 | } |
||
1924 | |||
1925 | static struct platform_driver ltq_atm_driver = { |
||
1926 | .probe = ltq_atm_probe, |
||
1927 | .remove = ltq_atm_remove, |
||
1928 | .driver = { |
||
1929 | .name = "atm", |
||
1930 | .owner = THIS_MODULE, |
||
1931 | .of_match_table = ltq_atm_match, |
||
1932 | }, |
||
1933 | }; |
||
1934 | |||
1935 | module_platform_driver(ltq_atm_driver); |
||
1936 | |||
1937 | MODULE_LICENSE("Dual BSD/GPL"); |