OpenWrt – Blame information for rev 3
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Rev | Author | Line No. | Line |
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1 | office | 1 | --- a/arch/arm/mach-kirkwood/Kconfig |
2 | +++ b/arch/arm/mach-kirkwood/Kconfig |
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3 | @@ -25,6 +25,9 @@ config TARGET_LSXL |
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4 | config TARGET_POGO_E02 |
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5 | bool "pogo_e02 Board" |
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3 | office | 6 | |
1 | office | 7 | +config TARGET_POGOPLUGV4 |
8 | + bool "Pogoplug V4 Board" |
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9 | + |
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10 | config TARGET_DNS325 |
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11 | bool "dns325 Board" |
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3 | office | 12 | |
13 | @@ -77,6 +80,7 @@ source "board/Marvell/guruplug/Kconfig" |
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1 | office | 14 | source "board/Marvell/sheevaplug/Kconfig" |
15 | source "board/buffalo/lsxl/Kconfig" |
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16 | source "board/cloudengines/pogo_e02/Kconfig" |
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17 | +source "board/cloudengines/pogoplugv4/Kconfig" |
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18 | source "board/d-link/dns325/Kconfig" |
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19 | source "board/iomega/iconnect/Kconfig" |
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20 | source "board/keymile/km_arm/Kconfig" |
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21 | --- a/arch/arm/mach-kirkwood/include/mach/kw88f6192.h |
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22 | +++ b/arch/arm/mach-kirkwood/include/mach/kw88f6192.h |
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3 | office | 23 | @@ -16,6 +16,6 @@ |
1 | office | 24 | #define KW_REGS_PHY_BASE KW88F6192_REGS_PHYS_BASE |
3 | office | 25 | |
1 | office | 26 | /* TCLK Core Clock defination */ |
27 | -#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ |
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28 | +#define CONFIG_SYS_TCLK 166666667 /* 166MHz */ |
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3 | office | 29 | |
1 | office | 30 | #endif /* _CONFIG_KW88F6192_H */ |
31 | --- a/arch/arm/mach-kirkwood/include/mach/mpp.h |
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32 | +++ b/arch/arm/mach-kirkwood/include/mach/mpp.h |
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3 | office | 33 | @@ -217,10 +217,12 @@ |
1 | office | 34 | #define MPP33_GPIO MPP( 33, 0x0, 1, 1, 0, 1, 1, 1 ) |
35 | #define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1 ) |
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36 | #define MPP33_GE1_13 MPP( 33, 0x3, 0, 0, 0, 1, 1, 1 ) |
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37 | +#define MPP33_SATA1_ACTn MPP( 33, 0x5, 0, 1, 0, 1, 1, 1 ) |
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3 | office | 38 | |
1 | office | 39 | #define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1 ) |
40 | #define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1 ) |
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41 | #define MPP34_GE1_14 MPP( 34, 0x3, 0, 0, 0, 1, 1, 1 ) |
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42 | +#define MPP34_SATA1_ACTn MPP( 34, 0x5, 0, 1, 0, 1, 1, 1 ) |
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3 | office | 43 | |
1 | office | 44 | #define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1 ) |
45 | #define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1 ) |
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46 | --- /dev/null |
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47 | +++ b/board/cloudengines/pogoplugv4/Kconfig |
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48 | @@ -0,0 +1,12 @@ |
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49 | +if TARGET_POGOPLUGV4 |
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50 | + |
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51 | +config SYS_BOARD |
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52 | + default "pogoplugv4" |
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53 | + |
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54 | +config SYS_VENDOR |
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55 | + default "cloudengines" |
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56 | + |
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57 | +config SYS_CONFIG_NAME |
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58 | + default "pogoplugv4" |
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59 | + |
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60 | +endif |
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61 | --- /dev/null |
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62 | +++ b/board/cloudengines/pogoplugv4/MAINTAINERS |
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63 | @@ -0,0 +1,6 @@ |
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64 | +POGOPLUGV4 BOARD |
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65 | +M: Alberto Bursi <alberto.bursi@outlook.it> |
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66 | +S: Maintained |
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67 | +F: board/cloudengines/pogoplugv4/ |
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68 | +F: include/configs/pogoplugv4.h |
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69 | +F: configs/pogoplugv4_defconfig |
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70 | --- /dev/null |
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71 | +++ b/board/cloudengines/pogoplugv4/Makefile |
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72 | @@ -0,0 +1,11 @@ |
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73 | +# |
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74 | +# (C) Copyright 2009 bodhi <mibodhi@gmail.com> |
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75 | +# |
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76 | +# Based on |
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77 | +# Marvell Semiconductor <www.marvell.com> |
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78 | +# Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
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79 | +# |
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80 | +# SPDX-License-Identifier: GPL-2.0+ |
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81 | +# |
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82 | + |
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83 | +obj-y := pogoplugv4.o |
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84 | --- /dev/null |
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85 | +++ b/board/cloudengines/pogoplugv4/kwbimage.cfg |
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86 | @@ -0,0 +1,167 @@ |
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87 | +# |
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88 | +# Copyright (C) 2012 |
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89 | +# David Purdy <david.c.purdy@gmail.com> |
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90 | +# |
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91 | +# Based on Kirkwood support: |
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92 | +# (C) Copyright 2009 |
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93 | +# Marvell Semiconductor <www.marvell.com> |
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94 | +# Written-by: Prafulla Wadaskar <prafulla <at> marvell.com> |
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95 | +# |
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96 | +# See file CREDITS for list of people who contributed to this |
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97 | +# project. |
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98 | +# |
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99 | +# This program is free software; you can redistribute it and/or |
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100 | +# modify it under the terms of the GNU General Public License as |
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101 | +# published by the Free Software Foundation; either version 2 of |
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102 | +# the License, or (at your option) any later version. |
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103 | +# |
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104 | +# This program is distributed in the hope that it will be useful, |
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105 | +# but WITHOUT ANY WARRANTY; without even the implied warranty of |
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106 | +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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107 | +# GNU General Public License for more details. |
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108 | +# |
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109 | +# You should have received a copy of the GNU General Public License |
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110 | +# along with this program; If not, see <http://www.gnu.org/licenses/>. |
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111 | +# |
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112 | +# Refer docs/README.kwimage for more details about how-to configure |
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113 | +# and create kirkwood boot image |
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114 | +# |
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115 | + |
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116 | +# Boot Media configurations (DONE) |
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117 | +BOOT_FROM nand |
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118 | +NAND_ECC_MODE default |
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119 | +NAND_PAGE_SIZE 0x0800 |
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120 | + |
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121 | +# SOC registers configuration using bootrom header extension |
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122 | +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed |
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123 | + |
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124 | +# Configure RGMII-0 interface pad voltage to 1.8V (SHOULD BE SAME) |
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125 | +DATA 0xffd100e0 0x1b1b1b9b |
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126 | + |
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127 | +#Dram initalization for SINGLE x16 CL=3 @ 200MHz (need CL=3 @ 200MHz?) |
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128 | +DATA 0xffd01400 0x43000618 # DDR Configuration register |
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129 | +# bit13-0: 0x200 (200 DDR2 clks refresh rate) |
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130 | +# bit23-14: zero |
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131 | +# bit24: 1= enable exit self refresh mode on DDR access |
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132 | +# bit25: 1 required |
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133 | +# bit29-26: zero |
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134 | +# bit31-30: 01 |
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135 | + |
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136 | +DATA 0xffd01404 0x34143000 # DDR Controller Control Low |
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137 | +# bit 4: 0=addr/cmd in smame cycle |
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138 | +# bit 5: 0=clk is driven during self refresh, we don't care for APX |
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139 | +# bit 6: 0=use recommended falling edge of clk for addr/cmd |
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140 | +# bit14: 0=input buffer always powered up |
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141 | +# bit18: 1=cpu lock transaction enabled |
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142 | +# bit23-20: 3=recommended value for CL=3 and STARTBURST_DEL disabled bit31=0 |
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143 | +# bit27-24: 6= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM |
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144 | +# bit30-28: 3 required |
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145 | +# bit31: 0=no additional STARTBURST delay |
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146 | + |
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147 | +DATA 0xffd01408 0x11012227 # DDR Timing (Low) (active cycles value +1) |
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148 | +# bit3-0: TRAS lsbs |
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149 | +# bit7-4: TRCD |
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150 | +# bit11- 8: TRP |
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151 | +# bit15-12: TWR |
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152 | +# bit19-16: TWTR |
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153 | +# bit20: TRAS msb |
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154 | +# bit23-21: 0x0 |
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155 | +# bit27-24: TRRD |
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156 | +# bit31-28: TRTP |
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157 | + |
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158 | +DATA 0xffd0140c 0x00000819 # DDR Timing (High) |
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159 | +# bit6-0: TRFC |
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160 | +# bit8-7: TR2R |
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161 | +# bit10-9: TR2W |
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162 | +# bit12-11: TW2W |
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163 | +# bit31-13: zero required |
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164 | + |
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165 | +DATA 0xffd01410 0x00000001 # DDR Address Control (changed to Dockstar vals) |
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166 | +# bit1-0: 00, Cs0width=x16 |
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167 | +# bit3-2: 10, Cs0size=512Mb |
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168 | +# bit5-4: 00, Cs2width=nonexistent |
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169 | +# bit7-6: 00, Cs1size =nonexistent |
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170 | +# bit9-8: 00, Cs2width=nonexistent |
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171 | +# bit11-10: 00, Cs2size =nonexistent |
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172 | +# bit13-12: 00, Cs3width=nonexistent |
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173 | +# bit15-14: 00, Cs3size =nonexistent |
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174 | +# bit16: 0, Cs0AddrSel |
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175 | +# bit17: 0, Cs1AddrSel |
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176 | +# bit18: 0, Cs2AddrSel |
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177 | +# bit19: 0, Cs3AddrSel |
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178 | +# bit31-20: 0 required |
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179 | + |
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180 | +DATA 0xffd01414 0x00000000 # DDR Open Pages Control |
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181 | +# bit0: 0, OpenPage enabled |
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182 | +# bit31-1: 0 required |
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183 | + |
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184 | +DATA 0xffd01418 0x00000000 # DDR Operation |
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185 | +# bit3-0: 0x0, DDR cmd |
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186 | +# bit31-4: 0 required |
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187 | + |
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188 | +DATA 0xffd0141c 0x00000632 # DDR Mode |
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189 | +# bit2-0: 2, BurstLen=2 required |
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190 | +# bit3: 0, BurstType=0 required |
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191 | +# bit6-4: 4, CL=5 (<===== change to CL=3 ?) |
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192 | +# bit7: 0, TestMode=0 normal |
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193 | +# bit8: 0, DLL reset=0 normal |
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194 | +# bit11-9: 6, auto-precharge write recovery ???????????? |
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195 | +# bit12: 0, PD must be zero |
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196 | +# bit31-13: 0 required |
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197 | + |
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198 | +DATA 0xffd01420 0x00000040 # DDR Extended Mode |
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199 | +# bit0: 0, DDR DLL enabled |
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200 | +# bit1: 0, DDR drive strenght normal |
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201 | +# bit2: 0, DDR ODT control lsd (disabled) |
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202 | +# bit5-3: 000, required |
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203 | +# bit6: 1, DDR ODT control msb, (disabled) |
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204 | +# bit9-7: 000, required |
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205 | +# bit10: 0, differential DQS enabled |
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206 | +# bit11: 0, required |
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207 | +# bit12: 0, DDR output buffer enabled |
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208 | +# bit31-13: 0 required |
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209 | + |
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210 | +DATA 0xffd01424 0x0000F07F # DDR Controller Control High |
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211 | +# bit2-0: 111, required |
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212 | +# bit3 : 1 , MBUS Burst Chop disabled |
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213 | +# bit6-4: 111, required |
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214 | +# bit7 : 0 |
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215 | +# bit8 : 0 , no sample stage |
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216 | +# bit9 : 0 , no half clock cycle addition to dataout |
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217 | +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals |
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218 | +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh |
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219 | +# bit15-12: 1111 required |
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220 | +# bit31-16: 0 required |
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221 | + |
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222 | +DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values) |
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223 | +DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values) |
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224 | + |
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225 | +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 |
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226 | +DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size |
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227 | +# bit0: 1, Window enabled |
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228 | +# bit1: 0, Write Protect disabled |
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229 | +# bit3-2: 00, CS0 hit selected |
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230 | +# bit23-4: ones, required |
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231 | +# bit31-24: 0x07, Size (i.e. 128MB) |
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232 | + |
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233 | +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled |
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234 | +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled |
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235 | +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled |
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236 | + |
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237 | +DATA 0xffd01494 0x00030000 # DDR ODT Control (Low) (DONE) |
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238 | +# bit3-0: 2, ODT0Rd, MODT[0] asserted during read from DRAM CS1 |
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239 | +# bit7-4: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0 |
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240 | +# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1 |
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241 | +# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 |
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242 | + |
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243 | +DATA 0xffd01498 0x00000000 # DDR ODT Control (High) (DONE) |
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244 | +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above |
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245 | +# bit3-2: 01, ODT1 active NEVER! |
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246 | +# bit31-4: zero, required |
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247 | + |
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248 | +DATA 0xffd0149c 0x0000e803 # CPU ODT Control (DONE) |
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249 | +DATA 0xffd01480 0x00000001 # DDR Initialization Control (DONE) |
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250 | +#bit0=1, enable DDR init upon this register write |
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251 | + |
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252 | +# End of Header extension |
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253 | +DATA 0x0 0x0 |
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254 | --- /dev/null |
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255 | +++ b/board/cloudengines/pogoplugv4/pogoplugv4.c |
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256 | @@ -0,0 +1,223 @@ |
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257 | +/* |
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258 | + * Copyright (C) 2016 bodhi <mibodhi@gmail.com> |
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259 | + * Copyright (C) 2014 bodhi <mibodhi@gmail.com> |
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260 | + * |
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261 | + * Based on |
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262 | + * |
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263 | + * Copyright (C) 2014 <ebbes.ebbes@gmail.com> |
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264 | + * |
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265 | + * Copyright (C) 2012 |
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266 | + * David Purdy <david.c.purdy@gmail.com> |
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267 | + * |
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268 | + * Based on Kirkwood support: |
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269 | + * (C) Copyright 2009 |
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270 | + * Marvell Semiconductor <www.marvell.com> |
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271 | + * Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
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272 | + * |
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273 | + * See file CREDITS for list of people who contributed to this |
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274 | + * project. |
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275 | + * |
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276 | + * This program is free software; you can redistribute it and/or |
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277 | + * modify it under the terms of the GNU General Public License as |
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278 | + * published by the Free Software Foundation; either version 2 of |
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279 | + * the License, or (at your option) any later version. |
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280 | + * |
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281 | + * This program is distributed in the hope that it will be useful, |
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282 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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283 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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284 | + * GNU General Public License for more details. |
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285 | + * |
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286 | + * You should have received a copy of the GNU General Public License |
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287 | + * along with this program; If not, see <http://www.gnu.org/licenses/>. |
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288 | + */ |
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289 | + |
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290 | +#include <common.h> |
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291 | +#include <miiphy.h> |
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292 | +#include <asm/arch/cpu.h> |
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293 | +#include <asm/arch/soc.h> |
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294 | +#include <asm/arch/mpp.h> |
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295 | +#include <asm/io.h> |
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296 | +#include "pogoplugv4.h" |
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297 | +#include <asm/arch/gpio.h> |
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298 | + |
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299 | +#ifdef CONFIG_KIRKWOOD_MMC |
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300 | +#include <kirkwood_mmc.h> |
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301 | +#endif /* CONFIG_KIRKWOOD_MMC */ |
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302 | + |
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303 | + |
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304 | +DECLARE_GLOBAL_DATA_PTR; |
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305 | + |
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306 | +int board_early_init_f(void) |
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307 | +{ |
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308 | + /* |
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309 | + * default gpio configuration |
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310 | + * There are maximum 64 gpios controlled through 2 sets of registers |
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311 | + * the below configuration configures mainly initial LED status |
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312 | + */ |
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313 | + mvebu_config_gpio(POGOPLUGV4_OE_VAL_LOW, |
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314 | + POGOPLUGV4_OE_VAL_HIGH, |
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315 | + POGOPLUGV4_OE_LOW, POGOPLUGV4_OE_HIGH); |
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316 | + |
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317 | + /* Multi-Purpose Pins Functionality configuration */ |
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318 | + u32 kwmpp_config[] = { |
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319 | + MPP0_NF_IO2, |
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320 | + MPP1_NF_IO3, |
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321 | + MPP2_NF_IO4, |
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322 | + MPP3_NF_IO5, |
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323 | + MPP4_NF_IO6, |
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324 | + MPP5_NF_IO7, |
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325 | + MPP6_SYSRST_OUTn, |
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326 | + MPP7_GPO, |
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327 | + MPP8_TW_SDA, |
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328 | + MPP9_TW_SCK, |
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329 | + MPP10_UART0_TXD, |
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330 | + MPP11_UART0_RXD, |
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331 | + MPP12_SD_CLK, |
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332 | + MPP13_SD_CMD, |
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333 | + MPP14_SD_D0, |
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334 | + MPP15_SD_D1, |
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335 | + MPP16_SD_D2, |
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336 | + MPP17_SD_D3, |
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337 | + MPP18_NF_IO0, |
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338 | + MPP19_NF_IO1, |
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339 | + MPP20_SATA1_ACTn, |
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340 | + MPP21_SATA0_ACTn, |
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341 | + MPP22_GPIO, /* Green LED */ |
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342 | + MPP23_GPIO, |
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343 | + MPP24_GPIO, /* Red LED */ |
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344 | + MPP25_GPIO, |
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345 | + MPP26_GPIO, |
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346 | + MPP27_GPIO, |
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347 | + MPP28_GPIO, |
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348 | + MPP29_GPIO, /* Eject button */ |
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349 | + MPP30_GPIO, |
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350 | + MPP31_GPIO, |
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351 | + MPP32_GPIO, |
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352 | + MPP33_GPIO, |
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353 | + MPP34_GPIO, |
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354 | + MPP35_GPIO, /* FR6192 has only 36 GPIOs */ |
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355 | + 0 |
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356 | + }; |
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357 | + kirkwood_mpp_conf(kwmpp_config, NULL); |
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358 | + |
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359 | + return 0; |
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360 | +} |
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361 | + |
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362 | +int board_init(void) |
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363 | +{ |
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364 | + /* Boot parameters address */ |
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365 | + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; |
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366 | + |
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367 | + kw_gpio_set_valid(20, 1); |
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368 | + kw_gpio_set_valid(21, 1); |
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369 | + kw_gpio_set_valid(22, 1); |
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370 | + kw_gpio_set_valid(24, 1); |
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371 | + |
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372 | + return 0; |
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373 | +} |
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374 | + |
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375 | +#ifdef CONFIG_RESET_PHY_R |
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376 | +/* Configure and initialize PHY */ |
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377 | +void reset_phy(void) |
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378 | +{ |
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379 | + u16 reg; |
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380 | + u16 devadr; |
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381 | + char *name = "egiga0"; |
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382 | + |
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383 | + if (miiphy_set_current_dev(name)) |
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384 | + return; |
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385 | + |
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386 | + /* command to read PHY dev address */ |
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387 | + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { |
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388 | + printf("Err..(%s) could not read PHY dev address\n", __func__); |
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389 | + return; |
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390 | + } |
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391 | + |
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392 | + /* |
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393 | + * Enable RGMII delay on Tx and Rx for CPU port |
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394 | + * Ref: sec 4.7.2 of chip datasheet |
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395 | + */ |
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396 | + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); |
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397 | + miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); |
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398 | + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); |
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399 | + miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); |
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400 | + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); |
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401 | + |
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402 | + /* reset the phy */ |
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403 | + miiphy_reset(name, devadr); |
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404 | + |
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405 | + debug("88E1116 Initialized on %s\n", name); |
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406 | +} |
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407 | +#endif /* CONFIG_RESET_PHY_R */ |
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408 | + |
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409 | +#ifdef CONFIG_KIRKWOOD_MMC |
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410 | +int board_mmc_init(bd_t *bis) |
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411 | +{ |
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412 | + kw_mmc_initialize(bis); |
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413 | + return 0; |
||
414 | +} |
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415 | +#endif /* CONFIG_KIRKWOOD_MMC */ |
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416 | + |
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417 | + |
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418 | +#define GREEN_LED (1 << 22) |
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419 | +#define RED_LED (1 << 24) |
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420 | +#define BOTH_LEDS (GREEN_LED | RED_LED) |
||
421 | +#define NEITHER_LED 0 |
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422 | + |
||
423 | +static void set_leds(u32 leds, u32 blinking) |
||
424 | +{ |
||
425 | + struct kwgpio_registers *r; |
||
426 | + u32 oe; |
||
427 | + u32 bl; |
||
428 | + |
||
429 | + r = (struct kwgpio_registers *)MVEBU_GPIO0_BASE; |
||
430 | + oe = readl(&r->oe) | BOTH_LEDS; |
||
431 | + writel(oe & ~leds, &r->oe); /* active low */ |
||
432 | + bl = readl(&r->blink_en) & ~BOTH_LEDS; |
||
433 | + writel(bl | blinking, &r->blink_en); |
||
434 | +} |
||
435 | + |
||
436 | +void show_boot_progress(int val) |
||
437 | +{ |
||
438 | + switch (val) { |
||
439 | + case BOOTSTAGE_ID_RUN_OS: /* booting Linux */ |
||
440 | + set_leds(BOTH_LEDS, NEITHER_LED); |
||
441 | + break; |
||
442 | + case BOOTSTAGE_ID_NET_ETH_START: /* Ethernet initialization */ |
||
443 | + set_leds(GREEN_LED, GREEN_LED); |
||
444 | + break; |
||
445 | + default: |
||
446 | + if (val < 0) /* error */ |
||
447 | + set_leds(RED_LED, RED_LED); |
||
448 | + break; |
||
449 | + } |
||
450 | +} |
||
451 | + |
||
452 | +#if defined(CONFIG_KIRKWOOD_GPIO) |
||
453 | +/* Return GPIO button status */ |
||
454 | +/* |
||
455 | +un-pressed: |
||
456 | + gpio-29 (Eject Button ) in hi (act lo) - IRQ edge (clear ) |
||
457 | +pressed |
||
458 | + gpio-29 (Eject Button ) in lo (act hi) - IRQ edge (clear ) |
||
459 | +*/ |
||
460 | + |
||
461 | +static int |
||
462 | +do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
||
463 | +{ |
||
464 | + if (strcmp(argv[1], "eject") == 0) { |
||
465 | + kw_gpio_set_valid(BTN_EJECT, GPIO_INPUT_OK); |
||
466 | + kw_gpio_direction_input(BTN_EJECT); |
||
467 | + return kw_gpio_get_value(BTN_EJECT); |
||
468 | + } |
||
469 | + else |
||
470 | + return -1; |
||
471 | +} |
||
472 | + |
||
473 | + |
||
474 | +U_BOOT_CMD(button, 2, 0, do_read_button, |
||
475 | + "Return GPIO button status 0=off 1=on", |
||
476 | + "- button eject: test buttons states\n" |
||
477 | +); |
||
478 | + |
||
479 | +#endif |
||
480 | --- /dev/null |
||
481 | +++ b/board/cloudengines/pogoplugv4/pogoplugv4.h |
||
482 | @@ -0,0 +1,50 @@ |
||
483 | +/* |
||
484 | + * Copyright (C) 2016 |
||
485 | + * bodhi <mibodhi@gmail.com> |
||
486 | + * |
||
487 | + * Copyright (C) 2012 |
||
488 | + * David Purdy <david.c.purdy@gmail.com> |
||
489 | + * |
||
490 | + * Based on Kirkwood support: |
||
491 | + * (C) Copyright 2009 |
||
492 | + * Marvell Semiconductor <www.marvell.com> |
||
493 | + * Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
||
494 | + * |
||
495 | + * See file CREDITS for list of people who contributed to this |
||
496 | + * project. |
||
497 | + * |
||
498 | + * This program is free software; you can redistribute it and/or |
||
499 | + * modify it under the terms of the GNU General Public License as |
||
500 | + * published by the Free Software Foundation; either version 2 of |
||
501 | + * the License, or (at your option) any later version. |
||
502 | + * |
||
503 | + * This program is distributed in the hope that it will be useful, |
||
504 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
||
505 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||
506 | + * GNU General Public License for more details. |
||
507 | + * |
||
508 | + * You should have received a copy of the GNU General Public License |
||
509 | + * along with this program; If not, see <http://www.gnu.org/licenses/>. |
||
510 | + */ |
||
511 | + |
||
512 | +#ifndef __POGOPLUGV4_H |
||
513 | +#define __POGOPLUGV4_H |
||
514 | + |
||
515 | +/* GPIO configuration */ |
||
516 | +#define POGOPLUGV4_OE_LOW (~(0)) |
||
517 | +#define POGOPLUGV4_OE_HIGH (~(0)) |
||
518 | +#define POGOPLUGV4_OE_VAL_LOW (1 << 29) |
||
519 | +#define POGOPLUGV4_OE_VAL_HIGH 0 |
||
520 | + |
||
521 | +/* PHY related */ |
||
522 | +#define MV88E1116_LED_FCTRL_REG 10 |
||
523 | +#define MV88E1116_CPRSP_CR3_REG 21 |
||
524 | +#define MV88E1116_MAC_CTRL_REG 21 |
||
525 | +#define MV88E1116_PGADR_REG 22 |
||
526 | +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) |
||
527 | +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) |
||
528 | + |
||
529 | +/* button */ |
||
530 | +#define BTN_EJECT 29 |
||
531 | + |
||
532 | +#endif /* __POGOPLUGV4_H */ |
||
533 | --- /dev/null |
||
534 | +++ b/configs/pogoplugv4_defconfig |
||
3 | office | 535 | @@ -0,0 +1,40 @@ |
1 | office | 536 | +CONFIG_ARM=y |
537 | +CONFIG_KIRKWOOD=y |
||
538 | +CONFIG_SYS_TEXT_BASE=0x600000 |
||
539 | +CONFIG_TARGET_POGOPLUGV4=y |
||
540 | +CONFIG_SYS_PROMPT="pogoplugv4> " |
||
541 | +CONFIG_IDENT_STRING="\nPogoplug V4" |
||
542 | +CONFIG_BOOTDELAY=3 |
||
543 | +# CONFIG_CMD_IMLS is not set |
||
544 | +# CONFIG_CMD_FLASH is not set |
||
545 | +CONFIG_SYS_NS16550=y |
||
546 | +CONFIG_CMD_FDT=y |
||
547 | +CONFIG_OF_LIBFDT=y |
||
548 | +CONFIG_OF_BOOTZ=y |
||
549 | +CONFIG_CMD_SETEXPR=y |
||
550 | +CONFIG_CMD_DHCP=y |
||
551 | +CONFIG_CMD_MII=y |
||
552 | +CONFIG_CMD_PING=y |
||
553 | +CONFIG_CMD_DNS=y |
||
554 | +CONFIG_CMD_SNTP=y |
||
555 | +CONFIG_CMD_USB=y |
||
556 | +CONFIG_CMD_DATE=y |
||
557 | +CONFIG_CMD_EXT2=y |
||
558 | +CONFIG_CMD_EXT4=y |
||
559 | +CONFIG_CMD_FAT=y |
||
560 | +CONFIG_CMD_JFFS2=y |
||
561 | +CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0x1c0000(uboot),0x40000(uboot_env),0x7e00000(ubi)" |
||
562 | +CONFIG_CMD_MTDPARTS=y |
||
563 | +CONFIG_CMD_ENV=y |
||
564 | +CONFIG_CMD_NAND=y |
||
565 | +CONFIG_CMD_MMC=y |
||
566 | +CONFIG_CMD_GPIO=y |
||
567 | +CONFIG_EFI_PARTITION=y |
||
568 | +CONFIG_ENV_IS_IN_NAND=y |
||
569 | +CONFIG_CMD_UBI=y |
||
570 | +CONFIG_USB=y |
||
571 | +CONFIG_USB_EHCI_HCD=y |
||
572 | +CONFIG_USB_STORAGE=y |
||
573 | +CONFIG_LZMA=y |
||
574 | +CONFIG_LZO=y |
||
575 | +CONFIG_SYS_LONGHELP=y |
||
576 | --- a/drivers/gpio/kw_gpio.c |
||
577 | +++ b/drivers/gpio/kw_gpio.c |
||
3 | office | 578 | @@ -148,3 +148,36 @@ void kw_gpio_set_blink(unsigned pin, int |
1 | office | 579 | /* Set blinking. */ |
580 | __set_blinking(pin, blink); |
||
581 | } |
||
582 | + |
||
583 | + |
||
584 | +/* |
||
585 | + * Hooks to GENERIC_GPIO primitives |
||
586 | + */ |
||
587 | + |
||
588 | +int gpio_direction_input(unsigned pin) |
||
589 | +{ |
||
590 | + return kw_gpio_direction_input(pin); |
||
591 | +} |
||
592 | + |
||
593 | +int gpio_direction_output(unsigned pin, int value) |
||
594 | +{ |
||
595 | + return kw_gpio_direction_output(pin, value); |
||
596 | +} |
||
597 | + |
||
598 | +void gpio_set_value(unsigned pin, int value) { |
||
599 | + kw_gpio_set_value(pin, value); |
||
600 | +} |
||
601 | + |
||
602 | +int gpio_get_value(unsigned pin) { |
||
603 | + return kw_gpio_get_value(pin); |
||
604 | +} |
||
605 | + |
||
606 | +int gpio_request(unsigned gpio, const char *label) |
||
607 | +{ |
||
608 | + return 0; |
||
609 | +} |
||
610 | + |
||
611 | +int gpio_free(unsigned gpio) |
||
612 | +{ |
||
613 | + return 0; |
||
614 | +} |
||
615 | --- a/drivers/mmc/Makefile |
||
616 | +++ b/drivers/mmc/Makefile |
||
617 | @@ -61,6 +61,7 @@ obj-$(CONFIG_MMC_SDHCI_TANGIER) += tang |
||
618 | obj-$(CONFIG_MMC_SDHCI_TEGRA) += tegra_mmc.o |
||
619 | obj-$(CONFIG_MMC_SDHCI_XENON) += xenon_sdhci.o |
||
620 | obj-$(CONFIG_MMC_SDHCI_ZYNQ) += zynq_sdhci.o |
||
621 | +obj-$(CONFIG_KIRKWOOD_MMC) += kirkwood_mmc.o |
||
3 | office | 622 | |
1 | office | 623 | obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o |
3 | office | 624 | obj-$(CONFIG_MMC_UNIPHIER) += uniphier-sd.o |
1 | office | 625 | --- /dev/null |
626 | +++ b/drivers/mmc/kirkwood_mmc.c |
||
627 | @@ -0,0 +1,482 @@ |
||
628 | +/* |
||
629 | + * (C) Copyright 2014 bodhi <mibodhi@gmail.com> |
||
630 | + * |
||
631 | + * Based on |
||
632 | + * |
||
633 | + * (C) Copyright 2014 <ebbes.ebbes@gmail.com> |
||
634 | + * |
||
635 | + * Based on |
||
636 | + * |
||
637 | + * Driver for Marvell SDIO/MMC controller |
||
638 | + * |
||
639 | + * (C) Copyright 2012 |
||
640 | + * Marvell Semiconductor <www.marvell.com> |
||
641 | + * Written-by: Gérald Kerma <uboot at doukki.net> |
||
642 | + * See file CREDITS for list of people who contributed to this |
||
643 | + * project. |
||
644 | + * |
||
645 | + * This program is free software; you can redistribute it and/or |
||
646 | + * modify it under the terms of the GNU General Public License as |
||
647 | + * published by the Free Software Foundation; either version 2 of |
||
648 | + * the License, or (at your option) any later version. |
||
649 | + * |
||
650 | + * This program is distributed in the hope that it will be useful, |
||
651 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
||
652 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||
653 | + * GNU General Public License for more details. |
||
654 | + * |
||
655 | + * You should have received a copy of the GNU General Public License |
||
656 | + * along with this program; if not, write to the Free Software |
||
657 | + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||
658 | + * MA 02111-1307 USA |
||
659 | + */ |
||
660 | + |
||
661 | +#include <common.h> |
||
662 | +#include <malloc.h> |
||
663 | +#include <part.h> |
||
664 | +#include <mmc.h> |
||
665 | +#include <asm/io.h> |
||
666 | +#include <asm/arch/cpu.h> |
||
667 | +#include <asm/arch/soc.h> |
||
668 | + |
||
669 | +#include <kirkwood_mmc.h> |
||
670 | + |
||
671 | +#define DRIVER_NAME "kwsdio" |
||
672 | + |
||
673 | +static int kw_mmc_setup_data(struct mmc_data *data) |
||
674 | +{ |
||
675 | + u32 ctrl_reg; |
||
676 | + |
||
677 | +#ifdef DEBUG |
||
678 | + printf("%s, data %s : blocks=%d blksz=%d\n", DRIVER_NAME, |
||
679 | + (data->flags & MMC_DATA_READ) ? "read" : "write", |
||
680 | + data->blocks, data->blocksize); |
||
681 | +#endif |
||
682 | + |
||
683 | + /* default to maximum timeout */ |
||
684 | + ctrl_reg = kwsd_read(SDIO_HOST_CTRL); |
||
685 | + ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX); |
||
686 | + kwsd_write(SDIO_HOST_CTRL, ctrl_reg); |
||
687 | + |
||
688 | + if (data->flags & MMC_DATA_READ) { |
||
689 | + kwsd_write(SDIO_SYS_ADDR_LOW,(u32)data->dest & 0xffff); |
||
690 | + kwsd_write(SDIO_SYS_ADDR_HI,(u32)data->dest >> 16); |
||
691 | + } else { |
||
692 | + kwsd_write(SDIO_SYS_ADDR_LOW,(u32)data->src & 0xffff); |
||
693 | + kwsd_write(SDIO_SYS_ADDR_HI,(u32)data->src >> 16); |
||
694 | + } |
||
695 | + |
||
696 | + kwsd_write(SDIO_BLK_COUNT, data->blocks); |
||
697 | + kwsd_write(SDIO_BLK_SIZE, data->blocksize); |
||
698 | + |
||
699 | + return 0; |
||
700 | +} |
||
701 | + |
||
702 | +static int kw_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) |
||
703 | +{ |
||
704 | + int timeout = 10; |
||
705 | + int err; |
||
706 | + ushort waittype = 0; |
||
707 | + ushort resptype = 0; |
||
708 | + ushort xfertype = 0; |
||
709 | + ushort resp_indx = 0; |
||
710 | + |
||
711 | +#ifdef CONFIG_MMC_DEBUG |
||
712 | + printf("cmdidx [0x%x] resp_type[0x%x] cmdarg[0x%x]\n", cmd->cmdidx, cmd->resp_type, cmd->cmdarg); |
||
713 | +#endif |
||
714 | + |
||
715 | + udelay(10000); |
||
716 | + |
||
717 | +#ifdef CONFIG_MMC_DEBUG |
||
718 | + printf("%s: cmd %d (hw state 0x%04x)\n", DRIVER_NAME, cmd->cmdidx, kwsd_read(SDIO_HW_STATE)); |
||
719 | +#endif |
||
720 | + |
||
721 | + /* Checking if card is busy */ |
||
722 | + while ((kwsd_read(SDIO_HW_STATE) & CARD_BUSY)) { |
||
723 | + if (timeout == 0) { |
||
724 | + printf("%s: card busy!\n", DRIVER_NAME); |
||
725 | + return -1; |
||
726 | + } |
||
727 | + timeout--; |
||
728 | + udelay(1000); |
||
729 | + } |
||
730 | + |
||
731 | + /* Set up for a data transfer if we have one */ |
||
732 | + if (data) { |
||
733 | + if ((err = kw_mmc_setup_data(data))) |
||
734 | + return err; |
||
735 | + } |
||
736 | + |
||
737 | + resptype = SDIO_CMD_INDEX(cmd->cmdidx); |
||
738 | + |
||
739 | + /* Analyzing resptype/xfertype/waittype for the command */ |
||
740 | + if (cmd->resp_type & MMC_RSP_BUSY) |
||
741 | + resptype |= SDIO_CMD_RSP_48BUSY; |
||
742 | + else if (cmd->resp_type & MMC_RSP_136) |
||
743 | + resptype |= SDIO_CMD_RSP_136; |
||
744 | + else if (cmd->resp_type & MMC_RSP_PRESENT) |
||
745 | + resptype |= SDIO_CMD_RSP_48; |
||
746 | + else |
||
747 | + resptype |= SDIO_CMD_RSP_NONE; |
||
748 | + |
||
749 | + if (cmd->resp_type & MMC_RSP_CRC) |
||
750 | + resptype |= SDIO_CMD_CHECK_CMDCRC; |
||
751 | + |
||
752 | + if (cmd->resp_type & MMC_RSP_OPCODE) |
||
753 | + resptype |= SDIO_CMD_INDX_CHECK; |
||
754 | + |
||
755 | + if (cmd->resp_type & MMC_RSP_PRESENT) { |
||
756 | + resptype |= SDIO_UNEXPECTED_RESP; |
||
757 | + waittype |= SDIO_NOR_UNEXP_RSP; |
||
758 | + } |
||
759 | + |
||
760 | + if (data) { |
||
761 | + resptype |= SDIO_CMD_DATA_PRESENT | SDIO_CMD_CHECK_DATACRC16; |
||
762 | + xfertype |= SDIO_XFER_MODE_HW_WR_DATA_EN; |
||
763 | + if (data->flags & MMC_DATA_READ) { |
||
764 | + xfertype |= SDIO_XFER_MODE_TO_HOST; |
||
765 | + waittype = SDIO_NOR_DMA_INI; |
||
766 | + } else |
||
767 | + waittype |= SDIO_NOR_XFER_DONE; |
||
768 | + } else |
||
769 | + waittype |= SDIO_NOR_CMD_DONE; |
||
770 | + |
||
771 | + /* Setting cmd arguments */ |
||
772 | + kwsd_write(SDIO_ARG_LOW, cmd->cmdarg & 0xffff); |
||
773 | + kwsd_write(SDIO_ARG_HI, cmd->cmdarg >> 16); |
||
774 | + |
||
775 | + /* Setting Xfer mode */ |
||
776 | + kwsd_write(SDIO_XFER_MODE, xfertype); |
||
777 | + |
||
778 | + kwsd_write(SDIO_NOR_INTR_STATUS, ~SDIO_NOR_CARD_INT); |
||
779 | + kwsd_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK); |
||
780 | + |
||
781 | + /* Sending command */ |
||
782 | + kwsd_write(SDIO_CMD, resptype); |
||
783 | +/* |
||
784 | + kwsd_write(SDIO_CMD, KW_MMC_MAKE_CMD(cmd->cmdidx, resptype)); |
||
785 | +*/ |
||
786 | + |
||
787 | + kwsd_write(SDIO_NOR_INTR_EN, SDIO_POLL_MASK); |
||
788 | + kwsd_write(SDIO_ERR_INTR_EN, SDIO_POLL_MASK); |
||
789 | + |
||
790 | + /* Waiting for completion */ |
||
791 | + timeout = 1000000; |
||
792 | + |
||
793 | + while (!((kwsd_read(SDIO_NOR_INTR_STATUS)) & waittype)) { |
||
794 | + if (kwsd_read(SDIO_NOR_INTR_STATUS) & SDIO_NOR_ERROR) { |
||
795 | +#ifdef DEBUG |
||
796 | + printf("%s: kw_mmc_send_cmd: error! cmdidx : %d, err reg: %04x\n", DRIVER_NAME, cmd->cmdidx, |
||
797 | +wsd_read(SDIO_ERR_INTR_STATUS)); |
||
798 | +#endif |
||
799 | + if (kwsd_read(SDIO_ERR_INTR_STATUS) & (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT)) { |
||
800 | + return -ETIMEDOUT; |
||
801 | + } |
||
802 | + return -ECOMM; |
||
803 | + } |
||
804 | + |
||
805 | + timeout--; |
||
806 | + udelay(1); |
||
807 | + if (timeout <= 0) { |
||
808 | + printf("%s: command timed out\n", DRIVER_NAME); |
||
809 | + return -ETIMEDOUT; |
||
810 | + } |
||
811 | + } |
||
812 | + |
||
813 | + /* Handling response */ |
||
814 | + if (cmd->resp_type & MMC_RSP_136) { |
||
815 | + uint response[8]; |
||
816 | + for (resp_indx = 0; resp_indx < 8; resp_indx++) |
||
817 | + response[resp_indx] = kwsd_read(SDIO_RSP(resp_indx)); |
||
818 | + |
||
819 | + cmd->response[0] = ((response[0] & 0x03ff) << 22) | |
||
820 | + ((response[1] & 0xffff) << 6) | |
||
821 | + ((response[2] & 0xfc00) >> 10); |
||
822 | + cmd->response[1] = ((response[2] & 0x03ff) << 22) | |
||
823 | + ((response[3] & 0xffff) << 6) | |
||
824 | + ((response[4] & 0xfc00) >> 10); |
||
825 | + cmd->response[2] = ((response[4] & 0x03ff) << 22) | |
||
826 | + ((response[5] & 0xffff) << 6) | |
||
827 | + ((response[6] & 0xfc00) >> 10); |
||
828 | + cmd->response[3] = ((response[6] & 0x03ff) << 22) | |
||
829 | + ((response[7] & 0x3fff) << 8); |
||
830 | + } else if (cmd->resp_type & MMC_RSP_PRESENT) { |
||
831 | + uint response[3]; |
||
832 | + for (resp_indx = 0; resp_indx < 3; resp_indx++) |
||
833 | + response[resp_indx] = kwsd_read(SDIO_RSP(resp_indx)); |
||
834 | + |
||
835 | + cmd->response[0] = ((response[2] & 0x003f) << (8 - 8)) | |
||
836 | + ((response[1] & 0xffff) << (14 - 8)) | |
||
837 | + ((response[0] & 0x03ff) << (30 - 8)); |
||
838 | + cmd->response[1] = ((response[0] & 0xfc00) >> 10); |
||
839 | + cmd->response[2] = 0; |
||
840 | + cmd->response[3] = 0; |
||
841 | + } |
||
842 | + |
||
843 | +#ifdef CONFIG_MMC_DEBUG |
||
844 | + printf("%s: resp[0x%x] ", DRIVER_NAME, cmd->resp_type); |
||
845 | + printf("[0x%x] ", cmd->response[0]); |
||
846 | + printf("[0x%x] ", cmd->response[1]); |
||
847 | + printf("[0x%x] ", cmd->response[2]); |
||
848 | + printf("[0x%x] ", cmd->response[3]); |
||
849 | + printf("\n"); |
||
850 | +#endif |
||
851 | + |
||
852 | + return 0; |
||
853 | +} |
||
854 | + |
||
855 | +#if 0 |
||
856 | +/* Disable these three functions as they are not used anyway */ |
||
857 | + |
||
858 | +static void kwsd_power_up(void) |
||
859 | +{ |
||
860 | +#ifdef DEBUG |
||
861 | + printf("%s: power up\n", DRIVER_NAME); |
||
862 | +#endif |
||
863 | + /* disable interrupts */ |
||
864 | + kwsd_write(SDIO_NOR_INTR_EN, 0); |
||
865 | + kwsd_write(SDIO_ERR_INTR_EN, 0); |
||
866 | + |
||
867 | + /* SW reset */ |
||
868 | + kwsd_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW); |
||
869 | + |
||
870 | + kwsd_write(SDIO_XFER_MODE, 0); |
||
871 | + |
||
872 | + /* enable status */ |
||
873 | + kwsd_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK); |
||
874 | + kwsd_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK); |
||
875 | + |
||
876 | + /* enable interrupts status */ |
||
877 | + kwsd_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK); |
||
878 | + kwsd_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK); |
||
879 | +} |
||
880 | + |
||
881 | +static void kwsd_power_down(void) |
||
882 | +{ |
||
883 | +#ifdef DEBUG |
||
884 | + printf("%s: power down\n", DRIVER_NAME); |
||
885 | +#endif |
||
886 | + /* disable interrupts */ |
||
887 | + kwsd_write(SDIO_NOR_INTR_EN, 0); |
||
888 | + kwsd_write(SDIO_ERR_INTR_EN, 0); |
||
889 | + |
||
890 | + /* SW reset */ |
||
891 | + kwsd_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW); |
||
892 | + |
||
893 | + kwsd_write(SDIO_XFER_MODE, SDIO_XFER_MODE_STOP_CLK); |
||
894 | + |
||
895 | + /* disable status */ |
||
896 | + kwsd_write(SDIO_NOR_STATUS_EN, 0); |
||
897 | + kwsd_write(SDIO_ERR_STATUS_EN, 0); |
||
898 | + |
||
899 | + /* enable interrupts status */ |
||
900 | + kwsd_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK); |
||
901 | + kwsd_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK); |
||
902 | +} |
||
903 | + |
||
904 | +static u32 kw_mmc_get_base_clock(void) |
||
905 | +{ |
||
906 | + /* Original version did a check for board device id and revision id |
||
907 | + * and assigned one of these clocks: |
||
908 | + * KW_MMC_BASE_FAST_CLK_100 (revid == 0 && devid != MV88F6282_DEV_ID) |
||
909 | + * KW_MMC_BASE_FAST_CLK_200 (revid != 0 || devid == MV88F6282_DEV_ID) |
||
910 | + * However, this check was disabled and |
||
911 | + * KW_MMC_BASE_FAST_CLOCK |
||
912 | + * was returned in every case. |
||
913 | + * Therefore, all of the dead logic was removed. */ |
||
914 | + return KW_MMC_BASE_FAST_CLOCK; |
||
915 | +} |
||
916 | +#endif /* #if 0 */ |
||
917 | + |
||
918 | +static inline u32 kw_mmc_get_base_clock(void) |
||
919 | +{ |
||
920 | + /* get MMC base clock. If any logic other than just returning |
||
921 | + * a fixed value is ever used, remove inline modifier. */ |
||
922 | + |
||
923 | + /* Possible values: |
||
924 | + * - KW_MMC_BASE_FAST_CLOCK (166 MHz) |
||
925 | + * - KW_MMC_BASE_FAST_CLK_100 (100 MHz) |
||
926 | + * - KW_MMC_BASE_FAST_CLK_200 (200 MHz) |
||
927 | + * |
||
928 | + * Tests have shown that 200 MHz is more reliable than |
||
929 | + * 166 MHz, so this value is used. */ |
||
930 | + return KW_MMC_BASE_FAST_CLK_200; |
||
931 | +} |
||
932 | + |
||
933 | +static void kw_mmc_set_clk(unsigned int clock) |
||
934 | +{ |
||
935 | + unsigned int m; |
||
936 | + |
||
937 | + if (clock == 0) { |
||
938 | +#ifdef DEBUG |
||
939 | + printf("%s: clock off\n", DRIVER_NAME); |
||
940 | +#endif |
||
941 | + kwsd_write(SDIO_XFER_MODE, SDIO_XFER_MODE_STOP_CLK); |
||
942 | + kwsd_write(SDIO_CLK_DIV, KW_MMC_BASE_DIV_MAX); |
||
943 | + } else { |
||
944 | + m = kw_mmc_get_base_clock() / (2 * clock) - 1; |
||
945 | + if (m > KW_MMC_BASE_DIV_MAX) |
||
946 | + m = KW_MMC_BASE_DIV_MAX; |
||
947 | +#ifdef DEBUG |
||
948 | + printf("%s: kw_mmc_set_clk: base = %d dividor = 0x%x clock=%d\n", DRIVER_NAME, |
||
949 | +w_mmc_get_base_clock(), m, clock); |
||
950 | +#endif |
||
951 | + kwsd_write(SDIO_CLK_DIV, m & KW_MMC_BASE_DIV_MAX); |
||
952 | + } |
||
953 | + udelay(10000); |
||
954 | +} |
||
955 | + |
||
956 | +static void kw_mmc_set_bus(unsigned int bus) |
||
957 | +{ |
||
958 | + u32 ctrl_reg = 0; |
||
959 | + |
||
960 | + ctrl_reg = kwsd_read(SDIO_HOST_CTRL); |
||
961 | + ctrl_reg &= ~SDIO_HOST_CTRL_DATA_WIDTH_4_BITS; |
||
962 | + |
||
963 | + switch (bus) { |
||
964 | + case 4: |
||
965 | + ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_4_BITS; |
||
966 | + break; |
||
967 | + case 1: |
||
968 | + default: |
||
969 | + ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_1_BIT; |
||
970 | + } |
||
971 | + /* default transfer mode */ |
||
972 | + ctrl_reg |= SDIO_HOST_CTRL_BIG_ENDIAN; |
||
973 | + ctrl_reg &= ~SDIO_HOST_CTRL_LSB_FIRST; |
||
974 | + |
||
975 | + /* default to maximum timeout */ |
||
976 | + ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX); |
||
977 | + |
||
978 | + ctrl_reg |= SDIO_HOST_CTRL_PUSH_PULL_EN; |
||
979 | + |
||
980 | + ctrl_reg |= SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY; |
||
981 | + |
||
982 | + /* |
||
983 | + * The HI_SPEED_EN bit is causing trouble with many (but not all) |
||
984 | + * high speed SD, SDHC and SDIO cards. Not enabling that bit |
||
985 | + * makes all cards work. So let's just ignore that bit for now |
||
986 | + * and revisit this issue if problems for not enabling this bit |
||
987 | + * are ever reported. |
||
988 | + */ |
||
989 | +#if 0 |
||
990 | + if (ios->timing == MMC_TIMING_MMC_HS || |
||
991 | + ios->timing == MMC_TIMING_SD_HS) |
||
992 | + ctrl_reg |= SDIO_HOST_CTRL_HI_SPEED_EN; |
||
993 | +#endif |
||
994 | + |
||
995 | +#ifdef DEBUG |
||
996 | + printf("%s: ctrl 0x%04x: %s %s %s\n", DRIVER_NAME, ctrl_reg, |
||
997 | + (ctrl_reg & SDIO_HOST_CTRL_PUSH_PULL_EN) ? |
||
998 | + "push-pull" : "open-drain", |
||
999 | + (ctrl_reg & SDIO_HOST_CTRL_DATA_WIDTH_4_BITS) ? |
||
1000 | + "4bit-width" : "1bit-width", |
||
1001 | + (ctrl_reg & SDIO_HOST_CTRL_HI_SPEED_EN) ? |
||
1002 | + "high-speed" : ""); |
||
1003 | +#endif |
||
1004 | + |
||
1005 | + kwsd_write(SDIO_HOST_CTRL, ctrl_reg); |
||
1006 | + udelay(10000); |
||
1007 | +} |
||
1008 | + |
||
1009 | +static void kw_mmc_set_ios(struct mmc *mmc) |
||
1010 | +{ |
||
1011 | +#ifdef DEBUG |
||
1012 | + printf("%s: bus[%d] clock[%d]\n", DRIVER_NAME, mmc->bus_width, mmc->clock); |
||
1013 | +#endif |
||
1014 | + kw_mmc_set_bus(mmc->bus_width); |
||
1015 | + kw_mmc_set_clk(mmc->clock); |
||
1016 | +} |
||
1017 | + |
||
1018 | +static int kw_mmc_init(struct mmc *mmc) |
||
1019 | +{ |
||
1020 | +#ifdef DEBUG |
||
1021 | + printf("%s: kw_mmc_init\n", DRIVER_NAME); |
||
1022 | +#endif |
||
1023 | + |
||
1024 | + /* |
||
1025 | + * Setting host parameters |
||
1026 | + * Initial Host Ctrl : Timeout : max , Normal Speed mode, 4-bit data mode |
||
1027 | + * Big Endian, SD memory Card, Push_pull CMD Line |
||
1028 | + */ |
||
1029 | + kwsd_write(SDIO_HOST_CTRL, |
||
1030 | + SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX) | |
||
1031 | + SDIO_HOST_CTRL_DATA_WIDTH_4_BITS | |
||
1032 | + SDIO_HOST_CTRL_BIG_ENDIAN | |
||
1033 | + SDIO_HOST_CTRL_PUSH_PULL_EN | |
||
1034 | + SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY); |
||
1035 | + |
||
1036 | + kwsd_write(SDIO_CLK_CTRL, 0); |
||
1037 | + |
||
1038 | + /* enable status */ |
||
1039 | + kwsd_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK); |
||
1040 | + kwsd_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK); |
||
1041 | + |
||
1042 | + /* disable interrupts */ |
||
1043 | + kwsd_write(SDIO_NOR_INTR_EN, 0); |
||
1044 | + kwsd_write(SDIO_ERR_INTR_EN, 0); |
||
1045 | + |
||
1046 | + /* SW reset */ |
||
1047 | + kwsd_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW); |
||
1048 | + |
||
1049 | + udelay(10000); |
||
1050 | + return 0; |
||
1051 | +} |
||
1052 | + |
||
1053 | +int kw_mmc_initialize(bd_t *bis) |
||
1054 | +{ |
||
1055 | + struct mmc *mmc = NULL; |
||
1056 | + struct mmc_config *cfg = NULL; |
||
1057 | + struct mmc_ops *ops = NULL; |
||
1058 | + char *name = NULL; |
||
1059 | + |
||
1060 | +#ifdef DEBUG |
||
1061 | + printf("%s: %s base_clock = %d\n", DRIVER_NAME, kirkwood_id(), kw_mmc_get_base_clock()); |
||
1062 | +#endif |
||
1063 | + mmc = malloc(sizeof(struct mmc)); |
||
1064 | + if (!mmc) |
||
1065 | + return -1; |
||
1066 | + memset(mmc, 0, sizeof(*mmc)); |
||
1067 | + |
||
1068 | + cfg = malloc(sizeof(*cfg)); |
||
1069 | + if (cfg == NULL) |
||
1070 | + return -1; |
||
1071 | + memset(cfg, 0, sizeof(*cfg)); |
||
1072 | + mmc->cfg = cfg; /* provided configuration */ |
||
1073 | + |
||
1074 | + ops = malloc(sizeof(*ops)); |
||
1075 | + if (ops == NULL) |
||
1076 | + return -1; |
||
1077 | + memset(ops, 0, sizeof(*ops)); |
||
1078 | + cfg->ops = ops; |
||
1079 | + |
||
1080 | + name = malloc(sizeof(DRIVER_NAME)+1); |
||
1081 | + if (name == NULL) |
||
1082 | + return -1; |
||
1083 | + cfg->name = name; |
||
1084 | + |
||
1085 | + sprintf(cfg->name, DRIVER_NAME); |
||
1086 | + |
||
1087 | + ops->send_cmd = kw_mmc_send_cmd; |
||
1088 | + ops->set_ios = kw_mmc_set_ios; |
||
1089 | + ops->init = kw_mmc_init; |
||
1090 | + |
||
1091 | + cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; |
||
1092 | + cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HS; |
||
1093 | + |
||
1094 | + cfg->f_min = kw_mmc_get_base_clock()/KW_MMC_BASE_DIV_MAX; |
||
1095 | + cfg->f_max = KW_MMC_CLOCKRATE_MAX; |
||
1096 | + cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; |
||
1097 | + |
||
1098 | + mmc = mmc_create (cfg, NULL); |
||
1099 | + |
||
1100 | + if (mmc == NULL) { |
||
1101 | + free(name); |
||
1102 | + free(ops); |
||
1103 | + free(cfg); |
||
1104 | + printf("\nFailed to Initialize MMC\n"); |
||
1105 | + return -1; |
||
1106 | + } |
||
1107 | + |
||
1108 | + return 0; |
||
1109 | +} |
||
1110 | --- a/include/configs/mv-common.h |
||
1111 | +++ b/include/configs/mv-common.h |
||
3 | office | 1112 | @@ -117,4 +117,10 @@ |
1113 | #define CONFIG_MTD_PARTITIONS |
||
1 | office | 1114 | #endif |
3 | office | 1115 | |
1 | office | 1116 | +/* |
1117 | + * Kirkwood MMC |
||
1118 | + */ |
||
1119 | +#if defined(CONFIG_KIRKWOOD) && defined(CONFIG_CMD_MMC) |
||
1120 | +#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE |
||
1121 | +#endif /* defined(CONFIG_KIRKWOOD) && defined(CONFIG_CMD_MMC) */ |
||
1122 | #endif /* _MV_COMMON_H */ |
||
1123 | --- /dev/null |
||
1124 | +++ b/include/configs/pogoplugv4.h |
||
3 | office | 1125 | @@ -0,0 +1,129 @@ |
1 | office | 1126 | +/* |
1127 | + * Copyright (C) 2014-2016 bodhi <mibodhi@gmail.com> |
||
1128 | + * Based on |
||
1129 | + * |
||
1130 | + * Copyright (C) 2012 |
||
1131 | + * David Purdy <david.c.purdy@gmail.com> |
||
1132 | + * |
||
1133 | + * Based on Kirkwood support: |
||
1134 | + * (C) Copyright 2009 |
||
1135 | + * Marvell Semiconductor <www.marvell.com> |
||
1136 | + * Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
||
1137 | + * |
||
1138 | + * See file CREDITS for list of people who contributed to this |
||
1139 | + * project. |
||
1140 | + * |
||
1141 | + * This program is free software; you can redistribute it and/or |
||
1142 | + * modify it under the terms of the GNU General Public License as |
||
1143 | + * published by the Free Software Foundation; either version 2 of |
||
1144 | + * the License, or (at your option) any later version. |
||
1145 | + * |
||
1146 | + * This program is distributed in the hope that it will be useful, |
||
1147 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
||
1148 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||
1149 | + * GNU General Public License for more details. |
||
1150 | + * |
||
1151 | + * You should have received a copy of the GNU General Public License |
||
1152 | + * along with this program; If not, see <http://www.gnu.org/licenses/>. |
||
1153 | + */ |
||
1154 | + |
||
1155 | +#ifndef _CONFIG_POGOPLUGV4_H |
||
1156 | +#define _CONFIG_POGOPLUGV4_H |
||
1157 | + |
||
1158 | +/* |
||
1159 | + * Machine type definition and ID |
||
1160 | + */ |
||
1161 | +#define MACH_TYPE_POGOPLUGV4 3960 |
||
1162 | +#define CONFIG_MACH_TYPE MACH_TYPE_POGOPLUGV4 |
||
1163 | + |
||
1164 | +/* |
||
1165 | + * High Level Configuration Options (easy to change) |
||
1166 | + */ |
||
1167 | +#define CONFIG_FEROCEON_88FR131 /* #define CPU Core subversion */ |
||
1168 | +#define CONFIG_KW88F6192 /* SOC Name */ |
||
1169 | +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ |
||
1170 | + |
||
1171 | +#define CONFIG_FEATURE_COMMAND_EDITING |
||
1172 | +#define CONFIG_SYS_64BIT_LBA |
||
1173 | + |
||
1174 | +/* |
||
1175 | + * Commands configuration |
||
1176 | + */ |
||
1177 | + |
||
1178 | +#define CONFIG_KIRKWOOD_GPIO |
||
1179 | +#define CONFIG_PREBOOT |
||
1180 | + |
||
1181 | +/* |
||
1182 | + * mv-common.h should be defined after CMD configs since it used them |
||
1183 | + * to enable certain macros |
||
1184 | + */ |
||
1185 | +#include "mv-common.h" |
||
1186 | + |
||
1187 | +/* |
||
1188 | + * Environment variables configurations |
||
1189 | + */ |
||
1190 | +#ifdef CONFIG_CMD_NAND |
||
1191 | + |
||
1192 | +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ |
||
1193 | + |
||
1194 | + |
||
1195 | +#endif |
||
1196 | + |
||
1197 | +#define CONFIG_ENV_SIZE 0x20000 /* 128k */ |
||
1198 | +#define CONFIG_ENV_ADDR 0x1c0000 |
||
1199 | +#define CONFIG_ENV_OFFSET 0x1c0000 /* env starts here */ |
||
1200 | + |
||
1201 | +/* |
||
1202 | + * Default environment variables |
||
1203 | + */ |
||
1204 | +#define CONFIG_BOOTCOMMAND \ |
||
1205 | + "usb reset ; " \ |
||
1206 | + "fatload usb 0:1 0x2000000 initramfs.bin ; "\ |
||
1207 | + "bootm 0x2000000 ; " \ |
||
1208 | + "ubi part ubi; " \ |
||
1209 | + "ubi read 0x800000 kernel; " \ |
||
1210 | + "bootm 0x800000" |
||
1211 | + |
||
1212 | +#define CONFIG_EXTRA_ENV_SETTINGS \ |
||
1213 | + "console=console=ttyS0,115200\0" \ |
||
1214 | + "mtdids=nand0=orion_nand\0" \ |
||
1215 | + "mtdparts="CONFIG_MTDPARTS_DEFAULT "\0" \ |
||
1216 | + "bootargs_root=\0" |
||
1217 | + |
||
1218 | +/* |
||
1219 | + * Ethernet Driver configuration |
||
1220 | + */ |
||
1221 | +#ifdef CONFIG_CMD_NET |
||
1222 | +#define CONFIG_NETCONSOLE |
||
1223 | +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ |
||
1224 | +#define CONFIG_PHY_BASE_ADR 0 |
||
1225 | +#endif /* CONFIG_CMD_NET */ |
||
1226 | + |
||
1227 | +/* |
||
1228 | + * File system |
||
1229 | + */ |
||
1230 | +#define CONFIG_JFFS2_NAND |
||
1231 | +#define CONFIG_JFFS2_LZO |
||
3 | office | 1232 | +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
1233 | +#define CONFIG_MTD_PARTITIONS |
||
1 | office | 1234 | + |
1235 | +/* |
||
1236 | + * SATA |
||
1237 | + */ |
||
1238 | +#ifdef CONFIG_MVSATA_IDE |
||
1239 | +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET |
||
1240 | +#endif |
||
1241 | + |
||
1242 | +/* |
||
1243 | + * Date Time |
||
1244 | + */ |
||
1245 | +#ifdef CONFIG_CMD_DATE |
||
1246 | +#define CONFIG_RTC_MV |
||
1247 | +#endif /* CONFIG_CMD_DATE */ |
||
1248 | + |
||
1249 | +/* |
||
1250 | + * Kirkwood GPIO |
||
1251 | + */ |
||
1252 | +#define CONFIG_KIRKWOOD_GPIO |
||
1253 | + |
||
1254 | +#endif /* _CONFIG_POGOPLUGV4_H */ |
||
1255 | --- /dev/null |
||
1256 | +++ b/include/kirkwood_mmc.h |
||
1257 | @@ -0,0 +1,268 @@ |
||
1258 | +/* |
||
1259 | + * (C) Copyright 2014 <ebbes.ebbes@gmail.com> |
||
1260 | + * |
||
1261 | + * Based on |
||
1262 | + * |
||
1263 | + * (C) Copyright 2012 |
||
1264 | + * Marvell Semiconductor <www.marvell.com> |
||
1265 | + * Written-by: Gérald Kerma <uboot at doukki.net> |
||
1266 | + * See file CREDITS for list of people who contributed to this |
||
1267 | + * project. |
||
1268 | + * |
||
1269 | + * This program is free software; you can redistribute it and/or |
||
1270 | + * modify it under the terms of the GNU General Public License as |
||
1271 | + * published by the Free Software Foundation; either version 2 of |
||
1272 | + * the License, or (at your option) any later version. |
||
1273 | + * |
||
1274 | + * This program is distributed in the hope that it will be useful, |
||
1275 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
||
1276 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||
1277 | + * GNU General Public License for more details. |
||
1278 | + * |
||
1279 | + * You should have received a copy of the GNU General Public License |
||
1280 | + * along with this program; if not, write to the Free Software |
||
1281 | + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||
1282 | + * MA 02111-1307 USA |
||
1283 | + */ |
||
1284 | + |
||
1285 | +#ifndef __KIRKWOOD_MMC_H__ |
||
1286 | +#define __KIRKWOOD_MMC_H__ |
||
1287 | + |
||
1288 | +/* |
||
1289 | + * Clock rates |
||
1290 | + */ |
||
1291 | + |
||
1292 | +#define KW_MMC_CLOCKRATE_MAX 50000000 |
||
1293 | +#define KW_MMC_BASE_DIV_MAX 0x7ff |
||
1294 | +#define KW_MMC_BASE_FAST_CLOCK CONFIG_SYS_TCLK |
||
1295 | +#define KW_MMC_BASE_FAST_CLK_100 100000000 |
||
1296 | +#define KW_MMC_BASE_FAST_CLK_200 200000000 |
||
1297 | + |
||
1298 | +/* |
||
1299 | + * Macros |
||
1300 | + */ |
||
1301 | +#define kwsd_write(offs, val) writel(val, CONFIG_SYS_MMC_BASE + (offs)) |
||
1302 | +#define kwsd_read(offs) readl(CONFIG_SYS_MMC_BASE + (offs)) |
||
1303 | + |
||
1304 | +#define KW_MMC_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) |
||
1305 | + |
||
1306 | +/* SDIO register */ |
||
1307 | +#define SDIO_SYS_ADDR_LOW 0x000 |
||
1308 | +#define SDIO_SYS_ADDR_HI 0x004 |
||
1309 | +#define SDIO_BLK_SIZE 0x008 |
||
1310 | +#define SDIO_BLK_COUNT 0x00c |
||
1311 | +#define SDIO_ARG_LOW 0x010 |
||
1312 | +#define SDIO_ARG_HI 0x014 |
||
1313 | +#define SDIO_XFER_MODE 0x018 |
||
1314 | +#define SDIO_CMD 0x01c |
||
1315 | +#define SDIO_RSP(i) (0x020 + ((i)<<2)) |
||
1316 | +#define SDIO_RSP0 0x020 |
||
1317 | +#define SDIO_RSP1 0x024 |
||
1318 | +#define SDIO_RSP2 0x028 |
||
1319 | +#define SDIO_RSP3 0x02c |
||
1320 | +#define SDIO_RSP4 0x030 |
||
1321 | +#define SDIO_RSP5 0x034 |
||
1322 | +#define SDIO_RSP6 0x038 |
||
1323 | +#define SDIO_RSP7 0x03c |
||
1324 | +#define SDIO_BUF_DATA_PORT 0x040 |
||
1325 | +#define SDIO_RSVED 0x044 |
||
1326 | +#define SDIO_HW_STATE 0x048 |
||
1327 | +#define SDIO_PRESENT_STATE0 0x048 |
||
1328 | +#define SDIO_PRESENT_STATE1 0x04c |
||
1329 | +#define SDIO_HOST_CTRL 0x050 |
||
1330 | +#define SDIO_BLK_GAP_CTRL 0x054 |
||
1331 | +#define SDIO_CLK_CTRL 0x058 |
||
1332 | +#define SDIO_SW_RESET 0x05c |
||
1333 | +#define SDIO_NOR_INTR_STATUS 0x060 |
||
1334 | +#define SDIO_ERR_INTR_STATUS 0x064 |
||
1335 | +#define SDIO_NOR_STATUS_EN 0x068 |
||
1336 | +#define SDIO_ERR_STATUS_EN 0x06c |
||
1337 | +#define SDIO_NOR_INTR_EN 0x070 |
||
1338 | +#define SDIO_ERR_INTR_EN 0x074 |
||
1339 | +#define SDIO_AUTOCMD12_ERR_STATUS 0x078 |
||
1340 | +#define SDIO_CURR_BYTE_LEFT 0x07c |
||
1341 | +#define SDIO_CURR_BLK_LEFT 0x080 |
||
1342 | +#define SDIO_AUTOCMD12_ARG_LOW 0x084 |
||
1343 | +#define SDIO_AUTOCMD12_ARG_HI 0x088 |
||
1344 | +#define SDIO_AUTOCMD12_INDEX 0x08c |
||
1345 | +#define SDIO_AUTO_RSP(i) (0x090 + ((i)<<2)) |
||
1346 | +#define SDIO_AUTO_RSP0 0x090 |
||
1347 | +#define SDIO_AUTO_RSP1 0x094 |
||
1348 | +#define SDIO_AUTO_RSP2 0x098 |
||
1349 | +#define SDIO_CLK_DIV 0x128 |
||
1350 | + |
||
1351 | +#define WINDOW_CTRL(i) (0x108 + ((i) << 3)) |
||
1352 | +#define WINDOW_BASE(i) (0x10c + ((i) << 3)) |
||
1353 | + |
||
1354 | +/* SDIO_PRESENT_STATE */ |
||
1355 | +#define CARD_BUSY (1 << 1) |
||
1356 | +#define CMD_INHIBIT (1 << 0) |
||
1357 | +#define CMD_TXACTIVE (1 << 8) |
||
1358 | +#define CMD_RXACTIVE (1 << 9) |
||
1359 | +#define CMD_AUTOCMD12ACTIVE (1 << 14) |
||
1360 | +#define CMD_BUS_BUSY (CMD_AUTOCMD12ACTIVE | \ |
||
1361 | + CMD_RXACTIVE | \ |
||
1362 | + CMD_TXACTIVE | \ |
||
1363 | + CMD_INHIBIT | \ |
||
1364 | + CARD_BUSY) |
||
1365 | + |
||
1366 | +/* |
||
1367 | + * SDIO_CMD |
||
1368 | + */ |
||
1369 | + |
||
1370 | +#define SDIO_CMD_RSP_NONE (0 << 0) |
||
1371 | +#define SDIO_CMD_RSP_136 (1 << 0) |
||
1372 | +#define SDIO_CMD_RSP_48 (2 << 0) |
||
1373 | +#define SDIO_CMD_RSP_48BUSY (3 << 0) |
||
1374 | + |
||
1375 | +#define SDIO_CMD_CHECK_DATACRC16 (1 << 2) |
||
1376 | +#define SDIO_CMD_CHECK_CMDCRC (1 << 3) |
||
1377 | +#define SDIO_CMD_INDX_CHECK (1 << 4) |
||
1378 | +#define SDIO_CMD_DATA_PRESENT (1 << 5) |
||
1379 | +#define SDIO_UNEXPECTED_RESP (1 << 7) |
||
1380 | + |
||
1381 | +#define SDIO_CMD_INDEX(x) ((x) << 8) |
||
1382 | + |
||
1383 | +/* |
||
1384 | + * SDIO_XFER_MODE |
||
1385 | + */ |
||
1386 | + |
||
1387 | +#define SDIO_XFER_MODE_STOP_CLK (1 << 5) |
||
1388 | +#define SDIO_XFER_MODE_HW_WR_DATA_EN (1 << 1) |
||
1389 | +#define SDIO_XFER_MODE_AUTO_CMD12 (1 << 2) |
||
1390 | +#define SDIO_XFER_MODE_INT_CHK_EN (1 << 3) |
||
1391 | +#define SDIO_XFER_MODE_TO_HOST (1 << 4) |
||
1392 | +#define SDIO_XFER_MODE_DMA (0 << 6) |
||
1393 | + |
||
1394 | +/* |
||
1395 | + * SDIO_HOST_CTRL |
||
1396 | + */ |
||
1397 | + |
||
1398 | +#define SDIO_HOST_CTRL_PUSH_PULL_EN (1 << 0) |
||
1399 | + |
||
1400 | +#define SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY (0 << 1) |
||
1401 | +#define SDIO_HOST_CTRL_CARD_TYPE_IO_ONLY (1 << 1) |
||
1402 | +#define SDIO_HOST_CTRL_CARD_TYPE_IO_MEM_COMBO (2 << 1) |
||
1403 | +#define SDIO_HOST_CTRL_CARD_TYPE_IO_MMC (3 << 1) |
||
1404 | +#define SDIO_HOST_CTRL_CARD_TYPE_MASK (3 << 1) |
||
1405 | + |
||
1406 | +#define SDIO_HOST_CTRL_BIG_ENDIAN (1 << 3) |
||
1407 | +#define SDIO_HOST_CTRL_LSB_FIRST (1 << 4) |
||
1408 | +#define SDIO_HOST_CTRL_DATA_WIDTH_1_BIT (0 << 9) |
||
1409 | +#define SDIO_HOST_CTRL_DATA_WIDTH_4_BITS (1 << 9) |
||
1410 | +#define SDIO_HOST_CTRL_HI_SPEED_EN (1 << 10) |
||
1411 | + |
||
1412 | +#define SDIO_HOST_CTRL_TMOUT_MAX 0xf |
||
1413 | +#define SDIO_HOST_CTRL_TMOUT_MASK (0xf << 11) |
||
1414 | +#define SDIO_HOST_CTRL_TMOUT(x) ((x) << 11) |
||
1415 | +#define SDIO_HOST_CTRL_TMOUT_EN (1 << 15) |
||
1416 | + |
||
1417 | +/* |
||
1418 | + * SDIO_SW_RESET |
||
1419 | + */ |
||
1420 | + |
||
1421 | +#define SDIO_SW_RESET_NOW (1 << 8) |
||
1422 | + |
||
1423 | +/* |
||
1424 | + * Normal interrupt status bits |
||
1425 | + */ |
||
1426 | + |
||
1427 | +#define SDIO_NOR_ERROR (1 << 15) |
||
1428 | +#define SDIO_NOR_UNEXP_RSP (1 << 14) |
||
1429 | +#define SDIO_NOR_AUTOCMD12_DONE (1 << 13) |
||
1430 | +#define SDIO_NOR_SUSPEND_ON (1 << 12) |
||
1431 | +#define SDIO_NOR_LMB_FF_8W_AVAIL (1 << 11) |
||
1432 | +#define SDIO_NOR_LMB_FF_8W_FILLED (1 << 10) |
||
1433 | +#define SDIO_NOR_READ_WAIT_ON (1 << 9) |
||
1434 | +#define SDIO_NOR_CARD_INT (1 << 8) |
||
1435 | +#define SDIO_NOR_READ_READY (1 << 5) |
||
1436 | +#define SDIO_NOR_WRITE_READY (1 << 4) |
||
1437 | +#define SDIO_NOR_DMA_INI (1 << 3) |
||
1438 | +#define SDIO_NOR_BLK_GAP_EVT (1 << 2) |
||
1439 | +#define SDIO_NOR_XFER_DONE (1 << 1) |
||
1440 | +#define SDIO_NOR_CMD_DONE (1 << 0) |
||
1441 | + |
||
1442 | +/* |
||
1443 | + * Error status bits |
||
1444 | + */ |
||
1445 | + |
||
1446 | +#define SDIO_ERR_CRC_STATUS (1 << 14) |
||
1447 | +#define SDIO_ERR_CRC_STARTBIT (1 << 13) |
||
1448 | +#define SDIO_ERR_CRC_ENDBIT (1 << 12) |
||
1449 | +#define SDIO_ERR_RESP_TBIT (1 << 11) |
||
1450 | +#define SDIO_ERR_XFER_SIZE (1 << 10) |
||
1451 | +#define SDIO_ERR_CMD_STARTBIT (1 << 9) |
||
1452 | +#define SDIO_ERR_AUTOCMD12 (1 << 8) |
||
1453 | +#define SDIO_ERR_DATA_ENDBIT (1 << 6) |
||
1454 | +#define SDIO_ERR_DATA_CRC (1 << 5) |
||
1455 | +#define SDIO_ERR_DATA_TIMEOUT (1 << 4) |
||
1456 | +#define SDIO_ERR_CMD_INDEX (1 << 3) |
||
1457 | +#define SDIO_ERR_CMD_ENDBIT (1 << 2) |
||
1458 | +#define SDIO_ERR_CMD_CRC (1 << 1) |
||
1459 | +#define SDIO_ERR_CMD_TIMEOUT (1 << 0) |
||
1460 | +#define SDIO_POLL_MASK 0xffff /* enable all for polling */ |
||
1461 | + |
||
1462 | +#define MMC_BLOCK_SIZE 512 |
||
1463 | + |
||
1464 | +/* |
||
1465 | + * CMD12 error status bits |
||
1466 | + */ |
||
1467 | + |
||
1468 | +#define SDIO_AUTOCMD12_ERR_NOTEXE (1 << 0) |
||
1469 | +#define SDIO_AUTOCMD12_ERR_TIMEOUT (1 << 1) |
||
1470 | +#define SDIO_AUTOCMD12_ERR_CRC (1 << 2) |
||
1471 | +#define SDIO_AUTOCMD12_ERR_ENDBIT (1 << 3) |
||
1472 | +#define SDIO_AUTOCMD12_ERR_INDEX (1 << 4) |
||
1473 | +#define SDIO_AUTOCMD12_ERR_RESP_T_BIT (1 << 5) |
||
1474 | +#define SDIO_AUTOCMD12_ERR_RESP_STARTBIT (1 << 6) |
||
1475 | + |
||
1476 | +#define MMC_RSP_PRESENT (1 << 0) |
||
1477 | +#define MMC_RSP_136 (1 << 1) /* 136 bit response */ |
||
1478 | +#define MMC_RSP_CRC (1 << 2) /* expect valid crc */ |
||
1479 | +#define MMC_RSP_BUSY (1 << 3) /* card may send busy */ |
||
1480 | +#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ |
||
1481 | + |
||
1482 | +#define MMC_BUSMODE_OPENDRAIN 1 |
||
1483 | +#define MMC_BUSMODE_PUSHPULL 2 |
||
1484 | + |
||
1485 | +#define MMC_BUS_WIDTH_1 0 |
||
1486 | +#define MMC_BUS_WIDTH_4 2 |
||
1487 | +#define MMC_BUS_WIDTH_8 3 |
||
1488 | + |
||
1489 | +#define MMC_CAP_4_BIT_DATA (1 << 0) /* Can the host do 4 bit transfers */ |
||
1490 | +#define MMC_CAP_MMC_HIGHSPEED (1 << 1) /* Can do MMC high-speed timing */ |
||
1491 | +#define MMC_CAP_SD_HIGHSPEED (1 << 2) /* Can do SD high-speed timing */ |
||
1492 | +#define MMC_CAP_SDIO_IRQ (1 << 3) /* Can signal pending SDIO IRQs */ |
||
1493 | +#define MMC_CAP_SPI (1 << 4) /* Talks only SPI protocols */ |
||
1494 | +#define MMC_CAP_NEEDS_POLL (1 << 5) /* Needs polling for card-detection */ |
||
1495 | +#define MMC_CAP_8_BIT_DATA (1 << 6) /* Can the host do 8 bit transfers */ |
||
1496 | + |
||
1497 | +#define MMC_CAP_NONREMOVABLE (1 << 8) /* Nonremovable e.g. eMMC */ |
||
1498 | +#define MMC_CAP_WAIT_WHILE_BUSY (1 << 9) /* Waits while card is busy */ |
||
1499 | +#define MMC_CAP_ERASE (1 << 10) /* Allow erase/trim commands */ |
||
1500 | +#define MMC_CAP_1_8V_DDR (1 << 11) /* can support */ |
||
1501 | + /* DDR mode at 1.8V */ |
||
1502 | +#define MMC_CAP_1_2V_DDR (1 << 12) /* can support */ |
||
1503 | + /* DDR mode at 1.2V */ |
||
1504 | +#define MMC_CAP_POWER_OFF_CARD (1 << 13) /* Can power off after boot */ |
||
1505 | +#define MMC_CAP_BUS_WIDTH_TEST (1 << 14) /* CMD14/CMD19 bus width ok */ |
||
1506 | +#define MMC_CAP_UHS_SDR12 (1 << 15) /* Host supports UHS SDR12 mode */ |
||
1507 | +#define MMC_CAP_UHS_SDR25 (1 << 16) /* Host supports UHS SDR25 mode */ |
||
1508 | +#define MMC_CAP_UHS_SDR50 (1 << 17) /* Host supports UHS SDR50 mode */ |
||
1509 | +#define MMC_CAP_UHS_SDR104 (1 << 18) /* Host supports UHS SDR104 mode */ |
||
1510 | +#define MMC_CAP_UHS_DDR50 (1 << 19) /* Host supports UHS DDR50 mode */ |
||
1511 | +#define MMC_CAP_DRIVER_TYPE_A (1 << 23) /* Host supports Driver Type A */ |
||
1512 | +#define MMC_CAP_DRIVER_TYPE_C (1 << 24) /* Host supports Driver Type C */ |
||
1513 | +#define MMC_CAP_DRIVER_TYPE_D (1 << 25) /* Host supports Driver Type D */ |
||
1514 | +#define MMC_CAP_CMD23 (1 << 30) /* CMD23 supported. */ |
||
1515 | +#define MMC_CAP_HW_RESET (1 << 31) /* Hardware reset */ |
||
1516 | + |
||
1517 | +/* |
||
1518 | + * Functions prototypes |
||
1519 | + * |
||
1520 | + * Original patch had static function declarations in this header file. |
||
1521 | + * Those should rather not be declared in the header as they only cause compiler warnings. |
||
1522 | + */ |
||
1523 | +int kw_mmc_initialize(bd_t *bis); |
||
1524 | + |
||
1525 | +#endif /* __KIRKWOOD_MMC_H__ */ |