OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | From 4904337fe34fa7fc529d6f4d9ee8b96fe7db310a Mon Sep 17 00:00:00 2001 |
2 | From: Corentin Labbe <clabbe.montjoie@gmail.com> |
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3 | Date: Tue, 31 Oct 2017 09:19:12 +0100 |
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4 | Subject: [PATCH] ARM: dts: sunxi: Restore EMAC changes (boards) |
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5 | |||
6 | The original dwmac-sun8i DT bindings have some issue on how to handle |
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7 | integrated PHY and was reverted in last RC of 4.13. |
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8 | But now we have a solution so we need to get back that was reverted. |
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9 | |||
10 | This patch restore all boards DT about dwmac-sun8i |
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11 | This reverts partially commit fe45174b72ae ("arm: dts: sunxi: Revert EMAC changes") |
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12 | |||
13 | Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> |
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14 | Acked-by: Florian Fainelli <f.fainelli@gmail.com> |
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15 | Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> |
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16 | --- |
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17 | arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 9 +++++++ |
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18 | arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 19 +++++++++++++++ |
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19 | arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 29 +++++++++++++++++++++++ |
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20 | arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 7 ++++++ |
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21 | arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 8 +++++++ |
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22 | arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 8 +++++++ |
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23 | arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts | 5 ++++ |
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24 | arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 8 +++++++ |
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25 | arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 22 +++++++++++++++++ |
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26 | arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts | 16 +++++++++++++ |
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27 | 10 files changed, 131 insertions(+) |
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28 | |||
29 | --- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts |
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30 | +++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts |
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31 | @@ -56,6 +56,8 @@ |
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32 | |||
33 | aliases { |
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34 | serial0 = &uart0; |
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35 | + /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ |
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36 | + ethernet0 = &emac; |
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37 | ethernet1 = &xr819; |
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38 | }; |
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39 | |||
40 | @@ -102,6 +104,13 @@ |
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41 | status = "okay"; |
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42 | }; |
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43 | |||
44 | +&emac { |
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45 | + phy-handle = <&int_mii_phy>; |
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46 | + phy-mode = "mii"; |
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47 | + allwinner,leds-active-low; |
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48 | + status = "okay"; |
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49 | +}; |
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50 | + |
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51 | &mmc0 { |
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52 | pinctrl-names = "default"; |
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53 | pinctrl-0 = <&mmc0_pins_a>; |
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54 | --- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts |
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55 | +++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts |
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56 | @@ -52,6 +52,7 @@ |
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57 | compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3"; |
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58 | |||
59 | aliases { |
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60 | + ethernet0 = &emac; |
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61 | serial0 = &uart0; |
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62 | serial1 = &uart1; |
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63 | }; |
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64 | @@ -114,6 +115,24 @@ |
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65 | status = "okay"; |
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66 | }; |
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67 | |||
68 | +&emac { |
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69 | + pinctrl-names = "default"; |
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70 | + pinctrl-0 = <&emac_rgmii_pins>; |
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71 | + phy-supply = <®_gmac_3v3>; |
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72 | + phy-handle = <&ext_rgmii_phy>; |
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73 | + phy-mode = "rgmii"; |
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74 | + |
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75 | + allwinner,leds-active-low; |
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76 | + status = "okay"; |
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77 | +}; |
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78 | + |
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79 | +&external_mdio { |
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80 | + ext_rgmii_phy: ethernet-phy@1 { |
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81 | + compatible = "ethernet-phy-ieee802.3-c22"; |
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82 | + reg = <0>; |
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83 | + }; |
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84 | +}; |
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85 | + |
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86 | &ir { |
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87 | pinctrl-names = "default"; |
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88 | pinctrl-0 = <&ir_pins_a>; |
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89 | --- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts |
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90 | +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts |
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91 | @@ -45,6 +45,16 @@ |
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92 | / { |
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93 | model = "FriendlyArm NanoPi M1 Plus"; |
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94 | compatible = "friendlyarm,nanopi-m1-plus", "allwinner,sun8i-h3"; |
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95 | + |
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96 | + reg_gmac_3v3: gmac-3v3 { |
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97 | + compatible = "regulator-fixed"; |
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98 | + regulator-name = "gmac-3v3"; |
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99 | + regulator-min-microvolt = <3300000>; |
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100 | + regulator-max-microvolt = <3300000>; |
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101 | + startup-delay-us = <100000>; |
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102 | + enable-active-high; |
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103 | + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; |
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104 | + }; |
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105 | }; |
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106 | |||
107 | &ehci1 { |
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108 | @@ -55,6 +65,25 @@ |
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109 | status = "okay"; |
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110 | }; |
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111 | |||
112 | +&emac { |
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113 | + pinctrl-names = "default"; |
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114 | + pinctrl-0 = <&emac_rgmii_pins>; |
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115 | + phy-supply = <®_gmac_3v3>; |
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116 | + phy-handle = <&ext_rgmii_phy>; |
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117 | + phy-mode = "rgmii"; |
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118 | + |
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119 | + allwinner,leds-active-low; |
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120 | + |
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121 | + status = "okay"; |
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122 | +}; |
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123 | + |
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124 | +&external_mdio { |
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125 | + ext_rgmii_phy: ethernet-phy@1 { |
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126 | + compatible = "ethernet-phy-ieee802.3-c22"; |
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127 | + reg = <7>; |
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128 | + }; |
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129 | +}; |
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130 | + |
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131 | &ohci1 { |
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132 | status = "okay"; |
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133 | }; |
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134 | --- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts |
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135 | +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts |
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136 | @@ -46,3 +46,10 @@ |
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137 | model = "FriendlyARM NanoPi NEO"; |
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138 | compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3"; |
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139 | }; |
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140 | + |
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141 | +&emac { |
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142 | + phy-handle = <&int_mii_phy>; |
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143 | + phy-mode = "mii"; |
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144 | + allwinner,leds-active-low; |
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145 | + status = "okay"; |
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146 | +}; |
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147 | --- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts |
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148 | +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts |
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149 | @@ -54,6 +54,7 @@ |
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150 | aliases { |
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151 | serial0 = &uart0; |
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152 | /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ |
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153 | + ethernet0 = &emac; |
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154 | ethernet1 = &rtl8189; |
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155 | }; |
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156 | |||
157 | @@ -117,6 +118,13 @@ |
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158 | status = "okay"; |
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159 | }; |
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160 | |||
161 | +&emac { |
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162 | + phy-handle = <&int_mii_phy>; |
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163 | + phy-mode = "mii"; |
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164 | + allwinner,leds-active-low; |
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165 | + status = "okay"; |
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166 | +}; |
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167 | + |
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168 | &ir { |
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169 | pinctrl-names = "default"; |
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170 | pinctrl-0 = <&ir_pins_a>; |
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171 | --- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts |
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172 | +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts |
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173 | @@ -52,6 +52,7 @@ |
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174 | compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3"; |
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175 | |||
176 | aliases { |
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177 | + ethernet0 = &emac; |
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178 | serial0 = &uart0; |
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179 | }; |
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180 | |||
181 | @@ -97,6 +98,13 @@ |
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182 | status = "okay"; |
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183 | }; |
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184 | |||
185 | +&emac { |
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186 | + phy-handle = <&int_mii_phy>; |
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187 | + phy-mode = "mii"; |
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188 | + allwinner,leds-active-low; |
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189 | + status = "okay"; |
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190 | +}; |
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191 | + |
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192 | &mmc0 { |
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193 | pinctrl-names = "default"; |
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194 | pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; |
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195 | --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts |
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196 | +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts |
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197 | @@ -53,6 +53,11 @@ |
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198 | }; |
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199 | }; |
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200 | |||
201 | +&emac { |
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202 | + /* LEDs changed to active high on the plus */ |
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203 | + /delete-property/ allwinner,leds-active-low; |
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204 | +}; |
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205 | + |
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206 | &mmc1 { |
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207 | pinctrl-names = "default"; |
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208 | pinctrl-0 = <&mmc1_pins_a>; |
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209 | --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts |
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210 | +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts |
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211 | @@ -52,6 +52,7 @@ |
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212 | compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3"; |
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213 | |||
214 | aliases { |
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215 | + ethernet0 = &emac; |
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216 | serial0 = &uart0; |
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217 | }; |
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218 | |||
219 | @@ -113,6 +114,13 @@ |
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220 | status = "okay"; |
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221 | }; |
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222 | |||
223 | +&emac { |
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224 | + phy-handle = <&int_mii_phy>; |
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225 | + phy-mode = "mii"; |
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226 | + allwinner,leds-active-low; |
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227 | + status = "okay"; |
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228 | +}; |
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229 | + |
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230 | &ir { |
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231 | pinctrl-names = "default"; |
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232 | pinctrl-0 = <&ir_pins_a>; |
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233 | --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts |
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234 | +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts |
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235 | @@ -47,6 +47,10 @@ |
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236 | model = "Xunlong Orange Pi Plus / Plus 2"; |
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237 | compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3"; |
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238 | |||
239 | + aliases { |
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240 | + ethernet0 = &emac; |
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241 | + }; |
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242 | + |
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243 | reg_gmac_3v3: gmac-3v3 { |
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244 | compatible = "regulator-fixed"; |
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245 | regulator-name = "gmac-3v3"; |
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246 | @@ -74,6 +78,24 @@ |
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247 | status = "okay"; |
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248 | }; |
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249 | |||
250 | +&emac { |
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251 | + pinctrl-names = "default"; |
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252 | + pinctrl-0 = <&emac_rgmii_pins>; |
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253 | + phy-supply = <®_gmac_3v3>; |
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254 | + phy-handle = <&ext_rgmii_phy>; |
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255 | + phy-mode = "rgmii"; |
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256 | + |
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257 | + allwinner,leds-active-low; |
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258 | + status = "okay"; |
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259 | +}; |
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260 | + |
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261 | +&external_mdio { |
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262 | + ext_rgmii_phy: ethernet-phy@1 { |
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263 | + compatible = "ethernet-phy-ieee802.3-c22"; |
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264 | + reg = <0>; |
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265 | + }; |
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266 | +}; |
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267 | + |
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268 | &mmc2 { |
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269 | pinctrl-names = "default"; |
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270 | pinctrl-0 = <&mmc2_8bit_pins>; |
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271 | --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts |
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272 | +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts |
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273 | @@ -61,3 +61,19 @@ |
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274 | gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ |
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275 | }; |
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276 | }; |
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277 | + |
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278 | +&emac { |
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279 | + pinctrl-names = "default"; |
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280 | + pinctrl-0 = <&emac_rgmii_pins>; |
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281 | + phy-supply = <®_gmac_3v3>; |
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282 | + phy-handle = <&ext_rgmii_phy>; |
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283 | + phy-mode = "rgmii"; |
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284 | + status = "okay"; |
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285 | +}; |
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286 | + |
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287 | +&external_mdio { |
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288 | + ext_rgmii_phy: ethernet-phy@1 { |
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289 | + compatible = "ethernet-phy-ieee802.3-c22"; |
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290 | + reg = <1>; |
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291 | + }; |
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292 | +}; |