OpenWrt – Blame information for rev 1

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1 office 1 From 723b8beaabf3c3c4b1ce69480141f1e926f3f3b2 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jul 2014 09:52:56 +0100
4 Subject: [PATCH 44/53] i2c: MIPS: adds ralink I2C driver
5  
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 .../devicetree/bindings/i2c/i2c-ralink.txt | 27 ++
9 drivers/i2c/busses/Kconfig | 4 +
10 drivers/i2c/busses/Makefile | 1 +
11 drivers/i2c/busses/i2c-ralink.c | 327 ++++++++++++++++++++
12 4 files changed, 359 insertions(+)
13 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-ralink.txt
14 create mode 100644 drivers/i2c/busses/i2c-ralink.c
15  
16 --- /dev/null
17 +++ b/Documentation/devicetree/bindings/i2c/i2c-ralink.txt
18 @@ -0,0 +1,27 @@
19 +I2C for Ralink platforms
20 +
21 +Required properties :
22 +- compatible : Must be "link,rt3052-i2c"
23 +- reg: physical base address of the controller and length of memory mapped
24 + region.
25 +- #address-cells = <1>;
26 +- #size-cells = <0>;
27 +
28 +Optional properties:
29 +- Child nodes conforming to i2c bus binding
30 +
31 +Example :
32 +
33 +palmbus@10000000 {
34 + i2c@900 {
35 + compatible = "link,rt3052-i2c";
36 + reg = <0x900 0x100>;
37 + #address-cells = <1>;
38 + #size-cells = <0>;
39 +
40 + hwmon@4b {
41 + compatible = "national,lm92";
42 + reg = <0x4b>;
43 + };
44 + };
45 +};
46 --- a/drivers/i2c/busses/Kconfig
47 +++ b/drivers/i2c/busses/Kconfig
48 @@ -863,6 +863,11 @@ config I2C_RK3X
49 This driver can also be built as a module. If so, the module will
50 be called i2c-rk3x.
51  
52 +config I2C_RALINK
53 + tristate "Ralink I2C Controller"
54 + depends on RALINK && !SOC_MT7621
55 + select OF_I2C
56 +
57 config HAVE_S3C2410_I2C
58 bool
59 help
60 --- a/drivers/i2c/busses/Makefile
61 +++ b/drivers/i2c/busses/Makefile
62 @@ -84,6 +84,7 @@ obj-$(CONFIG_I2C_PNX) += i2c-pnx.o
63 obj-$(CONFIG_I2C_PUV3) += i2c-puv3.o
64 obj-$(CONFIG_I2C_PXA) += i2c-pxa.o
65 obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o
66 +obj-$(CONFIG_I2C_RALINK) += i2c-ralink.o
67 obj-$(CONFIG_I2C_QUP) += i2c-qup.o
68 obj-$(CONFIG_I2C_RIIC) += i2c-riic.o
69 obj-$(CONFIG_I2C_RK3X) += i2c-rk3x.o
70 --- /dev/null
71 +++ b/drivers/i2c/busses/i2c-ralink.c
72 @@ -0,0 +1,435 @@
73 +/*
74 + * drivers/i2c/busses/i2c-ralink.c
75 + *
76 + * Copyright (C) 2013 Steven Liu <steven_liu@mediatek.com>
77 + * Copyright (C) 2016 Michael Lee <igvtee@gmail.com>
78 + *
79 + * Improve driver for i2cdetect from i2c-tools to detect i2c devices on the bus.
80 + * (C) 2014 Sittisak <sittisaks@hotmail.com>
81 + *
82 + * This software is licensed under the terms of the GNU General Public
83 + * License version 2, as published by the Free Software Foundation, and
84 + * may be copied, distributed, and modified under those terms.
85 + *
86 + * This program is distributed in the hope that it will be useful,
87 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
88 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
89 + * GNU General Public License for more details.
90 + *
91 + */
92 +
93 +#include <linux/interrupt.h>
94 +#include <linux/kernel.h>
95 +#include <linux/module.h>
96 +#include <linux/reset.h>
97 +#include <linux/delay.h>
98 +#include <linux/slab.h>
99 +#include <linux/init.h>
100 +#include <linux/errno.h>
101 +#include <linux/platform_device.h>
102 +#include <linux/of_platform.h>
103 +#include <linux/i2c.h>
104 +#include <linux/io.h>
105 +#include <linux/err.h>
106 +#include <linux/clk.h>
107 +
108 +#define REG_CONFIG_REG 0x00
109 +#define REG_CLKDIV_REG 0x04
110 +#define REG_DEVADDR_REG 0x08
111 +#define REG_ADDR_REG 0x0C
112 +#define REG_DATAOUT_REG 0x10
113 +#define REG_DATAIN_REG 0x14
114 +#define REG_STATUS_REG 0x18
115 +#define REG_STARTXFR_REG 0x1C
116 +#define REG_BYTECNT_REG 0x20
117 +
118 +/* REG_CONFIG_REG */
119 +#define I2C_ADDRLEN_OFFSET 5
120 +#define I2C_DEVADLEN_OFFSET 2
121 +#define I2C_ADDRLEN_MASK 0x3
122 +#define I2C_ADDR_DIS BIT(1)
123 +#define I2C_DEVADDR_DIS BIT(0)
124 +#define I2C_ADDRLEN_8 (7 << I2C_ADDRLEN_OFFSET)
125 +#define I2C_DEVADLEN_7 (6 << I2C_DEVADLEN_OFFSET)
126 +#define I2C_CONF_DEFAULT (I2C_ADDRLEN_8 | I2C_DEVADLEN_7)
127 +
128 +/* REG_CLKDIV_REG */
129 +#define I2C_CLKDIV_MASK 0xffff
130 +
131 +/* REG_DEVADDR_REG */
132 +#define I2C_DEVADDR_MASK 0x7f
133 +
134 +/* REG_ADDR_REG */
135 +#define I2C_ADDR_MASK 0xff
136 +
137 +/* REG_STATUS_REG */
138 +#define I2C_STARTERR BIT(4)
139 +#define I2C_ACKERR BIT(3)
140 +#define I2C_DATARDY BIT(2)
141 +#define I2C_SDOEMPTY BIT(1)
142 +#define I2C_BUSY BIT(0)
143 +
144 +/* REG_STARTXFR_REG */
145 +#define NOSTOP_CMD BIT(2)
146 +#define NODATA_CMD BIT(1)
147 +#define READ_CMD BIT(0)
148 +
149 +/* REG_BYTECNT_REG */
150 +#define BYTECNT_MAX 64
151 +#define SET_BYTECNT(x) (x - 1)
152 +
153 +/* timeout waiting for I2C devices to respond (clock streching) */
154 +#define TIMEOUT_MS 1000
155 +#define DELAY_INTERVAL_US 100
156 +
157 +struct rt_i2c {
158 + void __iomem *base;
159 + struct clk *clk;
160 + struct device *dev;
161 + struct i2c_adapter adap;
162 + u32 cur_clk;
163 + u32 clk_div;
164 + u32 flags;
165 +};
166 +
167 +static void rt_i2c_w32(struct rt_i2c *i2c, u32 val, unsigned reg)
168 +{
169 + iowrite32(val, i2c->base + reg);
170 +}
171 +
172 +static u32 rt_i2c_r32(struct rt_i2c *i2c, unsigned reg)
173 +{
174 + return ioread32(i2c->base + reg);
175 +}
176 +
177 +static int poll_down_timeout(void __iomem *addr, u32 mask)
178 +{
179 + unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);
180 +
181 + do {
182 + if (!(readl_relaxed(addr) & mask))
183 + return 0;
184 +
185 + usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50);
186 + } while (time_before(jiffies, timeout));
187 +
188 + return (readl_relaxed(addr) & mask) ? -EAGAIN : 0;
189 +}
190 +
191 +static int rt_i2c_wait_idle(struct rt_i2c *i2c)
192 +{
193 + int ret;
194 +
195 + ret = poll_down_timeout(i2c->base + REG_STATUS_REG, I2C_BUSY);
196 + if (ret < 0)
197 + dev_dbg(i2c->dev, "idle err(%d)\n", ret);
198 +
199 + return ret;
200 +}
201 +
202 +static int poll_up_timeout(void __iomem *addr, u32 mask)
203 +{
204 + unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);
205 + u32 status;
206 +
207 + do {
208 + status = readl_relaxed(addr);
209 +
210 + /* check error status */
211 + if (status & I2C_STARTERR)
212 + return -EAGAIN;
213 + else if (status & I2C_ACKERR)
214 + return -ENXIO;
215 + else if (status & mask)
216 + return 0;
217 +
218 + usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50);
219 + } while (time_before(jiffies, timeout));
220 +
221 + return -ETIMEDOUT;
222 +}
223 +
224 +static int rt_i2c_wait_rx_done(struct rt_i2c *i2c)
225 +{
226 + int ret;
227 +
228 + ret = poll_up_timeout(i2c->base + REG_STATUS_REG, I2C_DATARDY);
229 + if (ret < 0)
230 + dev_dbg(i2c->dev, "rx err(%d)\n", ret);
231 +
232 + return ret;
233 +}
234 +
235 +static int rt_i2c_wait_tx_done(struct rt_i2c *i2c)
236 +{
237 + int ret;
238 +
239 + ret = poll_up_timeout(i2c->base + REG_STATUS_REG, I2C_SDOEMPTY);
240 + if (ret < 0)
241 + dev_dbg(i2c->dev, "tx err(%d)\n", ret);
242 +
243 + return ret;
244 +}
245 +
246 +static void rt_i2c_reset(struct rt_i2c *i2c)
247 +{
248 + device_reset(i2c->adap.dev.parent);
249 + barrier();
250 + rt_i2c_w32(i2c, i2c->clk_div, REG_CLKDIV_REG);
251 +}
252 +
253 +static void rt_i2c_dump_reg(struct rt_i2c *i2c)
254 +{
255 + dev_dbg(i2c->dev, "conf %08x, clkdiv %08x, devaddr %08x, " \
256 + "addr %08x, dataout %08x, datain %08x, " \
257 + "status %08x, startxfr %08x, bytecnt %08x\n",
258 + rt_i2c_r32(i2c, REG_CONFIG_REG),
259 + rt_i2c_r32(i2c, REG_CLKDIV_REG),
260 + rt_i2c_r32(i2c, REG_DEVADDR_REG),
261 + rt_i2c_r32(i2c, REG_ADDR_REG),
262 + rt_i2c_r32(i2c, REG_DATAOUT_REG),
263 + rt_i2c_r32(i2c, REG_DATAIN_REG),
264 + rt_i2c_r32(i2c, REG_STATUS_REG),
265 + rt_i2c_r32(i2c, REG_STARTXFR_REG),
266 + rt_i2c_r32(i2c, REG_BYTECNT_REG));
267 +}
268 +
269 +static int rt_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
270 + int num)
271 +{
272 + struct rt_i2c *i2c;
273 + struct i2c_msg *pmsg;
274 + unsigned char addr;
275 + int i, j, ret;
276 + u32 cmd;
277 +
278 + i2c = i2c_get_adapdata(adap);
279 +
280 + for (i = 0; i < num; i++) {
281 + pmsg = &msgs[i];
282 + if (i == (num - 1))
283 + cmd = 0;
284 + else
285 + cmd = NOSTOP_CMD;
286 +
287 + dev_dbg(i2c->dev, "addr: 0x%x, len: %d, flags: 0x%x, stop: %d\n",
288 + pmsg->addr, pmsg->len, pmsg->flags,
289 + (cmd == 0)? 1 : 0);
290 +
291 + /* wait hardware idle */
292 + if ((ret = rt_i2c_wait_idle(i2c)))
293 + goto err_timeout;
294 +
295 + if (pmsg->flags & I2C_M_TEN) {
296 + rt_i2c_w32(i2c, I2C_CONF_DEFAULT, REG_CONFIG_REG);
297 + /* 10 bits address */
298 + addr = 0x78 | ((pmsg->addr >> 8) & 0x03);
299 + rt_i2c_w32(i2c, addr & I2C_DEVADDR_MASK,
300 + REG_DEVADDR_REG);
301 + rt_i2c_w32(i2c, pmsg->addr & I2C_ADDR_MASK,
302 + REG_ADDR_REG);
303 + } else {
304 + rt_i2c_w32(i2c, I2C_CONF_DEFAULT | I2C_ADDR_DIS,
305 + REG_CONFIG_REG);
306 + /* 7 bits address */
307 + rt_i2c_w32(i2c, pmsg->addr & I2C_DEVADDR_MASK,
308 + REG_DEVADDR_REG);
309 + }
310 +
311 + /* buffer length */
312 + if (pmsg->len == 0)
313 + cmd |= NODATA_CMD;
314 + else
315 + rt_i2c_w32(i2c, SET_BYTECNT(pmsg->len),
316 + REG_BYTECNT_REG);
317 +
318 + j = 0;
319 + if (pmsg->flags & I2C_M_RD) {
320 + cmd |= READ_CMD;
321 + /* start transfer */
322 + barrier();
323 + rt_i2c_w32(i2c, cmd, REG_STARTXFR_REG);
324 + do {
325 + /* wait */
326 + if ((ret = rt_i2c_wait_rx_done(i2c)))
327 + goto err_timeout;
328 + /* read data */
329 + if (pmsg->len)
330 + pmsg->buf[j] = rt_i2c_r32(i2c,
331 + REG_DATAIN_REG);
332 + j++;
333 + } while (j < pmsg->len);
334 + } else {
335 + do {
336 + /* write data */
337 + if (pmsg->len)
338 + rt_i2c_w32(i2c, pmsg->buf[j],
339 + REG_DATAOUT_REG);
340 + /* start transfer */
341 + if (j == 0) {
342 + barrier();
343 + rt_i2c_w32(i2c, cmd, REG_STARTXFR_REG);
344 + }
345 + /* wait */
346 + if ((ret = rt_i2c_wait_tx_done(i2c)))
347 + goto err_timeout;
348 + j++;
349 + } while (j < pmsg->len);
350 + }
351 + }
352 + /* the return value is number of executed messages */
353 + ret = i;
354 +
355 + return ret;
356 +
357 +err_timeout:
358 + rt_i2c_dump_reg(i2c);
359 + rt_i2c_reset(i2c);
360 + return ret;
361 +}
362 +
363 +static u32 rt_i2c_func(struct i2c_adapter *a)
364 +{
365 + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
366 +}
367 +
368 +static const struct i2c_algorithm rt_i2c_algo = {
369 + .master_xfer = rt_i2c_master_xfer,
370 + .functionality = rt_i2c_func,
371 +};
372 +
373 +static const struct of_device_id i2c_rt_dt_ids[] = {
374 + { .compatible = "ralink,rt2880-i2c" },
375 + { /* sentinel */ }
376 +};
377 +
378 +MODULE_DEVICE_TABLE(of, i2c_rt_dt_ids);
379 +
380 +static struct i2c_adapter_quirks rt_i2c_quirks = {
381 + .max_write_len = BYTECNT_MAX,
382 + .max_read_len = BYTECNT_MAX,
383 +};
384 +
385 +static int rt_i2c_init(struct rt_i2c *i2c)
386 +{
387 + u32 reg;
388 +
389 + /* i2c_sclk = periph_clk / ((2 * clk_div) + 5) */
390 + i2c->clk_div = (clk_get_rate(i2c->clk) - (5 * i2c->cur_clk)) /
391 + (2 * i2c->cur_clk);
392 + if (i2c->clk_div < 8)
393 + i2c->clk_div = 8;
394 + if (i2c->clk_div > I2C_CLKDIV_MASK)
395 + i2c->clk_div = I2C_CLKDIV_MASK;
396 +
397 + /* check support combinde/repeated start message */
398 + rt_i2c_w32(i2c, NOSTOP_CMD, REG_STARTXFR_REG);
399 + reg = rt_i2c_r32(i2c, REG_STARTXFR_REG) & NOSTOP_CMD;
400 +
401 + rt_i2c_reset(i2c);
402 +
403 + return reg;
404 +}
405 +
406 +static int rt_i2c_probe(struct platform_device *pdev)
407 +{
408 + struct resource *res;
409 + struct rt_i2c *i2c;
410 + struct i2c_adapter *adap;
411 + const struct of_device_id *match;
412 + int ret, restart;
413 +
414 + match = of_match_device(i2c_rt_dt_ids, &pdev->dev);
415 +
416 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
417 + if (!res) {
418 + dev_err(&pdev->dev, "no memory resource found\n");
419 + return -ENODEV;
420 + }
421 +
422 + i2c = devm_kzalloc(&pdev->dev, sizeof(struct rt_i2c), GFP_KERNEL);
423 + if (!i2c) {
424 + dev_err(&pdev->dev, "failed to allocate i2c_adapter\n");
425 + return -ENOMEM;
426 + }
427 +
428 + i2c->base = devm_ioremap_resource(&pdev->dev, res);
429 + if (IS_ERR(i2c->base))
430 + return PTR_ERR(i2c->base);
431 +
432 + i2c->clk = devm_clk_get(&pdev->dev, NULL);
433 + if (IS_ERR(i2c->clk)) {
434 + dev_err(&pdev->dev, "no clock defined\n");
435 + return -ENODEV;
436 + }
437 + clk_prepare_enable(i2c->clk);
438 + i2c->dev = &pdev->dev;
439 +
440 + if (of_property_read_u32(pdev->dev.of_node,
441 + "clock-frequency", &i2c->cur_clk))
442 + i2c->cur_clk = 100000;
443 +
444 + adap = &i2c->adap;
445 + adap->owner = THIS_MODULE;
446 + adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
447 + adap->algo = &rt_i2c_algo;
448 + adap->retries = 3;
449 + adap->dev.parent = &pdev->dev;
450 + i2c_set_adapdata(adap, i2c);
451 + adap->dev.of_node = pdev->dev.of_node;
452 + strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));
453 + adap->quirks = &rt_i2c_quirks;
454 +
455 + platform_set_drvdata(pdev, i2c);
456 +
457 + restart = rt_i2c_init(i2c);
458 +
459 + ret = i2c_add_adapter(adap);
460 + if (ret < 0) {
461 + dev_err(&pdev->dev, "failed to add adapter\n");
462 + clk_disable_unprepare(i2c->clk);
463 + return ret;
464 + }
465 +
466 + dev_info(&pdev->dev, "clock %uKHz, re-start %ssupport\n",
467 + i2c->cur_clk/1000, restart ? "" : "not ");
468 +
469 + return ret;
470 +}
471 +
472 +static int rt_i2c_remove(struct platform_device *pdev)
473 +{
474 + struct rt_i2c *i2c = platform_get_drvdata(pdev);
475 +
476 + i2c_del_adapter(&i2c->adap);
477 + clk_disable_unprepare(i2c->clk);
478 +
479 + return 0;
480 +}
481 +
482 +static struct platform_driver rt_i2c_driver = {
483 + .probe = rt_i2c_probe,
484 + .remove = rt_i2c_remove,
485 + .driver = {
486 + .owner = THIS_MODULE,
487 + .name = "i2c-ralink",
488 + .of_match_table = i2c_rt_dt_ids,
489 + },
490 +};
491 +
492 +static int __init i2c_rt_init (void)
493 +{
494 + return platform_driver_register(&rt_i2c_driver);
495 +}
496 +subsys_initcall(i2c_rt_init);
497 +
498 +static void __exit i2c_rt_exit (void)
499 +{
500 + platform_driver_unregister(&rt_i2c_driver);
501 +}
502 +module_exit(i2c_rt_exit);
503 +
504 +MODULE_AUTHOR("Steven Liu <steven_liu@mediatek.com>");
505 +MODULE_DESCRIPTION("Ralink I2c host driver");
506 +MODULE_LICENSE("GPL");
507 +MODULE_ALIAS("platform:Ralink-I2C");