OpenWrt – Blame information for rev 1

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1 office 1 From 61ac7d9b4228de8c332900902c2b93189b042eab Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jul 2014 11:00:32 +0100
4 Subject: [PATCH 28/53] GPIO: ralink: add mt7621 gpio controller
5  
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 arch/mips/Kconfig | 3 +
9 drivers/gpio/Kconfig | 6 +
10 drivers/gpio/Makefile | 1 +
11 drivers/gpio/gpio-mt7621.c | 354 ++++++++++++++++++++++++++++++++++++++++++++
12 4 files changed, 364 insertions(+)
13 create mode 100644 drivers/gpio/gpio-mt7621.c
14  
15 --- a/arch/mips/Kconfig
16 +++ b/arch/mips/Kconfig
17 @@ -631,6 +631,9 @@ config RALINK
18 select RESET_CONTROLLER
19 select PINCTRL
20 select PINCTRL_RT2880
21 + select ARCH_HAS_RESET_CONTROLLER
22 + select RESET_CONTROLLER
23 + select ARCH_REQUIRE_GPIOLIB
24  
25 config SGI_IP22
26 bool "SGI IP22 (Indy/Indigo2)"
27 --- a/drivers/gpio/Kconfig
28 +++ b/drivers/gpio/Kconfig
29 @@ -298,6 +298,12 @@ config GPIO_MENZ127
30 help
31 Say yes here to support the MEN 16Z127 GPIO Controller
32  
33 +config GPIO_MT7621
34 + bool "Mediatek GPIO Support"
35 + depends on SOC_MT7620 || SOC_MT7621
36 + help
37 + Say yes here to support the Mediatek SoC GPIO device
38 +
39 config GPIO_MM_LANTIQ
40 bool "Lantiq Memory mapped GPIOs"
41 depends on LANTIQ && SOC_XWAY
42 --- a/drivers/gpio/Makefile
43 +++ b/drivers/gpio/Makefile
44 @@ -152,3 +152,4 @@ obj-$(CONFIG_GPIO_ZEVIO) += gpio-zevio.o
45 obj-$(CONFIG_GPIO_ZYNQ) += gpio-zynq.o
46 obj-$(CONFIG_GPIO_ZX) += gpio-zx.o
47 obj-$(CONFIG_GPIO_LOONGSON1) += gpio-loongson1.o
48 +obj-$(CONFIG_GPIO_MT7621) += gpio-mt7621.o
49 --- /dev/null
50 +++ b/drivers/gpio/gpio-mt7621.c
51 @@ -0,0 +1,354 @@
52 +/*
53 + * This program is free software; you can redistribute it and/or modify it
54 + * under the terms of the GNU General Public License version 2 as published
55 + * by the Free Software Foundation.
56 + *
57 + * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
58 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
59 + */
60 +
61 +#include <linux/io.h>
62 +#include <linux/err.h>
63 +#include <linux/gpio.h>
64 +#include <linux/module.h>
65 +#include <linux/of_irq.h>
66 +#include <linux/spinlock.h>
67 +#include <linux/irqdomain.h>
68 +#include <linux/interrupt.h>
69 +#include <linux/platform_device.h>
70 +
71 +#define MTK_MAX_BANK 3
72 +#define MTK_BANK_WIDTH 32
73 +
74 +enum mediatek_gpio_reg {
75 + GPIO_REG_CTRL = 0,
76 + GPIO_REG_POL,
77 + GPIO_REG_DATA,
78 + GPIO_REG_DSET,
79 + GPIO_REG_DCLR,
80 + GPIO_REG_REDGE,
81 + GPIO_REG_FEDGE,
82 + GPIO_REG_HLVL,
83 + GPIO_REG_LLVL,
84 + GPIO_REG_STAT,
85 + GPIO_REG_EDGE,
86 +};
87 +
88 +static void __iomem *mediatek_gpio_membase;
89 +static int mediatek_gpio_irq;
90 +static struct irq_domain *mediatek_gpio_irq_domain;
91 +static atomic_t irq_refcount = ATOMIC_INIT(0);
92 +
93 +struct mtk_gc {
94 + struct gpio_chip chip;
95 + spinlock_t lock;
96 + int bank;
97 + u32 rising;
98 + u32 falling;
99 +} *gc_map[MTK_MAX_BANK];
100 +
101 +static inline struct mtk_gc
102 +*to_mediatek_gpio(struct gpio_chip *chip)
103 +{
104 + struct mtk_gc *mgc;
105 +
106 + mgc = container_of(chip, struct mtk_gc, chip);
107 +
108 + return mgc;
109 +}
110 +
111 +static inline void
112 +mtk_gpio_w32(struct mtk_gc *rg, u8 reg, u32 val)
113 +{
114 + iowrite32(val, mediatek_gpio_membase + (reg * 0x10) + (rg->bank * 0x4));
115 +}
116 +
117 +static inline u32
118 +mtk_gpio_r32(struct mtk_gc *rg, u8 reg)
119 +{
120 + return ioread32(mediatek_gpio_membase + (reg * 0x10) + (rg->bank * 0x4));
121 +}
122 +
123 +static void
124 +mediatek_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
125 +{
126 + struct mtk_gc *rg = to_mediatek_gpio(chip);
127 +
128 + mtk_gpio_w32(rg, (value) ? GPIO_REG_DSET : GPIO_REG_DCLR, BIT(offset));
129 +}
130 +
131 +static int
132 +mediatek_gpio_get(struct gpio_chip *chip, unsigned offset)
133 +{
134 + struct mtk_gc *rg = to_mediatek_gpio(chip);
135 +
136 + return !!(mtk_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
137 +}
138 +
139 +static int
140 +mediatek_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
141 +{
142 + struct mtk_gc *rg = to_mediatek_gpio(chip);
143 + unsigned long flags;
144 + u32 t;
145 +
146 + spin_lock_irqsave(&rg->lock, flags);
147 + t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
148 + t &= ~BIT(offset);
149 + mtk_gpio_w32(rg, GPIO_REG_CTRL, t);
150 + spin_unlock_irqrestore(&rg->lock, flags);
151 +
152 + return 0;
153 +}
154 +
155 +static int
156 +mediatek_gpio_direction_output(struct gpio_chip *chip,
157 + unsigned offset, int value)
158 +{
159 + struct mtk_gc *rg = to_mediatek_gpio(chip);
160 + unsigned long flags;
161 + u32 t;
162 +
163 + spin_lock_irqsave(&rg->lock, flags);
164 + t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
165 + t |= BIT(offset);
166 + mtk_gpio_w32(rg, GPIO_REG_CTRL, t);
167 + mediatek_gpio_set(chip, offset, value);
168 + spin_unlock_irqrestore(&rg->lock, flags);
169 +
170 + return 0;
171 +}
172 +
173 +static int
174 +mediatek_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
175 +{
176 + struct mtk_gc *rg = to_mediatek_gpio(chip);
177 + unsigned long flags;
178 + u32 t;
179 +
180 + spin_lock_irqsave(&rg->lock, flags);
181 + t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
182 + spin_unlock_irqrestore(&rg->lock, flags);
183 +
184 + if (t & BIT(offset))
185 + return 0;
186 +
187 + return 1;
188 +}
189 +
190 +static int
191 +mediatek_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
192 +{
193 + struct mtk_gc *rg = to_mediatek_gpio(chip);
194 +
195 + return irq_create_mapping(mediatek_gpio_irq_domain, pin + (rg->bank * MTK_BANK_WIDTH));
196 +}
197 +
198 +static int
199 +mediatek_gpio_bank_probe(struct platform_device *pdev, struct device_node *bank)
200 +{
201 + const __be32 *id = of_get_property(bank, "reg", NULL);
202 + struct mtk_gc *rg = devm_kzalloc(&pdev->dev,
203 + sizeof(struct mtk_gc), GFP_KERNEL);
204 +
205 + if (!rg || !id || be32_to_cpu(*id) > MTK_MAX_BANK)
206 + return -ENOMEM;
207 +
208 + gc_map[be32_to_cpu(*id)] = rg;
209 +
210 + memset(rg, 0, sizeof(struct mtk_gc));
211 +
212 + spin_lock_init(&rg->lock);
213 +
214 + rg->chip.parent = &pdev->dev;
215 + rg->chip.label = dev_name(&pdev->dev);
216 + rg->chip.of_node = bank;
217 + rg->chip.base = MTK_BANK_WIDTH * be32_to_cpu(*id);
218 + rg->chip.ngpio = MTK_BANK_WIDTH;
219 + rg->chip.direction_input = mediatek_gpio_direction_input;
220 + rg->chip.direction_output = mediatek_gpio_direction_output;
221 + rg->chip.get_direction = mediatek_gpio_get_direction;
222 + rg->chip.get = mediatek_gpio_get;
223 + rg->chip.set = mediatek_gpio_set;
224 + if (mediatek_gpio_irq_domain)
225 + rg->chip.to_irq = mediatek_gpio_to_irq;
226 + rg->bank = be32_to_cpu(*id);
227 +
228 + /* set polarity to low for all gpios */
229 + mtk_gpio_w32(rg, GPIO_REG_POL, 0);
230 +
231 + dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
232 +
233 + return gpiochip_add(&rg->chip);
234 +}
235 +
236 +static void
237 +mediatek_gpio_irq_handler(struct irq_desc *desc)
238 +{
239 + int i;
240 +
241 + for (i = 0; i < MTK_MAX_BANK; i++) {
242 + struct mtk_gc *rg = gc_map[i];
243 + unsigned long pending;
244 + int bit;
245 +
246 + if (!rg)
247 + continue;
248 +
249 + pending = mtk_gpio_r32(rg, GPIO_REG_STAT);
250 +
251 + for_each_set_bit(bit, &pending, MTK_BANK_WIDTH) {
252 + u32 map = irq_find_mapping(mediatek_gpio_irq_domain, (MTK_BANK_WIDTH * i) + bit);
253 +
254 + generic_handle_irq(map);
255 + mtk_gpio_w32(rg, GPIO_REG_STAT, BIT(bit));
256 + }
257 + }
258 +}
259 +
260 +static void
261 +mediatek_gpio_irq_unmask(struct irq_data *d)
262 +{
263 + int pin = d->hwirq;
264 + int bank = pin / 32;
265 + struct mtk_gc *rg = gc_map[bank];
266 + unsigned long flags;
267 + u32 rise, fall;
268 +
269 + if (!rg)
270 + return;
271 +
272 + rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
273 + fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
274 +
275 + spin_lock_irqsave(&rg->lock, flags);
276 + mtk_gpio_w32(rg, GPIO_REG_REDGE, rise | (BIT(d->hwirq) & rg->rising));
277 + mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall | (BIT(d->hwirq) & rg->falling));
278 + spin_unlock_irqrestore(&rg->lock, flags);
279 +}
280 +
281 +static void
282 +mediatek_gpio_irq_mask(struct irq_data *d)
283 +{
284 + int pin = d->hwirq;
285 + int bank = pin / 32;
286 + struct mtk_gc *rg = gc_map[bank];
287 + unsigned long flags;
288 + u32 rise, fall;
289 +
290 + if (!rg)
291 + return;
292 +
293 + rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
294 + fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
295 +
296 + spin_lock_irqsave(&rg->lock, flags);
297 + mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall & ~BIT(d->hwirq));
298 + mtk_gpio_w32(rg, GPIO_REG_REDGE, rise & ~BIT(d->hwirq));
299 + spin_unlock_irqrestore(&rg->lock, flags);
300 +}
301 +
302 +static int
303 +mediatek_gpio_irq_type(struct irq_data *d, unsigned int type)
304 +{
305 + int pin = d->hwirq;
306 + int bank = pin / 32;
307 + struct mtk_gc *rg = gc_map[bank];
308 + u32 mask = BIT(d->hwirq);
309 +
310 + if (!rg)
311 + return -1;
312 +
313 + if (type == IRQ_TYPE_PROBE) {
314 + if ((rg->rising | rg->falling) & mask)
315 + return 0;
316 +
317 + type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
318 + }
319 +
320 + if (type & IRQ_TYPE_EDGE_RISING)
321 + rg->rising |= mask;
322 + else
323 + rg->rising &= ~mask;
324 +
325 + if (type & IRQ_TYPE_EDGE_FALLING)
326 + rg->falling |= mask;
327 + else
328 + rg->falling &= ~mask;
329 +
330 + return 0;
331 +}
332 +
333 +static struct irq_chip mediatek_gpio_irq_chip = {
334 + .name = "GPIO",
335 + .irq_unmask = mediatek_gpio_irq_unmask,
336 + .irq_mask = mediatek_gpio_irq_mask,
337 + .irq_mask_ack = mediatek_gpio_irq_mask,
338 + .irq_set_type = mediatek_gpio_irq_type,
339 +};
340 +
341 +static int
342 +mediatek_gpio_gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
343 +{
344 + irq_set_chip_and_handler(irq, &mediatek_gpio_irq_chip, handle_level_irq);
345 + irq_set_handler_data(irq, d);
346 +
347 + return 0;
348 +}
349 +
350 +static const struct irq_domain_ops irq_domain_ops = {
351 + .xlate = irq_domain_xlate_onecell,
352 + .map = mediatek_gpio_gpio_map,
353 +};
354 +
355 +static int
356 +mediatek_gpio_probe(struct platform_device *pdev)
357 +{
358 + struct device_node *bank, *np = pdev->dev.of_node;
359 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
360 +
361 + mediatek_gpio_membase = devm_ioremap_resource(&pdev->dev, res);
362 + if (IS_ERR(mediatek_gpio_membase))
363 + return PTR_ERR(mediatek_gpio_membase);
364 +
365 + mediatek_gpio_irq = irq_of_parse_and_map(np, 0);
366 + if (mediatek_gpio_irq) {
367 + mediatek_gpio_irq_domain = irq_domain_add_linear(np,
368 + MTK_MAX_BANK * MTK_BANK_WIDTH,
369 + &irq_domain_ops, NULL);
370 + if (!mediatek_gpio_irq_domain)
371 + dev_err(&pdev->dev, "irq_domain_add_linear failed\n");
372 + }
373 +
374 + for_each_child_of_node(np, bank)
375 + if (of_device_is_compatible(bank, "mtk,mt7621-gpio-bank"))
376 + mediatek_gpio_bank_probe(pdev, bank);
377 +
378 + if (mediatek_gpio_irq_domain)
379 + irq_set_chained_handler(mediatek_gpio_irq, mediatek_gpio_irq_handler);
380 +
381 + return 0;
382 +}
383 +
384 +static const struct of_device_id mediatek_gpio_match[] = {
385 + { .compatible = "mtk,mt7621-gpio" },
386 + {},
387 +};
388 +MODULE_DEVICE_TABLE(of, mediatek_gpio_match);
389 +
390 +static struct platform_driver mediatek_gpio_driver = {
391 + .probe = mediatek_gpio_probe,
392 + .driver = {
393 + .name = "mt7621_gpio",
394 + .owner = THIS_MODULE,
395 + .of_match_table = mediatek_gpio_match,
396 + },
397 +};
398 +
399 +static int __init
400 +mediatek_gpio_init(void)
401 +{
402 + return platform_driver_register(&mediatek_gpio_driver);
403 +}
404 +
405 +subsys_initcall(mediatek_gpio_init);