OpenWrt – Blame information for rev 1

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1 office 1 From fec11d4e8dc5cc79bcd7c8fd55038ac21ac39965 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 16 Mar 2014 05:22:39 +0000
4 Subject: [PATCH 04/53] MIPS: ralink: add MT7621 pcie driver
5  
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 arch/mips/pci/Makefile | 1 +
9 arch/mips/pci/pci-mt7621.c | 813 ++++++++++++++++++++++++++++++++++++++++++++
10 2 files changed, 814 insertions(+)
11 create mode 100644 arch/mips/pci/pci-mt7621.c
12  
13 --- a/arch/mips/pci/Makefile
14 +++ b/arch/mips/pci/Makefile
15 @@ -47,6 +47,7 @@ obj-$(CONFIG_SNI_RM) += fixup-sni.o ops
16 obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
17 obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
18 obj-$(CONFIG_SOC_MT7620) += pci-mt7620.o
19 +obj-$(CONFIG_SOC_MT7621) += pci-mt7621.o
20 obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o
21 obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
22 obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
23 --- /dev/null
24 +++ b/arch/mips/pci/pci-mt7621.c
25 @@ -0,0 +1,836 @@
26 +/**************************************************************************
27 + *
28 + * BRIEF MODULE DESCRIPTION
29 + * PCI init for Ralink RT2880 solution
30 + *
31 + * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
32 + *
33 + * This program is free software; you can redistribute it and/or modify it
34 + * under the terms of the GNU General Public License as published by the
35 + * Free Software Foundation; either version 2 of the License, or (at your
36 + * option) any later version.
37 + *
38 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
39 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
40 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
41 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
42 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
43 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
44 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
45 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
46 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
47 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48 + *
49 + * You should have received a copy of the GNU General Public License along
50 + * with this program; if not, write to the Free Software Foundation, Inc.,
51 + * 675 Mass Ave, Cambridge, MA 02139, USA.
52 + *
53 + *
54 + **************************************************************************
55 + * May 2007 Bruce Chang
56 + * Initial Release
57 + *
58 + * May 2009 Bruce Chang
59 + * support RT2880/RT3883 PCIe
60 + *
61 + * May 2011 Bruce Chang
62 + * support RT6855/MT7620 PCIe
63 + *
64 + **************************************************************************
65 + */
66 +
67 +#include <linux/types.h>
68 +#include <linux/pci.h>
69 +#include <linux/kernel.h>
70 +#include <linux/slab.h>
71 +#include <linux/version.h>
72 +#include <asm/pci.h>
73 +#include <asm/io.h>
74 +#include <asm/mips-cm.h>
75 +#include <linux/init.h>
76 +#include <linux/module.h>
77 +#include <linux/delay.h>
78 +#include <linux/of.h>
79 +#include <linux/of_pci.h>
80 +#include <linux/of_irq.h>
81 +#include <linux/platform_device.h>
82 +
83 +#include <ralink_regs.h>
84 +
85 +extern void pcie_phy_init(void);
86 +extern void chk_phy_pll(void);
87 +
88 +/*
89 + * These functions and structures provide the BIOS scan and mapping of the PCI
90 + * devices.
91 + */
92 +
93 +#define CONFIG_PCIE_PORT0
94 +#define CONFIG_PCIE_PORT1
95 +#define CONFIG_PCIE_PORT2
96 +#define RALINK_PCIE0_CLK_EN (1<<24)
97 +#define RALINK_PCIE1_CLK_EN (1<<25)
98 +#define RALINK_PCIE2_CLK_EN (1<<26)
99 +
100 +#define RALINK_PCI_CONFIG_ADDR 0x20
101 +#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
102 +#define RALINK_INT_PCIE0 pcie_irq[0]
103 +#define RALINK_INT_PCIE1 pcie_irq[1]
104 +#define RALINK_INT_PCIE2 pcie_irq[2]
105 +#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
106 +#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
107 +#define RALINK_PCIE0_RST (1<<24)
108 +#define RALINK_PCIE1_RST (1<<25)
109 +#define RALINK_PCIE2_RST (1<<26)
110 +#define RALINK_SYSCTL_BASE 0xBE000000
111 +
112 +#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
113 +#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
114 +#define RALINK_PCI_BASE 0xBE140000
115 +
116 +#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
117 +#define RT6855_PCIE0_OFFSET 0x2000
118 +#define RT6855_PCIE1_OFFSET 0x3000
119 +#define RT6855_PCIE2_OFFSET 0x4000
120 +
121 +#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
122 +#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
123 +#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
124 +#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
125 +#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
126 +#define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
127 +#define RALINK_PCI0_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
128 +#define RALINK_PCI0_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
129 +
130 +#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
131 +#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
132 +#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
133 +#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
134 +#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
135 +#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
136 +#define RALINK_PCI1_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
137 +#define RALINK_PCI1_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
138 +
139 +#define RALINK_PCI2_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010)
140 +#define RALINK_PCI2_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018)
141 +#define RALINK_PCI2_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0030)
142 +#define RALINK_PCI2_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034)
143 +#define RALINK_PCI2_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038)
144 +#define RALINK_PCI2_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050)
145 +#define RALINK_PCI2_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0060)
146 +#define RALINK_PCI2_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0064)
147 +
148 +#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
149 +#define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000)
150 +
151 +
152 +#define MV_WRITE(ofs, data) \
153 + *(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
154 +#define MV_READ(ofs, data) \
155 + *(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
156 +#define MV_READ_DATA(ofs) \
157 + le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
158 +
159 +#define MV_WRITE_16(ofs, data) \
160 + *(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data)
161 +#define MV_READ_16(ofs, data) \
162 + *(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs)))
163 +
164 +#define MV_WRITE_8(ofs, data) \
165 + *(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data
166 +#define MV_READ_8(ofs, data) \
167 + *(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
168 +
169 +
170 +
171 +#define RALINK_PCI_MM_MAP_BASE 0x60000000
172 +#define RALINK_PCI_IO_MAP_BASE 0x1e160000
173 +
174 +#define RALINK_SYSTEM_CONTROL_BASE 0xbe000000
175 +#define GPIO_PERST
176 +#define ASSERT_SYSRST_PCIE(val) do { \
177 + if (*(unsigned int *)(0xbe00000c) == 0x00030101) \
178 + RALINK_RSTCTRL |= val; \
179 + else \
180 + RALINK_RSTCTRL &= ~val; \
181 + } while(0)
182 +#define DEASSERT_SYSRST_PCIE(val) do { \
183 + if (*(unsigned int *)(0xbe00000c) == 0x00030101) \
184 + RALINK_RSTCTRL &= ~val; \
185 + else \
186 + RALINK_RSTCTRL |= val; \
187 + } while(0)
188 +#define RALINK_SYSCFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x14)
189 +#define RALINK_CLKCFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x30)
190 +#define RALINK_RSTCTRL *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x34)
191 +#define RALINK_GPIOMODE *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x60)
192 +#define RALINK_PCIE_CLK_GEN *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x7c)
193 +#define RALINK_PCIE_CLK_GEN1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x80)
194 +#define PPLL_CFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x9c)
195 +#define PPLL_DRV *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0xa0)
196 +//RALINK_SYSCFG1 bit
197 +#define RALINK_PCI_HOST_MODE_EN (1<<7)
198 +#define RALINK_PCIE_RC_MODE_EN (1<<8)
199 +//RALINK_RSTCTRL bit
200 +#define RALINK_PCIE_RST (1<<23)
201 +#define RALINK_PCI_RST (1<<24)
202 +//RALINK_CLKCFG1 bit
203 +#define RALINK_PCI_CLK_EN (1<<19)
204 +#define RALINK_PCIE_CLK_EN (1<<21)
205 +//RALINK_GPIOMODE bit
206 +#define PCI_SLOTx2 (1<<11)
207 +#define PCI_SLOTx1 (2<<11)
208 +//MTK PCIE PLL bit
209 +#define PDRV_SW_SET (1<<31)
210 +#define LC_CKDRVPD_ (1<<19)
211 +
212 +#define MEMORY_BASE 0x0
213 +static int pcie_link_status = 0;
214 +
215 +#define PCI_ACCESS_READ_1 0
216 +#define PCI_ACCESS_READ_2 1
217 +#define PCI_ACCESS_READ_4 2
218 +#define PCI_ACCESS_WRITE_1 3
219 +#define PCI_ACCESS_WRITE_2 4
220 +#define PCI_ACCESS_WRITE_4 5
221 +
222 +static int pcie_irq[3];
223 +
224 +static int config_access(unsigned char access_type, struct pci_bus *bus,
225 + unsigned int devfn, unsigned int where, u32 * data)
226 +{
227 + unsigned int slot = PCI_SLOT(devfn);
228 + u8 func = PCI_FUNC(devfn);
229 + uint32_t address_reg, data_reg;
230 + unsigned int address;
231 +
232 + address_reg = RALINK_PCI_CONFIG_ADDR;
233 + data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
234 +
235 + address = (((where&0xF00)>>8)<<24) |(bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
236 + MV_WRITE(address_reg, address);
237 +
238 + switch(access_type) {
239 + case PCI_ACCESS_WRITE_1:
240 + MV_WRITE_8(data_reg+(where&0x3), *data);
241 + break;
242 + case PCI_ACCESS_WRITE_2:
243 + MV_WRITE_16(data_reg+(where&0x3), *data);
244 + break;
245 + case PCI_ACCESS_WRITE_4:
246 + MV_WRITE(data_reg, *data);
247 + break;
248 + case PCI_ACCESS_READ_1:
249 + MV_READ_8( data_reg+(where&0x3), data);
250 + break;
251 + case PCI_ACCESS_READ_2:
252 + MV_READ_16(data_reg+(where&0x3), data);
253 + break;
254 + case PCI_ACCESS_READ_4:
255 + MV_READ(data_reg, data);
256 + break;
257 + default:
258 + printk("no specify access type\n");
259 + break;
260 + }
261 + return 0;
262 +}
263 +
264 +static int
265 +read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 * val)
266 +{
267 + return config_access(PCI_ACCESS_READ_1, bus, devfn, (unsigned int)where, (u32 *)val);
268 +}
269 +
270 +static int
271 +read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 * val)
272 +{
273 + return config_access(PCI_ACCESS_READ_2, bus, devfn, (unsigned int)where, (u32 *)val);
274 +}
275 +
276 +static int
277 +read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 * val)
278 +{
279 + return config_access(PCI_ACCESS_READ_4, bus, devfn, (unsigned int)where, (u32 *)val);
280 +}
281 +
282 +static int
283 +write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val)
284 +{
285 + if (config_access(PCI_ACCESS_WRITE_1, bus, devfn, (unsigned int)where, (u32 *)&val))
286 + return -1;
287 +
288 + return PCIBIOS_SUCCESSFUL;
289 +}
290 +
291 +static int
292 +write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val)
293 +{
294 + if (config_access(PCI_ACCESS_WRITE_2, bus, devfn, where, (u32 *)&val))
295 + return -1;
296 +
297 + return PCIBIOS_SUCCESSFUL;
298 +}
299 +
300 +static int
301 +write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
302 +{
303 + if (config_access(PCI_ACCESS_WRITE_4, bus, devfn, where, &val))
304 + return -1;
305 +
306 + return PCIBIOS_SUCCESSFUL;
307 +}
308 +
309 +
310 +static int
311 +pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
312 +{
313 + switch (size) {
314 + case 1:
315 + return read_config_byte(bus, devfn, where, (u8 *) val);
316 + case 2:
317 + return read_config_word(bus, devfn, where, (u16 *) val);
318 + default:
319 + return read_config_dword(bus, devfn, where, val);
320 + }
321 +}
322 +
323 +static int
324 +pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
325 +{
326 + switch (size) {
327 + case 1:
328 + return write_config_byte(bus, devfn, where, (u8) val);
329 + case 2:
330 + return write_config_word(bus, devfn, where, (u16) val);
331 + default:
332 + return write_config_dword(bus, devfn, where, val);
333 + }
334 +}
335 +
336 +struct pci_ops mt7621_pci_ops= {
337 + .read = pci_config_read,
338 + .write = pci_config_write,
339 +};
340 +
341 +static struct resource mt7621_res_pci_mem1 = {
342 + .name = "PCI MEM1",
343 + .start = RALINK_PCI_MM_MAP_BASE,
344 + .end = (u32)((RALINK_PCI_MM_MAP_BASE + (unsigned char *)0x0fffffff)),
345 + .flags = IORESOURCE_MEM,
346 +};
347 +static struct resource mt7621_res_pci_io1 = {
348 + .name = "PCI I/O1",
349 + .start = RALINK_PCI_IO_MAP_BASE,
350 + .end = (u32)((RALINK_PCI_IO_MAP_BASE + (unsigned char *)0x0ffff)),
351 + .flags = IORESOURCE_IO,
352 +};
353 +
354 +static struct pci_controller mt7621_controller = {
355 + .pci_ops = &mt7621_pci_ops,
356 + .mem_resource = &mt7621_res_pci_mem1,
357 + .io_resource = &mt7621_res_pci_io1,
358 + .mem_offset = 0x00000000UL,
359 + .io_offset = 0x00000000UL,
360 + .io_map_base = 0xa0000000,
361 +};
362 +
363 +static void
364 +read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long *val)
365 +{
366 + unsigned int address_reg, data_reg, address;
367 +
368 + address_reg = RALINK_PCI_CONFIG_ADDR;
369 + data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
370 + address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
371 + MV_WRITE(address_reg, address);
372 + MV_READ(data_reg, val);
373 + return;
374 +}
375 +
376 +static void
377 +write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long val)
378 +{
379 + unsigned int address_reg, data_reg, address;
380 +
381 + address_reg = RALINK_PCI_CONFIG_ADDR;
382 + data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
383 + address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
384 + MV_WRITE(address_reg, address);
385 + MV_WRITE(data_reg, val);
386 + return;
387 +}
388 +
389 +
390 +int
391 +pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
392 +{
393 + u16 cmd;
394 + u32 val;
395 + int irq = 0;
396 +
397 + if ((dev->bus->number == 0) && (slot == 0)) {
398 + write_config(0, 0, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
399 + read_config(0, 0, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
400 + printk("BAR0 at slot 0 = %x\n", val);
401 + printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
402 + } else if((dev->bus->number == 0) && (slot == 0x1)) {
403 + write_config(0, 1, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
404 + read_config(0, 1, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
405 + printk("BAR0 at slot 1 = %x\n", val);
406 + printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
407 + } else if((dev->bus->number == 0) && (slot == 0x2)) {
408 + write_config(0, 2, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
409 + read_config(0, 2, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
410 + printk("BAR0 at slot 2 = %x\n", val);
411 + printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
412 + } else if ((dev->bus->number == 1) && (slot == 0x0)) {
413 + switch (pcie_link_status) {
414 + case 2:
415 + case 6:
416 + irq = RALINK_INT_PCIE1;
417 + break;
418 + case 4:
419 + irq = RALINK_INT_PCIE2;
420 + break;
421 + default:
422 + irq = RALINK_INT_PCIE0;
423 + }
424 + printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
425 + } else if ((dev->bus->number == 2) && (slot == 0x0)) {
426 + switch (pcie_link_status) {
427 + case 5:
428 + case 6:
429 + irq = RALINK_INT_PCIE2;
430 + break;
431 + default:
432 + irq = RALINK_INT_PCIE1;
433 + }
434 + printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
435 + } else if ((dev->bus->number == 2) && (slot == 0x1)) {
436 + switch (pcie_link_status) {
437 + case 5:
438 + case 6:
439 + irq = RALINK_INT_PCIE2;
440 + break;
441 + default:
442 + irq = RALINK_INT_PCIE1;
443 + }
444 + printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
445 + } else if ((dev->bus->number ==3) && (slot == 0x0)) {
446 + irq = RALINK_INT_PCIE2;
447 + printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
448 + } else if ((dev->bus->number ==3) && (slot == 0x1)) {
449 + irq = RALINK_INT_PCIE2;
450 + printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
451 + } else if ((dev->bus->number ==3) && (slot == 0x2)) {
452 + irq = RALINK_INT_PCIE2;
453 + printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
454 + } else {
455 + printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
456 + return 0;
457 + }
458 +
459 + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14); //configure cache line size 0x14
460 + pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF); //configure latency timer 0x10
461 + pci_read_config_word(dev, PCI_COMMAND, &cmd);
462 + cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
463 + pci_write_config_word(dev, PCI_COMMAND, cmd);
464 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
465 + return irq;
466 +}
467 +
468 +void
469 +set_pcie_phy(u32 *addr, int start_b, int bits, int val)
470 +{
471 +// printk("0x%p:", addr);
472 +// printk(" %x", *addr);
473 + *(unsigned int *)(addr) &= ~(((1<<bits) - 1)<<start_b);
474 + *(unsigned int *)(addr) |= val << start_b;
475 +// printk(" -> %x\n", *addr);
476 +}
477 +
478 +void
479 +bypass_pipe_rst(void)
480 +{
481 +#if defined (CONFIG_PCIE_PORT0)
482 + /* PCIe Port 0 */
483 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
484 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
485 +#endif
486 +#if defined (CONFIG_PCIE_PORT1)
487 + /* PCIe Port 1 */
488 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
489 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
490 +#endif
491 +#if defined (CONFIG_PCIE_PORT2)
492 + /* PCIe Port 2 */
493 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
494 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
495 +#endif
496 +}
497 +
498 +void
499 +set_phy_for_ssc(void)
500 +{
501 + unsigned long reg = (*(volatile u32 *)(RALINK_SYSCTL_BASE + 0x10));
502 +
503 + reg = (reg >> 6) & 0x7;
504 +#if defined (CONFIG_PCIE_PORT0) || defined (CONFIG_PCIE_PORT1)
505 + /* Set PCIe Port0 & Port1 PHY to disable SSC */
506 + /* Debug Xtal Type */
507 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type
508 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type
509 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
510 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 1 enable control
511 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
512 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x00); // rg_pe1_phy_en //Port 1 disable
513 + if(reg <= 5 && reg >= 3) { // 40MHz Xtal
514 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
515 + printk("***** Xtal 40MHz *****\n");
516 + } else { // 25MHz | 20MHz Xtal
517 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
518 + if (reg >= 6) {
519 + printk("***** Xtal 25MHz *****\n");
520 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
521 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
522 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4), 0,16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
523 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 0,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
524 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
525 + } else {
526 + printk("***** Xtal 20MHz *****\n");
527 + }
528 + }
529 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
530 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
531 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
532 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
533 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
534 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
535 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
536 + if(reg <= 5 && reg >= 3) { // 40MHz Xtal
537 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
538 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
539 + }
540 + /* Enable PHY and disable force mode */
541 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
542 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x01); // rg_pe1_phy_en //Port 1 enable
543 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
544 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 1 disable control
545 +#endif
546 +#if defined (CONFIG_PCIE_PORT2)
547 + /* Set PCIe Port2 PHY to disable SSC */
548 + /* Debug Xtal Type */
549 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type
550 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type
551 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
552 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
553 + if(reg <= 5 && reg >= 3) { // 40MHz Xtal
554 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
555 + } else { // 25MHz | 20MHz Xtal
556 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
557 + if (reg >= 6) { // 25MHz Xtal
558 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
559 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
560 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4), 0,16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
561 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 0,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
562 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
563 + }
564 + }
565 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
566 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
567 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
568 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
569 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
570 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
571 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
572 + if(reg <= 5 && reg >= 3) { // 40MHz Xtal
573 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
574 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
575 + }
576 + /* Enable PHY and disable force mode */
577 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
578 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
579 +#endif
580 +}
581 +
582 +void setup_cm_memory_region(struct resource *mem_resource)
583 +{
584 + resource_size_t mask;
585 + if (mips_cps_numiocu(0)) {
586 + /* FIXME: hardware doesn't accept mask values with 1s after
587 + 0s (e.g. 0xffef), so it would be great to warn if that's
588 + about to happen */
589 + mask = ~(mem_resource->end - mem_resource->start);
590 +
591 + write_gcr_reg1_base(mem_resource->start);
592 + write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
593 + printk("PCI coherence region base: 0x%08lx, mask/settings: 0x%08lx\n",
594 + read_gcr_reg1_base(),
595 + read_gcr_reg1_mask());
596 + }
597 +}
598 +
599 +static int mt7621_pci_probe(struct platform_device *pdev)
600 +{
601 + unsigned long val = 0;
602 + int i;
603 +
604 + for (i = 0; i < 3; i++)
605 + pcie_irq[i] = irq_of_parse_and_map(pdev->dev.of_node, i);
606 +
607 + iomem_resource.start = 0;
608 + iomem_resource.end= ~0;
609 + ioport_resource.start= 0;
610 + ioport_resource.end = ~0;
611 +
612 +#if defined (CONFIG_PCIE_PORT0)
613 + val = RALINK_PCIE0_RST;
614 +#endif
615 +#if defined (CONFIG_PCIE_PORT1)
616 + val |= RALINK_PCIE1_RST;
617 +#endif
618 +#if defined (CONFIG_PCIE_PORT2)
619 + val |= RALINK_PCIE2_RST;
620 +#endif
621 + ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
622 + printk("pull PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
623 +#if defined GPIO_PERST /* add GPIO control instead of PERST_N */ /*chhung*/
624 + *(unsigned int *)(0xbe000060) &= ~(0x3<<10 | 0x3<<3);
625 + *(unsigned int *)(0xbe000060) |= 0x1<<10 | 0x1<<3;
626 + mdelay(100);
627 + *(unsigned int *)(0xbe000600) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // use GPIO19/GPIO8/GPIO7 (PERST_N/UART_RXD3/UART_TXD3)
628 + mdelay(100);
629 + *(unsigned int *)(0xbe000620) &= ~(0x1<<19 | 0x1<<8 | 0x1<<7); // clear DATA
630 +
631 + mdelay(100);
632 +#else
633 + *(unsigned int *)(0xbe000060) &= ~0x00000c00;
634 +#endif
635 +#if defined (CONFIG_PCIE_PORT0)
636 + val = RALINK_PCIE0_RST;
637 +#endif
638 +#if defined (CONFIG_PCIE_PORT1)
639 + val |= RALINK_PCIE1_RST;
640 +#endif
641 +#if defined (CONFIG_PCIE_PORT2)
642 + val |= RALINK_PCIE2_RST;
643 +#endif
644 + DEASSERT_SYSRST_PCIE(val);
645 + printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
646 +
647 + if ((*(unsigned int *)(0xbe00000c)&0xFFFF) == 0x0101) // MT7621 E2
648 + bypass_pipe_rst();
649 + set_phy_for_ssc();
650 + printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
651 +
652 +#if defined (CONFIG_PCIE_PORT0)
653 + read_config(0, 0, 0, 0x70c, &val);
654 + printk("Port 0 N_FTS = %x\n", (unsigned int)val);
655 +#endif
656 +#if defined (CONFIG_PCIE_PORT1)
657 + read_config(0, 1, 0, 0x70c, &val);
658 + printk("Port 1 N_FTS = %x\n", (unsigned int)val);
659 +#endif
660 +#if defined (CONFIG_PCIE_PORT2)
661 + read_config(0, 2, 0, 0x70c, &val);
662 + printk("Port 2 N_FTS = %x\n", (unsigned int)val);
663 +#endif
664 +
665 + RALINK_RSTCTRL = (RALINK_RSTCTRL | RALINK_PCIE_RST);
666 + RALINK_SYSCFG1 &= ~(0x30);
667 + RALINK_SYSCFG1 |= (2<<4);
668 + RALINK_PCIE_CLK_GEN &= 0x7fffffff;
669 + RALINK_PCIE_CLK_GEN1 &= 0x80ffffff;
670 + RALINK_PCIE_CLK_GEN1 |= 0xa << 24;
671 + RALINK_PCIE_CLK_GEN |= 0x80000000;
672 + mdelay(50);
673 + RALINK_RSTCTRL = (RALINK_RSTCTRL & ~RALINK_PCIE_RST);
674 +
675 +
676 +#if defined GPIO_PERST /* add GPIO control instead of PERST_N */ /*chhung*/
677 + *(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // set DATA
678 + mdelay(100);
679 +#else
680 + RALINK_PCI_PCICFG_ADDR &= ~(1<<1); //de-assert PERST
681 +#endif
682 + mdelay(500);
683 +
684 +
685 + mdelay(500);
686 +#if defined (CONFIG_PCIE_PORT0)
687 + if(( RALINK_PCI0_STATUS & 0x1) == 0)
688 + {
689 + printk("PCIE0 no card, disable it(RST&CLK)\n");
690 + ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
691 + RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE0_CLK_EN);
692 + pcie_link_status &= ~(1<<0);
693 + } else {
694 + pcie_link_status |= 1<<0;
695 + RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
696 + }
697 +#endif
698 +#if defined (CONFIG_PCIE_PORT1)
699 + if(( RALINK_PCI1_STATUS & 0x1) == 0)
700 + {
701 + printk("PCIE1 no card, disable it(RST&CLK)\n");
702 + ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
703 + RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE1_CLK_EN);
704 + pcie_link_status &= ~(1<<1);
705 + } else {
706 + pcie_link_status |= 1<<1;
707 + RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
708 + }
709 +#endif
710 +#if defined (CONFIG_PCIE_PORT2)
711 + if (( RALINK_PCI2_STATUS & 0x1) == 0) {
712 + printk("PCIE2 no card, disable it(RST&CLK)\n");
713 + ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
714 + RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE2_CLK_EN);
715 + pcie_link_status &= ~(1<<2);
716 + } else {
717 + pcie_link_status |= 1<<2;
718 + RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt
719 + }
720 +#endif
721 + if (pcie_link_status == 0)
722 + return 0;
723 +
724 +/*
725 +pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
726 +3'b000 x x x
727 +3'b001 x x 0
728 +3'b010 x 0 x
729 +3'b011 x 1 0
730 +3'b100 0 x x
731 +3'b101 1 x 0
732 +3'b110 1 0 x
733 +3'b111 2 1 0
734 +*/
735 + switch(pcie_link_status) {
736 + case 2:
737 + RALINK_PCI_PCICFG_ADDR &= ~0x00ff0000;
738 + RALINK_PCI_PCICFG_ADDR |= 0x1 << 16; //port0
739 + RALINK_PCI_PCICFG_ADDR |= 0x0 << 20; //port1
740 + break;
741 + case 4:
742 + RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
743 + RALINK_PCI_PCICFG_ADDR |= 0x1 << 16; //port0
744 + RALINK_PCI_PCICFG_ADDR |= 0x2 << 20; //port1
745 + RALINK_PCI_PCICFG_ADDR |= 0x0 << 24; //port2
746 + break;
747 + case 5:
748 + RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
749 + RALINK_PCI_PCICFG_ADDR |= 0x0 << 16; //port0
750 + RALINK_PCI_PCICFG_ADDR |= 0x2 << 20; //port1
751 + RALINK_PCI_PCICFG_ADDR |= 0x1 << 24; //port2
752 + break;
753 + case 6:
754 + RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
755 + RALINK_PCI_PCICFG_ADDR |= 0x2 << 16; //port0
756 + RALINK_PCI_PCICFG_ADDR |= 0x0 << 20; //port1
757 + RALINK_PCI_PCICFG_ADDR |= 0x1 << 24; //port2
758 + break;
759 + }
760 + printk(" -> %x\n", RALINK_PCI_PCICFG_ADDR);
761 + //printk(" RALINK_PCI_ARBCTL = %x\n", RALINK_PCI_ARBCTL);
762 +
763 +/*
764 + ioport_resource.start = mt7621_res_pci_io1.start;
765 + ioport_resource.end = mt7621_res_pci_io1.end;
766 +*/
767 +
768 + RALINK_PCI_MEMBASE = 0xffffffff; //RALINK_PCI_MM_MAP_BASE;
769 + RALINK_PCI_IOBASE = RALINK_PCI_IO_MAP_BASE;
770 +
771 +#if defined (CONFIG_PCIE_PORT0)
772 + //PCIe0
773 + if((pcie_link_status & 0x1) != 0) {
774 + RALINK_PCI0_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
775 + RALINK_PCI0_IMBASEBAR0_ADDR = MEMORY_BASE;
776 + RALINK_PCI0_CLASS = 0x06040001;
777 + printk("PCIE0 enabled\n");
778 + }
779 +#endif
780 +#if defined (CONFIG_PCIE_PORT1)
781 + //PCIe1
782 + if ((pcie_link_status & 0x2) != 0) {
783 + RALINK_PCI1_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
784 + RALINK_PCI1_IMBASEBAR0_ADDR = MEMORY_BASE;
785 + RALINK_PCI1_CLASS = 0x06040001;
786 + printk("PCIE1 enabled\n");
787 + }
788 +#endif
789 +#if defined (CONFIG_PCIE_PORT2)
790 + //PCIe2
791 + if ((pcie_link_status & 0x4) != 0) {
792 + RALINK_PCI2_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
793 + RALINK_PCI2_IMBASEBAR0_ADDR = MEMORY_BASE;
794 + RALINK_PCI2_CLASS = 0x06040001;
795 + printk("PCIE2 enabled\n");
796 + }
797 +#endif
798 +
799 +
800 + switch(pcie_link_status) {
801 + case 7:
802 + read_config(0, 2, 0, 0x4, &val);
803 + write_config(0, 2, 0, 0x4, val|0x4);
804 + // write_config(0, 1, 0, 0x4, val|0x7);
805 + read_config(0, 2, 0, 0x70c, &val);
806 + val &= ~(0xff)<<8;
807 + val |= 0x50<<8;
808 + write_config(0, 2, 0, 0x70c, val);
809 + case 3:
810 + case 5:
811 + case 6:
812 + read_config(0, 1, 0, 0x4, &val);
813 + write_config(0, 1, 0, 0x4, val|0x4);
814 + // write_config(0, 1, 0, 0x4, val|0x7);
815 + read_config(0, 1, 0, 0x70c, &val);
816 + val &= ~(0xff)<<8;
817 + val |= 0x50<<8;
818 + write_config(0, 1, 0, 0x70c, val);
819 + default:
820 + read_config(0, 0, 0, 0x4, &val);
821 + write_config(0, 0, 0, 0x4, val|0x4); //bus master enable
822 + // write_config(0, 0, 0, 0x4, val|0x7); //bus master enable
823 + read_config(0, 0, 0, 0x70c, &val);
824 + val &= ~(0xff)<<8;
825 + val |= 0x50<<8;
826 + write_config(0, 0, 0, 0x70c, val);
827 + }
828 +
829 + pci_load_of_ranges(&mt7621_controller, pdev->dev.of_node);
830 + setup_cm_memory_region(mt7621_controller.mem_resource);
831 + register_pci_controller(&mt7621_controller);
832 + return 0;
833 +
834 +}
835 +
836 +int pcibios_plat_dev_init(struct pci_dev *dev)
837 +{
838 + return 0;
839 +}
840 +
841 +static const struct of_device_id mt7621_pci_ids[] = {
842 + { .compatible = "mediatek,mt7621-pci" },
843 + {},
844 +};
845 +MODULE_DEVICE_TABLE(of, mt7621_pci_ids);
846 +
847 +static struct platform_driver mt7621_pci_driver = {
848 + .probe = mt7621_pci_probe,
849 + .driver = {
850 + .name = "mt7621-pci",
851 + .owner = THIS_MODULE,
852 + .of_match_table = of_match_ptr(mt7621_pci_ids),
853 + },
854 +};
855 +
856 +static int __init mt7621_pci_init(void)
857 +{
858 + return platform_driver_register(&mt7621_pci_driver);
859 +}
860 +
861 +arch_initcall(mt7621_pci_init);