OpenWrt – Blame information for rev 1
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1 | office | 1 | /* |
2 | * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards |
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3 | * |
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4 | * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org> |
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5 | * |
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6 | * The cache manipulation routine has been taken from the U-Boot project. |
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7 | * (C) Copyright 2003 |
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8 | * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> |
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9 | * |
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10 | * This program is free software; you can redistribute it and/or modify it |
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11 | * under the terms of the GNU General Public License version 2 as published |
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12 | * by the Free Software Foundation. |
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13 | * |
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14 | */ |
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15 | |||
16 | #include "cache.h" |
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17 | #include "cacheops.h" |
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18 | #include "config.h" |
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19 | |||
20 | #define cache_op(op,addr) \ |
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21 | __asm__ __volatile__( \ |
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22 | " .set push \n" \ |
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23 | " .set noreorder \n" \ |
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24 | " .set mips3\n\t \n" \ |
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25 | " cache %0, %1 \n" \ |
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26 | " .set pop \n" \ |
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27 | : \ |
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28 | : "i" (op), "R" (*(unsigned char *)(addr))) |
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29 | |||
30 | void flush_cache(unsigned long start_addr, unsigned long size) |
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31 | { |
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32 | unsigned long lsize = CONFIG_CACHELINE_SIZE; |
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33 | unsigned long addr = start_addr & ~(lsize - 1); |
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34 | unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); |
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35 | |||
36 | while (1) { |
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37 | cache_op(Hit_Writeback_Inv_D, addr); |
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38 | cache_op(Hit_Invalidate_I, addr); |
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39 | if (addr == aend) |
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40 | break; |
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41 | addr += lsize; |
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42 | } |
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43 | } |