OpenWrt – Blame information for rev 1
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1 | office | 1 | /* This program is free software; you can redistribute it and/or modify |
2 | * it under the terms of the GNU General Public License as published by |
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3 | * the Free Software Foundation; version 2 of the License |
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4 | * |
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5 | * This program is distributed in the hope that it will be useful, |
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6 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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7 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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8 | * GNU General Public License for more details. |
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9 | * |
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10 | * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org> |
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11 | * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name> |
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12 | * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com> |
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13 | */ |
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14 | |||
15 | #include <linux/module.h> |
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16 | |||
17 | #include <asm/mach-ralink/ralink_regs.h> |
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18 | |||
19 | #include "mtk_eth_soc.h" |
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20 | #include "mdio_rt2880.h" |
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21 | |||
22 | #define RT305X_RESET_FE BIT(21) |
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23 | #define RT305X_RESET_ESW BIT(23) |
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24 | |||
25 | static const u16 rt5350_reg_table[FE_REG_COUNT] = { |
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26 | [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG, |
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27 | [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG, |
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28 | [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG, |
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29 | [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0, |
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30 | [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0, |
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31 | [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0, |
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32 | [FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0, |
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33 | [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0, |
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34 | [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0, |
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35 | [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0, |
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36 | [FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0, |
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37 | [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE, |
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38 | [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS, |
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39 | [FE_REG_FE_RST_GL] = 0, |
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40 | [FE_REG_FE_DMA_VID_BASE] = 0, |
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41 | }; |
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42 | |||
43 | static void rt305x_init_data(struct fe_soc_data *data, |
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44 | struct net_device *netdev) |
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45 | { |
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46 | struct fe_priv *priv = netdev_priv(netdev); |
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47 | |||
48 | priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_PADDING_BUG | |
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49 | FE_FLAG_CALIBRATE_CLK | FE_FLAG_HAS_SWITCH; |
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50 | netdev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | |
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51 | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX; |
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52 | } |
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53 | |||
54 | static int rt3050_fwd_config(struct fe_priv *priv) |
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55 | { |
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56 | int ret; |
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57 | |||
58 | if (ralink_soc != RT305X_SOC_RT3052) { |
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59 | ret = fe_set_clock_cycle(priv); |
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60 | if (ret) |
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61 | return ret; |
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62 | } |
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63 | |||
64 | fe_fwd_config(priv); |
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65 | if (ralink_soc != RT305X_SOC_RT3352) |
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66 | fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG); |
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67 | fe_csum_config(priv); |
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68 | |||
69 | return 0; |
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70 | } |
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71 | |||
72 | static void rt305x_fe_reset(void) |
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73 | { |
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74 | fe_reset(RT305X_RESET_FE); |
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75 | } |
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76 | |||
77 | static void rt5350_init_data(struct fe_soc_data *data, |
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78 | struct net_device *netdev) |
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79 | { |
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80 | struct fe_priv *priv = netdev_priv(netdev); |
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81 | |||
82 | priv->flags = FE_FLAG_HAS_SWITCH; |
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83 | netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM; |
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84 | } |
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85 | |||
86 | static void rt5350_set_mac(struct fe_priv *priv, unsigned char *mac) |
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87 | { |
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88 | unsigned long flags; |
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89 | |||
90 | spin_lock_irqsave(&priv->page_lock, flags); |
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91 | fe_w32((mac[0] << 8) | mac[1], RT5350_SDM_MAC_ADRH); |
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92 | fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], |
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93 | RT5350_SDM_MAC_ADRL); |
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94 | spin_unlock_irqrestore(&priv->page_lock, flags); |
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95 | } |
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96 | |||
97 | static void rt5350_rxcsum_config(bool enable) |
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98 | { |
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99 | if (enable) |
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100 | fe_w32(fe_r32(RT5350_SDM_CFG) | (RT5350_SDM_ICS_EN | |
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101 | RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN), |
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102 | RT5350_SDM_CFG); |
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103 | else |
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104 | fe_w32(fe_r32(RT5350_SDM_CFG) & ~(RT5350_SDM_ICS_EN | |
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105 | RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN), |
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106 | RT5350_SDM_CFG); |
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107 | } |
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108 | |||
109 | static int rt5350_fwd_config(struct fe_priv *priv) |
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110 | { |
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111 | struct net_device *dev = priv_netdev(priv); |
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112 | |||
113 | rt5350_rxcsum_config((dev->features & NETIF_F_RXCSUM)); |
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114 | |||
115 | return 0; |
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116 | } |
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117 | |||
118 | static void rt5350_tx_dma(struct fe_tx_dma *txd) |
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119 | { |
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120 | txd->txd4 = 0; |
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121 | } |
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122 | |||
123 | static void rt5350_fe_reset(void) |
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124 | { |
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125 | fe_reset(RT305X_RESET_FE | RT305X_RESET_ESW); |
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126 | } |
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127 | |||
128 | static struct fe_soc_data rt3050_data = { |
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129 | .init_data = rt305x_init_data, |
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130 | .reset_fe = rt305x_fe_reset, |
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131 | .fwd_config = rt3050_fwd_config, |
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132 | .pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS, |
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133 | .checksum_bit = RX_DMA_L4VALID, |
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134 | .rx_int = FE_RX_DONE_INT, |
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135 | .tx_int = FE_TX_DONE_INT, |
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136 | .status_int = FE_CNT_GDM_AF, |
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137 | }; |
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138 | |||
139 | static struct fe_soc_data rt5350_data = { |
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140 | .init_data = rt5350_init_data, |
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141 | .reg_table = rt5350_reg_table, |
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142 | .reset_fe = rt5350_fe_reset, |
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143 | .set_mac = rt5350_set_mac, |
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144 | .fwd_config = rt5350_fwd_config, |
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145 | .tx_dma = rt5350_tx_dma, |
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146 | .pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS, |
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147 | .checksum_bit = RX_DMA_L4VALID, |
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148 | .rx_int = RT5350_RX_DONE_INT, |
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149 | .tx_int = RT5350_TX_DONE_INT, |
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150 | }; |
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151 | |||
152 | const struct of_device_id of_fe_match[] = { |
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153 | { .compatible = "ralink,rt3050-eth", .data = &rt3050_data }, |
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154 | { .compatible = "ralink,rt5350-eth", .data = &rt5350_data }, |
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155 | {}, |
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156 | }; |
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157 | |||
158 | MODULE_DEVICE_TABLE(of, of_fe_match); |