OpenWrt – Blame information for rev 1
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1 | office | 1 | /* This program is free software; you can redistribute it and/or modify |
2 | * it under the terms of the GNU General Public License as published by |
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3 | * the Free Software Foundation; version 2 of the License |
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4 | * |
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5 | * This program is distributed in the hope that it will be useful, |
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6 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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7 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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8 | * GNU General Public License for more details. |
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9 | * |
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10 | * Copyright (C) 2014-2016 Sean Wang <sean.wang@mediatek.com> |
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11 | * Copyright (C) 2016-2017 John Crispin <blogic@openwrt.org> |
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12 | */ |
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13 | |||
14 | #include <linux/dma-mapping.h> |
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15 | #include <linux/delay.h> |
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16 | #include <linux/if.h> |
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17 | #include <linux/io.h> |
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18 | #include <linux/module.h> |
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19 | #include <linux/of_device.h> |
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20 | #include <linux/platform_device.h> |
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21 | #include <linux/reset.h> |
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22 | #include <linux/netfilter.h> |
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23 | #include <linux/netdevice.h> |
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24 | #include <net/netfilter/nf_flow_table.h> |
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25 | #include <linux/debugfs.h> |
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26 | #include <linux/etherdevice.h> |
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27 | #include <linux/bitfield.h> |
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28 | |||
29 | #include "mtk_eth_soc.h" |
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30 | |||
31 | #ifdef CONFIG_RALINK |
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32 | /* ramips compat */ |
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33 | #define mtk_eth fe_priv |
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34 | #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) |
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35 | #define mtk_m32 fe_m32 |
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36 | |||
37 | static inline u32 |
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38 | mtk_r32(struct mtk_eth *eth, u32 reg) |
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39 | { |
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40 | return fe_r32(reg); |
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41 | } |
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42 | |||
43 | static inline void |
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44 | mtk_w32(struct mtk_eth *eth, u32 val, u32 reg) |
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45 | { |
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46 | fe_w32(val, reg); |
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47 | } |
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48 | #endif |
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49 | |||
50 | #define MTK_REG_PPE_GLO_CFG 0xe00 |
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51 | #define MTK_PPE_GLO_CFG_BUSY BIT(31) |
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52 | #define MTK_PPE_GLO_CFG_TTL0_DROP BIT(4) |
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53 | #define MTK_PPE_GLO_CFG_EN BIT(0) |
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54 | |||
55 | #define MTK_REG_PPE_FLOW_CFG 0xe04 |
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56 | #define MTK_PPE_FLOW_CFG_IPV4_GREK_EN BIT(19) |
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57 | #define MTK_PPE_FLOW_CFG_IPV4_NAT_FRAG_EN BIT(17) |
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58 | #define MTK_PPE_FLOW_CFG_IPV4_NAPT_EN BIT(13) |
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59 | #define MTK_PPE_FLOW_CFG_IPV4_NAT_EN BIT(12) |
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60 | #define MTK_PPE_FLOW_CFG_FUC_FOE BIT(2) |
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61 | #define MTK_PPE_FLOW_CFG_FMC_FOE BIT(1) |
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62 | |||
63 | #define MTK_REG_PPE_IP_PROT_CHK 0xe08 |
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64 | |||
65 | #define MTK_REG_PPE_TB_BASE 0xe20 |
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66 | |||
67 | #define MTK_REG_PPE_BNDR 0xe28 |
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68 | #define MTK_PPE_BNDR_RATE_MASK 0xffff |
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69 | |||
70 | #define MTK_REG_PPE_BIND_LMT_0 0xe2C |
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71 | |||
72 | #define MTK_REG_PPE_BIND_LMT_1 0xe30 |
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73 | #define MTK_PPE_NTU_KA BIT(16) |
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74 | |||
75 | #define MTK_REG_PPE_KA 0xe34 |
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76 | #define MTK_PPE_KA_T BIT(0) |
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77 | #define MTK_PPE_KA_TCP BIT(16) |
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78 | #define MTK_PPE_KA_UDP BIT(24) |
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79 | |||
80 | #define MTK_REG_PPE_UNB_AGE 0xe38 |
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81 | #define MTK_PPE_UNB_AGE_MNP_MASK (0xffff << 16) |
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82 | #define MTK_PPE_UNB_AGE_MNP (1000 << 16) |
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83 | #define MTK_PPE_UNB_AGE_DLTA_MASK 0xff |
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84 | #define MTK_PPE_UNB_AGE_DLTA 3 |
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85 | |||
86 | #define MTK_REG_PPE_BND_AGE0 0xe3c |
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87 | #define MTK_PPE_BND_AGE0_NTU_DLTA_MASK (0xffff << 16) |
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88 | #define MTK_PPE_BND_AGE0_NTU_DLTA (5 << 16) |
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89 | #define MTK_PPE_BND_AGE0_UDP_DLTA_MASK 0xffff |
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90 | #define MTK_PPE_BND_AGE0_UDP_DLTA 5 |
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91 | |||
92 | #define MTK_REG_PPE_BND_AGE1 0xe40 |
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93 | #define MTK_PPE_BND_AGE1_FIN_DLTA_MASK (0xffff << 16) |
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94 | #define MTK_PPE_BND_AGE1_FIN_DLTA (5 << 16) |
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95 | #define MTK_PPE_BND_AGE1_TCP_DLTA_MASK 0xffff |
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96 | #define MTK_PPE_BND_AGE1_TCP_DLTA 5 |
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97 | |||
98 | #define MTK_REG_PPE_DFT_CPORT 0xe48 |
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99 | |||
100 | #define MTK_REG_PPE_TB_CFG 0xe1c |
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101 | #define MTK_PPE_TB_CFG_X_MODE_MASK (3 << 18) |
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102 | #define MTK_PPE_TB_CFG_HASH_MODE1 BIT(14) |
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103 | #define MTK_PPE_TB_CFG_HASH_MODE_MASK (0x3 << 14) |
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104 | #define MTK_PPE_TB_CFG_KA (3 << 12) |
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105 | #define MTK_PPE_TB_CFG_KA_MASK (0x3 << 12) |
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106 | #define MTK_PPE_TB_CFG_FIN_AGE BIT(11) |
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107 | #define MTK_PPE_TB_CFG_UDP_AGE BIT(10) |
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108 | #define MTK_PPE_TB_CFG_TCP_AGE BIT(9) |
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109 | #define MTK_PPE_TB_CFG_UNBD_AGE BIT(8) |
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110 | #define MTK_PPE_TB_CFG_NTU_AGE BIT(7) |
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111 | #define MTK_PPE_TB_CFG_SMA_FWD_CPU (0x3 << 4) |
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112 | #define MTK_PPE_TB_CFG_SMA_MASK (0x3 << 4) |
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113 | #define MTK_PPE_TB_CFG_ENTRY_SZ_64B 0 |
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114 | #define MTK_PPE_TB_CFG_ENTRY_SZ_MASK BIT(3) |
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115 | #define MTK_PPE_TB_CFG_TBL_SZ_4K 2 |
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116 | #define MTK_PPE_TB_CFG_TBL_SZ_MASK 0x7 |
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117 | |||
118 | #define MTK_REG_PPE_HASH_SEED 0xe44 |
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119 | #define MTK_PPE_HASH_SEED 0x12345678 |
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120 | |||
121 | |||
122 | #define MTK_REG_PPE_CAH_CTRL 0xf20 |
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123 | #define MTK_PPE_CAH_CTRL_X_MODE BIT(9) |
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124 | #define MTK_PPE_CAH_CTRL_EN BIT(0) |
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125 | |||
126 | struct mtk_foe_unbind_info_blk { |
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127 | u32 time_stamp:8; |
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128 | u32 pcnt:16; /* packet count */ |
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129 | u32 preb:1; |
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130 | u32 pkt_type:3; |
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131 | u32 state:2; |
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132 | u32 udp:1; |
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133 | u32 sta:1; /* static entry */ |
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134 | } __attribute__ ((packed)); |
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135 | |||
136 | struct mtk_foe_bind_info_blk { |
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137 | u32 time_stamp:15; |
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138 | u32 ka:1; /* keep alive */ |
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139 | u32 vlan_layer:3; |
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140 | u32 psn:1; /* egress packet has PPPoE session */ |
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141 | #ifdef CONFIG_RALINK |
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142 | u32 vpm:2; /* 0:ethertype remark, 1:0x8100(CR default) */ |
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143 | #else |
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144 | u32 vpm:1; /* 0:ethertype remark, 1:0x8100(CR default) */ |
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145 | u32 ps:1; /* packet sampling */ |
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146 | #endif |
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147 | u32 cah:1; /* cacheable flag */ |
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148 | u32 rmt:1; /* remove tunnel ip header (6rd/dslite only) */ |
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149 | u32 ttl:1; |
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150 | u32 pkt_type:3; |
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151 | u32 state:2; |
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152 | u32 udp:1; |
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153 | u32 sta:1; /* static entry */ |
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154 | } __attribute__ ((packed)); |
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155 | |||
156 | struct mtk_foe_info_blk2 { |
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157 | u32 qid:4; /* QID in Qos Port */ |
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158 | u32 fqos:1; /* force to PSE QoS port */ |
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159 | u32 dp:3; /* force to PSE port x |
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160 | 0:PSE,1:GSW, 2:GMAC,4:PPE,5:QDMA,7=DROP */ |
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161 | u32 mcast:1; /* multicast this packet to CPU */ |
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162 | u32 pcpl:1; /* OSBN */ |
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163 | u32 mlen:1; /* 0:post 1:pre packet length in meter */ |
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164 | u32 alen:1; /* 0:post 1:pre packet length in accounting */ |
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165 | u32 port_mg:6; /* port meter group */ |
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166 | u32 port_ag:6; /* port account group */ |
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167 | u32 dscp:8; /* DSCP value */ |
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168 | } __attribute__ ((packed)); |
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169 | |||
170 | struct mtk_foe_ipv4_hnapt { |
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171 | union { |
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172 | struct mtk_foe_bind_info_blk bfib1; |
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173 | struct mtk_foe_unbind_info_blk udib1; |
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174 | u32 info_blk1; |
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175 | }; |
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176 | u32 sip; |
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177 | u32 dip; |
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178 | u16 dport; |
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179 | u16 sport; |
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180 | union { |
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181 | struct mtk_foe_info_blk2 iblk2; |
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182 | u32 info_blk2; |
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183 | }; |
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184 | u32 new_sip; |
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185 | u32 new_dip; |
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186 | u16 new_dport; |
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187 | u16 new_sport; |
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188 | u32 resv1; |
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189 | u32 resv2; |
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190 | u32 resv3:26; |
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191 | u32 act_dp:6; /* UDF */ |
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192 | u16 vlan1; |
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193 | u16 etype; |
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194 | u32 dmac_hi; |
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195 | u16 vlan2; |
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196 | u16 dmac_lo; |
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197 | u32 smac_hi; |
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198 | u16 pppoe_id; |
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199 | u16 smac_lo; |
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200 | } __attribute__ ((packed)); |
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201 | |||
202 | struct mtk_foe_entry { |
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203 | union { |
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204 | struct mtk_foe_unbind_info_blk udib1; |
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205 | struct mtk_foe_bind_info_blk bfib1; |
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206 | struct mtk_foe_ipv4_hnapt ipv4_hnapt; |
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207 | }; |
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208 | }; |
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209 | |||
210 | enum mtk_foe_entry_state { |
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211 | FOE_STATE_INVALID = 0, |
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212 | FOE_STATE_UNBIND = 1, |
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213 | FOE_STATE_BIND = 2, |
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214 | FOE_STATE_FIN = 3 |
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215 | }; |
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216 | |||
217 | |||
218 | #define MTK_RXD4_FOE_ENTRY GENMASK(13, 0) |
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219 | #define MTK_RXD4_CPU_REASON GENMASK(18, 14) |
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220 | #define MTK_RXD4_SRC_PORT GENMASK(21, 19) |
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221 | #define MTK_RXD4_ALG GENMASK(31, 22) |
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222 | |||
223 | enum mtk_foe_cpu_reason { |
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224 | MTK_CPU_REASON_TTL_EXCEEDED = 0x02, |
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225 | MTK_CPU_REASON_OPTION_HEADER = 0x03, |
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226 | MTK_CPU_REASON_NO_FLOW = 0x07, |
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227 | MTK_CPU_REASON_IPV4_FRAG = 0x08, |
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228 | MTK_CPU_REASON_IPV4_DSLITE_FRAG = 0x09, |
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229 | MTK_CPU_REASON_IPV4_DSLITE_NO_TCP_UDP = 0x0a, |
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230 | MTK_CPU_REASON_IPV6_6RD_NO_TCP_UDP = 0x0b, |
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231 | MTK_CPU_REASON_TCP_FIN_SYN_RST = 0x0c, |
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232 | MTK_CPU_REASON_UN_HIT = 0x0d, |
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233 | MTK_CPU_REASON_HIT_UNBIND = 0x0e, |
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234 | MTK_CPU_REASON_HIT_UNBIND_RATE_REACHED = 0x0f, |
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235 | MTK_CPU_REASON_HIT_BIND_TCP_FIN = 0x10, |
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236 | MTK_CPU_REASON_HIT_TTL_1 = 0x11, |
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237 | MTK_CPU_REASON_HIT_BIND_VLAN_VIOLATION = 0x12, |
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238 | MTK_CPU_REASON_KEEPALIVE_UC_OLD_HDR = 0x13, |
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239 | MTK_CPU_REASON_KEEPALIVE_MC_NEW_HDR = 0x14, |
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240 | MTK_CPU_REASON_KEEPALIVE_DUP_OLD_HDR = 0x15, |
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241 | MTK_CPU_REASON_HIT_BIND_FORCE_CPU = 0x16, |
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242 | MTK_CPU_REASON_TUNNEL_OPTION_HEADER = 0x17, |
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243 | MTK_CPU_REASON_MULTICAST_TO_CPU = 0x18, |
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244 | MTK_CPU_REASON_MULTICAST_TO_GMAC1_CPU = 0x19, |
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245 | MTK_CPU_REASON_HIT_PRE_BIND = 0x1a, |
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246 | MTK_CPU_REASON_PACKET_SAMPLING = 0x1b, |
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247 | MTK_CPU_REASON_EXCEED_MTU = 0x1c, |
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248 | MTK_CPU_REASON_PPE_BYPASS = 0x1e, |
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249 | MTK_CPU_REASON_INVALID = 0x1f, |
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250 | }; |
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251 | |||
252 | |||
253 | /* our table size is 4K */ |
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254 | #define MTK_PPE_ENTRY_CNT 0x1000 |
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255 | #define MTK_PPE_TBL_SZ \ |
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256 | (MTK_PPE_ENTRY_CNT * sizeof(struct mtk_foe_entry)) |
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257 | |||
258 | int mtk_ppe_debugfs_init(struct mtk_eth *eth); |
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259 | |||
260 |