OpenWrt – Blame information for rev 1
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1 | office | 1 | /* Copyright Statement: |
2 | * |
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3 | * This software/firmware and related documentation ("MediaTek Software") are |
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4 | * protected under relevant copyright laws. The information contained herein |
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5 | * is confidential and proprietary to MediaTek Inc. and/or its licensors. |
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6 | * Without the prior written permission of MediaTek inc. and/or its licensors, |
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7 | * any reproduction, modification, use or disclosure of MediaTek Software, |
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8 | * and information contained herein, in whole or in part, shall be strictly prohibited. |
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9 | * |
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10 | * MediaTek Inc. (C) 2010. All rights reserved. |
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11 | * |
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12 | * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
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13 | * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
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14 | * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON |
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15 | * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
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16 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
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17 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
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18 | * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
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19 | * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
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20 | * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH |
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21 | * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES |
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22 | * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES |
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23 | * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK |
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24 | * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR |
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25 | * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND |
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26 | * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
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27 | * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
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28 | * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO |
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29 | * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
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30 | * |
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31 | * The following software/firmware and/or related documentation ("MediaTek Software") |
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32 | * have been modified by MediaTek Inc. All revisions are subject to any receiver's |
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33 | * applicable license agreements with MediaTek Inc. |
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34 | */ |
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35 | |||
36 | #include <linux/module.h> |
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37 | #include <linux/delay.h> |
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38 | #include <linux/dma-mapping.h> |
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39 | #include <linux/spinlock.h> |
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40 | #include <linux/platform_device.h> |
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41 | #include <linux/interrupt.h> |
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42 | |||
43 | #include <linux/mmc/host.h> |
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44 | #include <linux/mmc/mmc.h> |
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45 | #include <linux/mmc/sd.h> |
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46 | #include <linux/mmc/sdio.h> |
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47 | |||
48 | #include <asm/mach-ralink/ralink_regs.h> |
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49 | |||
50 | #include "board.h" |
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51 | #include "dbg.h" |
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52 | #include "mt6575_sd.h" |
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53 | |||
54 | //#define IRQ_SDC 14 //MT7620 /*FIXME*/ |
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55 | #ifdef CONFIG_SOC_MT7621 |
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56 | #define RALINK_SYSCTL_BASE 0xbe000000 |
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57 | #define RALINK_MSDC_BASE 0xbe130000 |
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58 | #else |
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59 | #define RALINK_SYSCTL_BASE 0xb0000000 |
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60 | #define RALINK_MSDC_BASE 0xb0130000 |
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61 | #endif |
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62 | #define IRQ_SDC 22 /*FIXME*/ |
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63 | |||
64 | #define DRV_NAME "mtk-sd" |
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65 | |||
66 | #if defined(CONFIG_SOC_MT7620) |
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67 | #define HOST_MAX_MCLK (48000000) /* +/- by chhung */ |
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68 | #elif defined(CONFIG_SOC_MT7621) |
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69 | #define HOST_MAX_MCLK (50000000) /* +/- by chhung */ |
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70 | #endif |
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71 | #define HOST_MIN_MCLK (260000) |
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72 | |||
73 | #define HOST_MAX_BLKSZ (2048) |
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74 | |||
75 | #define MSDC_OCR_AVAIL (MMC_VDD_28_29 | MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33) |
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76 | |||
77 | #define GPIO_PULL_DOWN (0) |
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78 | #define GPIO_PULL_UP (1) |
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79 | |||
80 | #if 0 /* --- by chhung */ |
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81 | #define MSDC_CLKSRC_REG (0xf100000C) |
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82 | #define PDN_REG (0xF1000010) |
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83 | #endif /* end of --- */ |
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84 | |||
85 | #define DEFAULT_DEBOUNCE (8) /* 8 cycles */ |
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86 | #define DEFAULT_DTOC (40) /* data timeout counter. 65536x40 sclk. */ |
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87 | |||
88 | #define CMD_TIMEOUT (HZ / 10) /* 100ms */ |
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89 | #define DAT_TIMEOUT (HZ / 2 * 5) /* 500ms x5 */ |
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90 | |||
91 | #define MAX_DMA_CNT (64 * 1024 - 512) /* a single transaction for WIFI may be 50K*/ |
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92 | |||
93 | #define MAX_GPD_NUM (1 + 1) /* one null gpd */ |
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94 | #define MAX_BD_NUM (1024) |
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95 | #define MAX_BD_PER_GPD (MAX_BD_NUM) |
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96 | |||
97 | #define MAX_HW_SGMTS (MAX_BD_NUM) |
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98 | #define MAX_PHY_SGMTS (MAX_BD_NUM) |
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99 | #define MAX_SGMT_SZ (MAX_DMA_CNT) |
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100 | #define MAX_REQ_SZ (MAX_SGMT_SZ * 8) |
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101 | |||
102 | static int cd_active_low = 1; |
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103 | |||
104 | //================================= |
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105 | #define PERI_MSDC0_PDN (15) |
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106 | //#define PERI_MSDC1_PDN (16) |
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107 | //#define PERI_MSDC2_PDN (17) |
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108 | //#define PERI_MSDC3_PDN (18) |
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109 | |||
110 | #if 0 /* --- by chhung */ |
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111 | /* gate means clock power down */ |
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112 | static int g_clk_gate = 0; |
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113 | #define msdc_gate_clock(id) \ |
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114 | do { \ |
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115 | g_clk_gate &= ~(1 << ((id) + PERI_MSDC0_PDN)); \ |
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116 | } while (0) |
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117 | /* not like power down register. 1 means clock on. */ |
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118 | #define msdc_ungate_clock(id) \ |
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119 | do { \ |
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120 | g_clk_gate |= 1 << ((id) + PERI_MSDC0_PDN); \ |
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121 | } while (0) |
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122 | |||
123 | // do we need sync object or not |
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124 | void msdc_clk_status(int *status) |
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125 | { |
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126 | *status = g_clk_gate; |
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127 | } |
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128 | #endif /* end of --- */ |
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129 | |||
130 | /* +++ by chhung */ |
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131 | struct msdc_hw msdc0_hw = { |
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132 | .clk_src = 0, |
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133 | .flags = MSDC_CD_PIN_EN | MSDC_REMOVABLE, |
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134 | // .flags = MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE, |
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135 | }; |
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136 | |||
137 | /* end of +++ */ |
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138 | |||
139 | static int msdc_rsp[] = { |
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140 | 0, /* RESP_NONE */ |
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141 | 1, /* RESP_R1 */ |
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142 | 2, /* RESP_R2 */ |
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143 | 3, /* RESP_R3 */ |
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144 | 4, /* RESP_R4 */ |
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145 | 1, /* RESP_R5 */ |
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146 | 1, /* RESP_R6 */ |
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147 | 1, /* RESP_R7 */ |
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148 | 7, /* RESP_R1b */ |
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149 | }; |
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150 | |||
151 | #define msdc_txfifocnt() ((sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16) |
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152 | #define msdc_rxfifocnt() ((sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) >> 0) |
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153 | #define msdc_fifo_write32(v) sdr_write32(MSDC_TXDATA, (v)) |
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154 | #define msdc_fifo_write8(v) sdr_write8(MSDC_TXDATA, (v)) |
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155 | #define msdc_fifo_read32() sdr_read32(MSDC_RXDATA) |
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156 | #define msdc_fifo_read8() sdr_read8(MSDC_RXDATA) |
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157 | |||
158 | #define msdc_dma_on() sdr_clr_bits(MSDC_CFG, MSDC_CFG_PIO) |
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159 | |||
160 | #define msdc_retry(expr, retry, cnt) \ |
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161 | do { \ |
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162 | int backup = cnt; \ |
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163 | while (retry) { \ |
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164 | if (!(expr)) \ |
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165 | break; \ |
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166 | if (cnt-- == 0) { \ |
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167 | retry--; mdelay(1); cnt = backup; \ |
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168 | } \ |
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169 | } \ |
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170 | WARN_ON(retry == 0); \ |
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171 | } while (0) |
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172 | |||
173 | static void msdc_reset_hw(struct msdc_host *host) |
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174 | { |
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175 | void __iomem *base = host->base; |
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176 | |||
177 | sdr_set_bits(MSDC_CFG, MSDC_CFG_RST); |
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178 | while (sdr_read32(MSDC_CFG) & MSDC_CFG_RST) |
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179 | cpu_relax(); |
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180 | } |
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181 | |||
182 | #define msdc_clr_int() \ |
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183 | do { \ |
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184 | volatile u32 val = sdr_read32(MSDC_INT); \ |
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185 | sdr_write32(MSDC_INT, val); \ |
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186 | } while (0) |
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187 | |||
188 | #define msdc_clr_fifo() \ |
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189 | do { \ |
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190 | int retry = 3, cnt = 1000; \ |
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191 | sdr_set_bits(MSDC_FIFOCS, MSDC_FIFOCS_CLR); \ |
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192 | msdc_retry(sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_CLR, retry, cnt); \ |
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193 | } while (0) |
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194 | |||
195 | #define msdc_irq_save(val) \ |
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196 | do { \ |
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197 | val = sdr_read32(MSDC_INTEN); \ |
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198 | sdr_clr_bits(MSDC_INTEN, val); \ |
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199 | } while (0) |
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200 | |||
201 | #define msdc_irq_restore(val) \ |
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202 | do { \ |
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203 | sdr_set_bits(MSDC_INTEN, val); \ |
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204 | } while (0) |
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205 | |||
206 | /* clock source for host: global */ |
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207 | #if defined(CONFIG_SOC_MT7620) |
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208 | static u32 hclks[] = {48000000}; /* +/- by chhung */ |
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209 | #elif defined(CONFIG_SOC_MT7621) |
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210 | static u32 hclks[] = {50000000}; /* +/- by chhung */ |
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211 | #endif |
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212 | |||
213 | //============================================ |
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214 | // the power for msdc host controller: global |
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215 | // always keep the VMC on. |
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216 | //============================================ |
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217 | #define msdc_vcore_on(host) \ |
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218 | do { \ |
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219 | INIT_MSG("[+]VMC ref. count<%d>", ++host->pwr_ref); \ |
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220 | (void)hwPowerOn(MT65XX_POWER_LDO_VMC, VOL_3300, "SD"); \ |
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221 | } while (0) |
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222 | #define msdc_vcore_off(host) \ |
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223 | do { \ |
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224 | INIT_MSG("[-]VMC ref. count<%d>", --host->pwr_ref); \ |
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225 | (void)hwPowerDown(MT65XX_POWER_LDO_VMC, "SD"); \ |
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226 | } while (0) |
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227 | |||
228 | //==================================== |
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229 | // the vdd output for card: global |
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230 | // always keep the VMCH on. |
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231 | //==================================== |
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232 | #define msdc_vdd_on(host) \ |
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233 | do { \ |
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234 | (void)hwPowerOn(MT65XX_POWER_LDO_VMCH, VOL_3300, "SD"); \ |
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235 | } while (0) |
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236 | #define msdc_vdd_off(host) \ |
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237 | do { \ |
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238 | (void)hwPowerDown(MT65XX_POWER_LDO_VMCH, "SD"); \ |
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239 | } while (0) |
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240 | |||
241 | #define sdc_is_busy() (sdr_read32(SDC_STS) & SDC_STS_SDCBUSY) |
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242 | #define sdc_is_cmd_busy() (sdr_read32(SDC_STS) & SDC_STS_CMDBUSY) |
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243 | |||
244 | #define sdc_send_cmd(cmd, arg) \ |
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245 | do { \ |
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246 | sdr_write32(SDC_ARG, (arg)); \ |
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247 | sdr_write32(SDC_CMD, (cmd)); \ |
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248 | } while (0) |
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249 | |||
250 | // can modify to read h/w register. |
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251 | //#define is_card_present(h) ((sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 0 : 1); |
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252 | #define is_card_present(h) (((struct msdc_host *)(h))->card_inserted) |
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253 | |||
254 | /* +++ by chhung */ |
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255 | #ifndef __ASSEMBLY__ |
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256 | #define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff) |
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257 | #else |
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258 | #define PHYSADDR(a) ((a) & 0x1fffffff) |
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259 | #endif |
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260 | /* end of +++ */ |
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261 | static unsigned int msdc_do_command(struct msdc_host *host, |
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262 | struct mmc_command *cmd, |
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263 | int tune, |
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264 | unsigned long timeout); |
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265 | |||
266 | static int msdc_tune_cmdrsp(struct msdc_host *host, struct mmc_command *cmd); |
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267 | |||
268 | #ifdef MT6575_SD_DEBUG |
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269 | static void msdc_dump_card_status(struct msdc_host *host, u32 status) |
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270 | { |
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271 | /* N_MSG is currently a no-op */ |
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272 | #if 0 |
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273 | static char *state[] = { |
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274 | "Idle", /* 0 */ |
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275 | "Ready", /* 1 */ |
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276 | "Ident", /* 2 */ |
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277 | "Stby", /* 3 */ |
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278 | "Tran", /* 4 */ |
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279 | "Data", /* 5 */ |
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280 | "Rcv", /* 6 */ |
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281 | "Prg", /* 7 */ |
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282 | "Dis", /* 8 */ |
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283 | "Reserved", /* 9 */ |
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284 | "Reserved", /* 10 */ |
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285 | "Reserved", /* 11 */ |
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286 | "Reserved", /* 12 */ |
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287 | "Reserved", /* 13 */ |
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288 | "Reserved", /* 14 */ |
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289 | "I/O mode", /* 15 */ |
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290 | }; |
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291 | #endif |
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292 | if (status & R1_OUT_OF_RANGE) |
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293 | N_MSG(RSP, "[CARD_STATUS] Out of Range"); |
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294 | if (status & R1_ADDRESS_ERROR) |
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295 | N_MSG(RSP, "[CARD_STATUS] Address Error"); |
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296 | if (status & R1_BLOCK_LEN_ERROR) |
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297 | N_MSG(RSP, "[CARD_STATUS] Block Len Error"); |
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298 | if (status & R1_ERASE_SEQ_ERROR) |
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299 | N_MSG(RSP, "[CARD_STATUS] Erase Seq Error"); |
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300 | if (status & R1_ERASE_PARAM) |
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301 | N_MSG(RSP, "[CARD_STATUS] Erase Param"); |
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302 | if (status & R1_WP_VIOLATION) |
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303 | N_MSG(RSP, "[CARD_STATUS] WP Violation"); |
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304 | if (status & R1_CARD_IS_LOCKED) |
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305 | N_MSG(RSP, "[CARD_STATUS] Card is Locked"); |
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306 | if (status & R1_LOCK_UNLOCK_FAILED) |
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307 | N_MSG(RSP, "[CARD_STATUS] Lock/Unlock Failed"); |
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308 | if (status & R1_COM_CRC_ERROR) |
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309 | N_MSG(RSP, "[CARD_STATUS] Command CRC Error"); |
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310 | if (status & R1_ILLEGAL_COMMAND) |
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311 | N_MSG(RSP, "[CARD_STATUS] Illegal Command"); |
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312 | if (status & R1_CARD_ECC_FAILED) |
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313 | N_MSG(RSP, "[CARD_STATUS] Card ECC Failed"); |
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314 | if (status & R1_CC_ERROR) |
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315 | N_MSG(RSP, "[CARD_STATUS] CC Error"); |
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316 | if (status & R1_ERROR) |
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317 | N_MSG(RSP, "[CARD_STATUS] Error"); |
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318 | if (status & R1_UNDERRUN) |
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319 | N_MSG(RSP, "[CARD_STATUS] Underrun"); |
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320 | if (status & R1_OVERRUN) |
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321 | N_MSG(RSP, "[CARD_STATUS] Overrun"); |
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322 | if (status & R1_CID_CSD_OVERWRITE) |
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323 | N_MSG(RSP, "[CARD_STATUS] CID/CSD Overwrite"); |
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324 | if (status & R1_WP_ERASE_SKIP) |
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325 | N_MSG(RSP, "[CARD_STATUS] WP Eraser Skip"); |
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326 | if (status & R1_CARD_ECC_DISABLED) |
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327 | N_MSG(RSP, "[CARD_STATUS] Card ECC Disabled"); |
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328 | if (status & R1_ERASE_RESET) |
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329 | N_MSG(RSP, "[CARD_STATUS] Erase Reset"); |
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330 | if (status & R1_READY_FOR_DATA) |
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331 | N_MSG(RSP, "[CARD_STATUS] Ready for Data"); |
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332 | if (status & R1_SWITCH_ERROR) |
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333 | N_MSG(RSP, "[CARD_STATUS] Switch error"); |
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334 | if (status & R1_APP_CMD) |
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335 | N_MSG(RSP, "[CARD_STATUS] App Command"); |
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336 | |||
337 | N_MSG(RSP, "[CARD_STATUS] '%s' State", state[R1_CURRENT_STATE(status)]); |
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338 | } |
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339 | |||
340 | static void msdc_dump_ocr_reg(struct msdc_host *host, u32 resp) |
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341 | { |
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342 | if (resp & (1 << 7)) |
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343 | N_MSG(RSP, "[OCR] Low Voltage Range"); |
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344 | if (resp & (1 << 15)) |
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345 | N_MSG(RSP, "[OCR] 2.7-2.8 volt"); |
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346 | if (resp & (1 << 16)) |
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347 | N_MSG(RSP, "[OCR] 2.8-2.9 volt"); |
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348 | if (resp & (1 << 17)) |
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349 | N_MSG(RSP, "[OCR] 2.9-3.0 volt"); |
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350 | if (resp & (1 << 18)) |
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351 | N_MSG(RSP, "[OCR] 3.0-3.1 volt"); |
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352 | if (resp & (1 << 19)) |
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353 | N_MSG(RSP, "[OCR] 3.1-3.2 volt"); |
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354 | if (resp & (1 << 20)) |
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355 | N_MSG(RSP, "[OCR] 3.2-3.3 volt"); |
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356 | if (resp & (1 << 21)) |
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357 | N_MSG(RSP, "[OCR] 3.3-3.4 volt"); |
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358 | if (resp & (1 << 22)) |
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359 | N_MSG(RSP, "[OCR] 3.4-3.5 volt"); |
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360 | if (resp & (1 << 23)) |
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361 | N_MSG(RSP, "[OCR] 3.5-3.6 volt"); |
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362 | if (resp & (1 << 24)) |
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363 | N_MSG(RSP, "[OCR] Switching to 1.8V Accepted (S18A)"); |
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364 | if (resp & (1 << 30)) |
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365 | N_MSG(RSP, "[OCR] Card Capacity Status (CCS)"); |
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366 | if (resp & (1 << 31)) |
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367 | N_MSG(RSP, "[OCR] Card Power Up Status (Idle)"); |
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368 | else |
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369 | N_MSG(RSP, "[OCR] Card Power Up Status (Busy)"); |
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370 | } |
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371 | |||
372 | static void msdc_dump_rca_resp(struct msdc_host *host, u32 resp) |
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373 | { |
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374 | u32 status = (((resp >> 15) & 0x1) << 23) | |
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375 | (((resp >> 14) & 0x1) << 22) | |
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376 | (((resp >> 13) & 0x1) << 19) | |
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377 | (resp & 0x1fff); |
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378 | |||
379 | N_MSG(RSP, "[RCA] 0x%.4x", resp >> 16); |
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380 | msdc_dump_card_status(host, status); |
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381 | } |
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382 | |||
383 | static void msdc_dump_io_resp(struct msdc_host *host, u32 resp) |
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384 | { |
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385 | u32 flags = (resp >> 8) & 0xFF; |
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386 | #if 0 |
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387 | char *state[] = {"DIS", "CMD", "TRN", "RFU"}; |
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388 | #endif |
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389 | if (flags & (1 << 7)) |
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390 | N_MSG(RSP, "[IO] COM_CRC_ERR"); |
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391 | if (flags & (1 << 6)) |
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392 | N_MSG(RSP, "[IO] Illgal command"); |
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393 | if (flags & (1 << 3)) |
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394 | N_MSG(RSP, "[IO] Error"); |
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395 | if (flags & (1 << 2)) |
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396 | N_MSG(RSP, "[IO] RFU"); |
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397 | if (flags & (1 << 1)) |
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398 | N_MSG(RSP, "[IO] Function number error"); |
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399 | if (flags & (1 << 0)) |
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400 | N_MSG(RSP, "[IO] Out of range"); |
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401 | |||
402 | N_MSG(RSP, "[IO] State: %s, Data:0x%x", state[(resp >> 12) & 0x3], resp & 0xFF); |
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403 | } |
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404 | #endif |
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405 | |||
406 | static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) |
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407 | { |
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408 | void __iomem *base = host->base; |
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409 | u32 timeout, clk_ns; |
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410 | |||
411 | host->timeout_ns = ns; |
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412 | host->timeout_clks = clks; |
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413 | |||
414 | clk_ns = 1000000000UL / host->sclk; |
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415 | timeout = ns / clk_ns + clks; |
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416 | timeout = timeout >> 16; /* in 65536 sclk cycle unit */ |
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417 | timeout = timeout > 1 ? timeout - 1 : 0; |
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418 | timeout = timeout > 255 ? 255 : timeout; |
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419 | |||
420 | sdr_set_field(SDC_CFG, SDC_CFG_DTOC, timeout); |
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421 | |||
422 | N_MSG(OPS, "Set read data timeout: %dns %dclks -> %d x 65536 cycles", |
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423 | ns, clks, timeout + 1); |
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424 | } |
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425 | |||
426 | static void msdc_tasklet_card(struct work_struct *work) |
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427 | { |
||
428 | struct msdc_host *host = (struct msdc_host *)container_of(work, |
||
429 | struct msdc_host, card_delaywork.work); |
||
430 | void __iomem *base = host->base; |
||
431 | u32 inserted; |
||
432 | u32 status = 0; |
||
433 | //u32 change = 0; |
||
434 | |||
435 | spin_lock(&host->lock); |
||
436 | |||
437 | status = sdr_read32(MSDC_PS); |
||
438 | if (cd_active_low) |
||
439 | inserted = (status & MSDC_PS_CDSTS) ? 0 : 1; |
||
440 | else |
||
441 | inserted = (status & MSDC_PS_CDSTS) ? 1 : 0; |
||
442 | |||
443 | #if 0 |
||
444 | change = host->card_inserted ^ inserted; |
||
445 | host->card_inserted = inserted; |
||
446 | |||
447 | if (change && !host->suspend) { |
||
448 | if (inserted) |
||
449 | host->mmc->f_max = HOST_MAX_MCLK; // work around |
||
450 | mmc_detect_change(host->mmc, msecs_to_jiffies(20)); |
||
451 | } |
||
452 | #else /* Make sure: handle the last interrupt */ |
||
453 | host->card_inserted = inserted; |
||
454 | |||
455 | if (!host->suspend) { |
||
456 | host->mmc->f_max = HOST_MAX_MCLK; |
||
457 | mmc_detect_change(host->mmc, msecs_to_jiffies(20)); |
||
458 | } |
||
459 | |||
460 | IRQ_MSG("card found<%s>", inserted ? "inserted" : "removed"); |
||
461 | #endif |
||
462 | |||
463 | spin_unlock(&host->lock); |
||
464 | } |
||
465 | |||
466 | #if 0 /* --- by chhung */ |
||
467 | /* For E2 only */ |
||
468 | static u8 clk_src_bit[4] = { |
||
469 | 0, 3, 5, 7 |
||
470 | }; |
||
471 | |||
472 | static void msdc_select_clksrc(struct msdc_host *host, unsigned char clksrc) |
||
473 | { |
||
474 | u32 val; |
||
475 | void __iomem *base = host->base; |
||
476 | |||
477 | BUG_ON(clksrc > 3); |
||
478 | INIT_MSG("set clock source to <%d>", clksrc); |
||
479 | |||
480 | val = sdr_read32(MSDC_CLKSRC_REG); |
||
481 | if (sdr_read32(MSDC_ECO_VER) >= 4) { |
||
482 | val &= ~(0x3 << clk_src_bit[host->id]); |
||
483 | val |= clksrc << clk_src_bit[host->id]; |
||
484 | } else { |
||
485 | val &= ~0x3; val |= clksrc; |
||
486 | } |
||
487 | sdr_write32(MSDC_CLKSRC_REG, val); |
||
488 | |||
489 | host->hclk = hclks[clksrc]; |
||
490 | host->hw->clk_src = clksrc; |
||
491 | } |
||
492 | #endif /* end of --- */ |
||
493 | |||
494 | static void msdc_set_mclk(struct msdc_host *host, int ddr, unsigned int hz) |
||
495 | { |
||
496 | //struct msdc_hw *hw = host->hw; |
||
497 | void __iomem *base = host->base; |
||
498 | u32 mode; |
||
499 | u32 flags; |
||
500 | u32 div; |
||
501 | u32 sclk; |
||
502 | u32 hclk = host->hclk; |
||
503 | //u8 clksrc = hw->clk_src; |
||
504 | |||
505 | if (!hz) { // set mmc system clock to 0 ? |
||
506 | //ERR_MSG("set mclk to 0!!!"); |
||
507 | msdc_reset_hw(host); |
||
508 | return; |
||
509 | } |
||
510 | |||
511 | msdc_irq_save(flags); |
||
512 | |||
513 | if (ddr) { |
||
514 | mode = 0x2; /* ddr mode and use divisor */ |
||
515 | if (hz >= (hclk >> 2)) { |
||
516 | div = 1; /* mean div = 1/4 */ |
||
517 | sclk = hclk >> 2; /* sclk = clk / 4 */ |
||
518 | } else { |
||
519 | div = (hclk + ((hz << 2) - 1)) / (hz << 2); |
||
520 | sclk = (hclk >> 2) / div; |
||
521 | } |
||
522 | } else if (hz >= hclk) { /* bug fix */ |
||
523 | mode = 0x1; /* no divisor and divisor is ignored */ |
||
524 | div = 0; |
||
525 | sclk = hclk; |
||
526 | } else { |
||
527 | mode = 0x0; /* use divisor */ |
||
528 | if (hz >= (hclk >> 1)) { |
||
529 | div = 0; /* mean div = 1/2 */ |
||
530 | sclk = hclk >> 1; /* sclk = clk / 2 */ |
||
531 | } else { |
||
532 | div = (hclk + ((hz << 2) - 1)) / (hz << 2); |
||
533 | sclk = (hclk >> 2) / div; |
||
534 | } |
||
535 | } |
||
536 | |||
537 | /* set clock mode and divisor */ |
||
538 | sdr_set_field(MSDC_CFG, MSDC_CFG_CKMOD, mode); |
||
539 | sdr_set_field(MSDC_CFG, MSDC_CFG_CKDIV, div); |
||
540 | |||
541 | /* wait clock stable */ |
||
542 | while (!(sdr_read32(MSDC_CFG) & MSDC_CFG_CKSTB)) |
||
543 | cpu_relax(); |
||
544 | |||
545 | host->sclk = sclk; |
||
546 | host->mclk = hz; |
||
547 | msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); // need? |
||
548 | |||
549 | INIT_MSG("================"); |
||
550 | INIT_MSG("!!! Set<%dKHz> Source<%dKHz> -> sclk<%dKHz>", hz / 1000, hclk / 1000, sclk / 1000); |
||
551 | INIT_MSG("================"); |
||
552 | |||
553 | msdc_irq_restore(flags); |
||
554 | } |
||
555 | |||
556 | /* Fix me. when need to abort */ |
||
557 | static void msdc_abort_data(struct msdc_host *host) |
||
558 | { |
||
559 | void __iomem *base = host->base; |
||
560 | struct mmc_command *stop = host->mrq->stop; |
||
561 | |||
562 | ERR_MSG("Need to Abort."); |
||
563 | |||
564 | msdc_reset_hw(host); |
||
565 | msdc_clr_fifo(); |
||
566 | msdc_clr_int(); |
||
567 | |||
568 | // need to check FIFO count 0 ? |
||
569 | |||
570 | if (stop) { /* try to stop, but may not success */ |
||
571 | ERR_MSG("stop when abort CMD<%d>", stop->opcode); |
||
572 | (void)msdc_do_command(host, stop, 0, CMD_TIMEOUT); |
||
573 | } |
||
574 | |||
575 | //if (host->mclk >= 25000000) { |
||
576 | // msdc_set_mclk(host, 0, host->mclk >> 1); |
||
577 | //} |
||
578 | } |
||
579 | |||
580 | #if 0 /* --- by chhung */ |
||
581 | static void msdc_pin_config(struct msdc_host *host, int mode) |
||
582 | { |
||
583 | struct msdc_hw *hw = host->hw; |
||
584 | void __iomem *base = host->base; |
||
585 | int pull = (mode == MSDC_PIN_PULL_UP) ? GPIO_PULL_UP : GPIO_PULL_DOWN; |
||
586 | |||
587 | /* Config WP pin */ |
||
588 | if (hw->flags & MSDC_WP_PIN_EN) { |
||
589 | if (hw->config_gpio_pin) /* NULL */ |
||
590 | hw->config_gpio_pin(MSDC_WP_PIN, pull); |
||
591 | } |
||
592 | |||
593 | switch (mode) { |
||
594 | case MSDC_PIN_PULL_UP: |
||
595 | //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 1); /* Check & FIXME */ |
||
596 | //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 0); /* Check & FIXME */ |
||
597 | sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 1); |
||
598 | sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 0); |
||
599 | sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 1); |
||
600 | sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 0); |
||
601 | break; |
||
602 | case MSDC_PIN_PULL_DOWN: |
||
603 | //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 0); /* Check & FIXME */ |
||
604 | //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 1); /* Check & FIXME */ |
||
605 | sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 0); |
||
606 | sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 1); |
||
607 | sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 0); |
||
608 | sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 1); |
||
609 | break; |
||
610 | case MSDC_PIN_PULL_NONE: |
||
611 | default: |
||
612 | //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 0); /* Check & FIXME */ |
||
613 | //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 0); /* Check & FIXME */ |
||
614 | sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 0); |
||
615 | sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 0); |
||
616 | sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 0); |
||
617 | sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 0); |
||
618 | break; |
||
619 | } |
||
620 | |||
621 | N_MSG(CFG, "Pins mode(%d), down(%d), up(%d)", |
||
622 | mode, MSDC_PIN_PULL_DOWN, MSDC_PIN_PULL_UP); |
||
623 | } |
||
624 | |||
625 | void msdc_pin_reset(struct msdc_host *host, int mode) |
||
626 | { |
||
627 | struct msdc_hw *hw = (struct msdc_hw *)host->hw; |
||
628 | void __iomem *base = host->base; |
||
629 | int pull = (mode == MSDC_PIN_PULL_UP) ? GPIO_PULL_UP : GPIO_PULL_DOWN; |
||
630 | |||
631 | /* Config reset pin */ |
||
632 | if (hw->flags & MSDC_RST_PIN_EN) { |
||
633 | if (hw->config_gpio_pin) /* NULL */ |
||
634 | hw->config_gpio_pin(MSDC_RST_PIN, pull); |
||
635 | |||
636 | if (mode == MSDC_PIN_PULL_UP) |
||
637 | sdr_clr_bits(EMMC_IOCON, EMMC_IOCON_BOOTRST); |
||
638 | else |
||
639 | sdr_set_bits(EMMC_IOCON, EMMC_IOCON_BOOTRST); |
||
640 | } |
||
641 | } |
||
642 | |||
643 | static void msdc_core_power(struct msdc_host *host, int on) |
||
644 | { |
||
645 | N_MSG(CFG, "Turn %s %s power (copower: %d -> %d)", |
||
646 | on ? "on" : "off", "core", host->core_power, on); |
||
647 | |||
648 | if (on && host->core_power == 0) { |
||
649 | msdc_vcore_on(host); |
||
650 | host->core_power = 1; |
||
651 | msleep(1); |
||
652 | } else if (!on && host->core_power == 1) { |
||
653 | msdc_vcore_off(host); |
||
654 | host->core_power = 0; |
||
655 | msleep(1); |
||
656 | } |
||
657 | } |
||
658 | |||
659 | static void msdc_host_power(struct msdc_host *host, int on) |
||
660 | { |
||
661 | N_MSG(CFG, "Turn %s %s power ", on ? "on" : "off", "host"); |
||
662 | |||
663 | if (on) { |
||
664 | //msdc_core_power(host, 1); // need do card detection. |
||
665 | msdc_pin_reset(host, MSDC_PIN_PULL_UP); |
||
666 | } else { |
||
667 | msdc_pin_reset(host, MSDC_PIN_PULL_DOWN); |
||
668 | //msdc_core_power(host, 0); |
||
669 | } |
||
670 | } |
||
671 | |||
672 | static void msdc_card_power(struct msdc_host *host, int on) |
||
673 | { |
||
674 | N_MSG(CFG, "Turn %s %s power ", on ? "on" : "off", "card"); |
||
675 | |||
676 | if (on) { |
||
677 | msdc_pin_config(host, MSDC_PIN_PULL_UP); |
||
678 | //msdc_vdd_on(host); // need todo card detection. |
||
679 | msleep(1); |
||
680 | } else { |
||
681 | //msdc_vdd_off(host); |
||
682 | msdc_pin_config(host, MSDC_PIN_PULL_DOWN); |
||
683 | msleep(1); |
||
684 | } |
||
685 | } |
||
686 | |||
687 | static void msdc_set_power_mode(struct msdc_host *host, u8 mode) |
||
688 | { |
||
689 | N_MSG(CFG, "Set power mode(%d)", mode); |
||
690 | |||
691 | if (host->power_mode == MMC_POWER_OFF && mode != MMC_POWER_OFF) { |
||
692 | msdc_host_power(host, 1); |
||
693 | msdc_card_power(host, 1); |
||
694 | } else if (host->power_mode != MMC_POWER_OFF && mode == MMC_POWER_OFF) { |
||
695 | msdc_card_power(host, 0); |
||
696 | msdc_host_power(host, 0); |
||
697 | } |
||
698 | host->power_mode = mode; |
||
699 | } |
||
700 | #endif /* end of --- */ |
||
701 | |||
702 | #ifdef CONFIG_PM |
||
703 | /* |
||
704 | register as callback function of WIFI(combo_sdio_register_pm) . |
||
705 | can called by msdc_drv_suspend/resume too. |
||
706 | */ |
||
707 | static void msdc_pm(pm_message_t state, void *data) |
||
708 | { |
||
709 | struct msdc_host *host = (struct msdc_host *)data; |
||
710 | int evt = state.event; |
||
711 | |||
712 | if (evt == PM_EVENT_USER_RESUME || evt == PM_EVENT_USER_SUSPEND) { |
||
713 | INIT_MSG("USR_%s: suspend<%d> power<%d>", |
||
714 | evt == PM_EVENT_USER_RESUME ? "EVENT_USER_RESUME" : "EVENT_USER_SUSPEND", |
||
715 | host->suspend, host->power_mode); |
||
716 | } |
||
717 | |||
718 | if (evt == PM_EVENT_SUSPEND || evt == PM_EVENT_USER_SUSPEND) { |
||
719 | if (host->suspend) /* already suspend */ /* default 0*/ |
||
720 | return; |
||
721 | |||
722 | /* for memory card. already power off by mmc */ |
||
723 | if (evt == PM_EVENT_SUSPEND && host->power_mode == MMC_POWER_OFF) |
||
724 | return; |
||
725 | |||
726 | host->suspend = 1; |
||
727 | host->pm_state = state; /* default PMSG_RESUME */ |
||
728 | |||
729 | } else if (evt == PM_EVENT_RESUME || evt == PM_EVENT_USER_RESUME) { |
||
730 | if (!host->suspend) { |
||
731 | //ERR_MSG("warning: already resume"); |
||
732 | return; |
||
733 | } |
||
734 | |||
735 | /* No PM resume when USR suspend */ |
||
736 | if (evt == PM_EVENT_RESUME && host->pm_state.event == PM_EVENT_USER_SUSPEND) { |
||
737 | ERR_MSG("PM Resume when in USR Suspend"); /* won't happen. */ |
||
738 | return; |
||
739 | } |
||
740 | |||
741 | host->suspend = 0; |
||
742 | host->pm_state = state; |
||
743 | |||
744 | } |
||
745 | } |
||
746 | #endif |
||
747 | |||
748 | /*--------------------------------------------------------------------------*/ |
||
749 | /* mmc_host_ops members */ |
||
750 | /*--------------------------------------------------------------------------*/ |
||
751 | static unsigned int msdc_command_start(struct msdc_host *host, |
||
752 | struct mmc_command *cmd, |
||
753 | int tune, /* not used */ |
||
754 | unsigned long timeout) |
||
755 | { |
||
756 | void __iomem *base = host->base; |
||
757 | u32 opcode = cmd->opcode; |
||
758 | u32 rawcmd; |
||
759 | u32 wints = MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO | |
||
760 | MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO | |
||
761 | MSDC_INT_ACMD19_DONE; |
||
762 | |||
763 | u32 resp; |
||
764 | unsigned long tmo; |
||
765 | |||
766 | /* Protocol layer does not provide response type, but our hardware needs |
||
767 | * to know exact type, not just size! |
||
768 | */ |
||
769 | if (opcode == MMC_SEND_OP_COND || opcode == SD_APP_OP_COND) { |
||
770 | resp = RESP_R3; |
||
771 | } else if (opcode == MMC_SET_RELATIVE_ADDR) { |
||
772 | resp = (mmc_cmd_type(cmd) == MMC_CMD_BCR) ? RESP_R6 : RESP_R1; |
||
773 | } else if (opcode == MMC_FAST_IO) { |
||
774 | resp = RESP_R4; |
||
775 | } else if (opcode == MMC_GO_IRQ_STATE) { |
||
776 | resp = RESP_R5; |
||
777 | } else if (opcode == MMC_SELECT_CARD) { |
||
778 | resp = (cmd->arg != 0) ? RESP_R1B : RESP_NONE; |
||
779 | } else if (opcode == SD_IO_RW_DIRECT || opcode == SD_IO_RW_EXTENDED) { |
||
780 | resp = RESP_R1; /* SDIO workaround. */ |
||
781 | } else if (opcode == SD_SEND_IF_COND && (mmc_cmd_type(cmd) == MMC_CMD_BCR)) { |
||
782 | resp = RESP_R1; |
||
783 | } else { |
||
784 | switch (mmc_resp_type(cmd)) { |
||
785 | case MMC_RSP_R1: |
||
786 | resp = RESP_R1; |
||
787 | break; |
||
788 | case MMC_RSP_R1B: |
||
789 | resp = RESP_R1B; |
||
790 | break; |
||
791 | case MMC_RSP_R2: |
||
792 | resp = RESP_R2; |
||
793 | break; |
||
794 | case MMC_RSP_R3: |
||
795 | resp = RESP_R3; |
||
796 | break; |
||
797 | case MMC_RSP_NONE: |
||
798 | default: |
||
799 | resp = RESP_NONE; |
||
800 | break; |
||
801 | } |
||
802 | } |
||
803 | |||
804 | cmd->error = 0; |
||
805 | /* rawcmd : |
||
806 | * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | |
||
807 | * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode |
||
808 | */ |
||
809 | rawcmd = opcode | msdc_rsp[resp] << 7 | host->blksz << 16; |
||
810 | |||
811 | if (opcode == MMC_READ_MULTIPLE_BLOCK) { |
||
812 | rawcmd |= (2 << 11); |
||
813 | } else if (opcode == MMC_READ_SINGLE_BLOCK) { |
||
814 | rawcmd |= (1 << 11); |
||
815 | } else if (opcode == MMC_WRITE_MULTIPLE_BLOCK) { |
||
816 | rawcmd |= ((2 << 11) | (1 << 13)); |
||
817 | } else if (opcode == MMC_WRITE_BLOCK) { |
||
818 | rawcmd |= ((1 << 11) | (1 << 13)); |
||
819 | } else if (opcode == SD_IO_RW_EXTENDED) { |
||
820 | if (cmd->data->flags & MMC_DATA_WRITE) |
||
821 | rawcmd |= (1 << 13); |
||
822 | if (cmd->data->blocks > 1) |
||
823 | rawcmd |= (2 << 11); |
||
824 | else |
||
825 | rawcmd |= (1 << 11); |
||
826 | } else if (opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int)-1) { |
||
827 | rawcmd |= (1 << 14); |
||
828 | } else if ((opcode == SD_APP_SEND_SCR) || |
||
829 | (opcode == SD_APP_SEND_NUM_WR_BLKS) || |
||
830 | (opcode == SD_SWITCH && (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) || |
||
831 | (opcode == SD_APP_SD_STATUS && (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) || |
||
832 | (opcode == MMC_SEND_EXT_CSD && (mmc_cmd_type(cmd) == MMC_CMD_ADTC))) { |
||
833 | rawcmd |= (1 << 11); |
||
834 | } else if (opcode == MMC_STOP_TRANSMISSION) { |
||
835 | rawcmd |= (1 << 14); |
||
836 | rawcmd &= ~(0x0FFF << 16); |
||
837 | } |
||
838 | |||
839 | N_MSG(CMD, "CMD<%d><0x%.8x> Arg<0x%.8x>", opcode, rawcmd, cmd->arg); |
||
840 | |||
841 | tmo = jiffies + timeout; |
||
842 | |||
843 | if (opcode == MMC_SEND_STATUS) { |
||
844 | for (;;) { |
||
845 | if (!sdc_is_cmd_busy()) |
||
846 | break; |
||
847 | |||
848 | if (time_after(jiffies, tmo)) { |
||
849 | ERR_MSG("XXX cmd_busy timeout: before CMD<%d>", opcode); |
||
850 | cmd->error = -ETIMEDOUT; |
||
851 | msdc_reset_hw(host); |
||
852 | goto end; |
||
853 | } |
||
854 | } |
||
855 | } else { |
||
856 | for (;;) { |
||
857 | if (!sdc_is_busy()) |
||
858 | break; |
||
859 | if (time_after(jiffies, tmo)) { |
||
860 | ERR_MSG("XXX sdc_busy timeout: before CMD<%d>", opcode); |
||
861 | cmd->error = -ETIMEDOUT; |
||
862 | msdc_reset_hw(host); |
||
863 | goto end; |
||
864 | } |
||
865 | } |
||
866 | } |
||
867 | |||
868 | //BUG_ON(in_interrupt()); |
||
869 | host->cmd = cmd; |
||
870 | host->cmd_rsp = resp; |
||
871 | |||
872 | init_completion(&host->cmd_done); |
||
873 | |||
874 | sdr_set_bits(MSDC_INTEN, wints); |
||
875 | sdc_send_cmd(rawcmd, cmd->arg); |
||
876 | |||
877 | end: |
||
878 | return cmd->error; |
||
879 | } |
||
880 | |||
881 | static unsigned int msdc_command_resp(struct msdc_host *host, |
||
882 | struct mmc_command *cmd, |
||
883 | int tune, |
||
884 | unsigned long timeout) |
||
885 | __must_hold(&host->lock) |
||
886 | { |
||
887 | void __iomem *base = host->base; |
||
888 | u32 opcode = cmd->opcode; |
||
889 | //u32 rawcmd; |
||
890 | u32 resp; |
||
891 | u32 wints = MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO | |
||
892 | MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO | |
||
893 | MSDC_INT_ACMD19_DONE; |
||
894 | |||
895 | resp = host->cmd_rsp; |
||
896 | |||
897 | BUG_ON(in_interrupt()); |
||
898 | //init_completion(&host->cmd_done); |
||
899 | //sdr_set_bits(MSDC_INTEN, wints); |
||
900 | |||
901 | spin_unlock(&host->lock); |
||
902 | if (!wait_for_completion_timeout(&host->cmd_done, 10 * timeout)) { |
||
903 | ERR_MSG("XXX CMD<%d> wait_for_completion timeout ARG<0x%.8x>", opcode, cmd->arg); |
||
904 | cmd->error = -ETIMEDOUT; |
||
905 | msdc_reset_hw(host); |
||
906 | } |
||
907 | spin_lock(&host->lock); |
||
908 | |||
909 | sdr_clr_bits(MSDC_INTEN, wints); |
||
910 | host->cmd = NULL; |
||
911 | |||
912 | //end: |
||
913 | #ifdef MT6575_SD_DEBUG |
||
914 | switch (resp) { |
||
915 | case RESP_NONE: |
||
916 | N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)", opcode, cmd->error, resp); |
||
917 | break; |
||
918 | case RESP_R2: |
||
919 | N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)= %.8x %.8x %.8x %.8x", |
||
920 | opcode, cmd->error, resp, cmd->resp[0], cmd->resp[1], |
||
921 | cmd->resp[2], cmd->resp[3]); |
||
922 | break; |
||
923 | default: /* Response types 1, 3, 4, 5, 6, 7(1b) */ |
||
924 | N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)= 0x%.8x", |
||
925 | opcode, cmd->error, resp, cmd->resp[0]); |
||
926 | if (cmd->error == 0) { |
||
927 | switch (resp) { |
||
928 | case RESP_R1: |
||
929 | case RESP_R1B: |
||
930 | msdc_dump_card_status(host, cmd->resp[0]); |
||
931 | break; |
||
932 | case RESP_R3: |
||
933 | msdc_dump_ocr_reg(host, cmd->resp[0]); |
||
934 | break; |
||
935 | case RESP_R5: |
||
936 | msdc_dump_io_resp(host, cmd->resp[0]); |
||
937 | break; |
||
938 | case RESP_R6: |
||
939 | msdc_dump_rca_resp(host, cmd->resp[0]); |
||
940 | break; |
||
941 | } |
||
942 | } |
||
943 | break; |
||
944 | } |
||
945 | #endif |
||
946 | |||
947 | /* do we need to save card's RCA when SD_SEND_RELATIVE_ADDR */ |
||
948 | |||
949 | if (!tune) |
||
950 | return cmd->error; |
||
951 | |||
952 | /* memory card CRC */ |
||
953 | if (host->hw->flags & MSDC_REMOVABLE && cmd->error == -EIO) { |
||
954 | if (sdr_read32(SDC_CMD) & 0x1800) { /* check if has data phase */ |
||
955 | msdc_abort_data(host); |
||
956 | } else { |
||
957 | /* do basic: reset*/ |
||
958 | msdc_reset_hw(host); |
||
959 | msdc_clr_fifo(); |
||
960 | msdc_clr_int(); |
||
961 | } |
||
962 | cmd->error = msdc_tune_cmdrsp(host, cmd); |
||
963 | } |
||
964 | |||
965 | // check DAT0 |
||
966 | /* if (resp == RESP_R1B) { |
||
967 | while ((sdr_read32(MSDC_PS) & 0x10000) != 0x10000); |
||
968 | } */ |
||
969 | /* CMD12 Error Handle */ |
||
970 | |||
971 | return cmd->error; |
||
972 | } |
||
973 | |||
974 | static unsigned int msdc_do_command(struct msdc_host *host, |
||
975 | struct mmc_command *cmd, |
||
976 | int tune, |
||
977 | unsigned long timeout) |
||
978 | { |
||
979 | if (msdc_command_start(host, cmd, tune, timeout)) |
||
980 | goto end; |
||
981 | |||
982 | if (msdc_command_resp(host, cmd, tune, timeout)) |
||
983 | goto end; |
||
984 | |||
985 | end: |
||
986 | |||
987 | N_MSG(CMD, " return<%d> resp<0x%.8x>", cmd->error, cmd->resp[0]); |
||
988 | return cmd->error; |
||
989 | } |
||
990 | |||
991 | #if 0 /* --- by chhung */ |
||
992 | // DMA resume / start / stop |
||
993 | static void msdc_dma_resume(struct msdc_host *host) |
||
994 | { |
||
995 | void __iomem *base = host->base; |
||
996 | |||
997 | sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_RESUME, 1); |
||
998 | |||
999 | N_MSG(DMA, "DMA resume"); |
||
1000 | } |
||
1001 | #endif /* end of --- */ |
||
1002 | |||
1003 | static void msdc_dma_start(struct msdc_host *host) |
||
1004 | { |
||
1005 | void __iomem *base = host->base; |
||
1006 | u32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR; |
||
1007 | |||
1008 | sdr_set_bits(MSDC_INTEN, wints); |
||
1009 | //dsb(); /* --- by chhung */ |
||
1010 | sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); |
||
1011 | |||
1012 | N_MSG(DMA, "DMA start"); |
||
1013 | } |
||
1014 | |||
1015 | static void msdc_dma_stop(struct msdc_host *host) |
||
1016 | { |
||
1017 | void __iomem *base = host->base; |
||
1018 | //u32 retries=500; |
||
1019 | u32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR; |
||
1020 | |||
1021 | N_MSG(DMA, "DMA status: 0x%.8x", sdr_read32(MSDC_DMA_CFG)); |
||
1022 | //while (sdr_read32(MSDC_DMA_CFG) & MSDC_DMA_CFG_STS); |
||
1023 | |||
1024 | sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1); |
||
1025 | while (sdr_read32(MSDC_DMA_CFG) & MSDC_DMA_CFG_STS) |
||
1026 | ; |
||
1027 | |||
1028 | //dsb(); /* --- by chhung */ |
||
1029 | sdr_clr_bits(MSDC_INTEN, wints); /* Not just xfer_comp */ |
||
1030 | |||
1031 | N_MSG(DMA, "DMA stop"); |
||
1032 | } |
||
1033 | |||
1034 | /* calc checksum */ |
||
1035 | static u8 msdc_dma_calcs(u8 *buf, u32 len) |
||
1036 | { |
||
1037 | u32 i, sum = 0; |
||
1038 | |||
1039 | for (i = 0; i < len; i++) |
||
1040 | sum += buf[i]; |
||
1041 | return 0xFF - (u8)sum; |
||
1042 | } |
||
1043 | |||
1044 | /* gpd bd setup + dma registers */ |
||
1045 | static void msdc_dma_config(struct msdc_host *host, struct msdc_dma *dma) |
||
1046 | { |
||
1047 | void __iomem *base = host->base; |
||
1048 | //u32 i, j, num, bdlen, arg, xfersz; |
||
1049 | u32 j, num; |
||
1050 | struct scatterlist *sg; |
||
1051 | struct gpd *gpd; |
||
1052 | struct bd *bd; |
||
1053 | |||
1054 | switch (dma->mode) { |
||
1055 | case MSDC_MODE_DMA_BASIC: |
||
1056 | BUG_ON(host->xfer_size > 65535); |
||
1057 | BUG_ON(dma->sglen != 1); |
||
1058 | sdr_write32(MSDC_DMA_SA, PHYSADDR(sg_dma_address(sg))); |
||
1059 | sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_LASTBUF, 1); |
||
1060 | //#if defined (CONFIG_RALINK_MT7620) |
||
1061 | if (ralink_soc == MT762X_SOC_MT7620A) |
||
1062 | sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_XFERSZ, sg_dma_len(sg)); |
||
1063 | //#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628) |
||
1064 | else |
||
1065 | sdr_write32((void __iomem *)(RALINK_MSDC_BASE + 0xa8), sg_dma_len(sg)); |
||
1066 | //#endif |
||
1067 | sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ, |
||
1068 | MSDC_BRUST_64B); |
||
1069 | sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 0); |
||
1070 | break; |
||
1071 | case MSDC_MODE_DMA_DESC: |
||
1072 | |||
1073 | /* calculate the required number of gpd */ |
||
1074 | num = (dma->sglen + MAX_BD_PER_GPD - 1) / MAX_BD_PER_GPD; |
||
1075 | BUG_ON(num != 1); |
||
1076 | |||
1077 | gpd = dma->gpd; |
||
1078 | bd = dma->bd; |
||
1079 | |||
1080 | /* modify gpd*/ |
||
1081 | //gpd->intr = 0; |
||
1082 | gpd->hwo = 1; /* hw will clear it */ |
||
1083 | gpd->bdp = 1; |
||
1084 | gpd->chksum = 0; /* need to clear first. */ |
||
1085 | gpd->chksum = msdc_dma_calcs((u8 *)gpd, 16); |
||
1086 | |||
1087 | /* modify bd*/ |
||
1088 | for_each_sg(dma->sg, sg, dma->sglen, j) { |
||
1089 | bd[j].blkpad = 0; |
||
1090 | bd[j].dwpad = 0; |
||
1091 | bd[j].ptr = (void *)sg_dma_address(sg); |
||
1092 | bd[j].buflen = sg_dma_len(sg); |
||
1093 | |||
1094 | if (j == dma->sglen - 1) |
||
1095 | bd[j].eol = 1; /* the last bd */ |
||
1096 | else |
||
1097 | bd[j].eol = 0; |
||
1098 | |||
1099 | bd[j].chksum = 0; /* checksume need to clear first */ |
||
1100 | bd[j].chksum = msdc_dma_calcs((u8 *)(&bd[j]), 16); |
||
1101 | } |
||
1102 | |||
1103 | sdr_set_field(MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); |
||
1104 | sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ, |
||
1105 | MSDC_BRUST_64B); |
||
1106 | sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 1); |
||
1107 | |||
1108 | sdr_write32(MSDC_DMA_SA, PHYSADDR((u32)dma->gpd_addr)); |
||
1109 | break; |
||
1110 | |||
1111 | default: |
||
1112 | break; |
||
1113 | } |
||
1114 | |||
1115 | N_MSG(DMA, "DMA_CTRL = 0x%x", sdr_read32(MSDC_DMA_CTRL)); |
||
1116 | N_MSG(DMA, "DMA_CFG = 0x%x", sdr_read32(MSDC_DMA_CFG)); |
||
1117 | N_MSG(DMA, "DMA_SA = 0x%x", sdr_read32(MSDC_DMA_SA)); |
||
1118 | |||
1119 | } |
||
1120 | |||
1121 | static void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, |
||
1122 | struct scatterlist *sg, unsigned int sglen) |
||
1123 | { |
||
1124 | BUG_ON(sglen > MAX_BD_NUM); /* not support currently */ |
||
1125 | |||
1126 | dma->sg = sg; |
||
1127 | dma->sglen = sglen; |
||
1128 | |||
1129 | dma->mode = MSDC_MODE_DMA_DESC; |
||
1130 | |||
1131 | N_MSG(DMA, "DMA mode<%d> sglen<%d> xfersz<%d>", dma->mode, dma->sglen, |
||
1132 | host->xfer_size); |
||
1133 | |||
1134 | msdc_dma_config(host, dma); |
||
1135 | } |
||
1136 | |||
1137 | static int msdc_do_request(struct mmc_host *mmc, struct mmc_request *mrq) |
||
1138 | __must_hold(&host->lock) |
||
1139 | { |
||
1140 | struct msdc_host *host = mmc_priv(mmc); |
||
1141 | struct mmc_command *cmd; |
||
1142 | struct mmc_data *data; |
||
1143 | void __iomem *base = host->base; |
||
1144 | //u32 intsts = 0; |
||
1145 | int read = 1, send_type = 0; |
||
1146 | |||
1147 | #define SND_DAT 0 |
||
1148 | #define SND_CMD 1 |
||
1149 | |||
1150 | BUG_ON(mmc == NULL); |
||
1151 | BUG_ON(mrq == NULL); |
||
1152 | |||
1153 | host->error = 0; |
||
1154 | |||
1155 | cmd = mrq->cmd; |
||
1156 | data = mrq->cmd->data; |
||
1157 | |||
1158 | #if 0 /* --- by chhung */ |
||
1159 | //if(host->id ==1){ |
||
1160 | N_MSG(OPS, "enable clock!"); |
||
1161 | msdc_ungate_clock(host->id); |
||
1162 | //} |
||
1163 | #endif /* end of --- */ |
||
1164 | |||
1165 | if (!data) { |
||
1166 | send_type = SND_CMD; |
||
1167 | if (msdc_do_command(host, cmd, 1, CMD_TIMEOUT) != 0) |
||
1168 | goto done; |
||
1169 | } else { |
||
1170 | BUG_ON(data->blksz > HOST_MAX_BLKSZ); |
||
1171 | send_type = SND_DAT; |
||
1172 | |||
1173 | data->error = 0; |
||
1174 | read = data->flags & MMC_DATA_READ ? 1 : 0; |
||
1175 | host->data = data; |
||
1176 | host->xfer_size = data->blocks * data->blksz; |
||
1177 | host->blksz = data->blksz; |
||
1178 | |||
1179 | if (read) { |
||
1180 | if ((host->timeout_ns != data->timeout_ns) || |
||
1181 | (host->timeout_clks != data->timeout_clks)) { |
||
1182 | msdc_set_timeout(host, data->timeout_ns, data->timeout_clks); |
||
1183 | } |
||
1184 | } |
||
1185 | |||
1186 | sdr_write32(SDC_BLK_NUM, data->blocks); |
||
1187 | //msdc_clr_fifo(); /* no need */ |
||
1188 | |||
1189 | msdc_dma_on(); /* enable DMA mode first!! */ |
||
1190 | init_completion(&host->xfer_done); |
||
1191 | |||
1192 | /* start the command first*/ |
||
1193 | if (msdc_command_start(host, cmd, 1, CMD_TIMEOUT) != 0) |
||
1194 | goto done; |
||
1195 | |||
1196 | data->sg_count = dma_map_sg(mmc_dev(mmc), data->sg, |
||
1197 | data->sg_len, |
||
1198 | mmc_get_dma_dir(data)); |
||
1199 | msdc_dma_setup(host, &host->dma, data->sg, |
||
1200 | data->sg_count); |
||
1201 | |||
1202 | /* then wait command done */ |
||
1203 | if (msdc_command_resp(host, cmd, 1, CMD_TIMEOUT) != 0) |
||
1204 | goto done; |
||
1205 | |||
1206 | /* for read, the data coming too fast, then CRC error |
||
1207 | start DMA no business with CRC. */ |
||
1208 | //init_completion(&host->xfer_done); |
||
1209 | msdc_dma_start(host); |
||
1210 | |||
1211 | spin_unlock(&host->lock); |
||
1212 | if (!wait_for_completion_timeout(&host->xfer_done, DAT_TIMEOUT)) { |
||
1213 | ERR_MSG("XXX CMD<%d> wait xfer_done<%d> timeout!!", cmd->opcode, data->blocks * data->blksz); |
||
1214 | ERR_MSG(" DMA_SA = 0x%x", sdr_read32(MSDC_DMA_SA)); |
||
1215 | ERR_MSG(" DMA_CA = 0x%x", sdr_read32(MSDC_DMA_CA)); |
||
1216 | ERR_MSG(" DMA_CTRL = 0x%x", sdr_read32(MSDC_DMA_CTRL)); |
||
1217 | ERR_MSG(" DMA_CFG = 0x%x", sdr_read32(MSDC_DMA_CFG)); |
||
1218 | data->error = -ETIMEDOUT; |
||
1219 | |||
1220 | msdc_reset_hw(host); |
||
1221 | msdc_clr_fifo(); |
||
1222 | msdc_clr_int(); |
||
1223 | } |
||
1224 | spin_lock(&host->lock); |
||
1225 | msdc_dma_stop(host); |
||
1226 | |||
1227 | /* Last: stop transfer */ |
||
1228 | if (data->stop) { |
||
1229 | if (msdc_do_command(host, data->stop, 0, CMD_TIMEOUT) != 0) |
||
1230 | goto done; |
||
1231 | } |
||
1232 | } |
||
1233 | |||
1234 | done: |
||
1235 | if (data != NULL) { |
||
1236 | host->data = NULL; |
||
1237 | dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, |
||
1238 | mmc_get_dma_dir(data)); |
||
1239 | host->blksz = 0; |
||
1240 | |||
1241 | #if 0 // don't stop twice! |
||
1242 | if (host->hw->flags & MSDC_REMOVABLE && data->error) { |
||
1243 | msdc_abort_data(host); |
||
1244 | /* reset in IRQ, stop command has issued. -> No need */ |
||
1245 | } |
||
1246 | #endif |
||
1247 | |||
1248 | N_MSG(OPS, "CMD<%d> data<%s %s> blksz<%d> block<%d> error<%d>", cmd->opcode, (dma ? "dma" : "pio"), |
||
1249 | (read ? "read " : "write"), data->blksz, data->blocks, data->error); |
||
1250 | } |
||
1251 | |||
1252 | #if 0 /* --- by chhung */ |
||
1253 | #if 1 |
||
1254 | //if(host->id==1) { |
||
1255 | if (send_type == SND_CMD) { |
||
1256 | if (cmd->opcode == MMC_SEND_STATUS) { |
||
1257 | if ((cmd->resp[0] & CARD_READY_FOR_DATA) || (CARD_CURRENT_STATE(cmd->resp[0]) != 7)) { |
||
1258 | N_MSG(OPS, "disable clock, CMD13 IDLE"); |
||
1259 | msdc_gate_clock(host->id); |
||
1260 | } |
||
1261 | } else { |
||
1262 | N_MSG(OPS, "disable clock, CMD<%d>", cmd->opcode); |
||
1263 | msdc_gate_clock(host->id); |
||
1264 | } |
||
1265 | } else { |
||
1266 | if (read) { |
||
1267 | N_MSG(OPS, "disable clock!!! Read CMD<%d>", cmd->opcode); |
||
1268 | msdc_gate_clock(host->id); |
||
1269 | } |
||
1270 | } |
||
1271 | //} |
||
1272 | #else |
||
1273 | msdc_gate_clock(host->id); |
||
1274 | #endif |
||
1275 | #endif /* end of --- */ |
||
1276 | |||
1277 | if (mrq->cmd->error) |
||
1278 | host->error = 0x001; |
||
1279 | if (mrq->data && mrq->data->error) |
||
1280 | host->error |= 0x010; |
||
1281 | if (mrq->stop && mrq->stop->error) |
||
1282 | host->error |= 0x100; |
||
1283 | |||
1284 | //if (host->error) ERR_MSG("host->error<%d>", host->error); |
||
1285 | |||
1286 | return host->error; |
||
1287 | } |
||
1288 | |||
1289 | static int msdc_app_cmd(struct mmc_host *mmc, struct msdc_host *host) |
||
1290 | { |
||
1291 | struct mmc_command cmd; |
||
1292 | struct mmc_request mrq; |
||
1293 | u32 err; |
||
1294 | |||
1295 | memset(&cmd, 0, sizeof(struct mmc_command)); |
||
1296 | cmd.opcode = MMC_APP_CMD; |
||
1297 | #if 0 /* bug: we meet mmc->card is null when ACMD6 */ |
||
1298 | cmd.arg = mmc->card->rca << 16; |
||
1299 | #else |
||
1300 | cmd.arg = host->app_cmd_arg; |
||
1301 | #endif |
||
1302 | cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_AC; |
||
1303 | |||
1304 | memset(&mrq, 0, sizeof(struct mmc_request)); |
||
1305 | mrq.cmd = &cmd; cmd.mrq = &mrq; |
||
1306 | cmd.data = NULL; |
||
1307 | |||
1308 | err = msdc_do_command(host, &cmd, 0, CMD_TIMEOUT); |
||
1309 | return err; |
||
1310 | } |
||
1311 | |||
1312 | static int msdc_tune_cmdrsp(struct msdc_host *host, struct mmc_command *cmd) |
||
1313 | { |
||
1314 | int result = -1; |
||
1315 | void __iomem *base = host->base; |
||
1316 | u32 rsmpl, cur_rsmpl, orig_rsmpl; |
||
1317 | u32 rrdly, cur_rrdly = 0xffffffff, orig_rrdly; |
||
1318 | u32 skip = 1; |
||
1319 | |||
1320 | /* ==== don't support 3.0 now ==== |
||
1321 | 1: R_SMPL[1] |
||
1322 | 2: PAD_CMD_RESP_RXDLY[26:22] |
||
1323 | ==========================*/ |
||
1324 | |||
1325 | // save the previous tune result |
||
1326 | sdr_get_field(MSDC_IOCON, MSDC_IOCON_RSPL, &orig_rsmpl); |
||
1327 | sdr_get_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, &orig_rrdly); |
||
1328 | |||
1329 | rrdly = 0; |
||
1330 | do { |
||
1331 | for (rsmpl = 0; rsmpl < 2; rsmpl++) { |
||
1332 | /* Lv1: R_SMPL[1] */ |
||
1333 | cur_rsmpl = (orig_rsmpl + rsmpl) % 2; |
||
1334 | if (skip == 1) { |
||
1335 | skip = 0; |
||
1336 | continue; |
||
1337 | } |
||
1338 | sdr_set_field(MSDC_IOCON, MSDC_IOCON_RSPL, cur_rsmpl); |
||
1339 | |||
1340 | if (host->app_cmd) { |
||
1341 | result = msdc_app_cmd(host->mmc, host); |
||
1342 | if (result) { |
||
1343 | ERR_MSG("TUNE_CMD app_cmd<%d> failed: RESP_RXDLY<%d>,R_SMPL<%d>", |
||
1344 | host->mrq->cmd->opcode, cur_rrdly, cur_rsmpl); |
||
1345 | continue; |
||
1346 | } |
||
1347 | } |
||
1348 | result = msdc_do_command(host, cmd, 0, CMD_TIMEOUT); // not tune. |
||
1349 | ERR_MSG("TUNE_CMD<%d> %s PAD_CMD_RESP_RXDLY[26:22]<%d> R_SMPL[1]<%d>", cmd->opcode, |
||
1350 | (result == 0) ? "PASS" : "FAIL", cur_rrdly, cur_rsmpl); |
||
1351 | |||
1352 | if (result == 0) |
||
1353 | return 0; |
||
1354 | if (result != -EIO) { |
||
1355 | ERR_MSG("TUNE_CMD<%d> Error<%d> not -EIO", cmd->opcode, result); |
||
1356 | return result; |
||
1357 | } |
||
1358 | |||
1359 | /* should be EIO */ |
||
1360 | if (sdr_read32(SDC_CMD) & 0x1800) { /* check if has data phase */ |
||
1361 | msdc_abort_data(host); |
||
1362 | } |
||
1363 | } |
||
1364 | |||
1365 | /* Lv2: PAD_CMD_RESP_RXDLY[26:22] */ |
||
1366 | cur_rrdly = (orig_rrdly + rrdly + 1) % 32; |
||
1367 | sdr_set_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, cur_rrdly); |
||
1368 | } while (++rrdly < 32); |
||
1369 | |||
1370 | return result; |
||
1371 | } |
||
1372 | |||
1373 | /* Support SD2.0 Only */ |
||
1374 | static int msdc_tune_bread(struct mmc_host *mmc, struct mmc_request *mrq) |
||
1375 | { |
||
1376 | struct msdc_host *host = mmc_priv(mmc); |
||
1377 | void __iomem *base = host->base; |
||
1378 | u32 ddr = 0; |
||
1379 | u32 dcrc = 0; |
||
1380 | u32 rxdly, cur_rxdly0, cur_rxdly1; |
||
1381 | u32 dsmpl, cur_dsmpl, orig_dsmpl; |
||
1382 | u32 cur_dat0, cur_dat1, cur_dat2, cur_dat3; |
||
1383 | u32 cur_dat4, cur_dat5, cur_dat6, cur_dat7; |
||
1384 | u32 orig_dat0, orig_dat1, orig_dat2, orig_dat3; |
||
1385 | u32 orig_dat4, orig_dat5, orig_dat6, orig_dat7; |
||
1386 | int result = -1; |
||
1387 | u32 skip = 1; |
||
1388 | |||
1389 | sdr_get_field(MSDC_IOCON, MSDC_IOCON_DSPL, &orig_dsmpl); |
||
1390 | |||
1391 | /* Tune Method 2. */ |
||
1392 | sdr_set_field(MSDC_IOCON, MSDC_IOCON_DDLSEL, 1); |
||
1393 | |||
1394 | rxdly = 0; |
||
1395 | do { |
||
1396 | for (dsmpl = 0; dsmpl < 2; dsmpl++) { |
||
1397 | cur_dsmpl = (orig_dsmpl + dsmpl) % 2; |
||
1398 | if (skip == 1) { |
||
1399 | skip = 0; |
||
1400 | continue; |
||
1401 | } |
||
1402 | sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, cur_dsmpl); |
||
1403 | |||
1404 | if (host->app_cmd) { |
||
1405 | result = msdc_app_cmd(host->mmc, host); |
||
1406 | if (result) { |
||
1407 | ERR_MSG("TUNE_BREAD app_cmd<%d> failed", host->mrq->cmd->opcode); |
||
1408 | continue; |
||
1409 | } |
||
1410 | } |
||
1411 | result = msdc_do_request(mmc, mrq); |
||
1412 | |||
1413 | sdr_get_field(SDC_DCRC_STS, |
||
1414 | SDC_DCRC_STS_POS | SDC_DCRC_STS_NEG, |
||
1415 | &dcrc); /* RO */ |
||
1416 | if (!ddr) |
||
1417 | dcrc &= ~SDC_DCRC_STS_NEG; |
||
1418 | ERR_MSG("TUNE_BREAD<%s> dcrc<0x%x> DATRDDLY0/1<0x%x><0x%x> dsmpl<0x%x>", |
||
1419 | (result == 0 && dcrc == 0) ? "PASS" : "FAIL", dcrc, |
||
1420 | sdr_read32(MSDC_DAT_RDDLY0), sdr_read32(MSDC_DAT_RDDLY1), cur_dsmpl); |
||
1421 | |||
1422 | /* Fix me: result is 0, but dcrc is still exist */ |
||
1423 | if (result == 0 && dcrc == 0) { |
||
1424 | goto done; |
||
1425 | } else { |
||
1426 | /* there is a case: command timeout, and data phase not processed */ |
||
1427 | if (mrq->data->error != 0 && |
||
1428 | mrq->data->error != -EIO) { |
||
1429 | ERR_MSG("TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>", |
||
1430 | result, mrq->cmd->error, mrq->data->error); |
||
1431 | goto done; |
||
1432 | } |
||
1433 | } |
||
1434 | } |
||
1435 | |||
1436 | cur_rxdly0 = sdr_read32(MSDC_DAT_RDDLY0); |
||
1437 | cur_rxdly1 = sdr_read32(MSDC_DAT_RDDLY1); |
||
1438 | |||
1439 | /* E1 ECO. YD: Reverse */ |
||
1440 | if (sdr_read32(MSDC_ECO_VER) >= 4) { |
||
1441 | orig_dat0 = (cur_rxdly0 >> 24) & 0x1F; |
||
1442 | orig_dat1 = (cur_rxdly0 >> 16) & 0x1F; |
||
1443 | orig_dat2 = (cur_rxdly0 >> 8) & 0x1F; |
||
1444 | orig_dat3 = (cur_rxdly0 >> 0) & 0x1F; |
||
1445 | orig_dat4 = (cur_rxdly1 >> 24) & 0x1F; |
||
1446 | orig_dat5 = (cur_rxdly1 >> 16) & 0x1F; |
||
1447 | orig_dat6 = (cur_rxdly1 >> 8) & 0x1F; |
||
1448 | orig_dat7 = (cur_rxdly1 >> 0) & 0x1F; |
||
1449 | } else { |
||
1450 | orig_dat0 = (cur_rxdly0 >> 0) & 0x1F; |
||
1451 | orig_dat1 = (cur_rxdly0 >> 8) & 0x1F; |
||
1452 | orig_dat2 = (cur_rxdly0 >> 16) & 0x1F; |
||
1453 | orig_dat3 = (cur_rxdly0 >> 24) & 0x1F; |
||
1454 | orig_dat4 = (cur_rxdly1 >> 0) & 0x1F; |
||
1455 | orig_dat5 = (cur_rxdly1 >> 8) & 0x1F; |
||
1456 | orig_dat6 = (cur_rxdly1 >> 16) & 0x1F; |
||
1457 | orig_dat7 = (cur_rxdly1 >> 24) & 0x1F; |
||
1458 | } |
||
1459 | |||
1460 | if (ddr) { |
||
1461 | cur_dat0 = (dcrc & (1 << 0) || dcrc & (1 << 8)) ? ((orig_dat0 + 1) % 32) : orig_dat0; |
||
1462 | cur_dat1 = (dcrc & (1 << 1) || dcrc & (1 << 9)) ? ((orig_dat1 + 1) % 32) : orig_dat1; |
||
1463 | cur_dat2 = (dcrc & (1 << 2) || dcrc & (1 << 10)) ? ((orig_dat2 + 1) % 32) : orig_dat2; |
||
1464 | cur_dat3 = (dcrc & (1 << 3) || dcrc & (1 << 11)) ? ((orig_dat3 + 1) % 32) : orig_dat3; |
||
1465 | } else { |
||
1466 | cur_dat0 = (dcrc & (1 << 0)) ? ((orig_dat0 + 1) % 32) : orig_dat0; |
||
1467 | cur_dat1 = (dcrc & (1 << 1)) ? ((orig_dat1 + 1) % 32) : orig_dat1; |
||
1468 | cur_dat2 = (dcrc & (1 << 2)) ? ((orig_dat2 + 1) % 32) : orig_dat2; |
||
1469 | cur_dat3 = (dcrc & (1 << 3)) ? ((orig_dat3 + 1) % 32) : orig_dat3; |
||
1470 | } |
||
1471 | cur_dat4 = (dcrc & (1 << 4)) ? ((orig_dat4 + 1) % 32) : orig_dat4; |
||
1472 | cur_dat5 = (dcrc & (1 << 5)) ? ((orig_dat5 + 1) % 32) : orig_dat5; |
||
1473 | cur_dat6 = (dcrc & (1 << 6)) ? ((orig_dat6 + 1) % 32) : orig_dat6; |
||
1474 | cur_dat7 = (dcrc & (1 << 7)) ? ((orig_dat7 + 1) % 32) : orig_dat7; |
||
1475 | |||
1476 | cur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0); |
||
1477 | cur_rxdly1 = (cur_dat4 << 24) | (cur_dat5 << 16) | (cur_dat6 << 8) | (cur_dat7 << 0); |
||
1478 | |||
1479 | sdr_write32(MSDC_DAT_RDDLY0, cur_rxdly0); |
||
1480 | sdr_write32(MSDC_DAT_RDDLY1, cur_rxdly1); |
||
1481 | |||
1482 | } while (++rxdly < 32); |
||
1483 | |||
1484 | done: |
||
1485 | return result; |
||
1486 | } |
||
1487 | |||
1488 | static int msdc_tune_bwrite(struct mmc_host *mmc, struct mmc_request *mrq) |
||
1489 | { |
||
1490 | struct msdc_host *host = mmc_priv(mmc); |
||
1491 | void __iomem *base = host->base; |
||
1492 | |||
1493 | u32 wrrdly, cur_wrrdly = 0xffffffff, orig_wrrdly; |
||
1494 | u32 dsmpl, cur_dsmpl, orig_dsmpl; |
||
1495 | u32 rxdly, cur_rxdly0; |
||
1496 | u32 orig_dat0, orig_dat1, orig_dat2, orig_dat3; |
||
1497 | u32 cur_dat0, cur_dat1, cur_dat2, cur_dat3; |
||
1498 | int result = -1; |
||
1499 | u32 skip = 1; |
||
1500 | |||
1501 | // MSDC_IOCON_DDR50CKD need to check. [Fix me] |
||
1502 | |||
1503 | sdr_get_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY, &orig_wrrdly); |
||
1504 | sdr_get_field(MSDC_IOCON, MSDC_IOCON_DSPL, &orig_dsmpl); |
||
1505 | |||
1506 | /* Tune Method 2. just DAT0 */ |
||
1507 | sdr_set_field(MSDC_IOCON, MSDC_IOCON_DDLSEL, 1); |
||
1508 | cur_rxdly0 = sdr_read32(MSDC_DAT_RDDLY0); |
||
1509 | |||
1510 | /* E1 ECO. YD: Reverse */ |
||
1511 | if (sdr_read32(MSDC_ECO_VER) >= 4) { |
||
1512 | orig_dat0 = (cur_rxdly0 >> 24) & 0x1F; |
||
1513 | orig_dat1 = (cur_rxdly0 >> 16) & 0x1F; |
||
1514 | orig_dat2 = (cur_rxdly0 >> 8) & 0x1F; |
||
1515 | orig_dat3 = (cur_rxdly0 >> 0) & 0x1F; |
||
1516 | } else { |
||
1517 | orig_dat0 = (cur_rxdly0 >> 0) & 0x1F; |
||
1518 | orig_dat1 = (cur_rxdly0 >> 8) & 0x1F; |
||
1519 | orig_dat2 = (cur_rxdly0 >> 16) & 0x1F; |
||
1520 | orig_dat3 = (cur_rxdly0 >> 24) & 0x1F; |
||
1521 | } |
||
1522 | |||
1523 | rxdly = 0; |
||
1524 | do { |
||
1525 | wrrdly = 0; |
||
1526 | do { |
||
1527 | for (dsmpl = 0; dsmpl < 2; dsmpl++) { |
||
1528 | cur_dsmpl = (orig_dsmpl + dsmpl) % 2; |
||
1529 | if (skip == 1) { |
||
1530 | skip = 0; |
||
1531 | continue; |
||
1532 | } |
||
1533 | sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, cur_dsmpl); |
||
1534 | |||
1535 | if (host->app_cmd) { |
||
1536 | result = msdc_app_cmd(host->mmc, host); |
||
1537 | if (result) { |
||
1538 | ERR_MSG("TUNE_BWRITE app_cmd<%d> failed", host->mrq->cmd->opcode); |
||
1539 | continue; |
||
1540 | } |
||
1541 | } |
||
1542 | result = msdc_do_request(mmc, mrq); |
||
1543 | |||
1544 | ERR_MSG("TUNE_BWRITE<%s> DSPL<%d> DATWRDLY<%d> MSDC_DAT_RDDLY0<0x%x>", |
||
1545 | result == 0 ? "PASS" : "FAIL", |
||
1546 | cur_dsmpl, cur_wrrdly, cur_rxdly0); |
||
1547 | |||
1548 | if (result == 0) { |
||
1549 | goto done; |
||
1550 | } else { |
||
1551 | /* there is a case: command timeout, and data phase not processed */ |
||
1552 | if (mrq->data->error != -EIO) { |
||
1553 | ERR_MSG("TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>", |
||
1554 | result, mrq->cmd->error, mrq->data->error); |
||
1555 | goto done; |
||
1556 | } |
||
1557 | } |
||
1558 | } |
||
1559 | cur_wrrdly = (orig_wrrdly + wrrdly + 1) % 32; |
||
1560 | sdr_set_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY, cur_wrrdly); |
||
1561 | } while (++wrrdly < 32); |
||
1562 | |||
1563 | cur_dat0 = (orig_dat0 + rxdly) % 32; /* only adjust bit-1 for crc */ |
||
1564 | cur_dat1 = orig_dat1; |
||
1565 | cur_dat2 = orig_dat2; |
||
1566 | cur_dat3 = orig_dat3; |
||
1567 | |||
1568 | cur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0); |
||
1569 | sdr_write32(MSDC_DAT_RDDLY0, cur_rxdly0); |
||
1570 | } while (++rxdly < 32); |
||
1571 | |||
1572 | done: |
||
1573 | return result; |
||
1574 | } |
||
1575 | |||
1576 | static int msdc_get_card_status(struct mmc_host *mmc, struct msdc_host *host, u32 *status) |
||
1577 | { |
||
1578 | struct mmc_command cmd; |
||
1579 | struct mmc_request mrq; |
||
1580 | u32 err; |
||
1581 | |||
1582 | memset(&cmd, 0, sizeof(struct mmc_command)); |
||
1583 | cmd.opcode = MMC_SEND_STATUS; |
||
1584 | if (mmc->card) { |
||
1585 | cmd.arg = mmc->card->rca << 16; |
||
1586 | } else { |
||
1587 | ERR_MSG("cmd13 mmc card is null"); |
||
1588 | cmd.arg = host->app_cmd_arg; |
||
1589 | } |
||
1590 | cmd.flags = MMC_RSP_SPI_R2 | MMC_RSP_R1 | MMC_CMD_AC; |
||
1591 | |||
1592 | memset(&mrq, 0, sizeof(struct mmc_request)); |
||
1593 | mrq.cmd = &cmd; cmd.mrq = &mrq; |
||
1594 | cmd.data = NULL; |
||
1595 | |||
1596 | err = msdc_do_command(host, &cmd, 1, CMD_TIMEOUT); |
||
1597 | |||
1598 | if (status) |
||
1599 | *status = cmd.resp[0]; |
||
1600 | |||
1601 | return err; |
||
1602 | } |
||
1603 | |||
1604 | static int msdc_check_busy(struct mmc_host *mmc, struct msdc_host *host) |
||
1605 | { |
||
1606 | u32 err = 0; |
||
1607 | u32 status = 0; |
||
1608 | |||
1609 | do { |
||
1610 | err = msdc_get_card_status(mmc, host, &status); |
||
1611 | if (err) |
||
1612 | return err; |
||
1613 | /* need cmd12? */ |
||
1614 | ERR_MSG("cmd<13> resp<0x%x>", status); |
||
1615 | } while (R1_CURRENT_STATE(status) == 7); |
||
1616 | |||
1617 | return err; |
||
1618 | } |
||
1619 | |||
1620 | /* failed when msdc_do_request */ |
||
1621 | static int msdc_tune_request(struct mmc_host *mmc, struct mmc_request *mrq) |
||
1622 | { |
||
1623 | struct msdc_host *host = mmc_priv(mmc); |
||
1624 | struct mmc_command *cmd; |
||
1625 | struct mmc_data *data; |
||
1626 | //u32 base = host->base; |
||
1627 | int ret = 0, read; |
||
1628 | |||
1629 | cmd = mrq->cmd; |
||
1630 | data = mrq->cmd->data; |
||
1631 | |||
1632 | read = data->flags & MMC_DATA_READ ? 1 : 0; |
||
1633 | |||
1634 | if (read) { |
||
1635 | if (data->error == -EIO) |
||
1636 | ret = msdc_tune_bread(mmc, mrq); |
||
1637 | } else { |
||
1638 | ret = msdc_check_busy(mmc, host); |
||
1639 | if (ret) { |
||
1640 | ERR_MSG("XXX cmd13 wait program done failed"); |
||
1641 | return ret; |
||
1642 | } |
||
1643 | /* CRC and TO */ |
||
1644 | /* Fix me: don't care card status? */ |
||
1645 | ret = msdc_tune_bwrite(mmc, mrq); |
||
1646 | } |
||
1647 | |||
1648 | return ret; |
||
1649 | } |
||
1650 | |||
1651 | /* ops.request */ |
||
1652 | static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) |
||
1653 | { |
||
1654 | struct msdc_host *host = mmc_priv(mmc); |
||
1655 | |||
1656 | //=== for sdio profile === |
||
1657 | #if 0 /* --- by chhung */ |
||
1658 | u32 old_H32, old_L32, new_H32, new_L32; |
||
1659 | u32 ticks = 0, opcode = 0, sizes = 0, bRx = 0; |
||
1660 | #endif /* end of --- */ |
||
1661 | |||
1662 | WARN_ON(host->mrq); |
||
1663 | |||
1664 | /* start to process */ |
||
1665 | spin_lock(&host->lock); |
||
1666 | #if 0 /* --- by chhung */ |
||
1667 | if (sdio_pro_enable) { //=== for sdio profile === |
||
1668 | if (mrq->cmd->opcode == 52 || mrq->cmd->opcode == 53) |
||
1669 | GPT_GetCounter64(&old_L32, &old_H32); |
||
1670 | } |
||
1671 | #endif /* end of --- */ |
||
1672 | |||
1673 | host->mrq = mrq; |
||
1674 | |||
1675 | if (msdc_do_request(mmc, mrq)) { |
||
1676 | if (host->hw->flags & MSDC_REMOVABLE && ralink_soc == MT762X_SOC_MT7621AT && mrq->data && mrq->data->error) |
||
1677 | msdc_tune_request(mmc, mrq); |
||
1678 | } |
||
1679 | |||
1680 | /* ==== when request done, check if app_cmd ==== */ |
||
1681 | if (mrq->cmd->opcode == MMC_APP_CMD) { |
||
1682 | host->app_cmd = 1; |
||
1683 | host->app_cmd_arg = mrq->cmd->arg; /* save the RCA */ |
||
1684 | } else { |
||
1685 | host->app_cmd = 0; |
||
1686 | //host->app_cmd_arg = 0; |
||
1687 | } |
||
1688 | |||
1689 | host->mrq = NULL; |
||
1690 | |||
1691 | #if 0 /* --- by chhung */ |
||
1692 | //=== for sdio profile === |
||
1693 | if (sdio_pro_enable) { |
||
1694 | if (mrq->cmd->opcode == 52 || mrq->cmd->opcode == 53) { |
||
1695 | GPT_GetCounter64(&new_L32, &new_H32); |
||
1696 | ticks = msdc_time_calc(old_L32, old_H32, new_L32, new_H32); |
||
1697 | |||
1698 | opcode = mrq->cmd->opcode; |
||
1699 | if (mrq->cmd->data) { |
||
1700 | sizes = mrq->cmd->data->blocks * mrq->cmd->data->blksz; |
||
1701 | bRx = mrq->cmd->data->flags & MMC_DATA_READ ? 1 : 0; |
||
1702 | } else { |
||
1703 | bRx = mrq->cmd->arg & 0x80000000 ? 1 : 0; |
||
1704 | } |
||
1705 | |||
1706 | if (!mrq->cmd->error) |
||
1707 | msdc_performance(opcode, sizes, bRx, ticks); |
||
1708 | } |
||
1709 | } |
||
1710 | #endif /* end of --- */ |
||
1711 | spin_unlock(&host->lock); |
||
1712 | |||
1713 | mmc_request_done(mmc, mrq); |
||
1714 | |||
1715 | return; |
||
1716 | } |
||
1717 | |||
1718 | /* called by ops.set_ios */ |
||
1719 | static void msdc_set_buswidth(struct msdc_host *host, u32 width) |
||
1720 | { |
||
1721 | void __iomem *base = host->base; |
||
1722 | u32 val = sdr_read32(SDC_CFG); |
||
1723 | |||
1724 | val &= ~SDC_CFG_BUSWIDTH; |
||
1725 | |||
1726 | switch (width) { |
||
1727 | default: |
||
1728 | case MMC_BUS_WIDTH_1: |
||
1729 | width = 1; |
||
1730 | val |= (MSDC_BUS_1BITS << 16); |
||
1731 | break; |
||
1732 | case MMC_BUS_WIDTH_4: |
||
1733 | val |= (MSDC_BUS_4BITS << 16); |
||
1734 | break; |
||
1735 | case MMC_BUS_WIDTH_8: |
||
1736 | val |= (MSDC_BUS_8BITS << 16); |
||
1737 | break; |
||
1738 | } |
||
1739 | |||
1740 | sdr_write32(SDC_CFG, val); |
||
1741 | |||
1742 | N_MSG(CFG, "Bus Width = %d", width); |
||
1743 | } |
||
1744 | |||
1745 | /* ops.set_ios */ |
||
1746 | static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
||
1747 | { |
||
1748 | struct msdc_host *host = mmc_priv(mmc); |
||
1749 | void __iomem *base = host->base; |
||
1750 | u32 ddr = 0; |
||
1751 | |||
1752 | #ifdef MT6575_SD_DEBUG |
||
1753 | static char *vdd[] = { |
||
1754 | "1.50v", "1.55v", "1.60v", "1.65v", "1.70v", "1.80v", "1.90v", |
||
1755 | "2.00v", "2.10v", "2.20v", "2.30v", "2.40v", "2.50v", "2.60v", |
||
1756 | "2.70v", "2.80v", "2.90v", "3.00v", "3.10v", "3.20v", "3.30v", |
||
1757 | "3.40v", "3.50v", "3.60v" |
||
1758 | }; |
||
1759 | static char *power_mode[] = { |
||
1760 | "OFF", "UP", "ON" |
||
1761 | }; |
||
1762 | static char *bus_mode[] = { |
||
1763 | "UNKNOWN", "OPENDRAIN", "PUSHPULL" |
||
1764 | }; |
||
1765 | static char *timing[] = { |
||
1766 | "LEGACY", "MMC_HS", "SD_HS" |
||
1767 | }; |
||
1768 | |||
1769 | printk("SET_IOS: CLK(%dkHz), BUS(%s), BW(%u), PWR(%s), VDD(%s), TIMING(%s)", |
||
1770 | ios->clock / 1000, bus_mode[ios->bus_mode], |
||
1771 | (ios->bus_width == MMC_BUS_WIDTH_4) ? 4 : 1, |
||
1772 | power_mode[ios->power_mode], vdd[ios->vdd], timing[ios->timing]); |
||
1773 | #endif |
||
1774 | |||
1775 | msdc_set_buswidth(host, ios->bus_width); |
||
1776 | |||
1777 | /* Power control ??? */ |
||
1778 | switch (ios->power_mode) { |
||
1779 | case MMC_POWER_OFF: |
||
1780 | case MMC_POWER_UP: |
||
1781 | // msdc_set_power_mode(host, ios->power_mode); /* --- by chhung */ |
||
1782 | break; |
||
1783 | case MMC_POWER_ON: |
||
1784 | host->power_mode = MMC_POWER_ON; |
||
1785 | break; |
||
1786 | default: |
||
1787 | break; |
||
1788 | } |
||
1789 | |||
1790 | /* Clock control */ |
||
1791 | if (host->mclk != ios->clock) { |
||
1792 | if (ios->clock > 25000000) { |
||
1793 | //if (!(host->hw->flags & MSDC_REMOVABLE)) { |
||
1794 | INIT_MSG("SD data latch edge<%d>", MSDC_SMPL_FALLING); |
||
1795 | sdr_set_field(MSDC_IOCON, MSDC_IOCON_RSPL, |
||
1796 | MSDC_SMPL_FALLING); |
||
1797 | sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, |
||
1798 | MSDC_SMPL_FALLING); |
||
1799 | //} /* for tuning debug */ |
||
1800 | } else { /* default value */ |
||
1801 | sdr_write32(MSDC_IOCON, 0x00000000); |
||
1802 | // sdr_write32(MSDC_DAT_RDDLY0, 0x00000000); |
||
1803 | sdr_write32(MSDC_DAT_RDDLY0, 0x10101010); // for MT7620 E2 and afterward |
||
1804 | sdr_write32(MSDC_DAT_RDDLY1, 0x00000000); |
||
1805 | // sdr_write32(MSDC_PAD_TUNE, 0x00000000); |
||
1806 | sdr_write32(MSDC_PAD_TUNE, 0x84101010); // for MT7620 E2 and afterward |
||
1807 | } |
||
1808 | msdc_set_mclk(host, ddr, ios->clock); |
||
1809 | } |
||
1810 | } |
||
1811 | |||
1812 | /* ops.get_ro */ |
||
1813 | static int msdc_ops_get_ro(struct mmc_host *mmc) |
||
1814 | { |
||
1815 | struct msdc_host *host = mmc_priv(mmc); |
||
1816 | void __iomem *base = host->base; |
||
1817 | unsigned long flags; |
||
1818 | int ro = 0; |
||
1819 | |||
1820 | if (host->hw->flags & MSDC_WP_PIN_EN) { /* set for card */ |
||
1821 | spin_lock_irqsave(&host->lock, flags); |
||
1822 | ro = (sdr_read32(MSDC_PS) >> 31); |
||
1823 | spin_unlock_irqrestore(&host->lock, flags); |
||
1824 | } |
||
1825 | return ro; |
||
1826 | } |
||
1827 | |||
1828 | /* ops.get_cd */ |
||
1829 | static int msdc_ops_get_cd(struct mmc_host *mmc) |
||
1830 | { |
||
1831 | struct msdc_host *host = mmc_priv(mmc); |
||
1832 | void __iomem *base = host->base; |
||
1833 | unsigned long flags; |
||
1834 | int present = 1; |
||
1835 | |||
1836 | /* for sdio, MSDC_REMOVABLE not set, always return 1 */ |
||
1837 | if (!(host->hw->flags & MSDC_REMOVABLE)) { |
||
1838 | /* For sdio, read H/W always get<1>, but may timeout some times */ |
||
1839 | #if 1 |
||
1840 | host->card_inserted = 1; |
||
1841 | return 1; |
||
1842 | #else |
||
1843 | host->card_inserted = (host->pm_state.event == PM_EVENT_USER_RESUME) ? 1 : 0; |
||
1844 | INIT_MSG("sdio ops_get_cd<%d>", host->card_inserted); |
||
1845 | return host->card_inserted; |
||
1846 | #endif |
||
1847 | } |
||
1848 | |||
1849 | /* MSDC_CD_PIN_EN set for card */ |
||
1850 | if (host->hw->flags & MSDC_CD_PIN_EN) { |
||
1851 | spin_lock_irqsave(&host->lock, flags); |
||
1852 | #if 0 |
||
1853 | present = host->card_inserted; /* why not read from H/W: Fix me*/ |
||
1854 | #else |
||
1855 | // CD |
||
1856 | if (cd_active_low) |
||
1857 | present = (sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 0 : 1; |
||
1858 | else |
||
1859 | present = (sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 1 : 0; |
||
1860 | host->card_inserted = present; |
||
1861 | #endif |
||
1862 | spin_unlock_irqrestore(&host->lock, flags); |
||
1863 | } else { |
||
1864 | present = 0; /* TODO? Check DAT3 pins for card detection */ |
||
1865 | } |
||
1866 | |||
1867 | INIT_MSG("ops_get_cd return<%d>", present); |
||
1868 | return present; |
||
1869 | } |
||
1870 | |||
1871 | static struct mmc_host_ops mt_msdc_ops = { |
||
1872 | .request = msdc_ops_request, |
||
1873 | .set_ios = msdc_ops_set_ios, |
||
1874 | .get_ro = msdc_ops_get_ro, |
||
1875 | .get_cd = msdc_ops_get_cd, |
||
1876 | }; |
||
1877 | |||
1878 | /*--------------------------------------------------------------------------*/ |
||
1879 | /* interrupt handler */ |
||
1880 | /*--------------------------------------------------------------------------*/ |
||
1881 | static irqreturn_t msdc_irq(int irq, void *dev_id) |
||
1882 | { |
||
1883 | struct msdc_host *host = (struct msdc_host *)dev_id; |
||
1884 | struct mmc_data *data = host->data; |
||
1885 | struct mmc_command *cmd = host->cmd; |
||
1886 | void __iomem *base = host->base; |
||
1887 | |||
1888 | u32 cmdsts = MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO | MSDC_INT_CMDRDY | |
||
1889 | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO | MSDC_INT_ACMDRDY | |
||
1890 | MSDC_INT_ACMD19_DONE; |
||
1891 | u32 datsts = MSDC_INT_DATCRCERR | MSDC_INT_DATTMO; |
||
1892 | |||
1893 | u32 intsts = sdr_read32(MSDC_INT); |
||
1894 | u32 inten = sdr_read32(MSDC_INTEN); inten &= intsts; |
||
1895 | |||
1896 | sdr_write32(MSDC_INT, intsts); /* clear interrupts */ |
||
1897 | /* MSG will cause fatal error */ |
||
1898 | |||
1899 | /* card change interrupt */ |
||
1900 | if (intsts & MSDC_INT_CDSC) { |
||
1901 | if (host->mmc->caps & MMC_CAP_NEEDS_POLL) |
||
1902 | return IRQ_HANDLED; |
||
1903 | IRQ_MSG("MSDC_INT_CDSC irq<0x%.8x>", intsts); |
||
1904 | schedule_delayed_work(&host->card_delaywork, HZ); |
||
1905 | /* tuning when plug card ? */ |
||
1906 | } |
||
1907 | |||
1908 | /* sdio interrupt */ |
||
1909 | if (intsts & MSDC_INT_SDIOIRQ) { |
||
1910 | IRQ_MSG("XXX MSDC_INT_SDIOIRQ"); /* seems not sdio irq */ |
||
1911 | //mmc_signal_sdio_irq(host->mmc); |
||
1912 | } |
||
1913 | |||
1914 | /* transfer complete interrupt */ |
||
1915 | if (data != NULL) { |
||
1916 | if (inten & MSDC_INT_XFER_COMPL) { |
||
1917 | data->bytes_xfered = host->xfer_size; |
||
1918 | complete(&host->xfer_done); |
||
1919 | } |
||
1920 | |||
1921 | if (intsts & datsts) { |
||
1922 | /* do basic reset, or stop command will sdc_busy */ |
||
1923 | msdc_reset_hw(host); |
||
1924 | msdc_clr_fifo(); |
||
1925 | msdc_clr_int(); |
||
1926 | |||
1927 | if (intsts & MSDC_INT_DATTMO) { |
||
1928 | IRQ_MSG("XXX CMD<%d> MSDC_INT_DATTMO", host->mrq->cmd->opcode); |
||
1929 | data->error = -ETIMEDOUT; |
||
1930 | } else if (intsts & MSDC_INT_DATCRCERR) { |
||
1931 | IRQ_MSG("XXX CMD<%d> MSDC_INT_DATCRCERR, SDC_DCRC_STS<0x%x>", host->mrq->cmd->opcode, sdr_read32(SDC_DCRC_STS)); |
||
1932 | data->error = -EIO; |
||
1933 | } |
||
1934 | |||
1935 | //if(sdr_read32(MSDC_INTEN) & MSDC_INT_XFER_COMPL) { |
||
1936 | complete(&host->xfer_done); /* Read CRC come fast, XFER_COMPL not enabled */ |
||
1937 | } |
||
1938 | } |
||
1939 | |||
1940 | /* command interrupts */ |
||
1941 | if ((cmd != NULL) && (intsts & cmdsts)) { |
||
1942 | if ((intsts & MSDC_INT_CMDRDY) || (intsts & MSDC_INT_ACMDRDY) || |
||
1943 | (intsts & MSDC_INT_ACMD19_DONE)) { |
||
1944 | u32 *rsp = &cmd->resp[0]; |
||
1945 | |||
1946 | switch (host->cmd_rsp) { |
||
1947 | case RESP_NONE: |
||
1948 | break; |
||
1949 | case RESP_R2: |
||
1950 | *rsp++ = sdr_read32(SDC_RESP3); *rsp++ = sdr_read32(SDC_RESP2); |
||
1951 | *rsp++ = sdr_read32(SDC_RESP1); *rsp++ = sdr_read32(SDC_RESP0); |
||
1952 | break; |
||
1953 | default: /* Response types 1, 3, 4, 5, 6, 7(1b) */ |
||
1954 | if ((intsts & MSDC_INT_ACMDRDY) || (intsts & MSDC_INT_ACMD19_DONE)) |
||
1955 | *rsp = sdr_read32(SDC_ACMD_RESP); |
||
1956 | else |
||
1957 | *rsp = sdr_read32(SDC_RESP0); |
||
1958 | break; |
||
1959 | } |
||
1960 | } else if ((intsts & MSDC_INT_RSPCRCERR) || (intsts & MSDC_INT_ACMDCRCERR)) { |
||
1961 | if (intsts & MSDC_INT_ACMDCRCERR) |
||
1962 | IRQ_MSG("XXX CMD<%d> MSDC_INT_ACMDCRCERR", cmd->opcode); |
||
1963 | else |
||
1964 | IRQ_MSG("XXX CMD<%d> MSDC_INT_RSPCRCERR", cmd->opcode); |
||
1965 | cmd->error = -EIO; |
||
1966 | } else if ((intsts & MSDC_INT_CMDTMO) || (intsts & MSDC_INT_ACMDTMO)) { |
||
1967 | if (intsts & MSDC_INT_ACMDTMO) |
||
1968 | IRQ_MSG("XXX CMD<%d> MSDC_INT_ACMDTMO", cmd->opcode); |
||
1969 | else |
||
1970 | IRQ_MSG("XXX CMD<%d> MSDC_INT_CMDTMO", cmd->opcode); |
||
1971 | cmd->error = -ETIMEDOUT; |
||
1972 | msdc_reset_hw(host); |
||
1973 | msdc_clr_fifo(); |
||
1974 | msdc_clr_int(); |
||
1975 | } |
||
1976 | complete(&host->cmd_done); |
||
1977 | } |
||
1978 | |||
1979 | /* mmc irq interrupts */ |
||
1980 | if (intsts & MSDC_INT_MMCIRQ) |
||
1981 | printk(KERN_INFO "msdc[%d] MMCIRQ: SDC_CSTS=0x%.8x\r\n", host->id, sdr_read32(SDC_CSTS)); |
||
1982 | |||
1983 | #ifdef MT6575_SD_DEBUG |
||
1984 | { |
||
1985 | /* msdc_int_reg *int_reg = (msdc_int_reg*)&intsts;*/ |
||
1986 | N_MSG(INT, "IRQ_EVT(0x%x): MMCIRQ(%d) CDSC(%d), ACRDY(%d), ACTMO(%d), ACCRE(%d) AC19DN(%d)", |
||
1987 | intsts, |
||
1988 | int_reg->mmcirq, |
||
1989 | int_reg->cdsc, |
||
1990 | int_reg->atocmdrdy, |
||
1991 | int_reg->atocmdtmo, |
||
1992 | int_reg->atocmdcrc, |
||
1993 | int_reg->atocmd19done); |
||
1994 | N_MSG(INT, "IRQ_EVT(0x%x): SDIO(%d) CMDRDY(%d), CMDTMO(%d), RSPCRC(%d), CSTA(%d)", |
||
1995 | intsts, |
||
1996 | int_reg->sdioirq, |
||
1997 | int_reg->cmdrdy, |
||
1998 | int_reg->cmdtmo, |
||
1999 | int_reg->rspcrc, |
||
2000 | int_reg->csta); |
||
2001 | N_MSG(INT, "IRQ_EVT(0x%x): XFCMP(%d) DXDONE(%d), DATTMO(%d), DATCRC(%d), DMAEMP(%d)", |
||
2002 | intsts, |
||
2003 | int_reg->xfercomp, |
||
2004 | int_reg->dxferdone, |
||
2005 | int_reg->dattmo, |
||
2006 | int_reg->datcrc, |
||
2007 | int_reg->dmaqempty); |
||
2008 | } |
||
2009 | #endif |
||
2010 | |||
2011 | return IRQ_HANDLED; |
||
2012 | } |
||
2013 | |||
2014 | /*--------------------------------------------------------------------------*/ |
||
2015 | /* platform_driver members */ |
||
2016 | /*--------------------------------------------------------------------------*/ |
||
2017 | /* called by msdc_drv_probe/remove */ |
||
2018 | static void msdc_enable_cd_irq(struct msdc_host *host, int enable) |
||
2019 | { |
||
2020 | struct msdc_hw *hw = host->hw; |
||
2021 | void __iomem *base = host->base; |
||
2022 | |||
2023 | /* for sdio, not set */ |
||
2024 | if ((hw->flags & MSDC_CD_PIN_EN) == 0) { |
||
2025 | /* Pull down card detection pin since it is not avaiable */ |
||
2026 | /* |
||
2027 | if (hw->config_gpio_pin) |
||
2028 | hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN); |
||
2029 | */ |
||
2030 | sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN); |
||
2031 | sdr_clr_bits(MSDC_INTEN, MSDC_INTEN_CDSC); |
||
2032 | sdr_clr_bits(SDC_CFG, SDC_CFG_INSWKUP); |
||
2033 | return; |
||
2034 | } |
||
2035 | |||
2036 | N_MSG(CFG, "CD IRQ Eanable(%d)", enable); |
||
2037 | |||
2038 | if (enable) { |
||
2039 | /* card detection circuit relies on the core power so that the core power |
||
2040 | * shouldn't be turned off. Here adds a reference count to keep |
||
2041 | * the core power alive. |
||
2042 | */ |
||
2043 | //msdc_vcore_on(host); //did in msdc_init_hw() |
||
2044 | |||
2045 | if (hw->config_gpio_pin) /* NULL */ |
||
2046 | hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_UP); |
||
2047 | |||
2048 | sdr_set_field(MSDC_PS, MSDC_PS_CDDEBOUNCE, DEFAULT_DEBOUNCE); |
||
2049 | sdr_set_bits(MSDC_PS, MSDC_PS_CDEN); |
||
2050 | sdr_set_bits(MSDC_INTEN, MSDC_INTEN_CDSC); |
||
2051 | sdr_set_bits(SDC_CFG, SDC_CFG_INSWKUP); /* not in document! Fix me */ |
||
2052 | } else { |
||
2053 | if (hw->config_gpio_pin) /* NULL */ |
||
2054 | hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN); |
||
2055 | |||
2056 | sdr_clr_bits(SDC_CFG, SDC_CFG_INSWKUP); |
||
2057 | sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN); |
||
2058 | sdr_clr_bits(MSDC_INTEN, MSDC_INTEN_CDSC); |
||
2059 | |||
2060 | /* Here decreases a reference count to core power since card |
||
2061 | * detection circuit is shutdown. |
||
2062 | */ |
||
2063 | //msdc_vcore_off(host); |
||
2064 | } |
||
2065 | } |
||
2066 | |||
2067 | /* called by msdc_drv_probe */ |
||
2068 | static void msdc_init_hw(struct msdc_host *host) |
||
2069 | { |
||
2070 | void __iomem *base = host->base; |
||
2071 | |||
2072 | /* Power on */ |
||
2073 | #if 0 /* --- by chhung */ |
||
2074 | msdc_vcore_on(host); |
||
2075 | msdc_pin_reset(host, MSDC_PIN_PULL_UP); |
||
2076 | msdc_select_clksrc(host, hw->clk_src); |
||
2077 | enable_clock(PERI_MSDC0_PDN + host->id, "SD"); |
||
2078 | msdc_vdd_on(host); |
||
2079 | #endif /* end of --- */ |
||
2080 | /* Configure to MMC/SD mode */ |
||
2081 | sdr_set_field(MSDC_CFG, MSDC_CFG_MODE, MSDC_SDMMC); |
||
2082 | |||
2083 | /* Reset */ |
||
2084 | msdc_reset_hw(host); |
||
2085 | msdc_clr_fifo(); |
||
2086 | |||
2087 | /* Disable card detection */ |
||
2088 | sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN); |
||
2089 | |||
2090 | /* Disable and clear all interrupts */ |
||
2091 | sdr_clr_bits(MSDC_INTEN, sdr_read32(MSDC_INTEN)); |
||
2092 | sdr_write32(MSDC_INT, sdr_read32(MSDC_INT)); |
||
2093 | |||
2094 | #if 1 |
||
2095 | /* reset tuning parameter */ |
||
2096 | sdr_write32(MSDC_PAD_CTL0, 0x00090000); |
||
2097 | sdr_write32(MSDC_PAD_CTL1, 0x000A0000); |
||
2098 | sdr_write32(MSDC_PAD_CTL2, 0x000A0000); |
||
2099 | // sdr_write32(MSDC_PAD_TUNE, 0x00000000); |
||
2100 | sdr_write32(MSDC_PAD_TUNE, 0x84101010); // for MT7620 E2 and afterward |
||
2101 | // sdr_write32(MSDC_DAT_RDDLY0, 0x00000000); |
||
2102 | sdr_write32(MSDC_DAT_RDDLY0, 0x10101010); // for MT7620 E2 and afterward |
||
2103 | sdr_write32(MSDC_DAT_RDDLY1, 0x00000000); |
||
2104 | sdr_write32(MSDC_IOCON, 0x00000000); |
||
2105 | #if 0 // use MT7620 default value: 0x403c004f |
||
2106 | sdr_write32(MSDC_PATCH_BIT0, 0x003C000F); /* bit0 modified: Rx Data Clock Source: 1 -> 2.0*/ |
||
2107 | #endif |
||
2108 | |||
2109 | if (sdr_read32(MSDC_ECO_VER) >= 4) { |
||
2110 | if (host->id == 1) { |
||
2111 | sdr_set_field(MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_WRDAT_CRCS, 1); |
||
2112 | sdr_set_field(MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMD_RSP, 1); |
||
2113 | |||
2114 | /* internal clock: latch read data */ |
||
2115 | sdr_set_bits(MSDC_PATCH_BIT0, MSDC_PATCH_BIT_CKGEN_CK); |
||
2116 | } |
||
2117 | } |
||
2118 | #endif |
||
2119 | |||
2120 | /* for safety, should clear SDC_CFG.SDIO_INT_DET_EN & set SDC_CFG.SDIO in |
||
2121 | pre-loader,uboot,kernel drivers. and SDC_CFG.SDIO_INT_DET_EN will be only |
||
2122 | set when kernel driver wants to use SDIO bus interrupt */ |
||
2123 | /* Configure to enable SDIO mode. it's must otherwise sdio cmd5 failed */ |
||
2124 | sdr_set_bits(SDC_CFG, SDC_CFG_SDIO); |
||
2125 | |||
2126 | /* disable detect SDIO device interupt function */ |
||
2127 | sdr_clr_bits(SDC_CFG, SDC_CFG_SDIOIDE); |
||
2128 | |||
2129 | /* eneable SMT for glitch filter */ |
||
2130 | sdr_set_bits(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKSMT); |
||
2131 | sdr_set_bits(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDSMT); |
||
2132 | sdr_set_bits(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATSMT); |
||
2133 | |||
2134 | #if 1 |
||
2135 | /* set clk, cmd, dat pad driving */ |
||
2136 | sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, 4); |
||
2137 | sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, 4); |
||
2138 | sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, 4); |
||
2139 | sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, 4); |
||
2140 | sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, 4); |
||
2141 | sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, 4); |
||
2142 | #else |
||
2143 | sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, 0); |
||
2144 | sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, 0); |
||
2145 | sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, 0); |
||
2146 | sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, 0); |
||
2147 | sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, 0); |
||
2148 | sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, 0); |
||
2149 | #endif |
||
2150 | |||
2151 | /* set sampling edge */ |
||
2152 | |||
2153 | /* write crc timeout detection */ |
||
2154 | sdr_set_field(MSDC_PATCH_BIT0, 1 << 30, 1); |
||
2155 | |||
2156 | /* Configure to default data timeout */ |
||
2157 | sdr_set_field(SDC_CFG, SDC_CFG_DTOC, DEFAULT_DTOC); |
||
2158 | |||
2159 | msdc_set_buswidth(host, MMC_BUS_WIDTH_1); |
||
2160 | |||
2161 | N_MSG(FUC, "init hardware done!"); |
||
2162 | } |
||
2163 | |||
2164 | /* called by msdc_drv_remove */ |
||
2165 | static void msdc_deinit_hw(struct msdc_host *host) |
||
2166 | { |
||
2167 | void __iomem *base = host->base; |
||
2168 | |||
2169 | /* Disable and clear all interrupts */ |
||
2170 | sdr_clr_bits(MSDC_INTEN, sdr_read32(MSDC_INTEN)); |
||
2171 | sdr_write32(MSDC_INT, sdr_read32(MSDC_INT)); |
||
2172 | |||
2173 | /* Disable card detection */ |
||
2174 | msdc_enable_cd_irq(host, 0); |
||
2175 | // msdc_set_power_mode(host, MMC_POWER_OFF); /* make sure power down */ /* --- by chhung */ |
||
2176 | } |
||
2177 | |||
2178 | /* init gpd and bd list in msdc_drv_probe */ |
||
2179 | static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) |
||
2180 | { |
||
2181 | struct gpd *gpd = dma->gpd; |
||
2182 | struct bd *bd = dma->bd; |
||
2183 | int i; |
||
2184 | |||
2185 | /* we just support one gpd, but gpd->next must be set for desc |
||
2186 | * DMA. That's why we alloc 2 gpd structurs. |
||
2187 | */ |
||
2188 | |||
2189 | memset(gpd, 0, sizeof(struct gpd) * 2); |
||
2190 | |||
2191 | gpd->bdp = 1; /* hwo, cs, bd pointer */ |
||
2192 | gpd->ptr = (void *)dma->bd_addr; /* physical address */ |
||
2193 | gpd->next = (void *)((u32)dma->gpd_addr + sizeof(struct gpd)); |
||
2194 | |||
2195 | memset(bd, 0, sizeof(struct bd) * MAX_BD_NUM); |
||
2196 | for (i = 0; i < (MAX_BD_NUM - 1); i++) |
||
2197 | bd[i].next = (void *)(dma->bd_addr + sizeof(*bd) * (i + 1)); |
||
2198 | } |
||
2199 | |||
2200 | static int msdc_drv_probe(struct platform_device *pdev) |
||
2201 | { |
||
2202 | struct resource *res; |
||
2203 | __iomem void *base; |
||
2204 | struct mmc_host *mmc; |
||
2205 | struct msdc_host *host; |
||
2206 | struct msdc_hw *hw; |
||
2207 | int ret; |
||
2208 | u32 reg; |
||
2209 | |||
2210 | //FIXME: this should be done by pinconf and not by the sd driver |
||
2211 | if (ralink_soc == MT762X_SOC_MT7688 || |
||
2212 | ralink_soc == MT762X_SOC_MT7628AN) { |
||
2213 | /* set EPHY pads to digital mode */ |
||
2214 | reg = sdr_read32((void __iomem *)(RALINK_SYSCTL_BASE + 0x3c)); |
||
2215 | reg |= 0x1e << 16; |
||
2216 | sdr_write32((void __iomem *)(RALINK_SYSCTL_BASE + 0x3c), reg); |
||
2217 | } |
||
2218 | |||
2219 | hw = &msdc0_hw; |
||
2220 | |||
2221 | if (of_property_read_bool(pdev->dev.of_node, "mtk,wp-en")) |
||
2222 | msdc0_hw.flags |= MSDC_WP_PIN_EN; |
||
2223 | |||
2224 | /* Allocate MMC host for this device */ |
||
2225 | mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); |
||
2226 | if (!mmc) |
||
2227 | return -ENOMEM; |
||
2228 | |||
2229 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
||
2230 | base = devm_ioremap_resource(&pdev->dev, res); |
||
2231 | if (IS_ERR(base)) { |
||
2232 | ret = PTR_ERR(base); |
||
2233 | goto host_free; |
||
2234 | } |
||
2235 | |||
2236 | /* Set host parameters to mmc */ |
||
2237 | mmc->ops = &mt_msdc_ops; |
||
2238 | mmc->f_min = HOST_MIN_MCLK; |
||
2239 | mmc->f_max = HOST_MAX_MCLK; |
||
2240 | mmc->ocr_avail = MSDC_OCR_AVAIL; |
||
2241 | |||
2242 | mmc->caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED; |
||
2243 | |||
2244 | //TODO: read this as bus-width from dt (via mmc_of_parse) |
||
2245 | mmc->caps |= MMC_CAP_4_BIT_DATA; |
||
2246 | |||
2247 | cd_active_low = !of_property_read_bool(pdev->dev.of_node, "mediatek,cd-high"); |
||
2248 | |||
2249 | if (of_property_read_bool(pdev->dev.of_node, "mediatek,cd-poll")) |
||
2250 | mmc->caps |= MMC_CAP_NEEDS_POLL; |
||
2251 | |||
2252 | /* MMC core transfer sizes tunable parameters */ |
||
2253 | mmc->max_segs = MAX_HW_SGMTS; |
||
2254 | |||
2255 | mmc->max_seg_size = MAX_SGMT_SZ; |
||
2256 | mmc->max_blk_size = HOST_MAX_BLKSZ; |
||
2257 | mmc->max_req_size = MAX_REQ_SZ; |
||
2258 | mmc->max_blk_count = mmc->max_req_size; |
||
2259 | |||
2260 | host = mmc_priv(mmc); |
||
2261 | host->hw = hw; |
||
2262 | host->mmc = mmc; |
||
2263 | host->id = pdev->id; |
||
2264 | if (host->id < 0 || host->id >= 4) |
||
2265 | host->id = 0; |
||
2266 | host->error = 0; |
||
2267 | |||
2268 | host->irq = platform_get_irq(pdev, 0); |
||
2269 | if (host->irq < 0) { |
||
2270 | ret = -EINVAL; |
||
2271 | goto host_free; |
||
2272 | } |
||
2273 | |||
2274 | host->base = base; |
||
2275 | host->mclk = 0; /* mclk: the request clock of mmc sub-system */ |
||
2276 | host->hclk = hclks[hw->clk_src]; /* hclk: clock of clock source to msdc controller */ |
||
2277 | host->sclk = 0; /* sclk: the really clock after divition */ |
||
2278 | host->pm_state = PMSG_RESUME; |
||
2279 | host->suspend = 0; |
||
2280 | host->core_clkon = 0; |
||
2281 | host->card_clkon = 0; |
||
2282 | host->core_power = 0; |
||
2283 | host->power_mode = MMC_POWER_OFF; |
||
2284 | // host->card_inserted = hw->flags & MSDC_REMOVABLE ? 0 : 1; |
||
2285 | host->timeout_ns = 0; |
||
2286 | host->timeout_clks = DEFAULT_DTOC * 65536; |
||
2287 | |||
2288 | host->mrq = NULL; |
||
2289 | //init_MUTEX(&host->sem); /* we don't need to support multiple threads access */ |
||
2290 | |||
2291 | mmc_dev(mmc)->dma_mask = NULL; |
||
2292 | |||
2293 | /* using dma_alloc_coherent*/ /* todo: using 1, for all 4 slots */ |
||
2294 | host->dma.gpd = dma_alloc_coherent(&pdev->dev, |
||
2295 | MAX_GPD_NUM * sizeof(struct gpd), |
||
2296 | &host->dma.gpd_addr, GFP_KERNEL); |
||
2297 | host->dma.bd = dma_alloc_coherent(&pdev->dev, |
||
2298 | MAX_BD_NUM * sizeof(struct bd), |
||
2299 | &host->dma.bd_addr, GFP_KERNEL); |
||
2300 | if (!host->dma.gpd || !host->dma.bd) { |
||
2301 | ret = -ENOMEM; |
||
2302 | goto release_mem; |
||
2303 | } |
||
2304 | msdc_init_gpd_bd(host, &host->dma); |
||
2305 | |||
2306 | INIT_DELAYED_WORK(&host->card_delaywork, msdc_tasklet_card); |
||
2307 | spin_lock_init(&host->lock); |
||
2308 | msdc_init_hw(host); |
||
2309 | |||
2310 | /* TODO check weather flags 0 is correct, the mtk-sd driver uses |
||
2311 | * IRQF_TRIGGER_LOW | IRQF_ONESHOT for flags |
||
2312 | * |
||
2313 | * for flags 0 the trigger polarity is determined by the |
||
2314 | * device tree, but not the oneshot flag, but maybe it is also |
||
2315 | * not needed because the soc could be oneshot safe. |
||
2316 | */ |
||
2317 | ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 0, pdev->name, |
||
2318 | host); |
||
2319 | if (ret) |
||
2320 | goto release; |
||
2321 | |||
2322 | platform_set_drvdata(pdev, mmc); |
||
2323 | |||
2324 | ret = mmc_add_host(mmc); |
||
2325 | if (ret) |
||
2326 | goto release; |
||
2327 | |||
2328 | /* Config card detection pin and enable interrupts */ |
||
2329 | if (hw->flags & MSDC_CD_PIN_EN) { /* set for card */ |
||
2330 | msdc_enable_cd_irq(host, 1); |
||
2331 | } else { |
||
2332 | msdc_enable_cd_irq(host, 0); |
||
2333 | } |
||
2334 | |||
2335 | return 0; |
||
2336 | |||
2337 | release: |
||
2338 | platform_set_drvdata(pdev, NULL); |
||
2339 | msdc_deinit_hw(host); |
||
2340 | cancel_delayed_work_sync(&host->card_delaywork); |
||
2341 | |||
2342 | release_mem: |
||
2343 | if (host->dma.gpd) |
||
2344 | dma_free_coherent(&pdev->dev, MAX_GPD_NUM * sizeof(struct gpd), |
||
2345 | host->dma.gpd, host->dma.gpd_addr); |
||
2346 | if (host->dma.bd) |
||
2347 | dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct bd), |
||
2348 | host->dma.bd, host->dma.bd_addr); |
||
2349 | host_free: |
||
2350 | mmc_free_host(mmc); |
||
2351 | |||
2352 | return ret; |
||
2353 | } |
||
2354 | |||
2355 | /* 4 device share one driver, using "drvdata" to show difference */ |
||
2356 | static int msdc_drv_remove(struct platform_device *pdev) |
||
2357 | { |
||
2358 | struct mmc_host *mmc; |
||
2359 | struct msdc_host *host; |
||
2360 | |||
2361 | mmc = platform_get_drvdata(pdev); |
||
2362 | BUG_ON(!mmc); |
||
2363 | |||
2364 | host = mmc_priv(mmc); |
||
2365 | BUG_ON(!host); |
||
2366 | |||
2367 | ERR_MSG("removed !!!"); |
||
2368 | |||
2369 | platform_set_drvdata(pdev, NULL); |
||
2370 | mmc_remove_host(host->mmc); |
||
2371 | msdc_deinit_hw(host); |
||
2372 | |||
2373 | cancel_delayed_work_sync(&host->card_delaywork); |
||
2374 | |||
2375 | dma_free_coherent(&pdev->dev, MAX_GPD_NUM * sizeof(struct gpd), |
||
2376 | host->dma.gpd, host->dma.gpd_addr); |
||
2377 | dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct bd), |
||
2378 | host->dma.bd, host->dma.bd_addr); |
||
2379 | |||
2380 | mmc_free_host(host->mmc); |
||
2381 | |||
2382 | return 0; |
||
2383 | } |
||
2384 | |||
2385 | /* Fix me: Power Flow */ |
||
2386 | #ifdef CONFIG_PM |
||
2387 | |||
2388 | static void msdc_drv_pm(struct platform_device *pdev, pm_message_t state) |
||
2389 | { |
||
2390 | struct mmc_host *mmc = platform_get_drvdata(pdev); |
||
2391 | if (mmc) { |
||
2392 | struct msdc_host *host = mmc_priv(mmc); |
||
2393 | msdc_pm(state, (void *)host); |
||
2394 | } |
||
2395 | } |
||
2396 | |||
2397 | static int msdc_drv_suspend(struct platform_device *pdev, pm_message_t state) |
||
2398 | { |
||
2399 | if (state.event == PM_EVENT_SUSPEND) |
||
2400 | msdc_drv_pm(pdev, state); |
||
2401 | return 0; |
||
2402 | } |
||
2403 | |||
2404 | static int msdc_drv_resume(struct platform_device *pdev) |
||
2405 | { |
||
2406 | struct pm_message state; |
||
2407 | |||
2408 | state.event = PM_EVENT_RESUME; |
||
2409 | msdc_drv_pm(pdev, state); |
||
2410 | return 0; |
||
2411 | } |
||
2412 | #endif |
||
2413 | |||
2414 | static const struct of_device_id mt7620_sdhci_match[] = { |
||
2415 | { .compatible = "ralink,mt7620-sdhci" }, |
||
2416 | {}, |
||
2417 | }; |
||
2418 | MODULE_DEVICE_TABLE(of, mt7620_sdhci_match); |
||
2419 | |||
2420 | static struct platform_driver mt_msdc_driver = { |
||
2421 | .probe = msdc_drv_probe, |
||
2422 | .remove = msdc_drv_remove, |
||
2423 | #ifdef CONFIG_PM |
||
2424 | .suspend = msdc_drv_suspend, |
||
2425 | .resume = msdc_drv_resume, |
||
2426 | #endif |
||
2427 | .driver = { |
||
2428 | .name = DRV_NAME, |
||
2429 | .of_match_table = mt7620_sdhci_match, |
||
2430 | }, |
||
2431 | }; |
||
2432 | |||
2433 | /*--------------------------------------------------------------------------*/ |
||
2434 | /* module init/exit */ |
||
2435 | /*--------------------------------------------------------------------------*/ |
||
2436 | static int __init mt_msdc_init(void) |
||
2437 | { |
||
2438 | int ret; |
||
2439 | |||
2440 | ret = platform_driver_register(&mt_msdc_driver); |
||
2441 | if (ret) { |
||
2442 | printk(KERN_ERR DRV_NAME ": Can't register driver"); |
||
2443 | return ret; |
||
2444 | } |
||
2445 | |||
2446 | #if defined(MT6575_SD_DEBUG) |
||
2447 | msdc_debug_proc_init(); |
||
2448 | #endif |
||
2449 | return 0; |
||
2450 | } |
||
2451 | |||
2452 | static void __exit mt_msdc_exit(void) |
||
2453 | { |
||
2454 | platform_driver_unregister(&mt_msdc_driver); |
||
2455 | } |
||
2456 | |||
2457 | module_init(mt_msdc_init); |
||
2458 | module_exit(mt_msdc_exit); |
||
2459 | MODULE_LICENSE("GPL"); |
||
2460 | MODULE_DESCRIPTION("MediaTek MT6575 SD/MMC Card Driver"); |
||
2461 | MODULE_AUTHOR("Infinity Chen <infinity.chen@mediatek.com>"); |