OpenWrt – Blame information for rev 1

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1 office 1 / {
2 #address-cells = <1>;
3 #size-cells = <1>;
4 compatible = "mediatek,mt7628an-soc";
5  
6 cpus {
7 #address-cells = <1>;
8 #size-cells = <0>;
9  
10 cpu@0 {
11 compatible = "mips,mips24KEc";
12 reg = <0>;
13 };
14 };
15  
16 chosen {
17 bootargs = "console=ttyS0,57600";
18 };
19  
20 aliases {
21 serial0 = &uartlite;
22 };
23  
24 cpuintc: cpuintc {
25 #address-cells = <0>;
26 #interrupt-cells = <1>;
27 interrupt-controller;
28 compatible = "mti,cpu-interrupt-controller";
29 };
30  
31 palmbus: palmbus@10000000 {
32 compatible = "palmbus";
33 reg = <0x10000000 0x200000>;
34 ranges = <0x0 0x10000000 0x1FFFFF>;
35  
36 #address-cells = <1>;
37 #size-cells = <1>;
38  
39 sysc: sysc@0 {
40 compatible = "ralink,mt7620a-sysc", "syscon";
41 reg = <0x0 0x100>;
42 };
43  
44 watchdog: watchdog@100 {
45 compatible = "ralink,mt7628an-wdt", "mediatek,mt7621-wdt";
46 reg = <0x100 0x30>;
47  
48 resets = <&rstctrl 8>;
49 reset-names = "wdt";
50  
51 interrupt-parent = <&intc>;
52 interrupts = <24>;
53 };
54  
55 intc: intc@200 {
56 compatible = "ralink,mt7628an-intc", "ralink,rt2880-intc";
57 reg = <0x200 0x100>;
58  
59 resets = <&rstctrl 9>;
60 reset-names = "intc";
61  
62 interrupt-controller;
63 #interrupt-cells = <1>;
64  
65 interrupt-parent = <&cpuintc>;
66 interrupts = <2>;
67  
68 ralink,intc-registers = <0x9c 0xa0
69 0x6c 0xa4
70 0x80 0x78>;
71 };
72  
73 memc: memc@300 {
74 compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
75 reg = <0x300 0x100>;
76  
77 resets = <&rstctrl 20>;
78 reset-names = "mc";
79  
80 interrupt-parent = <&intc>;
81 interrupts = <3>;
82 };
83  
84 gpio@600 {
85 #address-cells = <1>;
86 #size-cells = <0>;
87  
88 compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
89 reg = <0x600 0x100>;
90  
91 interrupt-parent = <&intc>;
92 interrupts = <6>;
93  
94 gpio0: bank@0 {
95 reg = <0>;
96 compatible = "mtk,mt7621-gpio-bank";
97 gpio-controller;
98 #gpio-cells = <2>;
99 };
100  
101 gpio1: bank@1 {
102 reg = <1>;
103 compatible = "mtk,mt7621-gpio-bank";
104 gpio-controller;
105 #gpio-cells = <2>;
106 };
107  
108 gpio2: bank@2 {
109 reg = <2>;
110 compatible = "mtk,mt7621-gpio-bank";
111 gpio-controller;
112 #gpio-cells = <2>;
113 };
114 };
115  
116 i2c: i2c@900 {
117 compatible = "mediatek,mt7621-i2c";
118 reg = <0x900 0x100>;
119  
120 resets = <&rstctrl 16>;
121 reset-names = "i2c";
122  
123 #address-cells = <1>;
124 #size-cells = <0>;
125  
126 status = "disabled";
127  
128 pinctrl-names = "default";
129 pinctrl-0 = <&i2c_pins>;
130 };
131  
132 i2s: i2s@a00 {
133 compatible = "mediatek,mt7628-i2s";
134 reg = <0xa00 0x100>;
135  
136 resets = <&rstctrl 17>;
137 reset-names = "i2s";
138  
139 interrupt-parent = <&intc>;
140 interrupts = <10>;
141  
142 txdma-req = <2>;
143 rxdma-req = <3>;
144  
145 dmas = <&gdma 4>,
146 <&gdma 6>;
147 dma-names = "tx", "rx";
148  
149 status = "disabled";
150 };
151  
152 spi0: spi@b00 {
153 compatible = "ralink,mt7621-spi";
154 reg = <0xb00 0x100>;
155  
156 resets = <&rstctrl 18>;
157 reset-names = "spi";
158  
159 #address-cells = <1>;
160 #size-cells = <0>;
161  
162 pinctrl-names = "default";
163 pinctrl-0 = <&spi_pins>;
164  
165 status = "disabled";
166 };
167  
168 uartlite: uartlite@c00 {
169 compatible = "ns16550a";
170 reg = <0xc00 0x100>;
171  
172 reg-shift = <2>;
173 reg-io-width = <4>;
174 no-loopback-test;
175  
176 clock-frequency = <40000000>;
177  
178 resets = <&rstctrl 12>;
179 reset-names = "uartl";
180  
181 interrupt-parent = <&intc>;
182 interrupts = <20>;
183  
184 pinctrl-names = "default";
185 pinctrl-0 = <&uart0_pins>;
186 };
187  
188 uart1: uart1@d00 {
189 compatible = "ns16550a";
190 reg = <0xd00 0x100>;
191  
192 reg-shift = <2>;
193 reg-io-width = <4>;
194 no-loopback-test;
195  
196 clock-frequency = <40000000>;
197  
198 resets = <&rstctrl 19>;
199 reset-names = "uart1";
200  
201 interrupt-parent = <&intc>;
202 interrupts = <21>;
203  
204 pinctrl-names = "default";
205 pinctrl-0 = <&uart1_pins>;
206  
207 status = "disabled";
208 };
209  
210 uart2: uart2@e00 {
211 compatible = "ns16550a";
212 reg = <0xe00 0x100>;
213  
214 reg-shift = <2>;
215 reg-io-width = <4>;
216 no-loopback-test;
217  
218 clock-frequency = <40000000>;
219  
220 resets = <&rstctrl 20>;
221 reset-names = "uart2";
222  
223 interrupt-parent = <&intc>;
224 interrupts = <22>;
225  
226 pinctrl-names = "default";
227 pinctrl-0 = <&uart2_pins>;
228  
229 status = "disabled";
230 };
231  
232 pwm: pwm@5000 {
233 compatible = "mediatek,mt7628-pwm";
234 reg = <0x5000 0x1000>;
235  
236 resets = <&rstctrl 31>;
237 reset-names = "pwm";
238  
239 pinctrl-names = "default";
240 pinctrl-0 = <&pwm0_pins>, <&pwm1_pins>;
241  
242 status = "disabled";
243 };
244  
245 pcm: pcm@2000 {
246 compatible = "ralink,mt7620a-pcm";
247 reg = <0x2000 0x800>;
248  
249 resets = <&rstctrl 11>;
250 reset-names = "pcm";
251  
252 interrupt-parent = <&intc>;
253 interrupts = <4>;
254  
255 status = "disabled";
256 };
257  
258 gdma: gdma@2800 {
259 compatible = "ralink,rt3883-gdma";
260 reg = <0x2800 0x800>;
261  
262 resets = <&rstctrl 14>;
263 reset-names = "dma";
264  
265 interrupt-parent = <&intc>;
266 interrupts = <7>;
267  
268 #dma-cells = <1>;
269 #dma-channels = <16>;
270 #dma-requests = <16>;
271  
272 status = "disabled";
273 };
274 };
275  
276 pinctrl: pinctrl {
277 compatible = "ralink,rt2880-pinmux";
278 pinctrl-names = "default";
279 pinctrl-0 = <&state_default>;
280  
281 state_default: pinctrl0 {
282 };
283  
284 spi_pins: spi_pins {
285 spi_pins {
286 ralink,group = "spi";
287 ralink,function = "spi";
288 };
289 };
290  
291 spi_cs1_pins: spi_cs1 {
292 spi_cs1 {
293 ralink,group = "spi cs1";
294 ralink,function = "spi cs1";
295 };
296 };
297  
298 i2c_pins: i2c_pins {
299 i2c_pins {
300 ralink,group = "i2c";
301 ralink,function = "i2c";
302 };
303 };
304  
305 i2s_pins: i2s {
306 i2s {
307 ralink,group = "i2s";
308 ralink,function = "i2s";
309 };
310 };
311  
312 uart0_pins: uartlite {
313 uartlite {
314 ralink,group = "uart0";
315 ralink,function = "uart0";
316 };
317 };
318  
319 uart1_pins: uart1 {
320 uart1 {
321 ralink,group = "uart1";
322 ralink,function = "uart1";
323 };
324 };
325  
326 uart2_pins: uart2 {
327 uart2 {
328 ralink,group = "uart2";
329 ralink,function = "uart2";
330 };
331 };
332  
333 sdxc_pins: sdxc {
334 sdxc {
335 ralink,group = "sdmode";
336 ralink,function = "sdxc";
337 };
338 };
339  
340 pwm0_pins: pwm0 {
341 pwm0 {
342 ralink,group = "pwm0";
343 ralink,function = "pwm0";
344 };
345 };
346  
347 pwm1_pins: pwm1 {
348 pwm1 {
349 ralink,group = "pwm1";
350 ralink,function = "pwm1";
351 };
352 };
353  
354 pcm_i2s_pins: pcm_i2s {
355 pcm_i2s {
356 ralink,group = "i2s";
357 ralink,function = "pcm";
358 };
359 };
360  
361 refclk_pins: refclk {
362 refclk {
363 ralink,group = "refclk";
364 ralink,function = "refclk";
365 };
366 };
367 };
368  
369 rstctrl: rstctrl {
370 compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
371 #reset-cells = <1>;
372 };
373  
374 clkctrl: clkctrl {
375 compatible = "ralink,rt2880-clock";
376 #clock-cells = <1>;
377 };
378  
379 usbphy: usbphy@10120000 {
380 compatible = "mediatek,mt7628-usbphy", "mediatek,mt7620-usbphy";
381 reg = <0x10120000 0x1000>;
382 #phy-cells = <0>;
383  
384 ralink,sysctl = <&sysc>;
385 resets = <&rstctrl 22 &rstctrl 25>;
386 reset-names = "host", "device";
387 clocks = <&clkctrl 22 &clkctrl 25>;
388 clock-names = "host", "device";
389 };
390  
391 sdhci: sdhci@10130000 {
392 compatible = "ralink,mt7620-sdhci";
393 reg = <0x10130000 0x4000>;
394  
395 interrupt-parent = <&intc>;
396 interrupts = <14>;
397  
398 pinctrl-names = "default";
399 pinctrl-0 = <&sdxc_pins>;
400  
401 status = "disabled";
402 };
403  
404 ehci: ehci@101c0000 {
405 #address-cells = <1>;
406 #size-cells = <0>;
407 compatible = "generic-ehci";
408 reg = <0x101c0000 0x1000>;
409  
410 phys = <&usbphy>;
411 phy-names = "usb";
412  
413 interrupt-parent = <&intc>;
414 interrupts = <18>;
415  
416 ehci_port1: port@1 {
417 reg = <1>;
418 #trigger-source-cells = <0>;
419 };
420 };
421  
422 ohci: ohci@101c1000 {
423 #address-cells = <1>;
424 #size-cells = <0>;
425 compatible = "generic-ohci";
426 reg = <0x101c1000 0x1000>;
427  
428 phys = <&usbphy>;
429 phy-names = "usb";
430  
431 interrupt-parent = <&intc>;
432 interrupts = <18>;
433  
434 ohci_port1: port@1 {
435 reg = <1>;
436 #trigger-source-cells = <0>;
437 };
438 };
439  
440 ethernet: ethernet@10100000 {
441 compatible = "ralink,rt5350-eth";
442 reg = <0x10100000 0x10000>;
443  
444 interrupt-parent = <&cpuintc>;
445 interrupts = <5>;
446  
447 resets = <&rstctrl 21 &rstctrl 23>;
448 reset-names = "fe", "esw";
449  
450 mediatek,switch = <&esw>;
451 };
452  
453 esw: esw@10110000 {
454 compatible = "mediatek,mt7628-esw", "ralink,rt3050-esw";
455 reg = <0x10110000 0x8000>;
456  
457 resets = <&rstctrl 23>;
458 reset-names = "esw";
459  
460 interrupt-parent = <&intc>;
461 interrupts = <17>;
462 };
463  
464 pcie: pcie@10140000 {
465 compatible = "mediatek,mt7620-pci";
466 reg = <0x10140000 0x100
467 0x10142000 0x100>;
468  
469 #address-cells = <3>;
470 #size-cells = <2>;
471  
472 interrupt-parent = <&cpuintc>;
473 interrupts = <4>;
474  
475 resets = <&rstctrl 26 &rstctrl 27>;
476 reset-names = "pcie0", "pcie1";
477 clocks = <&clkctrl 26 &clkctrl 27>;
478 clock-names = "pcie0", "pcie1";
479  
480 status = "disabled";
481  
482 device_type = "pci";
483  
484 bus-range = <0 255>;
485 ranges = <
486 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
487 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
488 >;
489  
490 pcie0: pcie@0,0 {
491 reg = <0x0000 0 0 0 0>;
492  
493 #address-cells = <3>;
494 #size-cells = <2>;
495  
496 device_type = "pci";
497  
498 ranges;
499 };
500 };
501  
502 wmac: wmac@10300000 {
503 compatible = "mediatek,mt7628-wmac";
504 reg = <0x10300000 0x100000>;
505  
506 interrupt-parent = <&cpuintc>;
507 interrupts = <6>;
508  
509 status = "disabled";
510  
511 mediatek,mtd-eeprom = <&factory 0x0000>;
512 };
513 };