OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | / { |
2 | #address-cells = <1>; |
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3 | #size-cells = <1>; |
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4 | compatible = "mediatek,mt7628an-soc"; |
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5 | |||
6 | cpus { |
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7 | #address-cells = <1>; |
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8 | #size-cells = <0>; |
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9 | |||
10 | cpu@0 { |
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11 | compatible = "mips,mips24KEc"; |
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12 | reg = <0>; |
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13 | }; |
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14 | }; |
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15 | |||
16 | chosen { |
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17 | bootargs = "console=ttyS0,57600"; |
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18 | }; |
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19 | |||
20 | aliases { |
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21 | serial0 = &uartlite; |
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22 | }; |
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23 | |||
24 | cpuintc: cpuintc { |
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25 | #address-cells = <0>; |
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26 | #interrupt-cells = <1>; |
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27 | interrupt-controller; |
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28 | compatible = "mti,cpu-interrupt-controller"; |
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29 | }; |
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30 | |||
31 | palmbus: palmbus@10000000 { |
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32 | compatible = "palmbus"; |
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33 | reg = <0x10000000 0x200000>; |
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34 | ranges = <0x0 0x10000000 0x1FFFFF>; |
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35 | |||
36 | #address-cells = <1>; |
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37 | #size-cells = <1>; |
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38 | |||
39 | sysc: sysc@0 { |
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40 | compatible = "ralink,mt7620a-sysc", "syscon"; |
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41 | reg = <0x0 0x100>; |
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42 | }; |
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43 | |||
44 | watchdog: watchdog@100 { |
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45 | compatible = "ralink,mt7628an-wdt", "mediatek,mt7621-wdt"; |
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46 | reg = <0x100 0x30>; |
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47 | |||
48 | resets = <&rstctrl 8>; |
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49 | reset-names = "wdt"; |
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50 | |||
51 | interrupt-parent = <&intc>; |
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52 | interrupts = <24>; |
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53 | }; |
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54 | |||
55 | intc: intc@200 { |
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56 | compatible = "ralink,mt7628an-intc", "ralink,rt2880-intc"; |
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57 | reg = <0x200 0x100>; |
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58 | |||
59 | resets = <&rstctrl 9>; |
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60 | reset-names = "intc"; |
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61 | |||
62 | interrupt-controller; |
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63 | #interrupt-cells = <1>; |
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64 | |||
65 | interrupt-parent = <&cpuintc>; |
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66 | interrupts = <2>; |
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67 | |||
68 | ralink,intc-registers = <0x9c 0xa0 |
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69 | 0x6c 0xa4 |
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70 | 0x80 0x78>; |
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71 | }; |
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72 | |||
73 | memc: memc@300 { |
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74 | compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc"; |
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75 | reg = <0x300 0x100>; |
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76 | |||
77 | resets = <&rstctrl 20>; |
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78 | reset-names = "mc"; |
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79 | |||
80 | interrupt-parent = <&intc>; |
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81 | interrupts = <3>; |
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82 | }; |
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83 | |||
84 | gpio@600 { |
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85 | #address-cells = <1>; |
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86 | #size-cells = <0>; |
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87 | |||
88 | compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio"; |
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89 | reg = <0x600 0x100>; |
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90 | |||
91 | interrupt-parent = <&intc>; |
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92 | interrupts = <6>; |
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93 | |||
94 | gpio0: bank@0 { |
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95 | reg = <0>; |
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96 | compatible = "mtk,mt7621-gpio-bank"; |
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97 | gpio-controller; |
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98 | #gpio-cells = <2>; |
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99 | }; |
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100 | |||
101 | gpio1: bank@1 { |
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102 | reg = <1>; |
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103 | compatible = "mtk,mt7621-gpio-bank"; |
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104 | gpio-controller; |
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105 | #gpio-cells = <2>; |
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106 | }; |
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107 | |||
108 | gpio2: bank@2 { |
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109 | reg = <2>; |
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110 | compatible = "mtk,mt7621-gpio-bank"; |
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111 | gpio-controller; |
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112 | #gpio-cells = <2>; |
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113 | }; |
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114 | }; |
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115 | |||
116 | i2c: i2c@900 { |
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117 | compatible = "mediatek,mt7621-i2c"; |
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118 | reg = <0x900 0x100>; |
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119 | |||
120 | resets = <&rstctrl 16>; |
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121 | reset-names = "i2c"; |
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122 | |||
123 | #address-cells = <1>; |
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124 | #size-cells = <0>; |
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125 | |||
126 | status = "disabled"; |
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127 | |||
128 | pinctrl-names = "default"; |
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129 | pinctrl-0 = <&i2c_pins>; |
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130 | }; |
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131 | |||
132 | i2s: i2s@a00 { |
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133 | compatible = "mediatek,mt7628-i2s"; |
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134 | reg = <0xa00 0x100>; |
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135 | |||
136 | resets = <&rstctrl 17>; |
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137 | reset-names = "i2s"; |
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138 | |||
139 | interrupt-parent = <&intc>; |
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140 | interrupts = <10>; |
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141 | |||
142 | txdma-req = <2>; |
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143 | rxdma-req = <3>; |
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144 | |||
145 | dmas = <&gdma 4>, |
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146 | <&gdma 6>; |
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147 | dma-names = "tx", "rx"; |
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148 | |||
149 | status = "disabled"; |
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150 | }; |
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151 | |||
152 | spi0: spi@b00 { |
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153 | compatible = "ralink,mt7621-spi"; |
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154 | reg = <0xb00 0x100>; |
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155 | |||
156 | resets = <&rstctrl 18>; |
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157 | reset-names = "spi"; |
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158 | |||
159 | #address-cells = <1>; |
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160 | #size-cells = <0>; |
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161 | |||
162 | pinctrl-names = "default"; |
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163 | pinctrl-0 = <&spi_pins>; |
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164 | |||
165 | status = "disabled"; |
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166 | }; |
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167 | |||
168 | uartlite: uartlite@c00 { |
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169 | compatible = "ns16550a"; |
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170 | reg = <0xc00 0x100>; |
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171 | |||
172 | reg-shift = <2>; |
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173 | reg-io-width = <4>; |
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174 | no-loopback-test; |
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175 | |||
176 | clock-frequency = <40000000>; |
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177 | |||
178 | resets = <&rstctrl 12>; |
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179 | reset-names = "uartl"; |
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180 | |||
181 | interrupt-parent = <&intc>; |
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182 | interrupts = <20>; |
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183 | |||
184 | pinctrl-names = "default"; |
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185 | pinctrl-0 = <&uart0_pins>; |
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186 | }; |
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187 | |||
188 | uart1: uart1@d00 { |
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189 | compatible = "ns16550a"; |
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190 | reg = <0xd00 0x100>; |
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191 | |||
192 | reg-shift = <2>; |
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193 | reg-io-width = <4>; |
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194 | no-loopback-test; |
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195 | |||
196 | clock-frequency = <40000000>; |
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197 | |||
198 | resets = <&rstctrl 19>; |
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199 | reset-names = "uart1"; |
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200 | |||
201 | interrupt-parent = <&intc>; |
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202 | interrupts = <21>; |
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203 | |||
204 | pinctrl-names = "default"; |
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205 | pinctrl-0 = <&uart1_pins>; |
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206 | |||
207 | status = "disabled"; |
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208 | }; |
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209 | |||
210 | uart2: uart2@e00 { |
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211 | compatible = "ns16550a"; |
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212 | reg = <0xe00 0x100>; |
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213 | |||
214 | reg-shift = <2>; |
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215 | reg-io-width = <4>; |
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216 | no-loopback-test; |
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217 | |||
218 | clock-frequency = <40000000>; |
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219 | |||
220 | resets = <&rstctrl 20>; |
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221 | reset-names = "uart2"; |
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222 | |||
223 | interrupt-parent = <&intc>; |
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224 | interrupts = <22>; |
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225 | |||
226 | pinctrl-names = "default"; |
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227 | pinctrl-0 = <&uart2_pins>; |
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228 | |||
229 | status = "disabled"; |
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230 | }; |
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231 | |||
232 | pwm: pwm@5000 { |
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233 | compatible = "mediatek,mt7628-pwm"; |
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234 | reg = <0x5000 0x1000>; |
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235 | |||
236 | resets = <&rstctrl 31>; |
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237 | reset-names = "pwm"; |
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238 | |||
239 | pinctrl-names = "default"; |
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240 | pinctrl-0 = <&pwm0_pins>, <&pwm1_pins>; |
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241 | |||
242 | status = "disabled"; |
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243 | }; |
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244 | |||
245 | pcm: pcm@2000 { |
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246 | compatible = "ralink,mt7620a-pcm"; |
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247 | reg = <0x2000 0x800>; |
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248 | |||
249 | resets = <&rstctrl 11>; |
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250 | reset-names = "pcm"; |
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251 | |||
252 | interrupt-parent = <&intc>; |
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253 | interrupts = <4>; |
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254 | |||
255 | status = "disabled"; |
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256 | }; |
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257 | |||
258 | gdma: gdma@2800 { |
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259 | compatible = "ralink,rt3883-gdma"; |
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260 | reg = <0x2800 0x800>; |
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261 | |||
262 | resets = <&rstctrl 14>; |
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263 | reset-names = "dma"; |
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264 | |||
265 | interrupt-parent = <&intc>; |
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266 | interrupts = <7>; |
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267 | |||
268 | #dma-cells = <1>; |
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269 | #dma-channels = <16>; |
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270 | #dma-requests = <16>; |
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271 | |||
272 | status = "disabled"; |
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273 | }; |
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274 | }; |
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275 | |||
276 | pinctrl: pinctrl { |
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277 | compatible = "ralink,rt2880-pinmux"; |
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278 | pinctrl-names = "default"; |
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279 | pinctrl-0 = <&state_default>; |
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280 | |||
281 | state_default: pinctrl0 { |
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282 | }; |
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283 | |||
284 | spi_pins: spi_pins { |
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285 | spi_pins { |
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286 | ralink,group = "spi"; |
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287 | ralink,function = "spi"; |
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288 | }; |
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289 | }; |
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290 | |||
291 | spi_cs1_pins: spi_cs1 { |
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292 | spi_cs1 { |
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293 | ralink,group = "spi cs1"; |
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294 | ralink,function = "spi cs1"; |
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295 | }; |
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296 | }; |
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297 | |||
298 | i2c_pins: i2c_pins { |
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299 | i2c_pins { |
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300 | ralink,group = "i2c"; |
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301 | ralink,function = "i2c"; |
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302 | }; |
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303 | }; |
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304 | |||
305 | i2s_pins: i2s { |
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306 | i2s { |
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307 | ralink,group = "i2s"; |
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308 | ralink,function = "i2s"; |
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309 | }; |
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310 | }; |
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311 | |||
312 | uart0_pins: uartlite { |
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313 | uartlite { |
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314 | ralink,group = "uart0"; |
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315 | ralink,function = "uart0"; |
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316 | }; |
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317 | }; |
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318 | |||
319 | uart1_pins: uart1 { |
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320 | uart1 { |
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321 | ralink,group = "uart1"; |
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322 | ralink,function = "uart1"; |
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323 | }; |
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324 | }; |
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325 | |||
326 | uart2_pins: uart2 { |
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327 | uart2 { |
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328 | ralink,group = "uart2"; |
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329 | ralink,function = "uart2"; |
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330 | }; |
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331 | }; |
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332 | |||
333 | sdxc_pins: sdxc { |
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334 | sdxc { |
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335 | ralink,group = "sdmode"; |
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336 | ralink,function = "sdxc"; |
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337 | }; |
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338 | }; |
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339 | |||
340 | pwm0_pins: pwm0 { |
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341 | pwm0 { |
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342 | ralink,group = "pwm0"; |
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343 | ralink,function = "pwm0"; |
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344 | }; |
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345 | }; |
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346 | |||
347 | pwm1_pins: pwm1 { |
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348 | pwm1 { |
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349 | ralink,group = "pwm1"; |
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350 | ralink,function = "pwm1"; |
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351 | }; |
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352 | }; |
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353 | |||
354 | pcm_i2s_pins: pcm_i2s { |
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355 | pcm_i2s { |
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356 | ralink,group = "i2s"; |
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357 | ralink,function = "pcm"; |
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358 | }; |
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359 | }; |
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360 | |||
361 | refclk_pins: refclk { |
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362 | refclk { |
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363 | ralink,group = "refclk"; |
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364 | ralink,function = "refclk"; |
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365 | }; |
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366 | }; |
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367 | }; |
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368 | |||
369 | rstctrl: rstctrl { |
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370 | compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset"; |
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371 | #reset-cells = <1>; |
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372 | }; |
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373 | |||
374 | clkctrl: clkctrl { |
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375 | compatible = "ralink,rt2880-clock"; |
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376 | #clock-cells = <1>; |
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377 | }; |
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378 | |||
379 | usbphy: usbphy@10120000 { |
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380 | compatible = "mediatek,mt7628-usbphy", "mediatek,mt7620-usbphy"; |
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381 | reg = <0x10120000 0x1000>; |
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382 | #phy-cells = <0>; |
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383 | |||
384 | ralink,sysctl = <&sysc>; |
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385 | resets = <&rstctrl 22 &rstctrl 25>; |
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386 | reset-names = "host", "device"; |
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387 | clocks = <&clkctrl 22 &clkctrl 25>; |
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388 | clock-names = "host", "device"; |
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389 | }; |
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390 | |||
391 | sdhci: sdhci@10130000 { |
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392 | compatible = "ralink,mt7620-sdhci"; |
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393 | reg = <0x10130000 0x4000>; |
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394 | |||
395 | interrupt-parent = <&intc>; |
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396 | interrupts = <14>; |
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397 | |||
398 | pinctrl-names = "default"; |
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399 | pinctrl-0 = <&sdxc_pins>; |
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400 | |||
401 | status = "disabled"; |
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402 | }; |
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403 | |||
404 | ehci: ehci@101c0000 { |
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405 | #address-cells = <1>; |
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406 | #size-cells = <0>; |
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407 | compatible = "generic-ehci"; |
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408 | reg = <0x101c0000 0x1000>; |
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409 | |||
410 | phys = <&usbphy>; |
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411 | phy-names = "usb"; |
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412 | |||
413 | interrupt-parent = <&intc>; |
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414 | interrupts = <18>; |
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415 | |||
416 | ehci_port1: port@1 { |
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417 | reg = <1>; |
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418 | #trigger-source-cells = <0>; |
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419 | }; |
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420 | }; |
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421 | |||
422 | ohci: ohci@101c1000 { |
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423 | #address-cells = <1>; |
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424 | #size-cells = <0>; |
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425 | compatible = "generic-ohci"; |
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426 | reg = <0x101c1000 0x1000>; |
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427 | |||
428 | phys = <&usbphy>; |
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429 | phy-names = "usb"; |
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430 | |||
431 | interrupt-parent = <&intc>; |
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432 | interrupts = <18>; |
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433 | |||
434 | ohci_port1: port@1 { |
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435 | reg = <1>; |
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436 | #trigger-source-cells = <0>; |
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437 | }; |
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438 | }; |
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439 | |||
440 | ethernet: ethernet@10100000 { |
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441 | compatible = "ralink,rt5350-eth"; |
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442 | reg = <0x10100000 0x10000>; |
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443 | |||
444 | interrupt-parent = <&cpuintc>; |
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445 | interrupts = <5>; |
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446 | |||
447 | resets = <&rstctrl 21 &rstctrl 23>; |
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448 | reset-names = "fe", "esw"; |
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449 | |||
450 | mediatek,switch = <&esw>; |
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451 | }; |
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452 | |||
453 | esw: esw@10110000 { |
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454 | compatible = "mediatek,mt7628-esw", "ralink,rt3050-esw"; |
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455 | reg = <0x10110000 0x8000>; |
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456 | |||
457 | resets = <&rstctrl 23>; |
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458 | reset-names = "esw"; |
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459 | |||
460 | interrupt-parent = <&intc>; |
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461 | interrupts = <17>; |
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462 | }; |
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463 | |||
464 | pcie: pcie@10140000 { |
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465 | compatible = "mediatek,mt7620-pci"; |
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466 | reg = <0x10140000 0x100 |
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467 | 0x10142000 0x100>; |
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468 | |||
469 | #address-cells = <3>; |
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470 | #size-cells = <2>; |
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471 | |||
472 | interrupt-parent = <&cpuintc>; |
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473 | interrupts = <4>; |
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474 | |||
475 | resets = <&rstctrl 26 &rstctrl 27>; |
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476 | reset-names = "pcie0", "pcie1"; |
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477 | clocks = <&clkctrl 26 &clkctrl 27>; |
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478 | clock-names = "pcie0", "pcie1"; |
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479 | |||
480 | status = "disabled"; |
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481 | |||
482 | device_type = "pci"; |
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483 | |||
484 | bus-range = <0 255>; |
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485 | ranges = < |
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486 | 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */ |
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487 | 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */ |
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488 | >; |
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489 | |||
490 | pcie0: pcie@0,0 { |
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491 | reg = <0x0000 0 0 0 0>; |
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492 | |||
493 | #address-cells = <3>; |
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494 | #size-cells = <2>; |
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495 | |||
496 | device_type = "pci"; |
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497 | |||
498 | ranges; |
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499 | }; |
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500 | }; |
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501 | |||
502 | wmac: wmac@10300000 { |
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503 | compatible = "mediatek,mt7628-wmac"; |
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504 | reg = <0x10300000 0x100000>; |
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505 | |||
506 | interrupt-parent = <&cpuintc>; |
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507 | interrupts = <6>; |
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508 | |||
509 | status = "disabled"; |
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510 | |||
511 | mediatek,mtd-eeprom = <&factory 0x0000>; |
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512 | }; |
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513 | }; |