OpenWrt – Blame information for rev 1
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1 | office | 1 | From 56466f505f58f44b69feb7eaed3b506842800456 Mon Sep 17 00:00:00 2001 |
2 | From: Ionela Voinescu <ionela.voinescu@imgtec.com> |
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3 | Date: Tue, 1 Mar 2016 17:49:45 +0000 |
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4 | Subject: spi: img-spfi: RX maximum burst size for DMA is 8 |
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5 | |||
6 | The depth of the FIFOs is 16 bytes. The DMA request line is tied |
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7 | to the half full/empty (depending on the use of the TX or RX FIFO) |
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8 | threshold. For the TX FIFO, if you set a burst size of 8 (equal to |
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9 | half the depth) the first burst goes into FIFO without any issues, |
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10 | but due the latency involved (the time the data leaves the DMA |
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11 | engine to the time it arrives at the FIFO), the DMA might trigger |
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12 | another burst of 8. But given that there is no space for 2 additonal |
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13 | bursts of 8, this would result in a failure. Therefore, we have to |
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14 | keep the burst size for TX to 4 to accomodate for an extra burst. |
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15 | |||
16 | For the read (RX) scenario, the DMA request line goes high when |
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17 | there is at least 8 entries in the FIFO (half full), and we can |
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18 | program the burst size to be 8 because the risk of accidental burst |
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19 | does not exist. The DMA engine will not trigger another read until |
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20 | the read data for all the burst it has sent out has been received. |
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21 | |||
22 | While here, move the burst size setting outside of the if/else branches |
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23 | as they have the same value for both 8 and 32 bit data widths. |
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24 | |||
25 | Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> |
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26 | --- |
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27 | drivers/spi/spi-img-spfi.c | 6 ++---- |
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28 | 1 file changed, 2 insertions(+), 4 deletions(-) |
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29 | |||
30 | --- a/drivers/spi/spi-img-spfi.c |
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31 | +++ b/drivers/spi/spi-img-spfi.c |
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32 | @@ -346,12 +346,11 @@ static int img_spfi_start_dma(struct spi |
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33 | if (xfer->len % 4 == 0) { |
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34 | rxconf.src_addr = spfi->phys + SPFI_RX_32BIT_VALID_DATA; |
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35 | rxconf.src_addr_width = 4; |
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36 | - rxconf.src_maxburst = 4; |
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37 | } else { |
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38 | rxconf.src_addr = spfi->phys + SPFI_RX_8BIT_VALID_DATA; |
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39 | rxconf.src_addr_width = 1; |
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40 | - rxconf.src_maxburst = 4; |
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41 | } |
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42 | + rxconf.src_maxburst = 8; |
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43 | dmaengine_slave_config(spfi->rx_ch, &rxconf); |
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44 | |||
45 | rxdesc = dmaengine_prep_slave_sg(spfi->rx_ch, xfer->rx_sg.sgl, |
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46 | @@ -370,12 +369,11 @@ static int img_spfi_start_dma(struct spi |
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47 | if (xfer->len % 4 == 0) { |
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48 | txconf.dst_addr = spfi->phys + SPFI_TX_32BIT_VALID_DATA; |
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49 | txconf.dst_addr_width = 4; |
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50 | - txconf.dst_maxburst = 4; |
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51 | } else { |
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52 | txconf.dst_addr = spfi->phys + SPFI_TX_8BIT_VALID_DATA; |
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53 | txconf.dst_addr_width = 1; |
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54 | - txconf.dst_maxburst = 4; |
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55 | } |
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56 | + txconf.dst_maxburst = 4; |
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57 | dmaengine_slave_config(spfi->tx_ch, &txconf); |
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58 | |||
59 | txdesc = dmaengine_prep_slave_sg(spfi->tx_ch, xfer->tx_sg.sgl, |