OpenWrt – Blame information for rev 1
?pathlinks?
Rev | Author | Line No. | Line |
---|---|---|---|
1 | office | 1 | From 552ed4955c1fee1109bf5ba137dc35a411a1448c Mon Sep 17 00:00:00 2001 |
2 | From: Daniel Golle <daniel@makrotopia.org> |
||
3 | Date: Fri, 1 Jun 2018 02:41:15 +0200 |
||
4 | Subject: [PATCH] arm: ox820: remove left-overs |
||
5 | |||
6 | Signed-off-by: Daniel Golle <daniel@makrotopia.org> |
||
7 | --- |
||
8 | drivers/clk/clk-oxnas.c | 2 -- |
||
9 | include/dt-bindings/clock/oxsemi,ox820.h | 32 +++++++++++------------- |
||
10 | 2 files changed, 14 insertions(+), 20 deletions(-) |
||
11 | |||
12 | --- a/drivers/clk/clk-oxnas.c |
||
13 | +++ b/drivers/clk/clk-oxnas.c |
||
14 | @@ -40,8 +40,6 @@ struct oxnas_stdclk_data { |
||
15 | struct clk_hw_onecell_data *onecell_data; |
||
16 | struct clk_oxnas_gate **gates; |
||
17 | unsigned int ngates; |
||
18 | - struct clk_oxnas_pll **plls; |
||
19 | - unsigned int nplls; |
||
20 | }; |
||
21 | |||
22 | /* Regmap offsets */ |
||
23 | --- a/include/dt-bindings/clock/oxsemi,ox820.h |
||
24 | +++ b/include/dt-bindings/clock/oxsemi,ox820.h |
||
25 | @@ -17,24 +17,20 @@ |
||
26 | #ifndef DT_CLOCK_OXSEMI_OX820_H |
||
27 | #define DT_CLOCK_OXSEMI_OX820_H |
||
28 | |||
29 | -/* PLLs */ |
||
30 | -#define CLK_820_PLLA 0 |
||
31 | -#define CLK_820_PLLB 1 |
||
32 | - |
||
33 | /* Gate Clocks */ |
||
34 | -#define CLK_820_LEON 2 |
||
35 | -#define CLK_820_DMA_SGDMA 3 |
||
36 | -#define CLK_820_CIPHER 4 |
||
37 | -#define CLK_820_SD 5 |
||
38 | -#define CLK_820_SATA 6 |
||
39 | -#define CLK_820_AUDIO 7 |
||
40 | -#define CLK_820_USBMPH 8 |
||
41 | -#define CLK_820_ETHA 9 |
||
42 | -#define CLK_820_PCIEA 10 |
||
43 | -#define CLK_820_NAND 11 |
||
44 | -#define CLK_820_PCIEB 12 |
||
45 | -#define CLK_820_ETHB 13 |
||
46 | -#define CLK_820_REF600 14 |
||
47 | -#define CLK_820_USBDEV 15 |
||
48 | +#define CLK_820_LEON 0 |
||
49 | +#define CLK_820_DMA_SGDMA 1 |
||
50 | +#define CLK_820_CIPHER 2 |
||
51 | +#define CLK_820_SD 3 |
||
52 | +#define CLK_820_SATA 4 |
||
53 | +#define CLK_820_AUDIO 5 |
||
54 | +#define CLK_820_USBMPH 6 |
||
55 | +#define CLK_820_ETHA 7 |
||
56 | +#define CLK_820_PCIEA 8 |
||
57 | +#define CLK_820_NAND 9 |
||
58 | +#define CLK_820_PCIEB 10 |
||
59 | +#define CLK_820_ETHB 11 |
||
60 | +#define CLK_820_REF600 12 |
||
61 | +#define CLK_820_USBDEV 13 |
||
62 | |||
63 | #endif /* DT_CLOCK_OXSEMI_OX820_H */ |