OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | /* |
2 | * PCIe driver for PLX NAS782X SoCs |
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3 | * |
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4 | * This file is licensed under the terms of the GNU General Public |
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5 | * License version 2. This program is licensed "as is" without any |
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6 | * warranty of any kind, whether express or implied. |
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7 | */ |
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8 | |||
9 | #include <linux/kernel.h> |
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10 | #include <linux/pci.h> |
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11 | #include <linux/clk.h> |
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12 | #include <linux/module.h> |
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13 | #include <linux/mbus.h> |
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14 | #include <linux/slab.h> |
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15 | #include <linux/platform_device.h> |
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16 | #include <linux/of_address.h> |
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17 | #include <linux/of_pci.h> |
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18 | #include <linux/of_irq.h> |
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19 | #include <linux/of_platform.h> |
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20 | #include <linux/of_gpio.h> |
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21 | #include <linux/gpio.h> |
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22 | #include <linux/delay.h> |
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23 | #include <linux/clk.h> |
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24 | #include <linux/reset.h> |
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25 | #include <linux/io.h> |
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26 | #include <linux/sizes.h> |
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27 | |||
28 | #define OXNAS_UART1_BASE 0x44200000 |
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29 | #define OXNAS_UART1_SIZE SZ_32 |
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30 | #define OXNAS_UART1_BASE_VA 0xF0000000 |
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31 | |||
32 | #define OXNAS_UART2_BASE 0x44300000 |
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33 | #define OXNAS_UART2_SIZE SZ_32 |
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34 | |||
35 | #define OXNAS_PERCPU_BASE 0x47000000 |
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36 | #define OXNAS_PERCPU_SIZE SZ_8K |
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37 | #define OXNAS_PERCPU_BASE_VA 0xF0002000 |
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38 | |||
39 | #define OXNAS_SYSCRTL_BASE 0x44E00000 |
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40 | #define OXNAS_SYSCRTL_SIZE SZ_4K |
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41 | #define OXNAS_SYSCRTL_BASE_VA 0xF0004000 |
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42 | |||
43 | #define OXNAS_SECCRTL_BASE 0x44F00000 |
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44 | #define OXNAS_SECCRTL_SIZE SZ_4K |
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45 | #define OXNAS_SECCRTL_BASE_VA 0xF0005000 |
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46 | |||
47 | #define OXNAS_RPSA_BASE 0x44400000 |
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48 | #define OXNAS_RPSA_SIZE SZ_4K |
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49 | #define OXNAS_RPSA_BASE_VA 0xF0006000 |
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50 | |||
51 | #define OXNAS_RPSC_BASE 0x44500000 |
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52 | #define OXNAS_RPSC_SIZE SZ_4K |
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53 | #define OXNAS_RPSC_BASE_VA 0xF0007000 |
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54 | |||
55 | |||
56 | /* |
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57 | * Location of flags and vectors in SRAM for controlling the booting of the |
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58 | * secondary ARM11 processors. |
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59 | */ |
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60 | |||
61 | #define OXNAS_SCU_BASE_VA OXNAS_PERCPU_BASE_VA |
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62 | #define OXNAS_GICN_BASE_VA(n) (OXNAS_PERCPU_BASE_VA + 0x200 + n*0x100) |
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63 | |||
64 | #define HOLDINGPEN_CPU IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc8) |
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65 | #define HOLDINGPEN_LOCATION IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc4) |
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66 | |||
67 | /** |
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68 | * System block reset and clock control |
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69 | */ |
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70 | #define SYS_CTRL_PCI_STAT IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x20) |
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71 | #define SYSCTRL_CLK_STAT IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x24) |
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72 | #define SYS_CTRL_CLK_SET_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x2C) |
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73 | #define SYS_CTRL_CLK_CLR_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x30) |
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74 | #define SYS_CTRL_RST_SET_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x34) |
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75 | #define SYS_CTRL_RST_CLR_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x38) |
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76 | |||
77 | #define SYS_CTRL_PLLSYS_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x48) |
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78 | #define SYS_CTRL_CLK_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x64) |
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79 | #define SYS_CTRL_PLLSYS_KEY_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x6C) |
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80 | #define SYS_CTRL_GMAC_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x78) |
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81 | #define SYS_CTRL_GMAC_DELAY_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x100) |
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82 | |||
83 | /* Scratch registers */ |
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84 | #define SYS_CTRL_SCRATCHWORD0 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc4) |
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85 | #define SYS_CTRL_SCRATCHWORD1 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc8) |
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86 | #define SYS_CTRL_SCRATCHWORD2 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xcc) |
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87 | #define SYS_CTRL_SCRATCHWORD3 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xd0) |
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88 | |||
89 | #define SYS_CTRL_PLLA_CTRL0 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1F0) |
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90 | #define SYS_CTRL_PLLA_CTRL1 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1F4) |
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91 | #define SYS_CTRL_PLLA_CTRL2 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1F8) |
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92 | #define SYS_CTRL_PLLA_CTRL3 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1FC) |
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93 | |||
94 | #define SYS_CTRL_USBHSMPH_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x40) |
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95 | #define SYS_CTRL_USBHSMPH_STAT IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x44) |
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96 | #define SYS_CTRL_REF300_DIV IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xF8) |
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97 | #define SYS_CTRL_USBHSPHY_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x84) |
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98 | #define SYS_CTRL_USB_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x90) |
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99 | |||
100 | /* pcie */ |
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101 | #define SYS_CTRL_HCSL_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x114) |
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102 | |||
103 | /* System control multi-function pin function selection */ |
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104 | #define SYS_CTRL_SECONDARY_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x14) |
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105 | #define SYS_CTRL_TERTIARY_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x8c) |
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106 | #define SYS_CTRL_QUATERNARY_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x94) |
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107 | #define SYS_CTRL_DEBUG_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x9c) |
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108 | #define SYS_CTRL_ALTERNATIVE_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xa4) |
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109 | #define SYS_CTRL_PULLUP_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xac) |
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110 | |||
111 | /* Secure control multi-function pin function selection */ |
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112 | #define SEC_CTRL_SECONDARY_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x14) |
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113 | #define SEC_CTRL_TERTIARY_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x8c) |
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114 | #define SEC_CTRL_QUATERNARY_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x94) |
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115 | #define SEC_CTRL_DEBUG_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x9c) |
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116 | #define SEC_CTRL_ALTERNATIVE_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0xa4) |
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117 | #define SEC_CTRL_PULLUP_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0xac) |
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118 | |||
119 | #define SEC_CTRL_COPRO_CTRL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x68) |
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120 | #define SEC_CTRL_SECURE_CTRL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x98) |
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121 | #define SEC_CTRL_LEON_DEBUG IOMEM(OXNAS_SECCRTL_BASE_VA + 0xF0) |
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122 | #define SEC_CTRL_PLLB_DIV_CTRL IOMEM(OXNAS_SECCRTL_BASE_VA + 0xF8) |
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123 | #define SEC_CTRL_PLLB_CTRL0 IOMEM(OXNAS_SECCRTL_BASE_VA + 0x1F0) |
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124 | #define SEC_CTRL_PLLB_CTRL1 IOMEM(OXNAS_SECCRTL_BASE_VA + 0x1F4) |
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125 | #define SEC_CTRL_PLLB_CTRL8 IOMEM(OXNAS_SECCRTL_BASE_VA + 0x1F4) |
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126 | |||
127 | #define RPSA_IRQ_SOFT IOMEM(OXNAS_RPSA_BASE_VA + 0x10) |
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128 | #define RPSA_FIQ_ENABLE IOMEM(OXNAS_RPSA_BASE_VA + 0x108) |
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129 | #define RPSA_FIQ_DISABLE IOMEM(OXNAS_RPSA_BASE_VA + 0x10C) |
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130 | #define RPSA_FIQ_IRQ_TO_FIQ IOMEM(OXNAS_RPSA_BASE_VA + 0x1FC) |
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131 | |||
132 | #define RPSC_IRQ_SOFT IOMEM(OXNAS_RPSC_BASE_VA + 0x10) |
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133 | #define RPSC_FIQ_ENABLE IOMEM(OXNAS_RPSC_BASE_VA + 0x108) |
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134 | #define RPSC_FIQ_DISABLE IOMEM(OXNAS_RPSC_BASE_VA + 0x10C) |
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135 | #define RPSC_FIQ_IRQ_TO_FIQ IOMEM(OXNAS_RPSC_BASE_VA + 0x1FC) |
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136 | |||
137 | #define RPSA_TIMER2_VAL IOMEM(OXNAS_RPSA_BASE_VA + 0x224) |
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138 | |||
139 | #define REF300_DIV_INT_SHIFT 8 |
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140 | #define REF300_DIV_FRAC_SHIFT 0 |
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141 | #define REF300_DIV_INT(val) ((val) << REF300_DIV_INT_SHIFT) |
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142 | #define REF300_DIV_FRAC(val) ((val) << REF300_DIV_FRAC_SHIFT) |
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143 | |||
144 | #define USBHSPHY_SUSPENDM_MANUAL_ENABLE 16 |
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145 | #define USBHSPHY_SUSPENDM_MANUAL_STATE 15 |
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146 | #define USBHSPHY_ATE_ESET 14 |
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147 | #define USBHSPHY_TEST_DIN 6 |
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148 | #define USBHSPHY_TEST_ADD 2 |
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149 | #define USBHSPHY_TEST_DOUT_SEL 1 |
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150 | #define USBHSPHY_TEST_CLK 0 |
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151 | |||
152 | #define USB_CTRL_USBAPHY_CKSEL_SHIFT 5 |
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153 | #define USB_CLK_XTAL0_XTAL1 (0 << USB_CTRL_USBAPHY_CKSEL_SHIFT) |
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154 | #define USB_CLK_XTAL0 (1 << USB_CTRL_USBAPHY_CKSEL_SHIFT) |
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155 | #define USB_CLK_INTERNAL (2 << USB_CTRL_USBAPHY_CKSEL_SHIFT) |
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156 | |||
157 | #define USBAMUX_DEVICE BIT(4) |
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158 | |||
159 | #define USBPHY_REFCLKDIV_SHIFT 2 |
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160 | #define USB_PHY_REF_12MHZ (0 << USBPHY_REFCLKDIV_SHIFT) |
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161 | #define USB_PHY_REF_24MHZ (1 << USBPHY_REFCLKDIV_SHIFT) |
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162 | #define USB_PHY_REF_48MHZ (2 << USBPHY_REFCLKDIV_SHIFT) |
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163 | |||
164 | #define USB_CTRL_USB_CKO_SEL_BIT 0 |
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165 | |||
166 | #define USB_INT_CLK_XTAL 0 |
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167 | #define USB_INT_CLK_REF300 2 |
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168 | #define USB_INT_CLK_PLLB 3 |
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169 | |||
170 | #define SYS_CTRL_GMAC_CKEN_RX_IN 14 |
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171 | #define SYS_CTRL_GMAC_CKEN_RXN_OUT 13 |
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172 | #define SYS_CTRL_GMAC_CKEN_RX_OUT 12 |
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173 | #define SYS_CTRL_GMAC_CKEN_TX_IN 10 |
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174 | #define SYS_CTRL_GMAC_CKEN_TXN_OUT 9 |
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175 | #define SYS_CTRL_GMAC_CKEN_TX_OUT 8 |
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176 | #define SYS_CTRL_GMAC_RX_SOURCE 7 |
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177 | #define SYS_CTRL_GMAC_TX_SOURCE 6 |
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178 | #define SYS_CTRL_GMAC_LOW_TX_SOURCE 4 |
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179 | #define SYS_CTRL_GMAC_AUTO_TX_SOURCE 3 |
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180 | #define SYS_CTRL_GMAC_RGMII 2 |
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181 | #define SYS_CTRL_GMAC_SIMPLE_MUX 1 |
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182 | #define SYS_CTRL_GMAC_CKEN_GTX 0 |
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183 | #define SYS_CTRL_GMAC_TX_VARDELAY_SHIFT 0 |
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184 | #define SYS_CTRL_GMAC_TXN_VARDELAY_SHIFT 8 |
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185 | #define SYS_CTRL_GMAC_RX_VARDELAY_SHIFT 16 |
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186 | #define SYS_CTRL_GMAC_RXN_VARDELAY_SHIFT 24 |
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187 | #define SYS_CTRL_GMAC_TX_VARDELAY(d) ((d)<<SYS_CTRL_GMAC_TX_VARDELAY_SHIFT) |
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188 | #define SYS_CTRL_GMAC_TXN_VARDELAY(d) ((d)<<SYS_CTRL_GMAC_TXN_VARDELAY_SHIFT) |
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189 | #define SYS_CTRL_GMAC_RX_VARDELAY(d) ((d)<<SYS_CTRL_GMAC_RX_VARDELAY_SHIFT) |
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190 | #define SYS_CTRL_GMAC_RXN_VARDELAY(d) ((d)<<SYS_CTRL_GMAC_RXN_VARDELAY_SHIFT) |
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191 | |||
192 | #define PLLB_BYPASS 1 |
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193 | #define PLLB_ENSAT 3 |
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194 | #define PLLB_OUTDIV 4 |
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195 | #define PLLB_REFDIV 8 |
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196 | #define PLLB_DIV_INT_SHIFT 8 |
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197 | #define PLLB_DIV_FRAC_SHIFT 0 |
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198 | #define PLLB_DIV_INT(val) ((val) << PLLB_DIV_INT_SHIFT) |
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199 | #define PLLB_DIV_FRAC(val) ((val) << PLLB_DIV_FRAC_SHIFT) |
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200 | |||
201 | #define SYS_CTRL_CKCTRL_PCI_DIV_BIT 0 |
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202 | #define SYS_CTRL_CKCTRL_SLOW_BIT 8 |
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203 | |||
204 | #define SYS_CTRL_UART2_DEQ_EN 0 |
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205 | #define SYS_CTRL_UART3_DEQ_EN 1 |
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206 | #define SYS_CTRL_UART3_IQ_EN 2 |
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207 | #define SYS_CTRL_UART4_IQ_EN 3 |
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208 | #define SYS_CTRL_UART4_NOT_PCI_MODE 4 |
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209 | |||
210 | #define SYS_CTRL_PCI_CTRL1_PCI_STATIC_RQ_BIT 11 |
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211 | |||
212 | #define PLLA_REFDIV_MASK 0x3F |
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213 | #define PLLA_REFDIV_SHIFT 8 |
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214 | #define PLLA_OUTDIV_MASK 0x7 |
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215 | #define PLLA_OUTDIV_SHIFT 4 |
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216 | |||
217 | /* bit numbers of clock control register */ |
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218 | #define SYS_CTRL_CLK_COPRO 0 |
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219 | #define SYS_CTRL_CLK_DMA 1 |
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220 | #define SYS_CTRL_CLK_CIPHER 2 |
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221 | #define SYS_CTRL_CLK_SD 3 |
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222 | #define SYS_CTRL_CLK_SATA 4 |
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223 | #define SYS_CTRL_CLK_I2S 5 |
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224 | #define SYS_CTRL_CLK_USBHS 6 |
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225 | #define SYS_CTRL_CLK_MACA 7 |
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226 | #define SYS_CTRL_CLK_MAC SYS_CTRL_CLK_MACA |
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227 | #define SYS_CTRL_CLK_PCIEA 8 |
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228 | #define SYS_CTRL_CLK_STATIC 9 |
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229 | #define SYS_CTRL_CLK_MACB 10 |
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230 | #define SYS_CTRL_CLK_PCIEB 11 |
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231 | #define SYS_CTRL_CLK_REF600 12 |
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232 | #define SYS_CTRL_CLK_USBDEV 13 |
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233 | #define SYS_CTRL_CLK_DDR 14 |
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234 | #define SYS_CTRL_CLK_DDRPHY 15 |
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235 | #define SYS_CTRL_CLK_DDRCK 16 |
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236 | |||
237 | |||
238 | /* bit numbers of reset control register */ |
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239 | #define SYS_CTRL_RST_SCU 0 |
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240 | #define SYS_CTRL_RST_COPRO 1 |
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241 | #define SYS_CTRL_RST_ARM0 2 |
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242 | #define SYS_CTRL_RST_ARM1 3 |
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243 | #define SYS_CTRL_RST_USBHS 4 |
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244 | #define SYS_CTRL_RST_USBHSPHYA 5 |
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245 | #define SYS_CTRL_RST_MACA 6 |
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246 | #define SYS_CTRL_RST_MAC SYS_CTRL_RST_MACA |
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247 | #define SYS_CTRL_RST_PCIEA 7 |
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248 | #define SYS_CTRL_RST_SGDMA 8 |
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249 | #define SYS_CTRL_RST_CIPHER 9 |
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250 | #define SYS_CTRL_RST_DDR 10 |
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251 | #define SYS_CTRL_RST_SATA 11 |
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252 | #define SYS_CTRL_RST_SATA_LINK 12 |
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253 | #define SYS_CTRL_RST_SATA_PHY 13 |
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254 | #define SYS_CTRL_RST_PCIEPHY 14 |
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255 | #define SYS_CTRL_RST_STATIC 15 |
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256 | #define SYS_CTRL_RST_GPIO 16 |
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257 | #define SYS_CTRL_RST_UART1 17 |
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258 | #define SYS_CTRL_RST_UART2 18 |
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259 | #define SYS_CTRL_RST_MISC 19 |
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260 | #define SYS_CTRL_RST_I2S 20 |
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261 | #define SYS_CTRL_RST_SD 21 |
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262 | #define SYS_CTRL_RST_MACB 22 |
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263 | #define SYS_CTRL_RST_PCIEB 23 |
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264 | #define SYS_CTRL_RST_VIDEO 24 |
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265 | #define SYS_CTRL_RST_DDR_PHY 25 |
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266 | #define SYS_CTRL_RST_USBHSPHYB 26 |
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267 | #define SYS_CTRL_RST_USBDEV 27 |
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268 | #define SYS_CTRL_RST_ARMDBG 29 |
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269 | #define SYS_CTRL_RST_PLLA 30 |
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270 | #define SYS_CTRL_RST_PLLB 31 |
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271 | |||
272 | static inline void oxnas_register_clear_mask(void __iomem *p, unsigned mask) |
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273 | { |
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274 | u32 val = readl_relaxed(p); |
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275 | |||
276 | val &= ~mask; |
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277 | writel_relaxed(val, p); |
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278 | } |
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279 | |||
280 | static inline void oxnas_register_set_mask(void __iomem *p, unsigned mask) |
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281 | { |
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282 | u32 val = readl_relaxed(p); |
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283 | |||
284 | val |= mask; |
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285 | writel_relaxed(val, p); |
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286 | } |
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287 | |||
288 | static inline void oxnas_register_value_mask(void __iomem *p, |
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289 | unsigned mask, unsigned new_value) |
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290 | { |
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291 | /* TODO sanity check mask & new_value = new_value */ |
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292 | u32 val = readl_relaxed(p); |
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293 | |||
294 | val &= ~mask; |
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295 | val |= new_value; |
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296 | writel_relaxed(val, p); |
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297 | } |
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298 | |||
299 | #define VERSION_ID_MAGIC 0x082510b5 |
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300 | #define LINK_UP_TIMEOUT_SECONDS 1 |
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301 | #define NUM_CONTROLLERS 1 |
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302 | |||
303 | enum { |
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304 | PCIE_DEVICE_TYPE_MASK = 0x0F, |
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305 | PCIE_DEVICE_TYPE_ENDPOINT = 0, |
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306 | PCIE_DEVICE_TYPE_LEGACY_ENDPOINT = 1, |
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307 | PCIE_DEVICE_TYPE_ROOT = 4, |
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308 | |||
309 | PCIE_LTSSM = BIT(4), |
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310 | PCIE_READY_ENTR_L23 = BIT(9), |
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311 | PCIE_LINK_UP = BIT(11), |
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312 | PCIE_OBTRANS = BIT(12), |
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313 | }; |
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314 | |||
315 | enum { |
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316 | HCSL_BIAS_ON = BIT(0), |
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317 | HCSL_PCIE_EN = BIT(1), |
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318 | HCSL_PCIEA_EN = BIT(2), |
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319 | HCSL_PCIEB_EN = BIT(3), |
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320 | }; |
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321 | |||
322 | enum { |
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323 | /* pcie phy reg offset */ |
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324 | PHY_ADDR = 0, |
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325 | PHY_DATA = 4, |
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326 | /* phy data reg bits */ |
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327 | READ_EN = BIT(16), |
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328 | WRITE_EN = BIT(17), |
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329 | CAP_DATA = BIT(18), |
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330 | }; |
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331 | |||
332 | /* core config registers */ |
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333 | enum { |
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334 | PCI_CONFIG_VERSION_DEVICEID = 0, |
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335 | PCI_CONFIG_COMMAND_STATUS = 4, |
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336 | }; |
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337 | |||
338 | /* inbound config registers */ |
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339 | enum { |
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340 | IB_ADDR_XLATE_ENABLE = 0xFC, |
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341 | |||
342 | /* bits */ |
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343 | ENABLE_IN_ADDR_TRANS = BIT(0), |
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344 | }; |
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345 | |||
346 | /* outbound config registers, offset relative to PCIE_POM0_MEM_ADDR */ |
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347 | enum { |
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348 | PCIE_POM0_MEM_ADDR = 0, |
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349 | PCIE_POM1_MEM_ADDR = 4, |
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350 | PCIE_IN0_MEM_ADDR = 8, |
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351 | PCIE_IN1_MEM_ADDR = 12, |
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352 | PCIE_IN_IO_ADDR = 16, |
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353 | PCIE_IN_CFG0_ADDR = 20, |
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354 | PCIE_IN_CFG1_ADDR = 24, |
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355 | PCIE_IN_MSG_ADDR = 28, |
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356 | PCIE_IN0_MEM_LIMIT = 32, |
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357 | PCIE_IN1_MEM_LIMIT = 36, |
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358 | PCIE_IN_IO_LIMIT = 40, |
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359 | PCIE_IN_CFG0_LIMIT = 44, |
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360 | PCIE_IN_CFG1_LIMIT = 48, |
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361 | PCIE_IN_MSG_LIMIT = 52, |
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362 | PCIE_AHB_SLAVE_CTRL = 56, |
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363 | |||
364 | PCIE_SLAVE_BE_SHIFT = 22, |
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365 | }; |
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366 | |||
367 | #define ADDR_VAL(val) ((val) & 0xFFFF) |
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368 | #define DATA_VAL(val) ((val) & 0xFFFF) |
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369 | |||
370 | #define PCIE_SLAVE_BE(val) ((val) << PCIE_SLAVE_BE_SHIFT) |
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371 | #define PCIE_SLAVE_BE_MASK PCIE_SLAVE_BE(0xF) |
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372 | |||
373 | struct oxnas_pcie_shared { |
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374 | /* seems all access are serialized, no lock required */ |
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375 | int refcount; |
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376 | }; |
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377 | |||
378 | /* Structure representing one PCIe interfaces */ |
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379 | struct oxnas_pcie { |
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380 | void __iomem *cfgbase; |
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381 | void __iomem *base; |
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382 | void __iomem *inbound; |
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383 | void __iomem *outbound; |
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384 | void __iomem *pcie_ctrl; |
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385 | |||
386 | int haslink; |
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387 | struct platform_device *pdev; |
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388 | struct resource io; |
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389 | struct resource cfg; |
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390 | struct resource pre_mem; /* prefetchable */ |
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391 | struct resource non_mem; /* non-prefetchable */ |
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392 | struct resource busn; /* max available bus numbers */ |
||
393 | int card_reset; /* gpio pin, optional */ |
||
394 | unsigned hcsl_en; /* hcsl pci enable bit */ |
||
395 | struct clk *clk; |
||
396 | struct clk *busclk; /* for pcie bus, actually the PLLB */ |
||
397 | void *private_data[1]; |
||
398 | spinlock_t lock; |
||
399 | }; |
||
400 | |||
401 | static struct oxnas_pcie_shared pcie_shared = { |
||
402 | .refcount = 0, |
||
403 | }; |
||
404 | |||
405 | static inline struct oxnas_pcie *sys_to_pcie(struct pci_sys_data *sys) |
||
406 | { |
||
407 | return sys->private_data; |
||
408 | } |
||
409 | |||
410 | |||
411 | static inline void set_out_lanes(struct oxnas_pcie *pcie, unsigned lanes) |
||
412 | { |
||
413 | oxnas_register_value_mask(pcie->outbound + PCIE_AHB_SLAVE_CTRL, |
||
414 | PCIE_SLAVE_BE_MASK, PCIE_SLAVE_BE(lanes)); |
||
415 | wmb(); |
||
416 | } |
||
417 | |||
418 | static int oxnas_pcie_link_up(struct oxnas_pcie *pcie) |
||
419 | { |
||
420 | unsigned long end; |
||
421 | |||
422 | /* Poll for PCIE link up */ |
||
423 | end = jiffies + (LINK_UP_TIMEOUT_SECONDS * HZ); |
||
424 | while (!time_after(jiffies, end)) { |
||
425 | if (readl(pcie->pcie_ctrl) & PCIE_LINK_UP) |
||
426 | return 1; |
||
427 | } |
||
428 | return 0; |
||
429 | } |
||
430 | |||
431 | static void __init oxnas_pcie_setup_hw(struct oxnas_pcie *pcie) |
||
432 | { |
||
433 | /* We won't have any inbound address translation. This allows PCI |
||
434 | * devices to access anywhere in the AHB address map. Might be regarded |
||
435 | * as a bit dangerous, but let's get things working before we worry |
||
436 | * about that |
||
437 | */ |
||
438 | oxnas_register_clear_mask(pcie->inbound + IB_ADDR_XLATE_ENABLE, |
||
439 | ENABLE_IN_ADDR_TRANS); |
||
440 | wmb(); |
||
441 | |||
442 | /* |
||
443 | * Program outbound translation windows |
||
444 | * |
||
445 | * Outbound window is what is referred to as "PCI client" region in HRM |
||
446 | * |
||
447 | * Could use the larger alternative address space to get >>64M regions |
||
448 | * for graphics cards etc., but will not bother at this point. |
||
449 | * |
||
450 | * IP bug means that AMBA window size must be a power of 2 |
||
451 | * |
||
452 | * Set mem0 window for first 16MB of outbound window non-prefetchable |
||
453 | * Set mem1 window for second 16MB of outbound window prefetchable |
||
454 | * Set io window for next 16MB of outbound window |
||
455 | * Set cfg0 for final 1MB of outbound window |
||
456 | * |
||
457 | * Ignore mem1, cfg1 and msg windows for now as no obvious use cases for |
||
458 | * 820 that would need them |
||
459 | * |
||
460 | * Probably ideally want no offset between mem0 window start as seen by |
||
461 | * ARM and as seen on PCI bus and get Linux to assign memory regions to |
||
462 | * PCI devices using the same "PCI client" region start address as seen |
||
463 | * by ARM |
||
464 | */ |
||
465 | |||
466 | /* Set PCIeA mem0 region to be 1st 16MB of the 64MB PCIeA window */ |
||
467 | writel_relaxed(pcie->non_mem.start, pcie->outbound + PCIE_IN0_MEM_ADDR); |
||
468 | writel_relaxed(pcie->non_mem.end, pcie->outbound + PCIE_IN0_MEM_LIMIT); |
||
469 | writel_relaxed(pcie->non_mem.start, pcie->outbound + PCIE_POM0_MEM_ADDR); |
||
470 | |||
471 | /* Set PCIeA mem1 region to be 2nd 16MB of the 64MB PCIeA window */ |
||
472 | writel_relaxed(pcie->pre_mem.start, pcie->outbound + PCIE_IN1_MEM_ADDR); |
||
473 | writel_relaxed(pcie->pre_mem.end, pcie->outbound + PCIE_IN1_MEM_LIMIT); |
||
474 | writel_relaxed(pcie->pre_mem.start, pcie->outbound + PCIE_POM1_MEM_ADDR); |
||
475 | |||
476 | /* Set PCIeA io to be third 16M region of the 64MB PCIeA window*/ |
||
477 | writel_relaxed(pcie->io.start, pcie->outbound + PCIE_IN_IO_ADDR); |
||
478 | writel_relaxed(pcie->io.end, pcie->outbound + PCIE_IN_IO_LIMIT); |
||
479 | |||
480 | /* Set PCIeA cgf0 to be last 16M region of the 64MB PCIeA window*/ |
||
481 | writel_relaxed(pcie->cfg.start, pcie->outbound + PCIE_IN_CFG0_ADDR); |
||
482 | writel_relaxed(pcie->cfg.end, pcie->outbound + PCIE_IN_CFG0_LIMIT); |
||
483 | wmb(); |
||
484 | |||
485 | /* Enable outbound address translation */ |
||
486 | oxnas_register_set_mask(pcie->pcie_ctrl, PCIE_OBTRANS); |
||
487 | wmb(); |
||
488 | |||
489 | /* |
||
490 | * Program PCIe command register for core to: |
||
491 | * enable memory space |
||
492 | * enable bus master |
||
493 | * enable io |
||
494 | */ |
||
495 | writel_relaxed(7, pcie->base + PCI_CONFIG_COMMAND_STATUS); |
||
496 | /* which is which */ |
||
497 | wmb(); |
||
498 | } |
||
499 | |||
500 | static unsigned oxnas_pcie_cfg_to_offset( |
||
501 | struct pci_sys_data *sys, |
||
502 | unsigned char bus_number, |
||
503 | unsigned int devfn, |
||
504 | int where) |
||
505 | { |
||
506 | unsigned int function = PCI_FUNC(devfn); |
||
507 | unsigned int slot = PCI_SLOT(devfn); |
||
508 | unsigned char bus_number_offset; |
||
509 | |||
510 | bus_number_offset = bus_number - sys->busnr; |
||
511 | |||
512 | /* |
||
513 | * We'll assume for now that the offset, function, slot, bus encoding |
||
514 | * should map onto linear, contiguous addresses in PCIe config space, |
||
515 | * albeit that the majority will be unused as only slot 0 is valid for |
||
516 | * any PCIe bus and most devices have only function 0 |
||
517 | * |
||
518 | * Could be that PCIe in fact works by not encoding the slot number into |
||
519 | * the config space address as it's known that only slot 0 is valid. |
||
520 | * We'll have to experiment if/when we get a PCIe switch connected to |
||
521 | * the PCIe host |
||
522 | */ |
||
523 | return (bus_number_offset << 20) | (slot << 15) | (function << 12) | |
||
524 | (where & ~3); |
||
525 | } |
||
526 | |||
527 | /* PCI configuration space write function */ |
||
528 | static int oxnas_pcie_wr_conf(struct pci_bus *bus, u32 devfn, |
||
529 | int where, int size, u32 val) |
||
530 | { |
||
531 | unsigned long flags; |
||
532 | struct oxnas_pcie *pcie = sys_to_pcie(bus->sysdata); |
||
533 | unsigned offset; |
||
534 | u32 value; |
||
535 | u32 lanes; |
||
536 | |||
537 | /* Only a single device per bus for PCIe point-to-point links */ |
||
538 | if (PCI_SLOT(devfn) > 0) |
||
539 | return PCIBIOS_DEVICE_NOT_FOUND; |
||
540 | |||
541 | if (!pcie->haslink) |
||
542 | return PCIBIOS_DEVICE_NOT_FOUND; |
||
543 | |||
544 | offset = oxnas_pcie_cfg_to_offset(bus->sysdata, bus->number, devfn, |
||
545 | where); |
||
546 | |||
547 | value = val << (8 * (where & 3)); |
||
548 | lanes = (0xf >> (4-size)) << (where & 3); |
||
549 | /* it race with mem and io write, but the possibility is low, normally |
||
550 | * all config writes happens at driver initialize stage, wont interleave |
||
551 | * with others. |
||
552 | * and many pcie cards use dword (4bytes) access mem/io access only, |
||
553 | * so not bother to copy that ugly work-around now. */ |
||
554 | spin_lock_irqsave(&pcie->lock, flags); |
||
555 | set_out_lanes(pcie, lanes); |
||
556 | writel_relaxed(value, pcie->cfgbase + offset); |
||
557 | set_out_lanes(pcie, 0xf); |
||
558 | spin_unlock_irqrestore(&pcie->lock, flags); |
||
559 | |||
560 | return PCIBIOS_SUCCESSFUL; |
||
561 | } |
||
562 | |||
563 | /* PCI configuration space read function */ |
||
564 | static int oxnas_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, |
||
565 | int size, u32 *val) |
||
566 | { |
||
567 | struct oxnas_pcie *pcie = sys_to_pcie(bus->sysdata); |
||
568 | unsigned offset; |
||
569 | u32 value; |
||
570 | u32 left_bytes, right_bytes; |
||
571 | |||
572 | /* Only a single device per bus for PCIe point-to-point links */ |
||
573 | if (PCI_SLOT(devfn) > 0) { |
||
574 | *val = 0xffffffff; |
||
575 | return PCIBIOS_DEVICE_NOT_FOUND; |
||
576 | } |
||
577 | |||
578 | if (!pcie->haslink) { |
||
579 | *val = 0xffffffff; |
||
580 | return PCIBIOS_DEVICE_NOT_FOUND; |
||
581 | } |
||
582 | |||
583 | offset = oxnas_pcie_cfg_to_offset(bus->sysdata, bus->number, devfn, |
||
584 | where); |
||
585 | value = readl_relaxed(pcie->cfgbase + offset); |
||
586 | left_bytes = where & 3; |
||
587 | right_bytes = 4 - left_bytes - size; |
||
588 | value <<= right_bytes * 8; |
||
589 | value >>= (left_bytes + right_bytes) * 8; |
||
590 | *val = value; |
||
591 | |||
592 | return PCIBIOS_SUCCESSFUL; |
||
593 | } |
||
594 | |||
595 | static struct pci_ops oxnas_pcie_ops = { |
||
596 | .read = oxnas_pcie_rd_conf, |
||
597 | .write = oxnas_pcie_wr_conf, |
||
598 | }; |
||
599 | |||
600 | static int __init oxnas_pcie_setup(int nr, struct pci_sys_data *sys) |
||
601 | { |
||
602 | struct oxnas_pcie *pcie = sys_to_pcie(sys); |
||
603 | |||
604 | pci_add_resource_offset(&sys->resources, &pcie->non_mem, sys->mem_offset); |
||
605 | pci_add_resource_offset(&sys->resources, &pcie->pre_mem, sys->mem_offset); |
||
606 | pci_add_resource_offset(&sys->resources, &pcie->io, sys->io_offset); |
||
607 | pci_add_resource(&sys->resources, &pcie->busn); |
||
608 | if (sys->busnr == 0) { /* default one */ |
||
609 | sys->busnr = pcie->busn.start; |
||
610 | } |
||
611 | /* do not use devm_ioremap_resource, it does not like cfg resource */ |
||
612 | pcie->cfgbase = devm_ioremap(&pcie->pdev->dev, pcie->cfg.start, |
||
613 | resource_size(&pcie->cfg)); |
||
614 | if (!pcie->cfgbase) |
||
615 | return -ENOMEM; |
||
616 | |||
617 | oxnas_pcie_setup_hw(pcie); |
||
618 | |||
619 | return 1; |
||
620 | } |
||
621 | |||
622 | static void __init oxnas_pcie_enable(struct device *dev, struct oxnas_pcie *pcie) |
||
623 | { |
||
624 | struct hw_pci hw; |
||
625 | int i; |
||
626 | |||
627 | memset(&hw, 0, sizeof(hw)); |
||
628 | for (i = 0; i < NUM_CONTROLLERS; i++) |
||
629 | pcie->private_data[i] = pcie; |
||
630 | |||
631 | hw.nr_controllers = NUM_CONTROLLERS; |
||
632 | /* I think use stack pointer is a bad idea though it is valid in this case */ |
||
633 | hw.private_data = pcie->private_data; |
||
634 | hw.setup = oxnas_pcie_setup; |
||
635 | hw.map_irq = of_irq_parse_and_map_pci; |
||
636 | hw.ops = &oxnas_pcie_ops; |
||
637 | |||
638 | /* pass dev to maintain of tree, interrupt mapping rely on this */ |
||
639 | pci_common_init_dev(dev, &hw); |
||
640 | } |
||
641 | |||
642 | void oxnas_pcie_init_shared_hw(struct platform_device *pdev, |
||
643 | void __iomem *phybase) |
||
644 | { |
||
645 | struct reset_control *rstc; |
||
646 | int ret; |
||
647 | |||
648 | /* generate clocks from HCSL buffers, shared parts */ |
||
649 | writel(HCSL_BIAS_ON|HCSL_PCIE_EN, SYS_CTRL_HCSL_CTRL); |
||
650 | |||
651 | /* Ensure PCIe PHY is properly reset */ |
||
652 | rstc = reset_control_get(&pdev->dev, "phy"); |
||
653 | if (IS_ERR(rstc)) { |
||
654 | ret = PTR_ERR(rstc); |
||
655 | } else { |
||
656 | ret = reset_control_reset(rstc); |
||
657 | reset_control_put(rstc); |
||
658 | } |
||
659 | |||
660 | if (ret) { |
||
661 | dev_err(&pdev->dev, "phy reset failed %d\n", ret); |
||
662 | return; |
||
663 | } |
||
664 | |||
665 | /* Enable PCIe Pre-Emphasis: What these value means? */ |
||
666 | |||
667 | writel(ADDR_VAL(0x0014), phybase + PHY_ADDR); |
||
668 | writel(DATA_VAL(0xce10) | CAP_DATA, phybase + PHY_DATA); |
||
669 | writel(DATA_VAL(0xce10) | WRITE_EN, phybase + PHY_DATA); |
||
670 | |||
671 | writel(ADDR_VAL(0x2004), phybase + PHY_ADDR); |
||
672 | writel(DATA_VAL(0x82c7) | CAP_DATA, phybase + PHY_DATA); |
||
673 | writel(DATA_VAL(0x82c7) | WRITE_EN, phybase + PHY_DATA); |
||
674 | } |
||
675 | |||
676 | static int oxnas_pcie_shared_init(struct platform_device *pdev) |
||
677 | { |
||
678 | if (++pcie_shared.refcount == 1) { |
||
679 | /* we are the first */ |
||
680 | struct device_node *np = pdev->dev.of_node; |
||
681 | void __iomem *phy = of_iomap(np, 2); |
||
682 | if (!phy) { |
||
683 | --pcie_shared.refcount; |
||
684 | return -ENOMEM; |
||
685 | } |
||
686 | oxnas_pcie_init_shared_hw(pdev, phy); |
||
687 | iounmap(phy); |
||
688 | return 0; |
||
689 | } else { |
||
690 | return 0; |
||
691 | } |
||
692 | } |
||
693 | |||
694 | #if 0 |
||
695 | /* maybe we will call it when enter low power state */ |
||
696 | static void oxnas_pcie_shared_deinit(struct platform_device *pdev) |
||
697 | { |
||
698 | if (--pcie_shared.refcount == 0) { |
||
699 | /* no cleanup needed */; |
||
700 | } |
||
701 | } |
||
702 | #endif |
||
703 | |||
704 | static int __init |
||
705 | oxnas_pcie_map_registers(struct platform_device *pdev, |
||
706 | struct device_node *np, |
||
707 | struct oxnas_pcie *pcie) |
||
708 | { |
||
709 | struct resource regs; |
||
710 | int ret = 0; |
||
711 | u32 outbound_ctrl_offset; |
||
712 | u32 pcie_ctrl_offset; |
||
713 | |||
714 | /* 2 is reserved for shared phy */ |
||
715 | ret = of_address_to_resource(np, 0, ®s); |
||
716 | if (ret) |
||
717 | return -EINVAL; |
||
718 | pcie->base = devm_ioremap_resource(&pdev->dev, ®s); |
||
719 | if (!pcie->base) |
||
720 | return -ENOMEM; |
||
721 | |||
722 | ret = of_address_to_resource(np, 1, ®s); |
||
723 | if (ret) |
||
724 | return -EINVAL; |
||
725 | pcie->inbound = devm_ioremap_resource(&pdev->dev, ®s); |
||
726 | if (!pcie->inbound) |
||
727 | return -ENOMEM; |
||
728 | |||
729 | |||
730 | if (of_property_read_u32(np, "plxtech,pcie-outbound-offset", |
||
731 | &outbound_ctrl_offset)) |
||
732 | return -EINVAL; |
||
733 | /* SYSCRTL is shared by too many drivers, so is mapped by board file */ |
||
734 | pcie->outbound = IOMEM(OXNAS_SYSCRTL_BASE_VA + outbound_ctrl_offset); |
||
735 | |||
736 | if (of_property_read_u32(np, "plxtech,pcie-ctrl-offset", |
||
737 | &pcie_ctrl_offset)) |
||
738 | return -EINVAL; |
||
739 | pcie->pcie_ctrl = IOMEM(OXNAS_SYSCRTL_BASE_VA + pcie_ctrl_offset); |
||
740 | |||
741 | return 0; |
||
742 | } |
||
743 | |||
744 | static int __init oxnas_pcie_init_res(struct platform_device *pdev, |
||
745 | struct oxnas_pcie *pcie, |
||
746 | struct device_node *np) |
||
747 | { |
||
748 | struct of_pci_range range; |
||
749 | struct of_pci_range_parser parser; |
||
750 | int ret; |
||
751 | |||
752 | if (of_pci_range_parser_init(&parser, np)) |
||
753 | return -EINVAL; |
||
754 | |||
755 | /* Get the I/O and memory ranges from DT */ |
||
756 | for_each_of_pci_range(&parser, &range) { |
||
757 | |||
758 | unsigned long restype = range.flags & IORESOURCE_TYPE_BITS; |
||
759 | if (restype == IORESOURCE_IO) { |
||
760 | of_pci_range_to_resource(&range, np, &pcie->io); |
||
761 | pcie->io.name = "I/O"; |
||
762 | } |
||
763 | if (restype == IORESOURCE_MEM) { |
||
764 | if (range.flags & IORESOURCE_PREFETCH) { |
||
765 | of_pci_range_to_resource(&range, np, &pcie->pre_mem); |
||
766 | pcie->pre_mem.name = "PRE MEM"; |
||
767 | } else { |
||
768 | of_pci_range_to_resource(&range, np, &pcie->non_mem); |
||
769 | pcie->non_mem.name = "NON MEM"; |
||
770 | } |
||
771 | |||
772 | } |
||
773 | if (restype == 0) |
||
774 | of_pci_range_to_resource(&range, np, &pcie->cfg); |
||
775 | } |
||
776 | |||
777 | /* Get the bus range */ |
||
778 | ret = of_pci_parse_bus_range(np, &pcie->busn); |
||
779 | |||
780 | if (ret) { |
||
781 | dev_err(&pdev->dev, "failed to parse bus-range property: %d\n", |
||
782 | ret); |
||
783 | return ret; |
||
784 | } |
||
785 | |||
786 | pcie->card_reset = of_get_gpio(np, 0); |
||
787 | if (pcie->card_reset < 0) |
||
788 | dev_info(&pdev->dev, "card reset gpio pin not exists\n"); |
||
789 | |||
790 | if (of_property_read_u32(np, "plxtech,pcie-hcsl-bit", &pcie->hcsl_en)) |
||
791 | return -EINVAL; |
||
792 | |||
793 | pcie->clk = of_clk_get_by_name(np, "pcie"); |
||
794 | if (IS_ERR(pcie->clk)) { |
||
795 | return PTR_ERR(pcie->clk); |
||
796 | } |
||
797 | |||
798 | pcie->busclk = of_clk_get_by_name(np, "busclk"); |
||
799 | if (IS_ERR(pcie->busclk)) { |
||
800 | clk_put(pcie->clk); |
||
801 | return PTR_ERR(pcie->busclk); |
||
802 | } |
||
803 | |||
804 | return 0; |
||
805 | } |
||
806 | |||
807 | static void oxnas_pcie_init_hw(struct platform_device *pdev, |
||
808 | struct oxnas_pcie *pcie) |
||
809 | { |
||
810 | u32 version_id; |
||
811 | int ret; |
||
812 | |||
813 | clk_prepare_enable(pcie->busclk); |
||
814 | |||
815 | /* reset PCIe cards use hard-wired gpio pin */ |
||
816 | if (pcie->card_reset >= 0 && |
||
817 | !gpio_direction_output(pcie->card_reset, 0)) { |
||
818 | wmb(); |
||
819 | mdelay(10); |
||
820 | /* must tri-state the pin to pull it up */ |
||
821 | gpio_direction_input(pcie->card_reset); |
||
822 | wmb(); |
||
823 | mdelay(100); |
||
824 | } |
||
825 | |||
826 | oxnas_register_set_mask(SYS_CTRL_HCSL_CTRL, BIT(pcie->hcsl_en)); |
||
827 | |||
828 | /* core */ |
||
829 | ret = device_reset(&pdev->dev); |
||
830 | if (ret) { |
||
831 | dev_err(&pdev->dev, "core reset failed %d\n", ret); |
||
832 | return; |
||
833 | } |
||
834 | |||
835 | /* Start PCIe core clocks */ |
||
836 | clk_prepare_enable(pcie->clk); |
||
837 | |||
838 | version_id = readl_relaxed(pcie->base + PCI_CONFIG_VERSION_DEVICEID); |
||
839 | dev_info(&pdev->dev, "PCIe version/deviceID 0x%x\n", version_id); |
||
840 | |||
841 | if (version_id != VERSION_ID_MAGIC) { |
||
842 | dev_info(&pdev->dev, "PCIe controller not found\n"); |
||
843 | pcie->haslink = 0; |
||
844 | return; |
||
845 | } |
||
846 | |||
847 | /* allow entry to L23 state */ |
||
848 | oxnas_register_set_mask(pcie->pcie_ctrl, PCIE_READY_ENTR_L23); |
||
849 | |||
850 | /* Set PCIe core into RootCore mode */ |
||
851 | oxnas_register_value_mask(pcie->pcie_ctrl, PCIE_DEVICE_TYPE_MASK, |
||
852 | PCIE_DEVICE_TYPE_ROOT); |
||
853 | wmb(); |
||
854 | |||
855 | /* Bring up the PCI core */ |
||
856 | oxnas_register_set_mask(pcie->pcie_ctrl, PCIE_LTSSM); |
||
857 | wmb(); |
||
858 | } |
||
859 | |||
860 | static int __init oxnas_pcie_probe(struct platform_device *pdev) |
||
861 | { |
||
862 | struct oxnas_pcie *pcie; |
||
863 | struct device_node *np = pdev->dev.of_node; |
||
864 | int ret; |
||
865 | |||
866 | pcie = devm_kzalloc(&pdev->dev, sizeof(struct oxnas_pcie), |
||
867 | GFP_KERNEL); |
||
868 | if (!pcie) |
||
869 | return -ENOMEM; |
||
870 | |||
871 | pcie->pdev = pdev; |
||
872 | pcie->haslink = 1; |
||
873 | spin_lock_init(&pcie->lock); |
||
874 | |||
875 | ret = oxnas_pcie_init_res(pdev, pcie, np); |
||
876 | if (ret) |
||
877 | return ret; |
||
878 | if (pcie->card_reset >= 0) { |
||
879 | ret = gpio_request_one(pcie->card_reset, GPIOF_DIR_IN, |
||
880 | dev_name(&pdev->dev)); |
||
881 | if (ret) { |
||
882 | dev_err(&pdev->dev, "cannot request gpio pin %d\n", |
||
883 | pcie->card_reset); |
||
884 | return ret; |
||
885 | } |
||
886 | } |
||
887 | |||
888 | ret = oxnas_pcie_map_registers(pdev, np, pcie); |
||
889 | if (ret) { |
||
890 | dev_err(&pdev->dev, "cannot map registers\n"); |
||
891 | goto err_free_gpio; |
||
892 | } |
||
893 | |||
894 | ret = oxnas_pcie_shared_init(pdev); |
||
895 | if (ret) |
||
896 | goto err_free_gpio; |
||
897 | |||
898 | /* if hw not found, haslink cleared */ |
||
899 | oxnas_pcie_init_hw(pdev, pcie); |
||
900 | |||
901 | if (pcie->haslink && oxnas_pcie_link_up(pcie)) { |
||
902 | pcie->haslink = 1; |
||
903 | dev_info(&pdev->dev, "link up\n"); |
||
904 | } else { |
||
905 | pcie->haslink = 0; |
||
906 | dev_info(&pdev->dev, "link down\n"); |
||
907 | } |
||
908 | /* should we register our controller even when pcie->haslink is 0 ? */ |
||
909 | /* register the controller with framework */ |
||
910 | oxnas_pcie_enable(&pdev->dev, pcie); |
||
911 | |||
912 | return 0; |
||
913 | |||
914 | err_free_gpio: |
||
915 | if (pcie->card_reset) |
||
916 | gpio_free(pcie->card_reset); |
||
917 | |||
918 | return ret; |
||
919 | } |
||
920 | |||
921 | static const struct of_device_id oxnas_pcie_of_match_table[] = { |
||
922 | { .compatible = "plxtech,nas782x-pcie", }, |
||
923 | {}, |
||
924 | }; |
||
925 | MODULE_DEVICE_TABLE(of, oxnas_pcie_of_match_table); |
||
926 | |||
927 | static struct platform_driver oxnas_pcie_driver = { |
||
928 | .driver = { |
||
929 | .owner = THIS_MODULE, |
||
930 | .name = "oxnas-pcie", |
||
931 | .of_match_table = |
||
932 | of_match_ptr(oxnas_pcie_of_match_table), |
||
933 | }, |
||
934 | }; |
||
935 | |||
936 | static int __init oxnas_pcie_init(void) |
||
937 | { |
||
938 | return platform_driver_probe(&oxnas_pcie_driver, |
||
939 | oxnas_pcie_probe); |
||
940 | } |
||
941 | |||
942 | subsys_initcall(oxnas_pcie_init); |
||
943 | |||
944 | MODULE_AUTHOR("Ma Haijun <mahaijuns@gmail.com>"); |
||
945 | MODULE_DESCRIPTION("NAS782x PCIe driver"); |
||
946 | MODULE_LICENSE("GPLv2"); |