OpenWrt – Blame information for rev 4
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Rev | Author | Line No. | Line |
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1 | office | 1 | From 0c8d249a70818f4f8e0d5543dc7157dfd8a5265e Mon Sep 17 00:00:00 2001 |
2 | From: Ryder Lee <ryder.lee@mediatek.com> |
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3 | Date: Wed, 20 Dec 2017 16:04:24 +0800 |
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4 | Subject: [PATCH 220/224] arm64: dts: mt7622: add SATA device nodes |
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5 | |||
6 | This patch adds SATA support fot MT7622. |
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7 | |||
8 | Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> |
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9 | Signed-off-by: Sean Wang <sean.wang@mediatek.com> |
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10 | --- |
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11 | arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 8 ++++++ |
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12 | arch/arm64/boot/dts/mediatek/mt7622.dtsi | 40 ++++++++++++++++++++++++++++ |
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13 | 2 files changed, 48 insertions(+) |
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14 | |||
15 | --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts |
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16 | +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts |
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17 | @@ -323,6 +323,14 @@ |
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18 | status = "okay"; |
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19 | }; |
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20 | |||
21 | +&sata { |
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22 | + status = "okay"; |
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23 | +}; |
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24 | + |
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25 | +&sata_phy { |
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26 | + status = "okay"; |
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27 | +}; |
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28 | + |
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29 | &spi0 { |
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30 | pinctrl-names = "default"; |
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31 | pinctrl-0 = <&spic0_pins>; |
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32 | --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi |
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33 | +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi |
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34 | @@ -9,6 +9,7 @@ |
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35 | #include <dt-bindings/interrupt-controller/irq.h> |
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36 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
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37 | #include <dt-bindings/clock/mt7622-clk.h> |
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38 | +#include <dt-bindings/phy/phy.h> |
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39 | #include <dt-bindings/power/mt7622-power.h> |
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40 | #include <dt-bindings/reset/mt7622-reset.h> |
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41 | #include <dt-bindings/thermal/thermal.h> |
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42 | @@ -616,6 +617,45 @@ |
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43 | }; |
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44 | }; |
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45 | |||
46 | + sata: sata@1a200000 { |
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47 | + compatible = "mediatek,mt7622-ahci", |
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48 | + "mediatek,mtk-ahci"; |
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49 | + reg = <0 0x1a200000 0 0x1100>; |
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50 | + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; |
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51 | + interrupt-names = "hostc"; |
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52 | + clocks = <&pciesys CLK_SATA_AHB_EN>, |
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53 | + <&pciesys CLK_SATA_AXI_EN>, |
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54 | + <&pciesys CLK_SATA_ASIC_EN>, |
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55 | + <&pciesys CLK_SATA_RBC_EN>, |
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56 | + <&pciesys CLK_SATA_PM_EN>; |
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57 | + clock-names = "ahb", "axi", "asic", "rbc", "pm"; |
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58 | + phys = <&sata_port PHY_TYPE_SATA>; |
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59 | + phy-names = "sata-phy"; |
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60 | + ports-implemented = <0x1>; |
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61 | + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; |
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62 | + resets = <&pciesys MT7622_SATA_AXI_BUS_RST>, |
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63 | + <&pciesys MT7622_SATA_PHY_SW_RST>, |
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64 | + <&pciesys MT7622_SATA_PHY_REG_RST>; |
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65 | + reset-names = "axi", "sw", "reg"; |
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66 | + mediatek,phy-mode = <&pciesys>; |
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67 | + status = "disabled"; |
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68 | + }; |
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69 | + |
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70 | + sata_phy: sata-phy@1a243000 { |
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71 | + compatible = "mediatek,generic-tphy-v1"; |
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72 | + #address-cells = <2>; |
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73 | + #size-cells = <2>; |
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74 | + ranges; |
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75 | + status = "disabled"; |
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76 | + |
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77 | + sata_port: sata-phy@1a243000 { |
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78 | + reg = <0 0x1a243000 0 0x0100>; |
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79 | + clocks = <&topckgen CLK_TOP_ETH_500M>; |
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80 | + clock-names = "ref"; |
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81 | + #phy-cells = <1>; |
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82 | + }; |
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83 | + }; |
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84 | + |
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85 | ethsys: syscon@1b000000 { |
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86 | compatible = "mediatek,mt7622-ethsys", |
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87 | "syscon"; |