OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | From 4a1990ee249df257848f9583cef71478e3411c3e Mon Sep 17 00:00:00 2001 |
2 | From: Sean Wang <sean.wang@mediatek.com> |
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3 | Date: Thu, 28 Dec 2017 11:24:45 +0800 |
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4 | Subject: [PATCH 201/224] dt-bindings: clock: mediatek: add missing required |
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5 | #reset-cells |
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6 | |||
7 | All ethsys, pciesys and ssusbsys internally include reset controller, so |
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8 | explicitly add back these missing cell definitions to related bindings |
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9 | and examples. |
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10 | |||
11 | Signed-off-by: Sean Wang <sean.wang@mediatek.com> |
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12 | Cc: Rob Herring <robh@kernel.org> |
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13 | Cc: Michael Turquette <mturquette@baylibre.com> |
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14 | Cc: Stephen Boyd <sboyd@codeaurora.org> |
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15 | Cc: linux-clk@vger.kernel.org |
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16 | Reviewed-by: Rob Herring <robh@kernel.org> |
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17 | --- |
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18 | Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt | 1 + |
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19 | Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt | 2 ++ |
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20 | Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt | 2 ++ |
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21 | 3 files changed, 5 insertions(+) |
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22 | |||
23 | --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt |
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24 | +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt |
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25 | @@ -9,6 +9,7 @@ Required Properties: |
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26 | - "mediatek,mt2701-ethsys", "syscon" |
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27 | - "mediatek,mt7622-ethsys", "syscon" |
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28 | - #clock-cells: Must be 1 |
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29 | +- #reset-cells: Must be 1 |
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30 | |||
31 | The ethsys controller uses the common clk binding from |
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32 | Documentation/devicetree/bindings/clock/clock-bindings.txt |
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33 | --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt |
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34 | +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt |
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35 | @@ -8,6 +8,7 @@ Required Properties: |
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36 | - compatible: Should be: |
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37 | - "mediatek,mt7622-pciesys", "syscon" |
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38 | - #clock-cells: Must be 1 |
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39 | +- #reset-cells: Must be 1 |
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40 | |||
41 | The PCIESYS controller uses the common clk binding from |
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42 | Documentation/devicetree/bindings/clock/clock-bindings.txt |
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43 | @@ -19,4 +20,5 @@ pciesys: pciesys@1a100800 { |
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44 | compatible = "mediatek,mt7622-pciesys", "syscon"; |
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45 | reg = <0 0x1a100800 0 0x1000>; |
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46 | #clock-cells = <1>; |
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47 | + #reset-cells = <1>; |
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48 | }; |
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49 | --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt |
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50 | +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt |
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51 | @@ -8,6 +8,7 @@ Required Properties: |
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52 | - compatible: Should be: |
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53 | - "mediatek,mt7622-ssusbsys", "syscon" |
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54 | - #clock-cells: Must be 1 |
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55 | +- #reset-cells: Must be 1 |
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56 | |||
57 | The SSUSBSYS controller uses the common clk binding from |
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58 | Documentation/devicetree/bindings/clock/clock-bindings.txt |
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59 | @@ -19,4 +20,5 @@ ssusbsys: ssusbsys@1a000000 { |
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60 | compatible = "mediatek,mt7622-ssusbsys", "syscon"; |
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61 | reg = <0 0x1a000000 0 0x1000>; |
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62 | #clock-cells = <1>; |
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63 | + #reset-cells = <1>; |
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64 | }; |