OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | From 4dab73d46eb58c142b5d2e7039f12e4e5df357ad Mon Sep 17 00:00:00 2001 |
2 | From: Guochun Mao <guochun.mao@mediatek.com> |
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3 | Date: Mon, 18 Dec 2017 09:47:35 +0800 |
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4 | Subject: [PATCH 196/224] mtd: mtk-nor: modify functions' name more generally |
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5 | |||
6 | Since more and more Mediatek's SoC can use this driver to |
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7 | control spi-nor flash, functions' name with "mt8173_" is |
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8 | no longer properly. Replacing "mt8173_" with "mtk_" will |
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9 | be more accurate to describe these functions' usable scope. |
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10 | |||
11 | Signed-off-by: Guochun Mao <guochun.mao@mediatek.com> |
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12 | Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr> |
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13 | --- |
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14 | drivers/mtd/spi-nor/mtk-quadspi.c | 240 +++++++++++++++++++------------------- |
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15 | 1 file changed, 120 insertions(+), 120 deletions(-) |
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16 | |||
17 | --- a/drivers/mtd/spi-nor/mtk-quadspi.c |
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18 | +++ b/drivers/mtd/spi-nor/mtk-quadspi.c |
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19 | @@ -110,7 +110,7 @@ |
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20 | #define MTK_NOR_PRG_REG(n) (MTK_NOR_PRGDATA0_REG + 4 * (n)) |
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21 | #define MTK_NOR_SHREG(n) (MTK_NOR_SHREG0_REG + 4 * (n)) |
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22 | |||
23 | -struct mt8173_nor { |
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24 | +struct mtk_nor { |
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25 | struct spi_nor nor; |
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26 | struct device *dev; |
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27 | void __iomem *base; /* nor flash base address */ |
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28 | @@ -118,48 +118,48 @@ struct mt8173_nor { |
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29 | struct clk *nor_clk; |
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30 | }; |
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31 | |||
32 | -static void mt8173_nor_set_read_mode(struct mt8173_nor *mt8173_nor) |
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33 | +static void mtk_nor_set_read_mode(struct mtk_nor *mtk_nor) |
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34 | { |
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35 | - struct spi_nor *nor = &mt8173_nor->nor; |
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36 | + struct spi_nor *nor = &mtk_nor->nor; |
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37 | |||
38 | switch (nor->read_proto) { |
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39 | case SNOR_PROTO_1_1_1: |
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40 | - writeb(nor->read_opcode, mt8173_nor->base + |
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41 | + writeb(nor->read_opcode, mtk_nor->base + |
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42 | MTK_NOR_PRGDATA3_REG); |
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43 | - writeb(MTK_NOR_FAST_READ, mt8173_nor->base + |
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44 | + writeb(MTK_NOR_FAST_READ, mtk_nor->base + |
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45 | MTK_NOR_CFG1_REG); |
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46 | break; |
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47 | case SNOR_PROTO_1_1_2: |
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48 | - writeb(nor->read_opcode, mt8173_nor->base + |
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49 | + writeb(nor->read_opcode, mtk_nor->base + |
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50 | MTK_NOR_PRGDATA3_REG); |
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51 | - writeb(MTK_NOR_DUAL_READ_EN, mt8173_nor->base + |
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52 | + writeb(MTK_NOR_DUAL_READ_EN, mtk_nor->base + |
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53 | MTK_NOR_DUAL_REG); |
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54 | break; |
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55 | case SNOR_PROTO_1_1_4: |
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56 | - writeb(nor->read_opcode, mt8173_nor->base + |
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57 | + writeb(nor->read_opcode, mtk_nor->base + |
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58 | MTK_NOR_PRGDATA4_REG); |
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59 | - writeb(MTK_NOR_QUAD_READ_EN, mt8173_nor->base + |
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60 | + writeb(MTK_NOR_QUAD_READ_EN, mtk_nor->base + |
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61 | MTK_NOR_DUAL_REG); |
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62 | break; |
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63 | default: |
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64 | - writeb(MTK_NOR_DUAL_DISABLE, mt8173_nor->base + |
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65 | + writeb(MTK_NOR_DUAL_DISABLE, mtk_nor->base + |
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66 | MTK_NOR_DUAL_REG); |
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67 | break; |
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68 | } |
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69 | } |
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70 | |||
71 | -static int mt8173_nor_execute_cmd(struct mt8173_nor *mt8173_nor, u8 cmdval) |
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72 | +static int mtk_nor_execute_cmd(struct mtk_nor *mtk_nor, u8 cmdval) |
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73 | { |
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74 | int reg; |
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75 | u8 val = cmdval & 0x1f; |
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76 | |||
77 | - writeb(cmdval, mt8173_nor->base + MTK_NOR_CMD_REG); |
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78 | - return readl_poll_timeout(mt8173_nor->base + MTK_NOR_CMD_REG, reg, |
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79 | + writeb(cmdval, mtk_nor->base + MTK_NOR_CMD_REG); |
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80 | + return readl_poll_timeout(mtk_nor->base + MTK_NOR_CMD_REG, reg, |
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81 | !(reg & val), 100, 10000); |
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82 | } |
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83 | |||
84 | -static int mt8173_nor_do_tx_rx(struct mt8173_nor *mt8173_nor, u8 op, |
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85 | - u8 *tx, int txlen, u8 *rx, int rxlen) |
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86 | +static int mtk_nor_do_tx_rx(struct mtk_nor *mtk_nor, u8 op, |
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87 | + u8 *tx, int txlen, u8 *rx, int rxlen) |
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88 | { |
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89 | int len = 1 + txlen + rxlen; |
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90 | int i, ret, idx; |
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91 | @@ -167,26 +167,26 @@ static int mt8173_nor_do_tx_rx(struct mt |
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92 | if (len > MTK_NOR_MAX_SHIFT) |
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93 | return -EINVAL; |
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94 | |||
95 | - writeb(len * 8, mt8173_nor->base + MTK_NOR_CNT_REG); |
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96 | + writeb(len * 8, mtk_nor->base + MTK_NOR_CNT_REG); |
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97 | |||
98 | /* start at PRGDATA5, go down to PRGDATA0 */ |
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99 | idx = MTK_NOR_MAX_RX_TX_SHIFT - 1; |
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100 | |||
101 | /* opcode */ |
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102 | - writeb(op, mt8173_nor->base + MTK_NOR_PRG_REG(idx)); |
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103 | + writeb(op, mtk_nor->base + MTK_NOR_PRG_REG(idx)); |
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104 | idx--; |
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105 | |||
106 | /* program TX data */ |
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107 | for (i = 0; i < txlen; i++, idx--) |
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108 | - writeb(tx[i], mt8173_nor->base + MTK_NOR_PRG_REG(idx)); |
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109 | + writeb(tx[i], mtk_nor->base + MTK_NOR_PRG_REG(idx)); |
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110 | |||
111 | /* clear out rest of TX registers */ |
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112 | while (idx >= 0) { |
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113 | - writeb(0, mt8173_nor->base + MTK_NOR_PRG_REG(idx)); |
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114 | + writeb(0, mtk_nor->base + MTK_NOR_PRG_REG(idx)); |
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115 | idx--; |
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116 | } |
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117 | |||
118 | - ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_PRG_CMD); |
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119 | + ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_PRG_CMD); |
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120 | if (ret) |
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121 | return ret; |
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122 | |||
123 | @@ -195,20 +195,20 @@ static int mt8173_nor_do_tx_rx(struct mt |
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124 | |||
125 | /* read out RX data */ |
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126 | for (i = 0; i < rxlen; i++, idx--) |
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127 | - rx[i] = readb(mt8173_nor->base + MTK_NOR_SHREG(idx)); |
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128 | + rx[i] = readb(mtk_nor->base + MTK_NOR_SHREG(idx)); |
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129 | |||
130 | return 0; |
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131 | } |
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132 | |||
133 | /* Do a WRSR (Write Status Register) command */ |
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134 | -static int mt8173_nor_wr_sr(struct mt8173_nor *mt8173_nor, u8 sr) |
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135 | +static int mtk_nor_wr_sr(struct mtk_nor *mtk_nor, u8 sr) |
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136 | { |
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137 | - writeb(sr, mt8173_nor->base + MTK_NOR_PRGDATA5_REG); |
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138 | - writeb(8, mt8173_nor->base + MTK_NOR_CNT_REG); |
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139 | - return mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_WRSR_CMD); |
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140 | + writeb(sr, mtk_nor->base + MTK_NOR_PRGDATA5_REG); |
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141 | + writeb(8, mtk_nor->base + MTK_NOR_CNT_REG); |
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142 | + return mtk_nor_execute_cmd(mtk_nor, MTK_NOR_WRSR_CMD); |
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143 | } |
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144 | |||
145 | -static int mt8173_nor_write_buffer_enable(struct mt8173_nor *mt8173_nor) |
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146 | +static int mtk_nor_write_buffer_enable(struct mtk_nor *mtk_nor) |
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147 | { |
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148 | u8 reg; |
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149 | |||
150 | @@ -216,27 +216,27 @@ static int mt8173_nor_write_buffer_enabl |
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151 | * 0: pre-fetch buffer use for read |
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152 | * 1: pre-fetch buffer use for page program |
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153 | */ |
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154 | - writel(MTK_NOR_WR_BUF_ENABLE, mt8173_nor->base + MTK_NOR_CFG2_REG); |
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155 | - return readb_poll_timeout(mt8173_nor->base + MTK_NOR_CFG2_REG, reg, |
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156 | + writel(MTK_NOR_WR_BUF_ENABLE, mtk_nor->base + MTK_NOR_CFG2_REG); |
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157 | + return readb_poll_timeout(mtk_nor->base + MTK_NOR_CFG2_REG, reg, |
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158 | 0x01 == (reg & 0x01), 100, 10000); |
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159 | } |
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160 | |||
161 | -static int mt8173_nor_write_buffer_disable(struct mt8173_nor *mt8173_nor) |
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162 | +static int mtk_nor_write_buffer_disable(struct mtk_nor *mtk_nor) |
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163 | { |
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164 | u8 reg; |
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165 | |||
166 | - writel(MTK_NOR_WR_BUF_DISABLE, mt8173_nor->base + MTK_NOR_CFG2_REG); |
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167 | - return readb_poll_timeout(mt8173_nor->base + MTK_NOR_CFG2_REG, reg, |
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168 | + writel(MTK_NOR_WR_BUF_DISABLE, mtk_nor->base + MTK_NOR_CFG2_REG); |
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169 | + return readb_poll_timeout(mtk_nor->base + MTK_NOR_CFG2_REG, reg, |
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170 | MTK_NOR_WR_BUF_DISABLE == (reg & 0x1), 100, |
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171 | 10000); |
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172 | } |
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173 | |||
174 | -static void mt8173_nor_set_addr_width(struct mt8173_nor *mt8173_nor) |
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175 | +static void mtk_nor_set_addr_width(struct mtk_nor *mtk_nor) |
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176 | { |
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177 | u8 val; |
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178 | - struct spi_nor *nor = &mt8173_nor->nor; |
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179 | + struct spi_nor *nor = &mtk_nor->nor; |
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180 | |||
181 | - val = readb(mt8173_nor->base + MTK_NOR_DUAL_REG); |
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182 | + val = readb(mtk_nor->base + MTK_NOR_DUAL_REG); |
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183 | |||
184 | switch (nor->addr_width) { |
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185 | case 3: |
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186 | @@ -246,115 +246,115 @@ static void mt8173_nor_set_addr_width(st |
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187 | val |= MTK_NOR_4B_ADDR_EN; |
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188 | break; |
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189 | default: |
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190 | - dev_warn(mt8173_nor->dev, "Unexpected address width %u.\n", |
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191 | + dev_warn(mtk_nor->dev, "Unexpected address width %u.\n", |
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192 | nor->addr_width); |
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193 | break; |
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194 | } |
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195 | |||
196 | - writeb(val, mt8173_nor->base + MTK_NOR_DUAL_REG); |
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197 | + writeb(val, mtk_nor->base + MTK_NOR_DUAL_REG); |
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198 | } |
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199 | |||
200 | -static void mt8173_nor_set_addr(struct mt8173_nor *mt8173_nor, u32 addr) |
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201 | +static void mtk_nor_set_addr(struct mtk_nor *mtk_nor, u32 addr) |
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202 | { |
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203 | int i; |
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204 | |||
205 | - mt8173_nor_set_addr_width(mt8173_nor); |
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206 | + mtk_nor_set_addr_width(mtk_nor); |
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207 | |||
208 | for (i = 0; i < 3; i++) { |
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209 | - writeb(addr & 0xff, mt8173_nor->base + MTK_NOR_RADR0_REG + i * 4); |
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210 | + writeb(addr & 0xff, mtk_nor->base + MTK_NOR_RADR0_REG + i * 4); |
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211 | addr >>= 8; |
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212 | } |
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213 | /* Last register is non-contiguous */ |
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214 | - writeb(addr & 0xff, mt8173_nor->base + MTK_NOR_RADR3_REG); |
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215 | + writeb(addr & 0xff, mtk_nor->base + MTK_NOR_RADR3_REG); |
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216 | } |
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217 | |||
218 | -static ssize_t mt8173_nor_read(struct spi_nor *nor, loff_t from, size_t length, |
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219 | - u_char *buffer) |
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220 | +static ssize_t mtk_nor_read(struct spi_nor *nor, loff_t from, size_t length, |
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221 | + u_char *buffer) |
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222 | { |
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223 | int i, ret; |
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224 | int addr = (int)from; |
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225 | u8 *buf = (u8 *)buffer; |
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226 | - struct mt8173_nor *mt8173_nor = nor->priv; |
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227 | + struct mtk_nor *mtk_nor = nor->priv; |
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228 | |||
229 | /* set mode for fast read mode ,dual mode or quad mode */ |
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230 | - mt8173_nor_set_read_mode(mt8173_nor); |
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231 | - mt8173_nor_set_addr(mt8173_nor, addr); |
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232 | + mtk_nor_set_read_mode(mtk_nor); |
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233 | + mtk_nor_set_addr(mtk_nor, addr); |
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234 | |||
235 | for (i = 0; i < length; i++) { |
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236 | - ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_PIO_READ_CMD); |
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237 | + ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_PIO_READ_CMD); |
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238 | if (ret < 0) |
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239 | return ret; |
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240 | - buf[i] = readb(mt8173_nor->base + MTK_NOR_RDATA_REG); |
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241 | + buf[i] = readb(mtk_nor->base + MTK_NOR_RDATA_REG); |
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242 | } |
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243 | return length; |
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244 | } |
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245 | |||
246 | -static int mt8173_nor_write_single_byte(struct mt8173_nor *mt8173_nor, |
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247 | - int addr, int length, u8 *data) |
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248 | +static int mtk_nor_write_single_byte(struct mtk_nor *mtk_nor, |
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249 | + int addr, int length, u8 *data) |
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250 | { |
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251 | int i, ret; |
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252 | |||
253 | - mt8173_nor_set_addr(mt8173_nor, addr); |
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254 | + mtk_nor_set_addr(mtk_nor, addr); |
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255 | |||
256 | for (i = 0; i < length; i++) { |
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257 | - writeb(*data++, mt8173_nor->base + MTK_NOR_WDATA_REG); |
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258 | - ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_PIO_WR_CMD); |
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259 | + writeb(*data++, mtk_nor->base + MTK_NOR_WDATA_REG); |
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260 | + ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_PIO_WR_CMD); |
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261 | if (ret < 0) |
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262 | return ret; |
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263 | } |
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264 | return 0; |
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265 | } |
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266 | |||
267 | -static int mt8173_nor_write_buffer(struct mt8173_nor *mt8173_nor, int addr, |
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268 | - const u8 *buf) |
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269 | +static int mtk_nor_write_buffer(struct mtk_nor *mtk_nor, int addr, |
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270 | + const u8 *buf) |
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271 | { |
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272 | int i, bufidx, data; |
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273 | |||
274 | - mt8173_nor_set_addr(mt8173_nor, addr); |
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275 | + mtk_nor_set_addr(mtk_nor, addr); |
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276 | |||
277 | bufidx = 0; |
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278 | for (i = 0; i < SFLASH_WRBUF_SIZE; i += 4) { |
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279 | data = buf[bufidx + 3]<<24 | buf[bufidx + 2]<<16 | |
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280 | buf[bufidx + 1]<<8 | buf[bufidx]; |
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281 | bufidx += 4; |
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282 | - writel(data, mt8173_nor->base + MTK_NOR_PP_DATA_REG); |
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283 | + writel(data, mtk_nor->base + MTK_NOR_PP_DATA_REG); |
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284 | } |
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285 | - return mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_WR_CMD); |
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286 | + return mtk_nor_execute_cmd(mtk_nor, MTK_NOR_WR_CMD); |
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287 | } |
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288 | |||
289 | -static ssize_t mt8173_nor_write(struct spi_nor *nor, loff_t to, size_t len, |
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290 | - const u_char *buf) |
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291 | +static ssize_t mtk_nor_write(struct spi_nor *nor, loff_t to, size_t len, |
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292 | + const u_char *buf) |
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293 | { |
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294 | int ret; |
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295 | - struct mt8173_nor *mt8173_nor = nor->priv; |
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296 | + struct mtk_nor *mtk_nor = nor->priv; |
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297 | size_t i; |
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298 | |||
299 | - ret = mt8173_nor_write_buffer_enable(mt8173_nor); |
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300 | + ret = mtk_nor_write_buffer_enable(mtk_nor); |
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301 | if (ret < 0) { |
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302 | - dev_warn(mt8173_nor->dev, "write buffer enable failed!\n"); |
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303 | + dev_warn(mtk_nor->dev, "write buffer enable failed!\n"); |
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304 | return ret; |
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305 | } |
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306 | |||
307 | for (i = 0; i + SFLASH_WRBUF_SIZE <= len; i += SFLASH_WRBUF_SIZE) { |
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308 | - ret = mt8173_nor_write_buffer(mt8173_nor, to, buf); |
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309 | + ret = mtk_nor_write_buffer(mtk_nor, to, buf); |
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310 | if (ret < 0) { |
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311 | - dev_err(mt8173_nor->dev, "write buffer failed!\n"); |
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312 | + dev_err(mtk_nor->dev, "write buffer failed!\n"); |
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313 | return ret; |
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314 | } |
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315 | to += SFLASH_WRBUF_SIZE; |
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316 | buf += SFLASH_WRBUF_SIZE; |
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317 | } |
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318 | - ret = mt8173_nor_write_buffer_disable(mt8173_nor); |
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319 | + ret = mtk_nor_write_buffer_disable(mtk_nor); |
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320 | if (ret < 0) { |
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321 | - dev_warn(mt8173_nor->dev, "write buffer disable failed!\n"); |
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322 | + dev_warn(mtk_nor->dev, "write buffer disable failed!\n"); |
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323 | return ret; |
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324 | } |
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325 | |||
326 | if (i < len) { |
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327 | - ret = mt8173_nor_write_single_byte(mt8173_nor, to, |
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328 | - (int)(len - i), (u8 *)buf); |
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329 | + ret = mtk_nor_write_single_byte(mtk_nor, to, |
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330 | + (int)(len - i), (u8 *)buf); |
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331 | if (ret < 0) { |
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332 | - dev_err(mt8173_nor->dev, "write single byte failed!\n"); |
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333 | + dev_err(mtk_nor->dev, "write single byte failed!\n"); |
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334 | return ret; |
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335 | } |
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336 | } |
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337 | @@ -362,72 +362,72 @@ static ssize_t mt8173_nor_write(struct s |
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338 | return len; |
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339 | } |
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340 | |||
341 | -static int mt8173_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) |
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342 | +static int mtk_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) |
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343 | { |
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344 | int ret; |
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345 | - struct mt8173_nor *mt8173_nor = nor->priv; |
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346 | + struct mtk_nor *mtk_nor = nor->priv; |
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347 | |||
348 | switch (opcode) { |
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349 | case SPINOR_OP_RDSR: |
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350 | - ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_RDSR_CMD); |
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351 | + ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_RDSR_CMD); |
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352 | if (ret < 0) |
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353 | return ret; |
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354 | if (len == 1) |
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355 | - *buf = readb(mt8173_nor->base + MTK_NOR_RDSR_REG); |
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356 | + *buf = readb(mtk_nor->base + MTK_NOR_RDSR_REG); |
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357 | else |
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358 | - dev_err(mt8173_nor->dev, "len should be 1 for read status!\n"); |
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359 | + dev_err(mtk_nor->dev, "len should be 1 for read status!\n"); |
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360 | break; |
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361 | default: |
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362 | - ret = mt8173_nor_do_tx_rx(mt8173_nor, opcode, NULL, 0, buf, len); |
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363 | + ret = mtk_nor_do_tx_rx(mtk_nor, opcode, NULL, 0, buf, len); |
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364 | break; |
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365 | } |
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366 | return ret; |
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367 | } |
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368 | |||
369 | -static int mt8173_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, |
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370 | - int len) |
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371 | +static int mtk_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, |
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372 | + int len) |
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373 | { |
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374 | int ret; |
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375 | - struct mt8173_nor *mt8173_nor = nor->priv; |
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376 | + struct mtk_nor *mtk_nor = nor->priv; |
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377 | |||
378 | switch (opcode) { |
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379 | case SPINOR_OP_WRSR: |
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380 | /* We only handle 1 byte */ |
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381 | - ret = mt8173_nor_wr_sr(mt8173_nor, *buf); |
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382 | + ret = mtk_nor_wr_sr(mtk_nor, *buf); |
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383 | break; |
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384 | default: |
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385 | - ret = mt8173_nor_do_tx_rx(mt8173_nor, opcode, buf, len, NULL, 0); |
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386 | + ret = mtk_nor_do_tx_rx(mtk_nor, opcode, buf, len, NULL, 0); |
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387 | if (ret) |
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388 | - dev_warn(mt8173_nor->dev, "write reg failure!\n"); |
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389 | + dev_warn(mtk_nor->dev, "write reg failure!\n"); |
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390 | break; |
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391 | } |
||
392 | return ret; |
||
393 | } |
||
394 | |||
395 | -static void mt8173_nor_disable_clk(struct mt8173_nor *mt8173_nor) |
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396 | +static void mtk_nor_disable_clk(struct mtk_nor *mtk_nor) |
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397 | { |
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398 | - clk_disable_unprepare(mt8173_nor->spi_clk); |
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399 | - clk_disable_unprepare(mt8173_nor->nor_clk); |
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400 | + clk_disable_unprepare(mtk_nor->spi_clk); |
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401 | + clk_disable_unprepare(mtk_nor->nor_clk); |
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402 | } |
||
403 | |||
404 | -static int mt8173_nor_enable_clk(struct mt8173_nor *mt8173_nor) |
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405 | +static int mtk_nor_enable_clk(struct mtk_nor *mtk_nor) |
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406 | { |
||
407 | int ret; |
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408 | |||
409 | - ret = clk_prepare_enable(mt8173_nor->spi_clk); |
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410 | + ret = clk_prepare_enable(mtk_nor->spi_clk); |
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411 | if (ret) |
||
412 | return ret; |
||
413 | |||
414 | - ret = clk_prepare_enable(mt8173_nor->nor_clk); |
||
415 | + ret = clk_prepare_enable(mtk_nor->nor_clk); |
||
416 | if (ret) { |
||
417 | - clk_disable_unprepare(mt8173_nor->spi_clk); |
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418 | + clk_disable_unprepare(mtk_nor->spi_clk); |
||
419 | return ret; |
||
420 | } |
||
421 | |||
422 | return 0; |
||
423 | } |
||
424 | |||
425 | -static int mtk_nor_init(struct mt8173_nor *mt8173_nor, |
||
426 | +static int mtk_nor_init(struct mtk_nor *mtk_nor, |
||
427 | struct device_node *flash_node) |
||
428 | { |
||
429 | const struct spi_nor_hwcaps hwcaps = { |
||
430 | @@ -439,18 +439,18 @@ static int mtk_nor_init(struct mt8173_no |
||
431 | struct spi_nor *nor; |
||
432 | |||
433 | /* initialize controller to accept commands */ |
||
434 | - writel(MTK_NOR_ENABLE_SF_CMD, mt8173_nor->base + MTK_NOR_WRPROT_REG); |
||
435 | + writel(MTK_NOR_ENABLE_SF_CMD, mtk_nor->base + MTK_NOR_WRPROT_REG); |
||
436 | |||
437 | - nor = &mt8173_nor->nor; |
||
438 | - nor->dev = mt8173_nor->dev; |
||
439 | - nor->priv = mt8173_nor; |
||
440 | + nor = &mtk_nor->nor; |
||
441 | + nor->dev = mtk_nor->dev; |
||
442 | + nor->priv = mtk_nor; |
||
443 | spi_nor_set_flash_node(nor, flash_node); |
||
444 | |||
445 | /* fill the hooks to spi nor */ |
||
446 | - nor->read = mt8173_nor_read; |
||
447 | - nor->read_reg = mt8173_nor_read_reg; |
||
448 | - nor->write = mt8173_nor_write; |
||
449 | - nor->write_reg = mt8173_nor_write_reg; |
||
450 | + nor->read = mtk_nor_read; |
||
451 | + nor->read_reg = mtk_nor_read_reg; |
||
452 | + nor->write = mtk_nor_write; |
||
453 | + nor->write_reg = mtk_nor_write_reg; |
||
454 | nor->mtd.name = "mtk_nor"; |
||
455 | /* initialized with NULL */ |
||
456 | ret = spi_nor_scan(nor, NULL, &hwcaps); |
||
457 | @@ -465,34 +465,34 @@ static int mtk_nor_drv_probe(struct plat |
||
458 | struct device_node *flash_np; |
||
459 | struct resource *res; |
||
460 | int ret; |
||
461 | - struct mt8173_nor *mt8173_nor; |
||
462 | + struct mtk_nor *mtk_nor; |
||
463 | |||
464 | if (!pdev->dev.of_node) { |
||
465 | dev_err(&pdev->dev, "No DT found\n"); |
||
466 | return -EINVAL; |
||
467 | } |
||
468 | |||
469 | - mt8173_nor = devm_kzalloc(&pdev->dev, sizeof(*mt8173_nor), GFP_KERNEL); |
||
470 | - if (!mt8173_nor) |
||
471 | + mtk_nor = devm_kzalloc(&pdev->dev, sizeof(*mtk_nor), GFP_KERNEL); |
||
472 | + if (!mtk_nor) |
||
473 | return -ENOMEM; |
||
474 | - platform_set_drvdata(pdev, mt8173_nor); |
||
475 | + platform_set_drvdata(pdev, mtk_nor); |
||
476 | |||
477 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
||
478 | - mt8173_nor->base = devm_ioremap_resource(&pdev->dev, res); |
||
479 | - if (IS_ERR(mt8173_nor->base)) |
||
480 | - return PTR_ERR(mt8173_nor->base); |
||
481 | + mtk_nor->base = devm_ioremap_resource(&pdev->dev, res); |
||
482 | + if (IS_ERR(mtk_nor->base)) |
||
483 | + return PTR_ERR(mtk_nor->base); |
||
484 | |||
485 | - mt8173_nor->spi_clk = devm_clk_get(&pdev->dev, "spi"); |
||
486 | - if (IS_ERR(mt8173_nor->spi_clk)) |
||
487 | - return PTR_ERR(mt8173_nor->spi_clk); |
||
488 | + mtk_nor->spi_clk = devm_clk_get(&pdev->dev, "spi"); |
||
489 | + if (IS_ERR(mtk_nor->spi_clk)) |
||
490 | + return PTR_ERR(mtk_nor->spi_clk); |
||
491 | |||
492 | - mt8173_nor->nor_clk = devm_clk_get(&pdev->dev, "sf"); |
||
493 | - if (IS_ERR(mt8173_nor->nor_clk)) |
||
494 | - return PTR_ERR(mt8173_nor->nor_clk); |
||
495 | + mtk_nor->nor_clk = devm_clk_get(&pdev->dev, "sf"); |
||
496 | + if (IS_ERR(mtk_nor->nor_clk)) |
||
497 | + return PTR_ERR(mtk_nor->nor_clk); |
||
498 | |||
499 | - mt8173_nor->dev = &pdev->dev; |
||
500 | + mtk_nor->dev = &pdev->dev; |
||
501 | |||
502 | - ret = mt8173_nor_enable_clk(mt8173_nor); |
||
503 | + ret = mtk_nor_enable_clk(mtk_nor); |
||
504 | if (ret) |
||
505 | return ret; |
||
506 | |||
507 | @@ -503,20 +503,20 @@ static int mtk_nor_drv_probe(struct plat |
||
508 | ret = -ENODEV; |
||
509 | goto nor_free; |
||
510 | } |
||
511 | - ret = mtk_nor_init(mt8173_nor, flash_np); |
||
512 | + ret = mtk_nor_init(mtk_nor, flash_np); |
||
513 | |||
514 | nor_free: |
||
515 | if (ret) |
||
516 | - mt8173_nor_disable_clk(mt8173_nor); |
||
517 | + mtk_nor_disable_clk(mtk_nor); |
||
518 | |||
519 | return ret; |
||
520 | } |
||
521 | |||
522 | static int mtk_nor_drv_remove(struct platform_device *pdev) |
||
523 | { |
||
524 | - struct mt8173_nor *mt8173_nor = platform_get_drvdata(pdev); |
||
525 | + struct mtk_nor *mtk_nor = platform_get_drvdata(pdev); |
||
526 | |||
527 | - mt8173_nor_disable_clk(mt8173_nor); |
||
528 | + mtk_nor_disable_clk(mtk_nor); |
||
529 | |||
530 | return 0; |
||
531 | } |
||
532 | @@ -524,18 +524,18 @@ static int mtk_nor_drv_remove(struct pla |
||
533 | #ifdef CONFIG_PM_SLEEP |
||
534 | static int mtk_nor_suspend(struct device *dev) |
||
535 | { |
||
536 | - struct mt8173_nor *mt8173_nor = dev_get_drvdata(dev); |
||
537 | + struct mtk_nor *mtk_nor = dev_get_drvdata(dev); |
||
538 | |||
539 | - mt8173_nor_disable_clk(mt8173_nor); |
||
540 | + mtk_nor_disable_clk(mtk_nor); |
||
541 | |||
542 | return 0; |
||
543 | } |
||
544 | |||
545 | static int mtk_nor_resume(struct device *dev) |
||
546 | { |
||
547 | - struct mt8173_nor *mt8173_nor = dev_get_drvdata(dev); |
||
548 | + struct mtk_nor *mtk_nor = dev_get_drvdata(dev); |
||
549 | |||
550 | - return mt8173_nor_enable_clk(mt8173_nor); |
||
551 | + return mtk_nor_enable_clk(mtk_nor); |
||
552 | } |
||
553 | |||
554 | static const struct dev_pm_ops mtk_nor_dev_pm_ops = { |