OpenWrt – Blame information for rev 1

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1 office 1 From de14d1d0dc7ecf5c3e7e2a591b4f14e688fa52e6 Mon Sep 17 00:00:00 2001
2 From: Chaotian Jing <chaotian.jing@mediatek.com>
3 Date: Mon, 16 Oct 2017 09:46:37 +0800
4 Subject: [PATCH 158/224] mmc: mediatek: add latch-ck support
5  
6 some platform(eg.mt2701) does not support "stop clk fix", in
7 this case, need set correct latch-ck to avoid crc error caused
8 by stop clock block-internally.
9  
10 Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
11 Tested-by: Sean Wang <sean.wang@mediatek.com>
12 Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
13 ---
14 drivers/mmc/host/mtk-sd.c | 6 ++++++
15 1 file changed, 6 insertions(+)
16  
17 --- a/drivers/mmc/host/mtk-sd.c
18 +++ b/drivers/mmc/host/mtk-sd.c
19 @@ -378,6 +378,7 @@ struct msdc_host {
20 u32 sclk; /* SD/MS bus clock frequency */
21 unsigned char timing;
22 bool vqmmc_enabled;
23 + u32 latch_ck;
24 u32 hs400_ds_delay;
25 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */
26 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */
27 @@ -1661,6 +1662,8 @@ static int msdc_tune_data(struct mmc_hos
28 u32 tune_reg = host->dev_comp->pad_tune_reg;
29 int i, ret;
30  
31 + sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
32 + host->latch_ck);
33 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
34 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
35 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
36 @@ -1773,6 +1776,9 @@ static const struct mmc_host_ops mt_msdc
37 static void msdc_of_property_parse(struct platform_device *pdev,
38 struct msdc_host *host)
39 {
40 + of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck",
41 + &host->latch_ck);
42 +
43 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay",
44 &host->hs400_ds_delay);
45