OpenWrt – Blame information for rev 1

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1 office 1 From ec5192303a3938d0972fde3b1f2526d8d6dd02d7 Mon Sep 17 00:00:00 2001
2 From: "weiyi.lu@mediatek.com" <weiyi.lu@mediatek.com>
3 Date: Mon, 23 Oct 2017 12:10:34 +0800
4 Subject: [PATCH 146/224] clk: mediatek: Add MT2712 clock support
5  
6 Add MT2712 clock support, include topckgen, apmixedsys,
7 infracfg, pericfg, mcucfg and subsystem clocks.
8  
9 Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
10 [sboyd@codeaurora.org: Static on top_clk_data]
11 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
12 ---
13 drivers/clk/mediatek/Kconfig | 50 ++
14 drivers/clk/mediatek/Makefile | 8 +
15 drivers/clk/mediatek/clk-mt2712-bdp.c | 102 +++
16 drivers/clk/mediatek/clk-mt2712-img.c | 80 ++
17 drivers/clk/mediatek/clk-mt2712-jpgdec.c | 76 ++
18 drivers/clk/mediatek/clk-mt2712-mfg.c | 75 ++
19 drivers/clk/mediatek/clk-mt2712-mm.c | 170 ++++
20 drivers/clk/mediatek/clk-mt2712-vdec.c | 94 ++
21 drivers/clk/mediatek/clk-mt2712-venc.c | 77 ++
22 drivers/clk/mediatek/clk-mt2712.c | 1435 ++++++++++++++++++++++++++++++
23 drivers/clk/mediatek/clk-mtk.h | 2 +
24 drivers/clk/mediatek/clk-pll.c | 13 +-
25 12 files changed, 2180 insertions(+), 2 deletions(-)
26 create mode 100644 drivers/clk/mediatek/clk-mt2712-bdp.c
27 create mode 100644 drivers/clk/mediatek/clk-mt2712-img.c
28 create mode 100644 drivers/clk/mediatek/clk-mt2712-jpgdec.c
29 create mode 100644 drivers/clk/mediatek/clk-mt2712-mfg.c
30 create mode 100644 drivers/clk/mediatek/clk-mt2712-mm.c
31 create mode 100644 drivers/clk/mediatek/clk-mt2712-vdec.c
32 create mode 100644 drivers/clk/mediatek/clk-mt2712-venc.c
33 create mode 100644 drivers/clk/mediatek/clk-mt2712.c
34  
35 --- a/drivers/clk/mediatek/Kconfig
36 +++ b/drivers/clk/mediatek/Kconfig
37 @@ -50,6 +50,56 @@ config COMMON_CLK_MT2701_BDPSYS
38 ---help---
39 This driver supports Mediatek MT2701 bdpsys clocks.
40  
41 +config COMMON_CLK_MT2712
42 + bool "Clock driver for Mediatek MT2712"
43 + depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
44 + select COMMON_CLK_MEDIATEK
45 + default ARCH_MEDIATEK && ARM64
46 + ---help---
47 + This driver supports Mediatek MT2712 basic clocks.
48 +
49 +config COMMON_CLK_MT2712_BDPSYS
50 + bool "Clock driver for Mediatek MT2712 bdpsys"
51 + depends on COMMON_CLK_MT2712
52 + ---help---
53 + This driver supports Mediatek MT2712 bdpsys clocks.
54 +
55 +config COMMON_CLK_MT2712_IMGSYS
56 + bool "Clock driver for Mediatek MT2712 imgsys"
57 + depends on COMMON_CLK_MT2712
58 + ---help---
59 + This driver supports Mediatek MT2712 imgsys clocks.
60 +
61 +config COMMON_CLK_MT2712_JPGDECSYS
62 + bool "Clock driver for Mediatek MT2712 jpgdecsys"
63 + depends on COMMON_CLK_MT2712
64 + ---help---
65 + This driver supports Mediatek MT2712 jpgdecsys clocks.
66 +
67 +config COMMON_CLK_MT2712_MFGCFG
68 + bool "Clock driver for Mediatek MT2712 mfgcfg"
69 + depends on COMMON_CLK_MT2712
70 + ---help---
71 + This driver supports Mediatek MT2712 mfgcfg clocks.
72 +
73 +config COMMON_CLK_MT2712_MMSYS
74 + bool "Clock driver for Mediatek MT2712 mmsys"
75 + depends on COMMON_CLK_MT2712
76 + ---help---
77 + This driver supports Mediatek MT2712 mmsys clocks.
78 +
79 +config COMMON_CLK_MT2712_VDECSYS
80 + bool "Clock driver for Mediatek MT2712 vdecsys"
81 + depends on COMMON_CLK_MT2712
82 + ---help---
83 + This driver supports Mediatek MT2712 vdecsys clocks.
84 +
85 +config COMMON_CLK_MT2712_VENCSYS
86 + bool "Clock driver for Mediatek MT2712 vencsys"
87 + depends on COMMON_CLK_MT2712
88 + ---help---
89 + This driver supports Mediatek MT2712 vencsys clocks.
90 +
91 config COMMON_CLK_MT6797
92 bool "Clock driver for Mediatek MT6797"
93 depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
94 --- a/drivers/clk/mediatek/Makefile
95 +++ b/drivers/clk/mediatek/Makefile
96 @@ -13,5 +13,13 @@ obj-$(CONFIG_COMMON_CLK_MT2701_HIFSYS) +
97 obj-$(CONFIG_COMMON_CLK_MT2701_IMGSYS) += clk-mt2701-img.o
98 obj-$(CONFIG_COMMON_CLK_MT2701_MMSYS) += clk-mt2701-mm.o
99 obj-$(CONFIG_COMMON_CLK_MT2701_VDECSYS) += clk-mt2701-vdec.o
100 +obj-$(CONFIG_COMMON_CLK_MT2712) += clk-mt2712.o
101 +obj-$(CONFIG_COMMON_CLK_MT2712_BDPSYS) += clk-mt2712-bdp.o
102 +obj-$(CONFIG_COMMON_CLK_MT2712_IMGSYS) += clk-mt2712-img.o
103 +obj-$(CONFIG_COMMON_CLK_MT2712_JPGDECSYS) += clk-mt2712-jpgdec.o
104 +obj-$(CONFIG_COMMON_CLK_MT2712_MFGCFG) += clk-mt2712-mfg.o
105 +obj-$(CONFIG_COMMON_CLK_MT2712_MMSYS) += clk-mt2712-mm.o
106 +obj-$(CONFIG_COMMON_CLK_MT2712_VDECSYS) += clk-mt2712-vdec.o
107 +obj-$(CONFIG_COMMON_CLK_MT2712_VENCSYS) += clk-mt2712-venc.o
108 obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
109 obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
110 --- /dev/null
111 +++ b/drivers/clk/mediatek/clk-mt2712-bdp.c
112 @@ -0,0 +1,102 @@
113 +/*
114 + * Copyright (c) 2017 MediaTek Inc.
115 + * Author: Weiyi Lu <weiyi.lu@mediatek.com>
116 + *
117 + * This program is free software; you can redistribute it and/or modify
118 + * it under the terms of the GNU General Public License version 2 as
119 + * published by the Free Software Foundation.
120 + *
121 + * This program is distributed in the hope that it will be useful,
122 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
123 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
124 + * GNU General Public License for more details.
125 + */
126 +
127 +#include <linux/clk-provider.h>
128 +#include <linux/platform_device.h>
129 +
130 +#include "clk-mtk.h"
131 +#include "clk-gate.h"
132 +
133 +#include <dt-bindings/clock/mt2712-clk.h>
134 +
135 +static const struct mtk_gate_regs bdp_cg_regs = {
136 + .set_ofs = 0x100,
137 + .clr_ofs = 0x100,
138 + .sta_ofs = 0x100,
139 +};
140 +
141 +#define GATE_BDP(_id, _name, _parent, _shift) { \
142 + .id = _id, \
143 + .name = _name, \
144 + .parent_name = _parent, \
145 + .regs = &bdp_cg_regs, \
146 + .shift = _shift, \
147 + .ops = &mtk_clk_gate_ops_no_setclr, \
148 + }
149 +
150 +static const struct mtk_gate bdp_clks[] = {
151 + GATE_BDP(CLK_BDP_BRIDGE_B, "bdp_bridge_b", "mm_sel", 0),
152 + GATE_BDP(CLK_BDP_BRIDGE_DRAM, "bdp_bridge_d", "mm_sel", 1),
153 + GATE_BDP(CLK_BDP_LARB_DRAM, "bdp_larb_d", "mm_sel", 2),
154 + GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_PXL, "bdp_vdi_pxl", "tvd_sel", 3),
155 + GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_DRAM, "bdp_vdi_d", "mm_sel", 4),
156 + GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_B, "bdp_vdi_b", "mm_sel", 5),
157 + GATE_BDP(CLK_BDP_MT_B, "bdp_fmt_b", "mm_sel", 9),
158 + GATE_BDP(CLK_BDP_DISPFMT_27M, "bdp_27m", "di_sel", 10),
159 + GATE_BDP(CLK_BDP_DISPFMT_27M_VDOUT, "bdp_27m_vdout", "di_sel", 11),
160 + GATE_BDP(CLK_BDP_DISPFMT_27_74_74, "bdp_27_74_74", "di_sel", 12),
161 + GATE_BDP(CLK_BDP_DISPFMT_2FS, "bdp_2fs", "di_sel", 13),
162 + GATE_BDP(CLK_BDP_DISPFMT_2FS_2FS74_148, "bdp_2fs74_148", "di_sel", 14),
163 + GATE_BDP(CLK_BDP_DISPFMT_B, "bdp_b", "mm_sel", 15),
164 + GATE_BDP(CLK_BDP_VDO_DRAM, "bdp_vdo_d", "mm_sel", 16),
165 + GATE_BDP(CLK_BDP_VDO_2FS, "bdp_vdo_2fs", "di_sel", 17),
166 + GATE_BDP(CLK_BDP_VDO_B, "bdp_vdo_b", "mm_sel", 18),
167 + GATE_BDP(CLK_BDP_WR_CHANNEL_DI_PXL, "bdp_di_pxl", "di_sel", 19),
168 + GATE_BDP(CLK_BDP_WR_CHANNEL_DI_DRAM, "bdp_di_d", "mm_sel", 20),
169 + GATE_BDP(CLK_BDP_WR_CHANNEL_DI_B, "bdp_di_b", "mm_sel", 21),
170 + GATE_BDP(CLK_BDP_NR_AGENT, "bdp_nr_agent", "nr_sel", 22),
171 + GATE_BDP(CLK_BDP_NR_DRAM, "bdp_nr_d", "mm_sel", 23),
172 + GATE_BDP(CLK_BDP_NR_B, "bdp_nr_b", "mm_sel", 24),
173 + GATE_BDP(CLK_BDP_BRIDGE_RT_B, "bdp_bridge_rt_b", "mm_sel", 25),
174 + GATE_BDP(CLK_BDP_BRIDGE_RT_DRAM, "bdp_bridge_rt_d", "mm_sel", 26),
175 + GATE_BDP(CLK_BDP_LARB_RT_DRAM, "bdp_larb_rt_d", "mm_sel", 27),
176 + GATE_BDP(CLK_BDP_TVD_TDC, "bdp_tvd_tdc", "mm_sel", 28),
177 + GATE_BDP(CLK_BDP_TVD_54, "bdp_tvd_clk_54", "tvd_sel", 29),
178 + GATE_BDP(CLK_BDP_TVD_CBUS, "bdp_tvd_cbus", "mm_sel", 30),
179 +};
180 +
181 +static int clk_mt2712_bdp_probe(struct platform_device *pdev)
182 +{
183 + struct clk_onecell_data *clk_data;
184 + int r;
185 + struct device_node *node = pdev->dev.of_node;
186 +
187 + clk_data = mtk_alloc_clk_data(CLK_BDP_NR_CLK);
188 +
189 + mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks),
190 + clk_data);
191 +
192 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
193 +
194 + if (r != 0)
195 + pr_err("%s(): could not register clock provider: %d\n",
196 + __func__, r);
197 +
198 + return r;
199 +}
200 +
201 +static const struct of_device_id of_match_clk_mt2712_bdp[] = {
202 + { .compatible = "mediatek,mt2712-bdpsys", },
203 + {}
204 +};
205 +
206 +static struct platform_driver clk_mt2712_bdp_drv = {
207 + .probe = clk_mt2712_bdp_probe,
208 + .driver = {
209 + .name = "clk-mt2712-bdp",
210 + .of_match_table = of_match_clk_mt2712_bdp,
211 + },
212 +};
213 +
214 +builtin_platform_driver(clk_mt2712_bdp_drv);
215 --- /dev/null
216 +++ b/drivers/clk/mediatek/clk-mt2712-img.c
217 @@ -0,0 +1,80 @@
218 +/*
219 + * Copyright (c) 2017 MediaTek Inc.
220 + * Author: Weiyi Lu <weiyi.lu@mediatek.com>
221 + *
222 + * This program is free software; you can redistribute it and/or modify
223 + * it under the terms of the GNU General Public License version 2 as
224 + * published by the Free Software Foundation.
225 + *
226 + * This program is distributed in the hope that it will be useful,
227 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
228 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
229 + * GNU General Public License for more details.
230 + */
231 +
232 +#include <linux/clk-provider.h>
233 +#include <linux/platform_device.h>
234 +
235 +#include "clk-mtk.h"
236 +#include "clk-gate.h"
237 +
238 +#include <dt-bindings/clock/mt2712-clk.h>
239 +
240 +static const struct mtk_gate_regs img_cg_regs = {
241 + .set_ofs = 0x0,
242 + .clr_ofs = 0x0,
243 + .sta_ofs = 0x0,
244 +};
245 +
246 +#define GATE_IMG(_id, _name, _parent, _shift) { \
247 + .id = _id, \
248 + .name = _name, \
249 + .parent_name = _parent, \
250 + .regs = &img_cg_regs, \
251 + .shift = _shift, \
252 + .ops = &mtk_clk_gate_ops_no_setclr, \
253 + }
254 +
255 +static const struct mtk_gate img_clks[] = {
256 + GATE_IMG(CLK_IMG_SMI_LARB2, "img_smi_larb2", "mm_sel", 0),
257 + GATE_IMG(CLK_IMG_SENINF_SCAM_EN, "img_scam_en", "csi0", 3),
258 + GATE_IMG(CLK_IMG_SENINF_CAM_EN, "img_cam_en", "mm_sel", 8),
259 + GATE_IMG(CLK_IMG_CAM_SV_EN, "img_cam_sv_en", "mm_sel", 9),
260 + GATE_IMG(CLK_IMG_CAM_SV1_EN, "img_cam_sv1_en", "mm_sel", 10),
261 + GATE_IMG(CLK_IMG_CAM_SV2_EN, "img_cam_sv2_en", "mm_sel", 11),
262 +};
263 +
264 +static int clk_mt2712_img_probe(struct platform_device *pdev)
265 +{
266 + struct clk_onecell_data *clk_data;
267 + int r;
268 + struct device_node *node = pdev->dev.of_node;
269 +
270 + clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
271 +
272 + mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
273 + clk_data);
274 +
275 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
276 +
277 + if (r != 0)
278 + pr_err("%s(): could not register clock provider: %d\n",
279 + __func__, r);
280 +
281 + return r;
282 +}
283 +
284 +static const struct of_device_id of_match_clk_mt2712_img[] = {
285 + { .compatible = "mediatek,mt2712-imgsys", },
286 + {}
287 +};
288 +
289 +static struct platform_driver clk_mt2712_img_drv = {
290 + .probe = clk_mt2712_img_probe,
291 + .driver = {
292 + .name = "clk-mt2712-img",
293 + .of_match_table = of_match_clk_mt2712_img,
294 + },
295 +};
296 +
297 +builtin_platform_driver(clk_mt2712_img_drv);
298 --- /dev/null
299 +++ b/drivers/clk/mediatek/clk-mt2712-jpgdec.c
300 @@ -0,0 +1,76 @@
301 +/*
302 + * Copyright (c) 2017 MediaTek Inc.
303 + * Author: Weiyi Lu <weiyi.lu@mediatek.com>
304 + *
305 + * This program is free software; you can redistribute it and/or modify
306 + * it under the terms of the GNU General Public License version 2 as
307 + * published by the Free Software Foundation.
308 + *
309 + * This program is distributed in the hope that it will be useful,
310 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
311 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
312 + * GNU General Public License for more details.
313 + */
314 +
315 +#include <linux/clk-provider.h>
316 +#include <linux/platform_device.h>
317 +
318 +#include "clk-mtk.h"
319 +#include "clk-gate.h"
320 +
321 +#include <dt-bindings/clock/mt2712-clk.h>
322 +
323 +static const struct mtk_gate_regs jpgdec_cg_regs = {
324 + .set_ofs = 0x4,
325 + .clr_ofs = 0x8,
326 + .sta_ofs = 0x0,
327 +};
328 +
329 +#define GATE_JPGDEC(_id, _name, _parent, _shift) { \
330 + .id = _id, \
331 + .name = _name, \
332 + .parent_name = _parent, \
333 + .regs = &jpgdec_cg_regs, \
334 + .shift = _shift, \
335 + .ops = &mtk_clk_gate_ops_setclr_inv, \
336 + }
337 +
338 +static const struct mtk_gate jpgdec_clks[] = {
339 + GATE_JPGDEC(CLK_JPGDEC_JPGDEC1, "jpgdec_jpgdec1", "jpgdec_sel", 0),
340 + GATE_JPGDEC(CLK_JPGDEC_JPGDEC, "jpgdec_jpgdec", "jpgdec_sel", 4),
341 +};
342 +
343 +static int clk_mt2712_jpgdec_probe(struct platform_device *pdev)
344 +{
345 + struct clk_onecell_data *clk_data;
346 + int r;
347 + struct device_node *node = pdev->dev.of_node;
348 +
349 + clk_data = mtk_alloc_clk_data(CLK_JPGDEC_NR_CLK);
350 +
351 + mtk_clk_register_gates(node, jpgdec_clks, ARRAY_SIZE(jpgdec_clks),
352 + clk_data);
353 +
354 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
355 +
356 + if (r != 0)
357 + pr_err("%s(): could not register clock provider: %d\n",
358 + __func__, r);
359 +
360 + return r;
361 +}
362 +
363 +static const struct of_device_id of_match_clk_mt2712_jpgdec[] = {
364 + { .compatible = "mediatek,mt2712-jpgdecsys", },
365 + {}
366 +};
367 +
368 +static struct platform_driver clk_mt2712_jpgdec_drv = {
369 + .probe = clk_mt2712_jpgdec_probe,
370 + .driver = {
371 + .name = "clk-mt2712-jpgdec",
372 + .of_match_table = of_match_clk_mt2712_jpgdec,
373 + },
374 +};
375 +
376 +builtin_platform_driver(clk_mt2712_jpgdec_drv);
377 --- /dev/null
378 +++ b/drivers/clk/mediatek/clk-mt2712-mfg.c
379 @@ -0,0 +1,75 @@
380 +/*
381 + * Copyright (c) 2017 MediaTek Inc.
382 + * Author: Weiyi Lu <weiyi.lu@mediatek.com>
383 + *
384 + * This program is free software; you can redistribute it and/or modify
385 + * it under the terms of the GNU General Public License version 2 as
386 + * published by the Free Software Foundation.
387 + *
388 + * This program is distributed in the hope that it will be useful,
389 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
390 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
391 + * GNU General Public License for more details.
392 + */
393 +
394 +#include <linux/clk-provider.h>
395 +#include <linux/platform_device.h>
396 +
397 +#include "clk-mtk.h"
398 +#include "clk-gate.h"
399 +
400 +#include <dt-bindings/clock/mt2712-clk.h>
401 +
402 +static const struct mtk_gate_regs mfg_cg_regs = {
403 + .set_ofs = 0x4,
404 + .clr_ofs = 0x8,
405 + .sta_ofs = 0x0,
406 +};
407 +
408 +#define GATE_MFG(_id, _name, _parent, _shift) { \
409 + .id = _id, \
410 + .name = _name, \
411 + .parent_name = _parent, \
412 + .regs = &mfg_cg_regs, \
413 + .shift = _shift, \
414 + .ops = &mtk_clk_gate_ops_setclr, \
415 + }
416 +
417 +static const struct mtk_gate mfg_clks[] = {
418 + GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0),
419 +};
420 +
421 +static int clk_mt2712_mfg_probe(struct platform_device *pdev)
422 +{
423 + struct clk_onecell_data *clk_data;
424 + int r;
425 + struct device_node *node = pdev->dev.of_node;
426 +
427 + clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK);
428 +
429 + mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks),
430 + clk_data);
431 +
432 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
433 +
434 + if (r != 0)
435 + pr_err("%s(): could not register clock provider: %d\n",
436 + __func__, r);
437 +
438 + return r;
439 +}
440 +
441 +static const struct of_device_id of_match_clk_mt2712_mfg[] = {
442 + { .compatible = "mediatek,mt2712-mfgcfg", },
443 + {}
444 +};
445 +
446 +static struct platform_driver clk_mt2712_mfg_drv = {
447 + .probe = clk_mt2712_mfg_probe,
448 + .driver = {
449 + .name = "clk-mt2712-mfg",
450 + .of_match_table = of_match_clk_mt2712_mfg,
451 + },
452 +};
453 +
454 +builtin_platform_driver(clk_mt2712_mfg_drv);
455 --- /dev/null
456 +++ b/drivers/clk/mediatek/clk-mt2712-mm.c
457 @@ -0,0 +1,170 @@
458 +/*
459 + * Copyright (c) 2017 MediaTek Inc.
460 + * Author: Weiyi Lu <weiyi.lu@mediatek.com>
461 + *
462 + * This program is free software; you can redistribute it and/or modify
463 + * it under the terms of the GNU General Public License version 2 as
464 + * published by the Free Software Foundation.
465 + *
466 + * This program is distributed in the hope that it will be useful,
467 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
468 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
469 + * GNU General Public License for more details.
470 + */
471 +
472 +#include <linux/clk-provider.h>
473 +#include <linux/platform_device.h>
474 +
475 +#include "clk-mtk.h"
476 +#include "clk-gate.h"
477 +
478 +#include <dt-bindings/clock/mt2712-clk.h>
479 +
480 +static const struct mtk_gate_regs mm0_cg_regs = {
481 + .set_ofs = 0x104,
482 + .clr_ofs = 0x108,
483 + .sta_ofs = 0x100,
484 +};
485 +
486 +static const struct mtk_gate_regs mm1_cg_regs = {
487 + .set_ofs = 0x114,
488 + .clr_ofs = 0x118,
489 + .sta_ofs = 0x110,
490 +};
491 +
492 +static const struct mtk_gate_regs mm2_cg_regs = {
493 + .set_ofs = 0x224,
494 + .clr_ofs = 0x228,
495 + .sta_ofs = 0x220,
496 +};
497 +
498 +#define GATE_MM0(_id, _name, _parent, _shift) { \
499 + .id = _id, \
500 + .name = _name, \
501 + .parent_name = _parent, \
502 + .regs = &mm0_cg_regs, \
503 + .shift = _shift, \
504 + .ops = &mtk_clk_gate_ops_setclr, \
505 + }
506 +
507 +#define GATE_MM1(_id, _name, _parent, _shift) { \
508 + .id = _id, \
509 + .name = _name, \
510 + .parent_name = _parent, \
511 + .regs = &mm1_cg_regs, \
512 + .shift = _shift, \
513 + .ops = &mtk_clk_gate_ops_setclr, \
514 + }
515 +
516 +#define GATE_MM2(_id, _name, _parent, _shift) { \
517 + .id = _id, \
518 + .name = _name, \
519 + .parent_name = _parent, \
520 + .regs = &mm2_cg_regs, \
521 + .shift = _shift, \
522 + .ops = &mtk_clk_gate_ops_setclr, \
523 + }
524 +
525 +static const struct mtk_gate mm_clks[] = {
526 + /* MM0 */
527 + GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
528 + GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
529 + GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 2),
530 + GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 3),
531 + GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 4),
532 + GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 5),
533 + GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6),
534 + GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 7),
535 + GATE_MM0(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 8),
536 + GATE_MM0(CLK_MM_MDP_TDSHP1, "mm_mdp_tdshp1", "mm_sel", 9),
537 + GATE_MM0(CLK_MM_MDP_CROP, "mm_mdp_crop", "mm_sel", 10),
538 + GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
539 + GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
540 + GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
541 + GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14),
542 + GATE_MM0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "clk32k", 15),
543 + GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 16),
544 + GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 17),
545 + GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18),
546 + GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19),
547 + GATE_MM0(CLK_MM_DISP_RDMA2, "mm_disp_rdma2", "mm_sel", 20),
548 + GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
549 + GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
550 + GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 23),
551 + GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "mm_sel", 24),
552 + GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25),
553 + GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26),
554 + GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 27),
555 + GATE_MM0(CLK_MM_DISP_SPLIT0, "mm_disp_split0", "mm_sel", 28),
556 + GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 31),
557 + /* MM1 */
558 + GATE_MM1(CLK_MM_DISP_PWM0_MM, "mm_pwm0_mm", "mm_sel", 0),
559 + GATE_MM1(CLK_MM_DISP_PWM0_26M, "mm_pwm0_26m", "pwm_sel", 1),
560 + GATE_MM1(CLK_MM_DISP_PWM1_MM, "mm_pwm1_mm", "mm_sel", 2),
561 + GATE_MM1(CLK_MM_DISP_PWM1_26M, "mm_pwm1_26m", "pwm_sel", 3),
562 + GATE_MM1(CLK_MM_DSI0_ENGINE, "mm_dsi0_engine", "mm_sel", 4),
563 + GATE_MM1(CLK_MM_DSI0_DIGITAL, "mm_dsi0_digital", "dsi0_lntc", 5),
564 + GATE_MM1(CLK_MM_DSI1_ENGINE, "mm_dsi1_engine", "mm_sel", 6),
565 + GATE_MM1(CLK_MM_DSI1_DIGITAL, "mm_dsi1_digital", "dsi1_lntc", 7),
566 + GATE_MM1(CLK_MM_DPI_PIXEL, "mm_dpi_pixel", "vpll_dpix", 8),
567 + GATE_MM1(CLK_MM_DPI_ENGINE, "mm_dpi_engine", "mm_sel", 9),
568 + GATE_MM1(CLK_MM_DPI1_PIXEL, "mm_dpi1_pixel", "vpll3_dpix", 10),
569 + GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "mm_sel", 11),
570 + GATE_MM1(CLK_MM_LVDS_PIXEL, "mm_lvds_pixel", "vpll_dpix", 16),
571 + GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvdstx", 17),
572 + GATE_MM1(CLK_MM_SMI_LARB4, "mm_smi_larb4", "mm_sel", 18),
573 + GATE_MM1(CLK_MM_SMI_COMMON1, "mm_smi_common1", "mm_sel", 21),
574 + GATE_MM1(CLK_MM_SMI_LARB5, "mm_smi_larb5", "mm_sel", 22),
575 + GATE_MM1(CLK_MM_MDP_RDMA2, "mm_mdp_rdma2", "mm_sel", 23),
576 + GATE_MM1(CLK_MM_MDP_TDSHP2, "mm_mdp_tdshp2", "mm_sel", 24),
577 + GATE_MM1(CLK_MM_DISP_OVL2, "mm_disp_ovl2", "mm_sel", 25),
578 + GATE_MM1(CLK_MM_DISP_WDMA2, "mm_disp_wdma2", "mm_sel", 26),
579 + GATE_MM1(CLK_MM_DISP_COLOR2, "mm_disp_color2", "mm_sel", 27),
580 + GATE_MM1(CLK_MM_DISP_AAL1, "mm_disp_aal1", "mm_sel", 28),
581 + GATE_MM1(CLK_MM_DISP_OD1, "mm_disp_od1", "mm_sel", 29),
582 + GATE_MM1(CLK_MM_LVDS1_PIXEL, "mm_lvds1_pixel", "vpll3_dpix", 30),
583 + GATE_MM1(CLK_MM_LVDS1_CTS, "mm_lvds1_cts", "lvdstx3", 31),
584 + /* MM2 */
585 + GATE_MM2(CLK_MM_SMI_LARB7, "mm_smi_larb7", "mm_sel", 0),
586 + GATE_MM2(CLK_MM_MDP_RDMA3, "mm_mdp_rdma3", "mm_sel", 1),
587 + GATE_MM2(CLK_MM_MDP_WROT2, "mm_mdp_wrot2", "mm_sel", 2),
588 + GATE_MM2(CLK_MM_DSI2, "mm_dsi2", "mm_sel", 3),
589 + GATE_MM2(CLK_MM_DSI2_DIGITAL, "mm_dsi2_digital", "dsi0_lntc", 4),
590 + GATE_MM2(CLK_MM_DSI3, "mm_dsi3", "mm_sel", 5),
591 + GATE_MM2(CLK_MM_DSI3_DIGITAL, "mm_dsi3_digital", "dsi1_lntc", 6),
592 +};
593 +
594 +static int clk_mt2712_mm_probe(struct platform_device *pdev)
595 +{
596 + struct clk_onecell_data *clk_data;
597 + int r;
598 + struct device_node *node = pdev->dev.of_node;
599 +
600 + clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
601 +
602 + mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
603 + clk_data);
604 +
605 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
606 +
607 + if (r != 0)
608 + pr_err("%s(): could not register clock provider: %d\n",
609 + __func__, r);
610 +
611 + return r;
612 +}
613 +
614 +static const struct of_device_id of_match_clk_mt2712_mm[] = {
615 + { .compatible = "mediatek,mt2712-mmsys", },
616 + {}
617 +};
618 +
619 +static struct platform_driver clk_mt2712_mm_drv = {
620 + .probe = clk_mt2712_mm_probe,
621 + .driver = {
622 + .name = "clk-mt2712-mm",
623 + .of_match_table = of_match_clk_mt2712_mm,
624 + },
625 +};
626 +
627 +builtin_platform_driver(clk_mt2712_mm_drv);
628 --- /dev/null
629 +++ b/drivers/clk/mediatek/clk-mt2712-vdec.c
630 @@ -0,0 +1,94 @@
631 +/*
632 + * Copyright (c) 2017 MediaTek Inc.
633 + * Author: Weiyi Lu <weiyi.lu@mediatek.com>
634 + *
635 + * This program is free software; you can redistribute it and/or modify
636 + * it under the terms of the GNU General Public License version 2 as
637 + * published by the Free Software Foundation.
638 + *
639 + * This program is distributed in the hope that it will be useful,
640 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
641 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
642 + * GNU General Public License for more details.
643 + */
644 +
645 +#include <linux/clk-provider.h>
646 +#include <linux/platform_device.h>
647 +
648 +#include "clk-mtk.h"
649 +#include "clk-gate.h"
650 +
651 +#include <dt-bindings/clock/mt2712-clk.h>
652 +
653 +static const struct mtk_gate_regs vdec0_cg_regs = {
654 + .set_ofs = 0x0,
655 + .clr_ofs = 0x4,
656 + .sta_ofs = 0x0,
657 +};
658 +
659 +static const struct mtk_gate_regs vdec1_cg_regs = {
660 + .set_ofs = 0x8,
661 + .clr_ofs = 0xc,
662 + .sta_ofs = 0x8,
663 +};
664 +
665 +#define GATE_VDEC0(_id, _name, _parent, _shift) { \
666 + .id = _id, \
667 + .name = _name, \
668 + .parent_name = _parent, \
669 + .regs = &vdec0_cg_regs, \
670 + .shift = _shift, \
671 + .ops = &mtk_clk_gate_ops_setclr_inv, \
672 + }
673 +
674 +#define GATE_VDEC1(_id, _name, _parent, _shift) { \
675 + .id = _id, \
676 + .name = _name, \
677 + .parent_name = _parent, \
678 + .regs = &vdec1_cg_regs, \
679 + .shift = _shift, \
680 + .ops = &mtk_clk_gate_ops_setclr_inv, \
681 + }
682 +
683 +static const struct mtk_gate vdec_clks[] = {
684 + /* VDEC0 */
685 + GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0),
686 + /* VDEC1 */
687 + GATE_VDEC1(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "vdec_sel", 0),
688 + GATE_VDEC1(CLK_VDEC_IMGRZ_CKEN, "vdec_imgrz_cken", "vdec_sel", 1),
689 +};
690 +
691 +static int clk_mt2712_vdec_probe(struct platform_device *pdev)
692 +{
693 + struct clk_onecell_data *clk_data;
694 + int r;
695 + struct device_node *node = pdev->dev.of_node;
696 +
697 + clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
698 +
699 + mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
700 + clk_data);
701 +
702 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
703 +
704 + if (r != 0)
705 + pr_err("%s(): could not register clock provider: %d\n",
706 + __func__, r);
707 +
708 + return r;
709 +}
710 +
711 +static const struct of_device_id of_match_clk_mt2712_vdec[] = {
712 + { .compatible = "mediatek,mt2712-vdecsys", },
713 + {}
714 +};
715 +
716 +static struct platform_driver clk_mt2712_vdec_drv = {
717 + .probe = clk_mt2712_vdec_probe,
718 + .driver = {
719 + .name = "clk-mt2712-vdec",
720 + .of_match_table = of_match_clk_mt2712_vdec,
721 + },
722 +};
723 +
724 +builtin_platform_driver(clk_mt2712_vdec_drv);
725 --- /dev/null
726 +++ b/drivers/clk/mediatek/clk-mt2712-venc.c
727 @@ -0,0 +1,77 @@
728 +/*
729 + * Copyright (c) 2017 MediaTek Inc.
730 + * Author: Weiyi Lu <weiyi.lu@mediatek.com>
731 + *
732 + * This program is free software; you can redistribute it and/or modify
733 + * it under the terms of the GNU General Public License version 2 as
734 + * published by the Free Software Foundation.
735 + *
736 + * This program is distributed in the hope that it will be useful,
737 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
738 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
739 + * GNU General Public License for more details.
740 + */
741 +
742 +#include <linux/clk-provider.h>
743 +#include <linux/platform_device.h>
744 +
745 +#include "clk-mtk.h"
746 +#include "clk-gate.h"
747 +
748 +#include <dt-bindings/clock/mt2712-clk.h>
749 +
750 +static const struct mtk_gate_regs venc_cg_regs = {
751 + .set_ofs = 0x4,
752 + .clr_ofs = 0x8,
753 + .sta_ofs = 0x0,
754 +};
755 +
756 +#define GATE_VENC(_id, _name, _parent, _shift) { \
757 + .id = _id, \
758 + .name = _name, \
759 + .parent_name = _parent, \
760 + .regs = &venc_cg_regs, \
761 + .shift = _shift, \
762 + .ops = &mtk_clk_gate_ops_setclr_inv, \
763 + }
764 +
765 +static const struct mtk_gate venc_clks[] = {
766 + GATE_VENC(CLK_VENC_SMI_COMMON_CON, "venc_smi", "mm_sel", 0),
767 + GATE_VENC(CLK_VENC_VENC, "venc_venc", "venc_sel", 4),
768 + GATE_VENC(CLK_VENC_SMI_LARB6, "venc_smi_larb6", "jpgdec_sel", 12),
769 +};
770 +
771 +static int clk_mt2712_venc_probe(struct platform_device *pdev)
772 +{
773 + struct clk_onecell_data *clk_data;
774 + int r;
775 + struct device_node *node = pdev->dev.of_node;
776 +
777 + clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK);
778 +
779 + mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
780 + clk_data);
781 +
782 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
783 +
784 + if (r != 0)
785 + pr_err("%s(): could not register clock provider: %d\n",
786 + __func__, r);
787 +
788 + return r;
789 +}
790 +
791 +static const struct of_device_id of_match_clk_mt2712_venc[] = {
792 + { .compatible = "mediatek,mt2712-vencsys", },
793 + {}
794 +};
795 +
796 +static struct platform_driver clk_mt2712_venc_drv = {
797 + .probe = clk_mt2712_venc_probe,
798 + .driver = {
799 + .name = "clk-mt2712-venc",
800 + .of_match_table = of_match_clk_mt2712_venc,
801 + },
802 +};
803 +
804 +builtin_platform_driver(clk_mt2712_venc_drv);
805 --- /dev/null
806 +++ b/drivers/clk/mediatek/clk-mt2712.c
807 @@ -0,0 +1,1435 @@
808 +/*
809 + * Copyright (c) 2017 MediaTek Inc.
810 + * Author: Weiyi Lu <weiyi.lu@mediatek.com>
811 + *
812 + * This program is free software; you can redistribute it and/or modify
813 + * it under the terms of the GNU General Public License version 2 as
814 + * published by the Free Software Foundation.
815 + *
816 + * This program is distributed in the hope that it will be useful,
817 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
818 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
819 + * GNU General Public License for more details.
820 + */
821 +
822 +#include <linux/clk.h>
823 +#include <linux/delay.h>
824 +#include <linux/mfd/syscon.h>
825 +#include <linux/of.h>
826 +#include <linux/of_address.h>
827 +#include <linux/of_device.h>
828 +#include <linux/platform_device.h>
829 +#include <linux/slab.h>
830 +
831 +#include "clk-mtk.h"
832 +#include "clk-gate.h"
833 +
834 +#include <dt-bindings/clock/mt2712-clk.h>
835 +
836 +static DEFINE_SPINLOCK(mt2712_clk_lock);
837 +
838 +static const struct mtk_fixed_clk top_fixed_clks[] = {
839 + FIXED_CLK(CLK_TOP_VPLL3_DPIX, "vpll3_dpix", NULL, 200000000),
840 + FIXED_CLK(CLK_TOP_VPLL_DPIX, "vpll_dpix", NULL, 200000000),
841 + FIXED_CLK(CLK_TOP_LTEPLL_FS26M, "ltepll_fs26m", NULL, 26000000),
842 + FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", NULL, 350000000),
843 + FIXED_CLK(CLK_TOP_DSI0_LNTC, "dsi0_lntc", NULL, 143000000),
844 + FIXED_CLK(CLK_TOP_DSI1_LNTC, "dsi1_lntc", NULL, 143000000),
845 + FIXED_CLK(CLK_TOP_LVDSTX3_CLKDIG_CTS, "lvdstx3", NULL, 140000000),
846 + FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, "lvdstx", NULL, 140000000),
847 + FIXED_CLK(CLK_TOP_CLKRTC_EXT, "clkrtc_ext", NULL, 32768),
848 + FIXED_CLK(CLK_TOP_CLKRTC_INT, "clkrtc_int", NULL, 32747),
849 + FIXED_CLK(CLK_TOP_CSI0, "csi0", NULL, 26000000),
850 + FIXED_CLK(CLK_TOP_CVBSPLL, "cvbspll", NULL, 108000000),
851 +};
852 +
853 +static const struct mtk_fixed_factor top_early_divs[] = {
854 + FACTOR(CLK_TOP_SYS_26M, "sys_26m", "clk26m", 1,
855 + 1),
856 + FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "sys_26m", 1,
857 + 2),
858 +};
859 +
860 +static const struct mtk_fixed_factor top_divs[] = {
861 + FACTOR(CLK_TOP_ARMCA35PLL, "armca35pll_ck", "armca35pll", 1,
862 + 1),
863 + FACTOR(CLK_TOP_ARMCA35PLL_600M, "armca35pll_600m", "armca35pll_ck", 1,
864 + 2),
865 + FACTOR(CLK_TOP_ARMCA35PLL_400M, "armca35pll_400m", "armca35pll_ck", 1,
866 + 3),
867 + FACTOR(CLK_TOP_ARMCA72PLL, "armca72pll_ck", "armca72pll", 1,
868 + 1),
869 + FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1,
870 + 1),
871 + FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1,
872 + 2),
873 + FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1,
874 + 2),
875 + FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1,
876 + 4),
877 + FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1,
878 + 8),
879 + FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1,
880 + 16),
881 + FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "syspll_ck", 1,
882 + 3),
883 + FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1,
884 + 2),
885 + FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1,
886 + 4),
887 + FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "syspll_ck", 1,
888 + 5),
889 + FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1,
890 + 2),
891 + FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1,
892 + 4),
893 + FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "syspll_ck", 1,
894 + 7),
895 + FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1,
896 + 2),
897 + FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1,
898 + 4),
899 + FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1,
900 + 1),
901 + FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_ck", 1,
902 + 7),
903 + FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_ck", 1,
904 + 26),
905 + FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll_ck", 1,
906 + 52),
907 + FACTOR(CLK_TOP_UNIVPLL_D104, "univpll_d104", "univpll_ck", 1,
908 + 104),
909 + FACTOR(CLK_TOP_UNIVPLL_D208, "univpll_d208", "univpll_ck", 1,
910 + 208),
911 + FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1,
912 + 2),
913 + FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1,
914 + 2),
915 + FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1,
916 + 4),
917 + FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1,
918 + 8),
919 + FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_ck", 1,
920 + 3),
921 + FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1,
922 + 2),
923 + FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1,
924 + 4),
925 + FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1,
926 + 8),
927 + FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_ck", 1,
928 + 5),
929 + FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1,
930 + 2),
931 + FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1,
932 + 4),
933 + FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1,
934 + 8),
935 + FACTOR(CLK_TOP_F_MP0_PLL1, "f_mp0_pll1_ck", "univpll_d2", 1,
936 + 1),
937 + FACTOR(CLK_TOP_F_MP0_PLL2, "f_mp0_pll2_ck", "univpll1_d2", 1,
938 + 1),
939 + FACTOR(CLK_TOP_F_BIG_PLL1, "f_big_pll1_ck", "univpll_d2", 1,
940 + 1),
941 + FACTOR(CLK_TOP_F_BIG_PLL2, "f_big_pll2_ck", "univpll1_d2", 1,
942 + 1),
943 + FACTOR(CLK_TOP_F_BUS_PLL1, "f_bus_pll1_ck", "univpll_d2", 1,
944 + 1),
945 + FACTOR(CLK_TOP_F_BUS_PLL2, "f_bus_pll2_ck", "univpll1_d2", 1,
946 + 1),
947 + FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1,
948 + 1),
949 + FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1,
950 + 2),
951 + FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1,
952 + 4),
953 + FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1,
954 + 8),
955 + FACTOR(CLK_TOP_APLL1_D16, "apll1_d16", "apll1_ck", 1,
956 + 16),
957 + FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1,
958 + 1),
959 + FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1,
960 + 2),
961 + FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1,
962 + 4),
963 + FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2_ck", 1,
964 + 8),
965 + FACTOR(CLK_TOP_APLL2_D16, "apll2_d16", "apll2_ck", 1,
966 + 16),
967 + FACTOR(CLK_TOP_LVDSPLL, "lvdspll_ck", "lvdspll", 1,
968 + 1),
969 + FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll_ck", 1,
970 + 2),
971 + FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll_ck", 1,
972 + 4),
973 + FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll_ck", 1,
974 + 8),
975 + FACTOR(CLK_TOP_LVDSPLL2, "lvdspll2_ck", "lvdspll2", 1,
976 + 1),
977 + FACTOR(CLK_TOP_LVDSPLL2_D2, "lvdspll2_d2", "lvdspll2_ck", 1,
978 + 2),
979 + FACTOR(CLK_TOP_LVDSPLL2_D4, "lvdspll2_d4", "lvdspll2_ck", 1,
980 + 4),
981 + FACTOR(CLK_TOP_LVDSPLL2_D8, "lvdspll2_d8", "lvdspll2_ck", 1,
982 + 8),
983 + FACTOR(CLK_TOP_ETHERPLL_125M, "etherpll_125m", "etherpll", 1,
984 + 1),
985 + FACTOR(CLK_TOP_ETHERPLL_50M, "etherpll_50m", "etherpll", 1,
986 + 1),
987 + FACTOR(CLK_TOP_CVBS, "cvbs", "cvbspll", 1,
988 + 1),
989 + FACTOR(CLK_TOP_CVBS_D2, "cvbs_d2", "cvbs", 1,
990 + 2),
991 + FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1,
992 + 1),
993 + FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll_ck", 1,
994 + 2),
995 + FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1,
996 + 1),
997 + FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll_ck", 1,
998 + 2),
999 + FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1,
1000 + 1),
1001 + FACTOR(CLK_TOP_VCODECPLL_D2, "vcodecpll_d2", "vcodecpll_ck", 1,
1002 + 2),
1003 + FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1,
1004 + 1),
1005 + FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1,
1006 + 2),
1007 + FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1,
1008 + 4),
1009 + FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1,
1010 + 8),
1011 + FACTOR(CLK_TOP_TVDPLL_429M, "tvdpll_429m", "tvdpll", 1,
1012 + 1),
1013 + FACTOR(CLK_TOP_TVDPLL_429M_D2, "tvdpll_429m_d2", "tvdpll_429m", 1,
1014 + 2),
1015 + FACTOR(CLK_TOP_TVDPLL_429M_D4, "tvdpll_429m_d4", "tvdpll_429m", 1,
1016 + 4),
1017 + FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1,
1018 + 1),
1019 + FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1,
1020 + 2),
1021 + FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1,
1022 + 4),
1023 + FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1,
1024 + 1),
1025 + FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2_ck", 1,
1026 + 2),
1027 + FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2_ck", 1,
1028 + 4),
1029 + FACTOR(CLK_TOP_D2A_ULCLK_6P5M, "d2a_ulclk_6p5m", "clk26m", 1,
1030 + 4),
1031 +};
1032 +
1033 +static const char * const axi_parents[] = {
1034 + "clk26m",
1035 + "syspll1_d2",
1036 + "syspll_d5",
1037 + "syspll1_d4",
1038 + "univpll_d5",
1039 + "univpll2_d2",
1040 + "msdcpll2_ck"
1041 +};
1042 +
1043 +static const char * const mem_parents[] = {
1044 + "clk26m",
1045 + "dmpll_ck"
1046 +};
1047 +
1048 +static const char * const mm_parents[] = {
1049 + "clk26m",
1050 + "vencpll_ck",
1051 + "syspll_d3",
1052 + "syspll1_d2",
1053 + "syspll_d5",
1054 + "syspll1_d4",
1055 + "univpll1_d2",
1056 + "univpll2_d2"
1057 +};
1058 +
1059 +static const char * const pwm_parents[] = {
1060 + "clk26m",
1061 + "univpll2_d4",
1062 + "univpll3_d2",
1063 + "univpll1_d4"
1064 +};
1065 +
1066 +static const char * const vdec_parents[] = {
1067 + "clk26m",
1068 + "vcodecpll_ck",
1069 + "tvdpll_429m",
1070 + "univpll_d3",
1071 + "vencpll_ck",
1072 + "syspll_d3",
1073 + "univpll1_d2",
1074 + "mmpll_d2",
1075 + "syspll3_d2",
1076 + "tvdpll_ck"
1077 +};
1078 +
1079 +static const char * const venc_parents[] = {
1080 + "clk26m",
1081 + "univpll1_d2",
1082 + "mmpll_d2",
1083 + "tvdpll_d2",
1084 + "syspll1_d2",
1085 + "univpll_d5",
1086 + "vcodecpll_d2",
1087 + "univpll2_d2",
1088 + "syspll3_d2"
1089 +};
1090 +
1091 +static const char * const mfg_parents[] = {
1092 + "clk26m",
1093 + "mmpll_ck",
1094 + "univpll_d3",
1095 + "clk26m",
1096 + "clk26m",
1097 + "clk26m",
1098 + "clk26m",
1099 + "clk26m",
1100 + "clk26m",
1101 + "syspll_d3",
1102 + "syspll1_d2",
1103 + "syspll_d5",
1104 + "univpll_d3",
1105 + "univpll1_d2",
1106 + "univpll_d5",
1107 + "univpll2_d2"
1108 +};
1109 +
1110 +static const char * const camtg_parents[] = {
1111 + "clk26m",
1112 + "univpll_d52",
1113 + "univpll_d208",
1114 + "univpll_d104",
1115 + "clk26m_d2",
1116 + "univpll_d26",
1117 + "univpll2_d8",
1118 + "syspll3_d4",
1119 + "syspll3_d2",
1120 + "univpll1_d4",
1121 + "univpll2_d2"
1122 +};
1123 +
1124 +static const char * const uart_parents[] = {
1125 + "clk26m",
1126 + "univpll2_d8"
1127 +};
1128 +
1129 +static const char * const spi_parents[] = {
1130 + "clk26m",
1131 + "univpll2_d4",
1132 + "univpll1_d4",
1133 + "univpll2_d2",
1134 + "univpll3_d2",
1135 + "univpll1_d8"
1136 +};
1137 +
1138 +static const char * const usb20_parents[] = {
1139 + "clk26m",
1140 + "univpll1_d8",
1141 + "univpll3_d4"
1142 +};
1143 +
1144 +static const char * const usb30_parents[] = {
1145 + "clk26m",
1146 + "univpll3_d2",
1147 + "univpll3_d4",
1148 + "univpll2_d4"
1149 +};
1150 +
1151 +static const char * const msdc50_0_h_parents[] = {
1152 + "clk26m",
1153 + "syspll1_d2",
1154 + "syspll2_d2",
1155 + "syspll4_d2",
1156 + "univpll_d5",
1157 + "univpll1_d4"
1158 +};
1159 +
1160 +static const char * const msdc50_0_parents[] = {
1161 + "clk26m",
1162 + "msdcpll_ck",
1163 + "msdcpll_d2",
1164 + "univpll1_d4",
1165 + "syspll2_d2",
1166 + "msdcpll_d4",
1167 + "vencpll_d2",
1168 + "univpll1_d2",
1169 + "msdcpll2_ck",
1170 + "msdcpll2_d2",
1171 + "msdcpll2_d4"
1172 +};
1173 +
1174 +static const char * const msdc30_1_parents[] = {
1175 + "clk26m",
1176 + "univpll2_d2",
1177 + "msdcpll_d2",
1178 + "univpll1_d4",
1179 + "syspll2_d2",
1180 + "univpll_d7",
1181 + "vencpll_d2"
1182 +};
1183 +
1184 +static const char * const msdc30_3_parents[] = {
1185 + "clk26m",
1186 + "msdcpll2_ck",
1187 + "msdcpll2_d2",
1188 + "univpll2_d2",
1189 + "msdcpll2_d4",
1190 + "univpll1_d4",
1191 + "syspll2_d2",
1192 + "syspll_d7",
1193 + "univpll_d7",
1194 + "vencpll_d2",
1195 + "msdcpll_ck",
1196 + "msdcpll_d2",
1197 + "msdcpll_d4"
1198 +};
1199 +
1200 +static const char * const audio_parents[] = {
1201 + "clk26m",
1202 + "syspll3_d4",
1203 + "syspll4_d4",
1204 + "syspll1_d16"
1205 +};
1206 +
1207 +static const char * const aud_intbus_parents[] = {
1208 + "clk26m",
1209 + "syspll1_d4",
1210 + "syspll4_d2",
1211 + "univpll3_d2",
1212 + "univpll2_d8",
1213 + "syspll3_d2",
1214 + "syspll3_d4"
1215 +};
1216 +
1217 +static const char * const pmicspi_parents[] = {
1218 + "clk26m",
1219 + "syspll1_d8",
1220 + "syspll3_d4",
1221 + "syspll1_d16",
1222 + "univpll3_d4",
1223 + "univpll_d26",
1224 + "syspll3_d4"
1225 +};
1226 +
1227 +static const char * const dpilvds1_parents[] = {
1228 + "clk26m",
1229 + "lvdspll2_ck",
1230 + "lvdspll2_d2",
1231 + "lvdspll2_d4",
1232 + "lvdspll2_d8",
1233 + "clkfpc"
1234 +};
1235 +
1236 +static const char * const atb_parents[] = {
1237 + "clk26m",
1238 + "syspll1_d2",
1239 + "univpll_d5",
1240 + "syspll_d5"
1241 +};
1242 +
1243 +static const char * const nr_parents[] = {
1244 + "clk26m",
1245 + "univpll1_d4",
1246 + "syspll2_d2",
1247 + "syspll1_d4",
1248 + "univpll1_d8",
1249 + "univpll3_d2",
1250 + "univpll2_d2",
1251 + "syspll_d5"
1252 +};
1253 +
1254 +static const char * const nfi2x_parents[] = {
1255 + "clk26m",
1256 + "syspll4_d4",
1257 + "univpll3_d4",
1258 + "univpll1_d8",
1259 + "syspll2_d4",
1260 + "univpll3_d2",
1261 + "syspll_d7",
1262 + "syspll2_d2",
1263 + "univpll2_d2",
1264 + "syspll_d5",
1265 + "syspll1_d2"
1266 +};
1267 +
1268 +static const char * const irda_parents[] = {
1269 + "clk26m",
1270 + "univpll2_d4",
1271 + "syspll2_d4",
1272 + "univpll2_d8"
1273 +};
1274 +
1275 +static const char * const cci400_parents[] = {
1276 + "clk26m",
1277 + "vencpll_ck",
1278 + "armca35pll_600m",
1279 + "armca35pll_400m",
1280 + "univpll_d2",
1281 + "syspll_d2",
1282 + "msdcpll_ck",
1283 + "univpll_d3"
1284 +};
1285 +
1286 +static const char * const aud_1_parents[] = {
1287 + "clk26m",
1288 + "apll1_ck",
1289 + "univpll2_d4",
1290 + "univpll2_d8"
1291 +};
1292 +
1293 +static const char * const aud_2_parents[] = {
1294 + "clk26m",
1295 + "apll2_ck",
1296 + "univpll2_d4",
1297 + "univpll2_d8"
1298 +};
1299 +
1300 +static const char * const mem_mfg_parents[] = {
1301 + "clk26m",
1302 + "mmpll_ck",
1303 + "univpll_d3"
1304 +};
1305 +
1306 +static const char * const axi_mfg_parents[] = {
1307 + "clk26m",
1308 + "axi_sel",
1309 + "univpll_d5"
1310 +};
1311 +
1312 +static const char * const scam_parents[] = {
1313 + "clk26m",
1314 + "syspll3_d2",
1315 + "univpll2_d4",
1316 + "syspll2_d4"
1317 +};
1318 +
1319 +static const char * const nfiecc_parents[] = {
1320 + "clk26m",
1321 + "nfi2x_sel",
1322 + "syspll_d7",
1323 + "syspll2_d2",
1324 + "univpll2_d2",
1325 + "univpll_d5",
1326 + "syspll1_d2"
1327 +};
1328 +
1329 +static const char * const pe2_mac_p0_parents[] = {
1330 + "clk26m",
1331 + "syspll1_d8",
1332 + "syspll4_d2",
1333 + "syspll2_d4",
1334 + "univpll2_d4",
1335 + "syspll3_d2"
1336 +};
1337 +
1338 +static const char * const dpilvds_parents[] = {
1339 + "clk26m",
1340 + "lvdspll_ck",
1341 + "lvdspll_d2",
1342 + "lvdspll_d4",
1343 + "lvdspll_d8",
1344 + "clkfpc"
1345 +};
1346 +
1347 +static const char * const hdcp_parents[] = {
1348 + "clk26m",
1349 + "syspll4_d2",
1350 + "syspll3_d4",
1351 + "univpll2_d4"
1352 +};
1353 +
1354 +static const char * const hdcp_24m_parents[] = {
1355 + "clk26m",
1356 + "univpll_d26",
1357 + "univpll_d52",
1358 + "univpll2_d8"
1359 +};
1360 +
1361 +static const char * const rtc_parents[] = {
1362 + "clkrtc_int",
1363 + "clkrtc_ext",
1364 + "clk26m",
1365 + "univpll3_d8"
1366 +};
1367 +
1368 +static const char * const spinor_parents[] = {
1369 + "clk26m",
1370 + "clk26m_d2",
1371 + "syspll4_d4",
1372 + "univpll2_d8",
1373 + "univpll3_d4",
1374 + "syspll4_d2",
1375 + "syspll2_d4",
1376 + "univpll2_d4",
1377 + "etherpll_125m",
1378 + "syspll1_d4"
1379 +};
1380 +
1381 +static const char * const apll_parents[] = {
1382 + "clk26m",
1383 + "apll1_ck",
1384 + "apll1_d2",
1385 + "apll1_d4",
1386 + "apll1_d8",
1387 + "apll1_d16",
1388 + "apll2_ck",
1389 + "apll2_d2",
1390 + "apll2_d4",
1391 + "apll2_d8",
1392 + "apll2_d16",
1393 + "clk26m",
1394 + "clk26m"
1395 +};
1396 +
1397 +static const char * const a1sys_hp_parents[] = {
1398 + "clk26m",
1399 + "apll1_ck",
1400 + "apll1_d2",
1401 + "apll1_d4",
1402 + "apll1_d8"
1403 +};
1404 +
1405 +static const char * const a2sys_hp_parents[] = {
1406 + "clk26m",
1407 + "apll2_ck",
1408 + "apll2_d2",
1409 + "apll2_d4",
1410 + "apll2_d8"
1411 +};
1412 +
1413 +static const char * const asm_l_parents[] = {
1414 + "clk26m",
1415 + "univpll2_d4",
1416 + "univpll2_d2",
1417 + "syspll_d5"
1418 +};
1419 +
1420 +static const char * const i2so1_parents[] = {
1421 + "clk26m",
1422 + "apll1_ck",
1423 + "apll2_ck"
1424 +};
1425 +
1426 +static const char * const ether_125m_parents[] = {
1427 + "clk26m",
1428 + "etherpll_125m",
1429 + "univpll3_d2"
1430 +};
1431 +
1432 +static const char * const ether_50m_parents[] = {
1433 + "clk26m",
1434 + "etherpll_50m",
1435 + "univpll_d26",
1436 + "univpll3_d4"
1437 +};
1438 +
1439 +static const char * const jpgdec_parents[] = {
1440 + "clk26m",
1441 + "univpll_d3",
1442 + "tvdpll_429m",
1443 + "vencpll_ck",
1444 + "syspll_d3",
1445 + "vcodecpll_ck",
1446 + "univpll1_d2",
1447 + "armca35pll_400m",
1448 + "tvdpll_429m_d2",
1449 + "tvdpll_429m_d4"
1450 +};
1451 +
1452 +static const char * const spislv_parents[] = {
1453 + "clk26m",
1454 + "univpll2_d4",
1455 + "univpll1_d4",
1456 + "univpll2_d2",
1457 + "univpll3_d2",
1458 + "univpll1_d8",
1459 + "univpll1_d2",
1460 + "univpll_d5"
1461 +};
1462 +
1463 +static const char * const ether_parents[] = {
1464 + "clk26m",
1465 + "etherpll_50m",
1466 + "univpll_d26"
1467 +};
1468 +
1469 +static const char * const di_parents[] = {
1470 + "clk26m",
1471 + "tvdpll_d2",
1472 + "tvdpll_d4",
1473 + "tvdpll_d8",
1474 + "vencpll_ck",
1475 + "vencpll_d2",
1476 + "cvbs",
1477 + "cvbs_d2"
1478 +};
1479 +
1480 +static const char * const tvd_parents[] = {
1481 + "clk26m",
1482 + "cvbs_d2",
1483 + "univpll2_d8"
1484 +};
1485 +
1486 +static const char * const i2c_parents[] = {
1487 + "clk26m",
1488 + "univpll_d26",
1489 + "univpll2_d4",
1490 + "univpll3_d2",
1491 + "univpll1_d4"
1492 +};
1493 +
1494 +static const char * const msdc0p_aes_parents[] = {
1495 + "clk26m",
1496 + "msdcpll_ck",
1497 + "univpll_d3",
1498 + "vcodecpll_ck"
1499 +};
1500 +
1501 +static const char * const cmsys_parents[] = {
1502 + "clk26m",
1503 + "univpll_d3",
1504 + "syspll_d3",
1505 + "syspll1_d2",
1506 + "syspll2_d2"
1507 +};
1508 +
1509 +static const char * const gcpu_parents[] = {
1510 + "clk26m",
1511 + "syspll_d3",
1512 + "syspll1_d2",
1513 + "univpll1_d2",
1514 + "univpll_d5",
1515 + "univpll3_d2",
1516 + "univpll_d3"
1517 +};
1518 +
1519 +static const char * const aud_apll1_parents[] = {
1520 + "apll1",
1521 + "clkaud_ext_i_1"
1522 +};
1523 +
1524 +static const char * const aud_apll2_parents[] = {
1525 + "apll2",
1526 + "clkaud_ext_i_2"
1527 +};
1528 +
1529 +static const char * const audull_vtx_parents[] = {
1530 + "d2a_ulclk_6p5m",
1531 + "clkaud_ext_i_0"
1532 +};
1533 +
1534 +static struct mtk_composite top_muxes[] = {
1535 + /* CLK_CFG_0 */
1536 + MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x040, 0, 3,
1537 + 7, CLK_IS_CRITICAL),
1538 + MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040, 8, 1,
1539 + 15, CLK_IS_CRITICAL),
1540 + MUX_GATE(CLK_TOP_MM_SEL, "mm_sel",
1541 + mm_parents, 0x040, 24, 3, 31),
1542 + /* CLK_CFG_1 */
1543 + MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel",
1544 + pwm_parents, 0x050, 0, 2, 7),
1545 + MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel",
1546 + vdec_parents, 0x050, 8, 4, 15),
1547 + MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel",
1548 + venc_parents, 0x050, 16, 4, 23),
1549 + MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel",
1550 + mfg_parents, 0x050, 24, 4, 31),
1551 + /* CLK_CFG_2 */
1552 + MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel",
1553 + camtg_parents, 0x060, 0, 4, 7),
1554 + MUX_GATE(CLK_TOP_UART_SEL, "uart_sel",
1555 + uart_parents, 0x060, 8, 1, 15),
1556 + MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel",
1557 + spi_parents, 0x060, 16, 3, 23),
1558 + MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel",
1559 + usb20_parents, 0x060, 24, 2, 31),
1560 + /* CLK_CFG_3 */
1561 + MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel",
1562 + usb30_parents, 0x070, 0, 2, 7),
1563 + MUX_GATE(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc50_0_h_sel",
1564 + msdc50_0_h_parents, 0x070, 8, 3, 15),
1565 + MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
1566 + msdc50_0_parents, 0x070, 16, 4, 23),
1567 + MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
1568 + msdc30_1_parents, 0x070, 24, 3, 31),
1569 + /* CLK_CFG_4 */
1570 + MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel",
1571 + msdc30_1_parents, 0x080, 0, 3, 7),
1572 + MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel",
1573 + msdc30_3_parents, 0x080, 8, 4, 15),
1574 + MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel",
1575 + audio_parents, 0x080, 16, 2, 23),
1576 + MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
1577 + aud_intbus_parents, 0x080, 24, 3, 31),
1578 + /* CLK_CFG_5 */
1579 + MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel",
1580 + pmicspi_parents, 0x090, 0, 3, 7),
1581 + MUX_GATE(CLK_TOP_DPILVDS1_SEL, "dpilvds1_sel",
1582 + dpilvds1_parents, 0x090, 8, 3, 15),
1583 + MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel",
1584 + atb_parents, 0x090, 16, 2, 23),
1585 + MUX_GATE(CLK_TOP_NR_SEL, "nr_sel",
1586 + nr_parents, 0x090, 24, 3, 31),
1587 + /* CLK_CFG_6 */
1588 + MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel",
1589 + nfi2x_parents, 0x0a0, 0, 4, 7),
1590 + MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel",
1591 + irda_parents, 0x0a0, 8, 2, 15),
1592 + MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel",
1593 + cci400_parents, 0x0a0, 16, 3, 23),
1594 + MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel",
1595 + aud_1_parents, 0x0a0, 24, 2, 31),
1596 + /* CLK_CFG_7 */
1597 + MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel",
1598 + aud_2_parents, 0x0b0, 0, 2, 7),
1599 + MUX_GATE(CLK_TOP_MEM_MFG_IN_AS_SEL, "mem_mfg_sel",
1600 + mem_mfg_parents, 0x0b0, 8, 2, 15),
1601 + MUX_GATE(CLK_TOP_AXI_MFG_IN_AS_SEL, "axi_mfg_sel",
1602 + axi_mfg_parents, 0x0b0, 16, 2, 23),
1603 + MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel",
1604 + scam_parents, 0x0b0, 24, 2, 31),
1605 + /* CLK_CFG_8 */
1606 + MUX_GATE(CLK_TOP_NFIECC_SEL, "nfiecc_sel",
1607 + nfiecc_parents, 0x0c0, 0, 3, 7),
1608 + MUX_GATE(CLK_TOP_PE2_MAC_P0_SEL, "pe2_mac_p0_sel",
1609 + pe2_mac_p0_parents, 0x0c0, 8, 3, 15),
1610 + MUX_GATE(CLK_TOP_PE2_MAC_P1_SEL, "pe2_mac_p1_sel",
1611 + pe2_mac_p0_parents, 0x0c0, 16, 3, 23),
1612 + MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel",
1613 + dpilvds_parents, 0x0c0, 24, 3, 31),
1614 + /* CLK_CFG_9 */
1615 + MUX_GATE(CLK_TOP_MSDC50_3_HCLK_SEL, "msdc50_3_h_sel",
1616 + msdc50_0_h_parents, 0x0d0, 0, 3, 7),
1617 + MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel",
1618 + hdcp_parents, 0x0d0, 8, 2, 15),
1619 + MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel",
1620 + hdcp_24m_parents, 0x0d0, 16, 2, 23),
1621 + MUX_GATE_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x0d0, 24, 2,
1622 + 31, CLK_IS_CRITICAL),
1623 + /* CLK_CFG_10 */
1624 + MUX_GATE(CLK_TOP_SPINOR_SEL, "spinor_sel",
1625 + spinor_parents, 0x500, 0, 4, 7),
1626 + MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel",
1627 + apll_parents, 0x500, 8, 4, 15),
1628 + MUX_GATE(CLK_TOP_APLL2_SEL, "apll2_sel",
1629 + apll_parents, 0x500, 16, 4, 23),
1630 + MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel",
1631 + a1sys_hp_parents, 0x500, 24, 3, 31),
1632 + /* CLK_CFG_11 */
1633 + MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel",
1634 + a2sys_hp_parents, 0x510, 0, 3, 7),
1635 + MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel",
1636 + asm_l_parents, 0x510, 8, 2, 15),
1637 + MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel",
1638 + asm_l_parents, 0x510, 16, 2, 23),
1639 + MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel",
1640 + asm_l_parents, 0x510, 24, 2, 31),
1641 + /* CLK_CFG_12 */
1642 + MUX_GATE(CLK_TOP_I2SO1_SEL, "i2so1_sel",
1643 + i2so1_parents, 0x520, 0, 2, 7),
1644 + MUX_GATE(CLK_TOP_I2SO2_SEL, "i2so2_sel",
1645 + i2so1_parents, 0x520, 8, 2, 15),
1646 + MUX_GATE(CLK_TOP_I2SO3_SEL, "i2so3_sel",
1647 + i2so1_parents, 0x520, 16, 2, 23),
1648 + MUX_GATE(CLK_TOP_TDMO0_SEL, "tdmo0_sel",
1649 + i2so1_parents, 0x520, 24, 2, 31),
1650 + /* CLK_CFG_13 */
1651 + MUX_GATE(CLK_TOP_TDMO1_SEL, "tdmo1_sel",
1652 + i2so1_parents, 0x530, 0, 2, 7),
1653 + MUX_GATE(CLK_TOP_I2SI1_SEL, "i2si1_sel",
1654 + i2so1_parents, 0x530, 8, 2, 15),
1655 + MUX_GATE(CLK_TOP_I2SI2_SEL, "i2si2_sel",
1656 + i2so1_parents, 0x530, 16, 2, 23),
1657 + MUX_GATE(CLK_TOP_I2SI3_SEL, "i2si3_sel",
1658 + i2so1_parents, 0x530, 24, 2, 31),
1659 + /* CLK_CFG_14 */
1660 + MUX_GATE(CLK_TOP_ETHER_125M_SEL, "ether_125m_sel",
1661 + ether_125m_parents, 0x540, 0, 2, 7),
1662 + MUX_GATE(CLK_TOP_ETHER_50M_SEL, "ether_50m_sel",
1663 + ether_50m_parents, 0x540, 8, 2, 15),
1664 + MUX_GATE(CLK_TOP_JPGDEC_SEL, "jpgdec_sel",
1665 + jpgdec_parents, 0x540, 16, 4, 23),
1666 + MUX_GATE(CLK_TOP_SPISLV_SEL, "spislv_sel",
1667 + spislv_parents, 0x540, 24, 3, 31),
1668 + /* CLK_CFG_15 */
1669 + MUX_GATE(CLK_TOP_ETHER_50M_RMII_SEL, "ether_sel",
1670 + ether_parents, 0x550, 0, 2, 7),
1671 + MUX_GATE(CLK_TOP_CAM2TG_SEL, "cam2tg_sel",
1672 + camtg_parents, 0x550, 8, 4, 15),
1673 + MUX_GATE(CLK_TOP_DI_SEL, "di_sel",
1674 + di_parents, 0x550, 16, 3, 23),
1675 + MUX_GATE(CLK_TOP_TVD_SEL, "tvd_sel",
1676 + tvd_parents, 0x550, 24, 2, 31),
1677 + /* CLK_CFG_16 */
1678 + MUX_GATE(CLK_TOP_I2C_SEL, "i2c_sel",
1679 + i2c_parents, 0x560, 0, 3, 7),
1680 + MUX_GATE(CLK_TOP_PWM_INFRA_SEL, "pwm_infra_sel",
1681 + pwm_parents, 0x560, 8, 2, 15),
1682 + MUX_GATE(CLK_TOP_MSDC0P_AES_SEL, "msdc0p_aes_sel",
1683 + msdc0p_aes_parents, 0x560, 16, 2, 23),
1684 + MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel",
1685 + cmsys_parents, 0x560, 24, 3, 31),
1686 + /* CLK_CFG_17 */
1687 + MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel",
1688 + gcpu_parents, 0x570, 0, 3, 7),
1689 + /* CLK_AUDDIV_4 */
1690 + MUX(CLK_TOP_AUD_APLL1_SEL, "aud_apll1_sel",
1691 + aud_apll1_parents, 0x134, 0, 1),
1692 + MUX(CLK_TOP_AUD_APLL2_SEL, "aud_apll2_sel",
1693 + aud_apll2_parents, 0x134, 1, 1),
1694 + MUX(CLK_TOP_DA_AUDULL_VTX_6P5M_SEL, "audull_vtx_sel",
1695 + audull_vtx_parents, 0x134, 31, 1),
1696 +};
1697 +
1698 +static const char * const mcu_mp0_parents[] = {
1699 + "clk26m",
1700 + "armca35pll_ck",
1701 + "f_mp0_pll1_ck",
1702 + "f_mp0_pll2_ck"
1703 +};
1704 +
1705 +static const char * const mcu_mp2_parents[] = {
1706 + "clk26m",
1707 + "armca72pll_ck",
1708 + "f_big_pll1_ck",
1709 + "f_big_pll2_ck"
1710 +};
1711 +
1712 +static const char * const mcu_bus_parents[] = {
1713 + "clk26m",
1714 + "cci400_sel",
1715 + "f_bus_pll1_ck",
1716 + "f_bus_pll2_ck"
1717 +};
1718 +
1719 +static struct mtk_composite mcu_muxes[] = {
1720 + /* mp0_pll_divider_cfg */
1721 + MUX_GATE_FLAGS(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0,
1722 + 9, 2, -1, CLK_IS_CRITICAL),
1723 + /* mp2_pll_divider_cfg */
1724 + MUX_GATE_FLAGS(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8,
1725 + 9, 2, -1, CLK_IS_CRITICAL),
1726 + /* bus_pll_divider_cfg */
1727 + MUX_GATE_FLAGS(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0,
1728 + 9, 2, -1, CLK_IS_CRITICAL),
1729 +};
1730 +
1731 +static const struct mtk_clk_divider top_adj_divs[] = {
1732 + DIV_ADJ(CLK_TOP_APLL_DIV0, "apll_div0", "i2so1_sel", 0x124, 0, 8),
1733 + DIV_ADJ(CLK_TOP_APLL_DIV1, "apll_div1", "i2so2_sel", 0x124, 8, 8),
1734 + DIV_ADJ(CLK_TOP_APLL_DIV2, "apll_div2", "i2so3_sel", 0x124, 16, 8),
1735 + DIV_ADJ(CLK_TOP_APLL_DIV3, "apll_div3", "tdmo0_sel", 0x124, 24, 8),
1736 + DIV_ADJ(CLK_TOP_APLL_DIV4, "apll_div4", "tdmo1_sel", 0x128, 0, 8),
1737 + DIV_ADJ(CLK_TOP_APLL_DIV5, "apll_div5", "i2si1_sel", 0x128, 8, 8),
1738 + DIV_ADJ(CLK_TOP_APLL_DIV6, "apll_div6", "i2si2_sel", 0x128, 16, 8),
1739 + DIV_ADJ(CLK_TOP_APLL_DIV7, "apll_div7", "i2si3_sel", 0x128, 24, 8),
1740 +};
1741 +
1742 +static const struct mtk_gate_regs top_cg_regs = {
1743 + .set_ofs = 0x120,
1744 + .clr_ofs = 0x120,
1745 + .sta_ofs = 0x120,
1746 +};
1747 +
1748 +#define GATE_TOP(_id, _name, _parent, _shift) { \
1749 + .id = _id, \
1750 + .name = _name, \
1751 + .parent_name = _parent, \
1752 + .regs = &top_cg_regs, \
1753 + .shift = _shift, \
1754 + .ops = &mtk_clk_gate_ops_no_setclr, \
1755 + }
1756 +
1757 +static const struct mtk_gate top_clks[] = {
1758 + GATE_TOP(CLK_TOP_APLL_DIV_PDN0, "apll_div_pdn0", "i2so1_sel", 0),
1759 + GATE_TOP(CLK_TOP_APLL_DIV_PDN1, "apll_div_pdn1", "i2so2_sel", 1),
1760 + GATE_TOP(CLK_TOP_APLL_DIV_PDN2, "apll_div_pdn2", "i2so3_sel", 2),
1761 + GATE_TOP(CLK_TOP_APLL_DIV_PDN3, "apll_div_pdn3", "tdmo0_sel", 3),
1762 + GATE_TOP(CLK_TOP_APLL_DIV_PDN4, "apll_div_pdn4", "tdmo1_sel", 4),
1763 + GATE_TOP(CLK_TOP_APLL_DIV_PDN5, "apll_div_pdn5", "i2si1_sel", 5),
1764 + GATE_TOP(CLK_TOP_APLL_DIV_PDN6, "apll_div_pdn6", "i2si2_sel", 6),
1765 + GATE_TOP(CLK_TOP_APLL_DIV_PDN7, "apll_div_pdn7", "i2si3_sel", 7),
1766 +};
1767 +
1768 +static const struct mtk_gate_regs infra_cg_regs = {
1769 + .set_ofs = 0x40,
1770 + .clr_ofs = 0x44,
1771 + .sta_ofs = 0x40,
1772 +};
1773 +
1774 +#define GATE_INFRA(_id, _name, _parent, _shift) { \
1775 + .id = _id, \
1776 + .name = _name, \
1777 + .parent_name = _parent, \
1778 + .regs = &infra_cg_regs, \
1779 + .shift = _shift, \
1780 + .ops = &mtk_clk_gate_ops_setclr, \
1781 + }
1782 +
1783 +static const struct mtk_gate infra_clks[] = {
1784 + GATE_INFRA(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0),
1785 + GATE_INFRA(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6),
1786 + GATE_INFRA(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8),
1787 + GATE_INFRA(CLK_INFRA_KP, "infra_kp", "axi_sel", 16),
1788 + GATE_INFRA(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "spi_sel", 24),
1789 + GATE_INFRA(CLK_INFRA_AO_SPI1, "infra_ao_spi1", "spislv_sel", 25),
1790 + GATE_INFRA(CLK_INFRA_AO_UART5, "infra_ao_uart5", "axi_sel", 26),
1791 +};
1792 +
1793 +static const struct mtk_gate_regs peri0_cg_regs = {
1794 + .set_ofs = 0x8,
1795 + .clr_ofs = 0x10,
1796 + .sta_ofs = 0x18,
1797 +};
1798 +
1799 +static const struct mtk_gate_regs peri1_cg_regs = {
1800 + .set_ofs = 0xc,
1801 + .clr_ofs = 0x14,
1802 + .sta_ofs = 0x1c,
1803 +};
1804 +
1805 +static const struct mtk_gate_regs peri2_cg_regs = {
1806 + .set_ofs = 0x42c,
1807 + .clr_ofs = 0x42c,
1808 + .sta_ofs = 0x42c,
1809 +};
1810 +
1811 +#define GATE_PERI0(_id, _name, _parent, _shift) { \
1812 + .id = _id, \
1813 + .name = _name, \
1814 + .parent_name = _parent, \
1815 + .regs = &peri0_cg_regs, \
1816 + .shift = _shift, \
1817 + .ops = &mtk_clk_gate_ops_setclr, \
1818 + }
1819 +
1820 +#define GATE_PERI1(_id, _name, _parent, _shift) { \
1821 + .id = _id, \
1822 + .name = _name, \
1823 + .parent_name = _parent, \
1824 + .regs = &peri1_cg_regs, \
1825 + .shift = _shift, \
1826 + .ops = &mtk_clk_gate_ops_setclr, \
1827 + }
1828 +
1829 +#define GATE_PERI2(_id, _name, _parent, _shift) { \
1830 + .id = _id, \
1831 + .name = _name, \
1832 + .parent_name = _parent, \
1833 + .regs = &peri2_cg_regs, \
1834 + .shift = _shift, \
1835 + .ops = &mtk_clk_gate_ops_no_setclr_inv, \
1836 + }
1837 +
1838 +static const struct mtk_gate peri_clks[] = {
1839 + /* PERI0 */
1840 + GATE_PERI0(CLK_PERI_NFI, "per_nfi",
1841 + "axi_sel", 0),
1842 + GATE_PERI0(CLK_PERI_THERM, "per_therm",
1843 + "axi_sel", 1),
1844 + GATE_PERI0(CLK_PERI_PWM0, "per_pwm0",
1845 + "pwm_sel", 2),
1846 + GATE_PERI0(CLK_PERI_PWM1, "per_pwm1",
1847 + "pwm_sel", 3),
1848 + GATE_PERI0(CLK_PERI_PWM2, "per_pwm2",
1849 + "pwm_sel", 4),
1850 + GATE_PERI0(CLK_PERI_PWM3, "per_pwm3",
1851 + "pwm_sel", 5),
1852 + GATE_PERI0(CLK_PERI_PWM4, "per_pwm4",
1853 + "pwm_sel", 6),
1854 + GATE_PERI0(CLK_PERI_PWM5, "per_pwm5",
1855 + "pwm_sel", 7),
1856 + GATE_PERI0(CLK_PERI_PWM6, "per_pwm6",
1857 + "pwm_sel", 8),
1858 + GATE_PERI0(CLK_PERI_PWM7, "per_pwm7",
1859 + "pwm_sel", 9),
1860 + GATE_PERI0(CLK_PERI_PWM, "per_pwm",
1861 + "pwm_sel", 10),
1862 + GATE_PERI0(CLK_PERI_AP_DMA, "per_ap_dma",
1863 + "axi_sel", 13),
1864 + GATE_PERI0(CLK_PERI_MSDC30_0, "per_msdc30_0",
1865 + "msdc50_0_sel", 14),
1866 + GATE_PERI0(CLK_PERI_MSDC30_1, "per_msdc30_1",
1867 + "msdc30_1_sel", 15),
1868 + GATE_PERI0(CLK_PERI_MSDC30_2, "per_msdc30_2",
1869 + "msdc30_2_sel", 16),
1870 + GATE_PERI0(CLK_PERI_MSDC30_3, "per_msdc30_3",
1871 + "msdc30_3_sel", 17),
1872 + GATE_PERI0(CLK_PERI_UART0, "per_uart0",
1873 + "uart_sel", 20),
1874 + GATE_PERI0(CLK_PERI_UART1, "per_uart1",
1875 + "uart_sel", 21),
1876 + GATE_PERI0(CLK_PERI_UART2, "per_uart2",
1877 + "uart_sel", 22),
1878 + GATE_PERI0(CLK_PERI_UART3, "per_uart3",
1879 + "uart_sel", 23),
1880 + GATE_PERI0(CLK_PERI_I2C0, "per_i2c0",
1881 + "axi_sel", 24),
1882 + GATE_PERI0(CLK_PERI_I2C1, "per_i2c1",
1883 + "axi_sel", 25),
1884 + GATE_PERI0(CLK_PERI_I2C2, "per_i2c2",
1885 + "axi_sel", 26),
1886 + GATE_PERI0(CLK_PERI_I2C3, "per_i2c3",
1887 + "axi_sel", 27),
1888 + GATE_PERI0(CLK_PERI_I2C4, "per_i2c4",
1889 + "axi_sel", 28),
1890 + GATE_PERI0(CLK_PERI_AUXADC, "per_auxadc",
1891 + "ltepll_fs26m", 29),
1892 + GATE_PERI0(CLK_PERI_SPI0, "per_spi0",
1893 + "spi_sel", 30),
1894 + /* PERI1 */
1895 + GATE_PERI1(CLK_PERI_SPI, "per_spi",
1896 + "spinor_sel", 1),
1897 + GATE_PERI1(CLK_PERI_I2C5, "per_i2c5",
1898 + "axi_sel", 3),
1899 + GATE_PERI1(CLK_PERI_SPI2, "per_spi2",
1900 + "spi_sel", 5),
1901 + GATE_PERI1(CLK_PERI_SPI3, "per_spi3",
1902 + "spi_sel", 6),
1903 + GATE_PERI1(CLK_PERI_SPI5, "per_spi5",
1904 + "spi_sel", 8),
1905 + GATE_PERI1(CLK_PERI_UART4, "per_uart4",
1906 + "uart_sel", 9),
1907 + GATE_PERI1(CLK_PERI_SFLASH, "per_sflash",
1908 + "uart_sel", 11),
1909 + GATE_PERI1(CLK_PERI_GMAC, "per_gmac",
1910 + "uart_sel", 12),
1911 + GATE_PERI1(CLK_PERI_PCIE0, "per_pcie0",
1912 + "uart_sel", 14),
1913 + GATE_PERI1(CLK_PERI_PCIE1, "per_pcie1",
1914 + "uart_sel", 15),
1915 + GATE_PERI1(CLK_PERI_GMAC_PCLK, "per_gmac_pclk",
1916 + "uart_sel", 16),
1917 + /* PERI2 */
1918 + GATE_PERI2(CLK_PERI_MSDC50_0_EN, "per_msdc50_0_en",
1919 + "msdc50_0_sel", 0),
1920 + GATE_PERI2(CLK_PERI_MSDC30_1_EN, "per_msdc30_1_en",
1921 + "msdc30_1_sel", 1),
1922 + GATE_PERI2(CLK_PERI_MSDC30_2_EN, "per_msdc30_2_en",
1923 + "msdc30_2_sel", 2),
1924 + GATE_PERI2(CLK_PERI_MSDC30_3_EN, "per_msdc30_3_en",
1925 + "msdc30_3_sel", 3),
1926 + GATE_PERI2(CLK_PERI_MSDC50_0_HCLK_EN, "per_msdc50_0_h",
1927 + "msdc50_0_h_sel", 4),
1928 + GATE_PERI2(CLK_PERI_MSDC50_3_HCLK_EN, "per_msdc50_3_h",
1929 + "msdc50_3_h_sel", 5),
1930 +};
1931 +
1932 +#define MT2712_PLL_FMAX (3000UL * MHZ)
1933 +
1934 +#define CON0_MT2712_RST_BAR BIT(24)
1935 +
1936 +#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
1937 + _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
1938 + _tuner_en_bit, _pcw_reg, _pcw_shift, \
1939 + _div_table) { \
1940 + .id = _id, \
1941 + .name = _name, \
1942 + .reg = _reg, \
1943 + .pwr_reg = _pwr_reg, \
1944 + .en_mask = _en_mask, \
1945 + .flags = _flags, \
1946 + .rst_bar_mask = CON0_MT2712_RST_BAR, \
1947 + .fmax = MT2712_PLL_FMAX, \
1948 + .pcwbits = _pcwbits, \
1949 + .pd_reg = _pd_reg, \
1950 + .pd_shift = _pd_shift, \
1951 + .tuner_reg = _tuner_reg, \
1952 + .tuner_en_reg = _tuner_en_reg, \
1953 + .tuner_en_bit = _tuner_en_bit, \
1954 + .pcw_reg = _pcw_reg, \
1955 + .pcw_shift = _pcw_shift, \
1956 + .div_table = _div_table, \
1957 + }
1958 +
1959 +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
1960 + _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
1961 + _tuner_en_bit, _pcw_reg, _pcw_shift) \
1962 + PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
1963 + _pcwbits, _pd_reg, _pd_shift, _tuner_reg, \
1964 + _tuner_en_reg, _tuner_en_bit, _pcw_reg, \
1965 + _pcw_shift, NULL)
1966 +
1967 +static const struct mtk_pll_div_table armca35pll_div_table[] = {
1968 + { .div = 0, .freq = MT2712_PLL_FMAX },
1969 + { .div = 1, .freq = 1202500000 },
1970 + { .div = 2, .freq = 500500000 },
1971 + { .div = 3, .freq = 315250000 },
1972 + { .div = 4, .freq = 157625000 },
1973 + { } /* sentinel */
1974 +};
1975 +
1976 +static const struct mtk_pll_div_table armca72pll_div_table[] = {
1977 + { .div = 0, .freq = MT2712_PLL_FMAX },
1978 + { .div = 1, .freq = 994500000 },
1979 + { .div = 2, .freq = 520000000 },
1980 + { .div = 3, .freq = 315250000 },
1981 + { .div = 4, .freq = 157625000 },
1982 + { } /* sentinel */
1983 +};
1984 +
1985 +static const struct mtk_pll_div_table mmpll_div_table[] = {
1986 + { .div = 0, .freq = MT2712_PLL_FMAX },
1987 + { .div = 1, .freq = 1001000000 },
1988 + { .div = 2, .freq = 601250000 },
1989 + { .div = 3, .freq = 250250000 },
1990 + { .div = 4, .freq = 125125000 },
1991 + { } /* sentinel */
1992 +};
1993 +
1994 +static const struct mtk_pll_data plls[] = {
1995 + PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000101,
1996 + HAVE_RST_BAR, 31, 0x0230, 4, 0, 0, 0, 0x0234, 0),
1997 + PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000101,
1998 + HAVE_RST_BAR, 31, 0x0240, 4, 0, 0, 0, 0x0244, 0),
1999 + PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x0320, 0x032C, 0xc0000101,
2000 + 0, 31, 0x0320, 4, 0, 0, 0, 0x0324, 0),
2001 + PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000101,
2002 + 0, 31, 0x0280, 4, 0, 0, 0, 0x0284, 0),
2003 + PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000101,
2004 + 0, 31, 0x0330, 4, 0x0338, 0x0014, 0, 0x0334, 0),
2005 + PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000101,
2006 + 0, 31, 0x0350, 4, 0x0358, 0x0014, 1, 0x0354, 0),
2007 + PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0370, 0x037c, 0x00000101,
2008 + 0, 31, 0x0370, 4, 0, 0, 0, 0x0374, 0),
2009 + PLL(CLK_APMIXED_LVDSPLL2, "lvdspll2", 0x0390, 0x039C, 0x00000101,
2010 + 0, 31, 0x0390, 4, 0, 0, 0, 0x0394, 0),
2011 + PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000101,
2012 + 0, 31, 0x0270, 4, 0, 0, 0, 0x0274, 0),
2013 + PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x0410, 0x041C, 0x00000101,
2014 + 0, 31, 0x0410, 4, 0, 0, 0, 0x0414, 0),
2015 + PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0290, 0x029C, 0xc0000101,
2016 + 0, 31, 0x0290, 4, 0, 0, 0, 0x0294, 0),
2017 + PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0250, 0x0260, 0x00000101,
2018 + 0, 31, 0x0250, 4, 0, 0, 0, 0x0254, 0,
2019 + mmpll_div_table),
2020 + PLL_B(CLK_APMIXED_ARMCA35PLL, "armca35pll", 0x0100, 0x0110, 0xf0000101,
2021 + HAVE_RST_BAR, 31, 0x0100, 4, 0, 0, 0, 0x0104, 0,
2022 + armca35pll_div_table),
2023 + PLL_B(CLK_APMIXED_ARMCA72PLL, "armca72pll", 0x0210, 0x0220, 0x00000101,
2024 + 0, 31, 0x0210, 4, 0, 0, 0, 0x0214, 0,
2025 + armca72pll_div_table),
2026 + PLL(CLK_APMIXED_ETHERPLL, "etherpll", 0x0300, 0x030C, 0xc0000101,
2027 + 0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0),
2028 +};
2029 +
2030 +static int clk_mt2712_apmixed_probe(struct platform_device *pdev)
2031 +{
2032 + struct clk_onecell_data *clk_data;
2033 + int r;
2034 + struct device_node *node = pdev->dev.of_node;
2035 +
2036 + clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
2037 +
2038 + mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
2039 +
2040 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
2041 +
2042 + if (r != 0)
2043 + pr_err("%s(): could not register clock provider: %d\n",
2044 + __func__, r);
2045 +
2046 + return r;
2047 +}
2048 +
2049 +static struct clk_onecell_data *top_clk_data;
2050 +
2051 +static void clk_mt2712_top_init_early(struct device_node *node)
2052 +{
2053 + int r, i;
2054 +
2055 + if (!top_clk_data) {
2056 + top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
2057 +
2058 + for (i = 0; i < CLK_TOP_NR_CLK; i++)
2059 + top_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
2060 + }
2061 +
2062 + mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
2063 + top_clk_data);
2064 +
2065 + r = of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
2066 + if (r)
2067 + pr_err("%s(): could not register clock provider: %d\n",
2068 + __func__, r);
2069 +}
2070 +
2071 +CLK_OF_DECLARE_DRIVER(mt2712_topckgen, "mediatek,mt2712-topckgen",
2072 + clk_mt2712_top_init_early);
2073 +
2074 +static int clk_mt2712_top_probe(struct platform_device *pdev)
2075 +{
2076 + int r, i;
2077 + struct device_node *node = pdev->dev.of_node;
2078 + void __iomem *base;
2079 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2080 +
2081 + base = devm_ioremap_resource(&pdev->dev, res);
2082 + if (IS_ERR(base)) {
2083 + pr_err("%s(): ioremap failed\n", __func__);
2084 + return PTR_ERR(base);
2085 + }
2086 +
2087 + if (!top_clk_data) {
2088 + top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
2089 + } else {
2090 + for (i = 0; i < CLK_TOP_NR_CLK; i++) {
2091 + if (top_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER))
2092 + top_clk_data->clks[i] = ERR_PTR(-ENOENT);
2093 + }
2094 + }
2095 +
2096 + mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
2097 + top_clk_data);
2098 + mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
2099 + top_clk_data);
2100 + mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
2101 + mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
2102 + &mt2712_clk_lock, top_clk_data);
2103 + mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
2104 + &mt2712_clk_lock, top_clk_data);
2105 + mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
2106 + top_clk_data);
2107 +
2108 + r = of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
2109 +
2110 + if (r != 0)
2111 + pr_err("%s(): could not register clock provider: %d\n",
2112 + __func__, r);
2113 +
2114 + return r;
2115 +}
2116 +
2117 +static int clk_mt2712_infra_probe(struct platform_device *pdev)
2118 +{
2119 + struct clk_onecell_data *clk_data;
2120 + int r;
2121 + struct device_node *node = pdev->dev.of_node;
2122 +
2123 + clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
2124 +
2125 + mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
2126 + clk_data);
2127 +
2128 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
2129 +
2130 + if (r != 0)
2131 + pr_err("%s(): could not register clock provider: %d\n",
2132 + __func__, r);
2133 +
2134 + mtk_register_reset_controller(node, 2, 0x30);
2135 +
2136 + return r;
2137 +}
2138 +
2139 +static int clk_mt2712_peri_probe(struct platform_device *pdev)
2140 +{
2141 + struct clk_onecell_data *clk_data;
2142 + int r;
2143 + struct device_node *node = pdev->dev.of_node;
2144 +
2145 + clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
2146 +
2147 + mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
2148 + clk_data);
2149 +
2150 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
2151 +
2152 + if (r != 0)
2153 + pr_err("%s(): could not register clock provider: %d\n",
2154 + __func__, r);
2155 +
2156 + mtk_register_reset_controller(node, 2, 0);
2157 +
2158 + return r;
2159 +}
2160 +
2161 +static int clk_mt2712_mcu_probe(struct platform_device *pdev)
2162 +{
2163 + struct clk_onecell_data *clk_data;
2164 + int r;
2165 + struct device_node *node = pdev->dev.of_node;
2166 + void __iomem *base;
2167 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2168 +
2169 + base = devm_ioremap_resource(&pdev->dev, res);
2170 + if (IS_ERR(base)) {
2171 + pr_err("%s(): ioremap failed\n", __func__);
2172 + return PTR_ERR(base);
2173 + }
2174 +
2175 + clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK);
2176 +
2177 + mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
2178 + &mt2712_clk_lock, clk_data);
2179 +
2180 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
2181 +
2182 + if (r != 0)
2183 + pr_err("%s(): could not register clock provider: %d\n",
2184 + __func__, r);
2185 +
2186 + return r;
2187 +}
2188 +
2189 +static const struct of_device_id of_match_clk_mt2712[] = {
2190 + {
2191 + .compatible = "mediatek,mt2712-apmixedsys",
2192 + .data = clk_mt2712_apmixed_probe,
2193 + }, {
2194 + .compatible = "mediatek,mt2712-topckgen",
2195 + .data = clk_mt2712_top_probe,
2196 + }, {
2197 + .compatible = "mediatek,mt2712-infracfg",
2198 + .data = clk_mt2712_infra_probe,
2199 + }, {
2200 + .compatible = "mediatek,mt2712-pericfg",
2201 + .data = clk_mt2712_peri_probe,
2202 + }, {
2203 + .compatible = "mediatek,mt2712-mcucfg",
2204 + .data = clk_mt2712_mcu_probe,
2205 + }, {
2206 + /* sentinel */
2207 + }
2208 +};
2209 +
2210 +static int clk_mt2712_probe(struct platform_device *pdev)
2211 +{
2212 + int (*clk_probe)(struct platform_device *);
2213 + int r;
2214 +
2215 + clk_probe = of_device_get_match_data(&pdev->dev);
2216 + if (!clk_probe)
2217 + return -EINVAL;
2218 +
2219 + r = clk_probe(pdev);
2220 + if (r != 0)
2221 + dev_err(&pdev->dev,
2222 + "could not register clock provider: %s: %d\n",
2223 + pdev->name, r);
2224 +
2225 + return r;
2226 +}
2227 +
2228 +static struct platform_driver clk_mt2712_drv = {
2229 + .probe = clk_mt2712_probe,
2230 + .driver = {
2231 + .name = "clk-mt2712",
2232 + .owner = THIS_MODULE,
2233 + .of_match_table = of_match_clk_mt2712,
2234 + },
2235 +};
2236 +
2237 +static int __init clk_mt2712_init(void)
2238 +{
2239 + return platform_driver_register(&clk_mt2712_drv);
2240 +}
2241 +
2242 +arch_initcall(clk_mt2712_init);
2243 --- a/drivers/clk/mediatek/clk-mtk.h
2244 +++ b/drivers/clk/mediatek/clk-mtk.h
2245 @@ -207,6 +207,8 @@ struct mtk_pll_data {
2246 uint32_t en_mask;
2247 uint32_t pd_reg;
2248 uint32_t tuner_reg;
2249 + uint32_t tuner_en_reg;
2250 + uint8_t tuner_en_bit;
2251 int pd_shift;
2252 unsigned int flags;
2253 const struct clk_ops *ops;
2254 --- a/drivers/clk/mediatek/clk-pll.c
2255 +++ b/drivers/clk/mediatek/clk-pll.c
2256 @@ -47,6 +47,7 @@ struct mtk_clk_pll {
2257 void __iomem *pd_addr;
2258 void __iomem *pwr_addr;
2259 void __iomem *tuner_addr;
2260 + void __iomem *tuner_en_addr;
2261 void __iomem *pcw_addr;
2262 const struct mtk_pll_data *data;
2263 };
2264 @@ -227,7 +228,10 @@ static int mtk_pll_prepare(struct clk_hw
2265 r |= pll->data->en_mask;
2266 writel(r, pll->base_addr + REG_CON0);
2267  
2268 - if (pll->tuner_addr) {
2269 + if (pll->tuner_en_addr) {
2270 + r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);
2271 + writel(r, pll->tuner_en_addr);
2272 + } else if (pll->tuner_addr) {
2273 r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
2274 writel(r, pll->tuner_addr);
2275 }
2276 @@ -254,7 +258,10 @@ static void mtk_pll_unprepare(struct clk
2277 writel(r, pll->base_addr + REG_CON0);
2278 }
2279  
2280 - if (pll->tuner_addr) {
2281 + if (pll->tuner_en_addr) {
2282 + r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);
2283 + writel(r, pll->tuner_en_addr);
2284 + } else if (pll->tuner_addr) {
2285 r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
2286 writel(r, pll->tuner_addr);
2287 }
2288 @@ -297,6 +304,8 @@ static struct clk *mtk_clk_register_pll(
2289 pll->pcw_addr = base + data->pcw_reg;
2290 if (data->tuner_reg)
2291 pll->tuner_addr = base + data->tuner_reg;
2292 + if (data->tuner_en_reg)
2293 + pll->tuner_en_addr = base + data->tuner_en_reg;
2294 pll->hw.init = &init;
2295 pll->data = data;
2296