OpenWrt – Blame information for rev 1

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1 office 1 From cfa7e6ed5a6ba529097ae8a50ed2c8fa12b4cad0 Mon Sep 17 00:00:00 2001
2 From: Biwen Li <biwen.li@nxp.com>
3 Date: Tue, 30 Oct 2018 18:27:13 +0800
4 Subject: [PATCH 22/40] qe: support layerscape
5 This is an integrated patch of qe for layerscape
6  
7 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com
8 Signed-off-by: Biwen Li <biwen.li@nxp.com>
9 ---
10 .../fsl/qe/qe_ic.c => irqchip/irq-qeic.c} | 389 +++++++++++-------
11 drivers/soc/fsl/qe/Kconfig | 2 +-
12 drivers/soc/fsl/qe/Makefile | 2 +-
13 drivers/soc/fsl/qe/qe.c | 78 ++--
14 drivers/soc/fsl/qe/qe_ic.h | 103 -----
15 drivers/soc/fsl/qe/qe_io.c | 42 +-
16 drivers/soc/fsl/qe/qe_tdm.c | 8 +-
17 drivers/soc/fsl/qe/ucc.c | 10 +-
18 drivers/soc/fsl/qe/ucc_fast.c | 74 ++--
19 drivers/tty/serial/ucc_uart.c | 1 +
20 include/soc/fsl/qe/qe.h | 1 -
21 include/soc/fsl/qe/qe_ic.h | 139 -------
22 12 files changed, 357 insertions(+), 492 deletions(-)
23 rename drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} (54%)
24 delete mode 100644 drivers/soc/fsl/qe/qe_ic.h
25 delete mode 100644 include/soc/fsl/qe/qe_ic.h
26  
27 --- a/drivers/soc/fsl/qe/qe_ic.c
28 +++ /dev/null
29 @@ -1,512 +0,0 @@
30 -/*
31 - * arch/powerpc/sysdev/qe_lib/qe_ic.c
32 - *
33 - * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
34 - *
35 - * Author: Li Yang <leoli@freescale.com>
36 - * Based on code from Shlomi Gridish <gridish@freescale.com>
37 - *
38 - * QUICC ENGINE Interrupt Controller
39 - *
40 - * This program is free software; you can redistribute it and/or modify it
41 - * under the terms of the GNU General Public License as published by the
42 - * Free Software Foundation; either version 2 of the License, or (at your
43 - * option) any later version.
44 - */
45 -
46 -#include <linux/of_irq.h>
47 -#include <linux/of_address.h>
48 -#include <linux/kernel.h>
49 -#include <linux/init.h>
50 -#include <linux/errno.h>
51 -#include <linux/reboot.h>
52 -#include <linux/slab.h>
53 -#include <linux/stddef.h>
54 -#include <linux/sched.h>
55 -#include <linux/signal.h>
56 -#include <linux/device.h>
57 -#include <linux/spinlock.h>
58 -#include <asm/irq.h>
59 -#include <asm/io.h>
60 -#include <soc/fsl/qe/qe_ic.h>
61 -
62 -#include "qe_ic.h"
63 -
64 -static DEFINE_RAW_SPINLOCK(qe_ic_lock);
65 -
66 -static struct qe_ic_info qe_ic_info[] = {
67 - [1] = {
68 - .mask = 0x00008000,
69 - .mask_reg = QEIC_CIMR,
70 - .pri_code = 0,
71 - .pri_reg = QEIC_CIPWCC,
72 - },
73 - [2] = {
74 - .mask = 0x00004000,
75 - .mask_reg = QEIC_CIMR,
76 - .pri_code = 1,
77 - .pri_reg = QEIC_CIPWCC,
78 - },
79 - [3] = {
80 - .mask = 0x00002000,
81 - .mask_reg = QEIC_CIMR,
82 - .pri_code = 2,
83 - .pri_reg = QEIC_CIPWCC,
84 - },
85 - [10] = {
86 - .mask = 0x00000040,
87 - .mask_reg = QEIC_CIMR,
88 - .pri_code = 1,
89 - .pri_reg = QEIC_CIPZCC,
90 - },
91 - [11] = {
92 - .mask = 0x00000020,
93 - .mask_reg = QEIC_CIMR,
94 - .pri_code = 2,
95 - .pri_reg = QEIC_CIPZCC,
96 - },
97 - [12] = {
98 - .mask = 0x00000010,
99 - .mask_reg = QEIC_CIMR,
100 - .pri_code = 3,
101 - .pri_reg = QEIC_CIPZCC,
102 - },
103 - [13] = {
104 - .mask = 0x00000008,
105 - .mask_reg = QEIC_CIMR,
106 - .pri_code = 4,
107 - .pri_reg = QEIC_CIPZCC,
108 - },
109 - [14] = {
110 - .mask = 0x00000004,
111 - .mask_reg = QEIC_CIMR,
112 - .pri_code = 5,
113 - .pri_reg = QEIC_CIPZCC,
114 - },
115 - [15] = {
116 - .mask = 0x00000002,
117 - .mask_reg = QEIC_CIMR,
118 - .pri_code = 6,
119 - .pri_reg = QEIC_CIPZCC,
120 - },
121 - [20] = {
122 - .mask = 0x10000000,
123 - .mask_reg = QEIC_CRIMR,
124 - .pri_code = 3,
125 - .pri_reg = QEIC_CIPRTA,
126 - },
127 - [25] = {
128 - .mask = 0x00800000,
129 - .mask_reg = QEIC_CRIMR,
130 - .pri_code = 0,
131 - .pri_reg = QEIC_CIPRTB,
132 - },
133 - [26] = {
134 - .mask = 0x00400000,
135 - .mask_reg = QEIC_CRIMR,
136 - .pri_code = 1,
137 - .pri_reg = QEIC_CIPRTB,
138 - },
139 - [27] = {
140 - .mask = 0x00200000,
141 - .mask_reg = QEIC_CRIMR,
142 - .pri_code = 2,
143 - .pri_reg = QEIC_CIPRTB,
144 - },
145 - [28] = {
146 - .mask = 0x00100000,
147 - .mask_reg = QEIC_CRIMR,
148 - .pri_code = 3,
149 - .pri_reg = QEIC_CIPRTB,
150 - },
151 - [32] = {
152 - .mask = 0x80000000,
153 - .mask_reg = QEIC_CIMR,
154 - .pri_code = 0,
155 - .pri_reg = QEIC_CIPXCC,
156 - },
157 - [33] = {
158 - .mask = 0x40000000,
159 - .mask_reg = QEIC_CIMR,
160 - .pri_code = 1,
161 - .pri_reg = QEIC_CIPXCC,
162 - },
163 - [34] = {
164 - .mask = 0x20000000,
165 - .mask_reg = QEIC_CIMR,
166 - .pri_code = 2,
167 - .pri_reg = QEIC_CIPXCC,
168 - },
169 - [35] = {
170 - .mask = 0x10000000,
171 - .mask_reg = QEIC_CIMR,
172 - .pri_code = 3,
173 - .pri_reg = QEIC_CIPXCC,
174 - },
175 - [36] = {
176 - .mask = 0x08000000,
177 - .mask_reg = QEIC_CIMR,
178 - .pri_code = 4,
179 - .pri_reg = QEIC_CIPXCC,
180 - },
181 - [40] = {
182 - .mask = 0x00800000,
183 - .mask_reg = QEIC_CIMR,
184 - .pri_code = 0,
185 - .pri_reg = QEIC_CIPYCC,
186 - },
187 - [41] = {
188 - .mask = 0x00400000,
189 - .mask_reg = QEIC_CIMR,
190 - .pri_code = 1,
191 - .pri_reg = QEIC_CIPYCC,
192 - },
193 - [42] = {
194 - .mask = 0x00200000,
195 - .mask_reg = QEIC_CIMR,
196 - .pri_code = 2,
197 - .pri_reg = QEIC_CIPYCC,
198 - },
199 - [43] = {
200 - .mask = 0x00100000,
201 - .mask_reg = QEIC_CIMR,
202 - .pri_code = 3,
203 - .pri_reg = QEIC_CIPYCC,
204 - },
205 -};
206 -
207 -static inline u32 qe_ic_read(volatile __be32 __iomem * base, unsigned int reg)
208 -{
209 - return in_be32(base + (reg >> 2));
210 -}
211 -
212 -static inline void qe_ic_write(volatile __be32 __iomem * base, unsigned int reg,
213 - u32 value)
214 -{
215 - out_be32(base + (reg >> 2), value);
216 -}
217 -
218 -static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)
219 -{
220 - return irq_get_chip_data(virq);
221 -}
222 -
223 -static inline struct qe_ic *qe_ic_from_irq_data(struct irq_data *d)
224 -{
225 - return irq_data_get_irq_chip_data(d);
226 -}
227 -
228 -static void qe_ic_unmask_irq(struct irq_data *d)
229 -{
230 - struct qe_ic *qe_ic = qe_ic_from_irq_data(d);
231 - unsigned int src = irqd_to_hwirq(d);
232 - unsigned long flags;
233 - u32 temp;
234 -
235 - raw_spin_lock_irqsave(&qe_ic_lock, flags);
236 -
237 - temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);
238 - qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,
239 - temp | qe_ic_info[src].mask);
240 -
241 - raw_spin_unlock_irqrestore(&qe_ic_lock, flags);
242 -}
243 -
244 -static void qe_ic_mask_irq(struct irq_data *d)
245 -{
246 - struct qe_ic *qe_ic = qe_ic_from_irq_data(d);
247 - unsigned int src = irqd_to_hwirq(d);
248 - unsigned long flags;
249 - u32 temp;
250 -
251 - raw_spin_lock_irqsave(&qe_ic_lock, flags);
252 -
253 - temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);
254 - qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,
255 - temp & ~qe_ic_info[src].mask);
256 -
257 - /* Flush the above write before enabling interrupts; otherwise,
258 - * spurious interrupts will sometimes happen. To be 100% sure
259 - * that the write has reached the device before interrupts are
260 - * enabled, the mask register would have to be read back; however,
261 - * this is not required for correctness, only to avoid wasting
262 - * time on a large number of spurious interrupts. In testing,
263 - * a sync reduced the observed spurious interrupts to zero.
264 - */
265 - mb();
266 -
267 - raw_spin_unlock_irqrestore(&qe_ic_lock, flags);
268 -}
269 -
270 -static struct irq_chip qe_ic_irq_chip = {
271 - .name = "QEIC",
272 - .irq_unmask = qe_ic_unmask_irq,
273 - .irq_mask = qe_ic_mask_irq,
274 - .irq_mask_ack = qe_ic_mask_irq,
275 -};
276 -
277 -static int qe_ic_host_match(struct irq_domain *h, struct device_node *node,
278 - enum irq_domain_bus_token bus_token)
279 -{
280 - /* Exact match, unless qe_ic node is NULL */
281 - struct device_node *of_node = irq_domain_get_of_node(h);
282 - return of_node == NULL || of_node == node;
283 -}
284 -
285 -static int qe_ic_host_map(struct irq_domain *h, unsigned int virq,
286 - irq_hw_number_t hw)
287 -{
288 - struct qe_ic *qe_ic = h->host_data;
289 - struct irq_chip *chip;
290 -
291 - if (hw >= ARRAY_SIZE(qe_ic_info)) {
292 - pr_err("%s: Invalid hw irq number for QEIC\n", __func__);
293 - return -EINVAL;
294 - }
295 -
296 - if (qe_ic_info[hw].mask == 0) {
297 - printk(KERN_ERR "Can't map reserved IRQ\n");
298 - return -EINVAL;
299 - }
300 - /* Default chip */
301 - chip = &qe_ic->hc_irq;
302 -
303 - irq_set_chip_data(virq, qe_ic);
304 - irq_set_status_flags(virq, IRQ_LEVEL);
305 -
306 - irq_set_chip_and_handler(virq, chip, handle_level_irq);
307 -
308 - return 0;
309 -}
310 -
311 -static const struct irq_domain_ops qe_ic_host_ops = {
312 - .match = qe_ic_host_match,
313 - .map = qe_ic_host_map,
314 - .xlate = irq_domain_xlate_onetwocell,
315 -};
316 -
317 -/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
318 -unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
319 -{
320 - int irq;
321 -
322 - BUG_ON(qe_ic == NULL);
323 -
324 - /* get the interrupt source vector. */
325 - irq = qe_ic_read(qe_ic->regs, QEIC_CIVEC) >> 26;
326 -
327 - if (irq == 0)
328 - return NO_IRQ;
329 -
330 - return irq_linear_revmap(qe_ic->irqhost, irq);
331 -}
332 -
333 -/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
334 -unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
335 -{
336 - int irq;
337 -
338 - BUG_ON(qe_ic == NULL);
339 -
340 - /* get the interrupt source vector. */
341 - irq = qe_ic_read(qe_ic->regs, QEIC_CHIVEC) >> 26;
342 -
343 - if (irq == 0)
344 - return NO_IRQ;
345 -
346 - return irq_linear_revmap(qe_ic->irqhost, irq);
347 -}
348 -
349 -void __init qe_ic_init(struct device_node *node, unsigned int flags,
350 - void (*low_handler)(struct irq_desc *desc),
351 - void (*high_handler)(struct irq_desc *desc))
352 -{
353 - struct qe_ic *qe_ic;
354 - struct resource res;
355 - u32 temp = 0, ret, high_active = 0;
356 -
357 - ret = of_address_to_resource(node, 0, &res);
358 - if (ret)
359 - return;
360 -
361 - qe_ic = kzalloc(sizeof(*qe_ic), GFP_KERNEL);
362 - if (qe_ic == NULL)
363 - return;
364 -
365 - qe_ic->irqhost = irq_domain_add_linear(node, NR_QE_IC_INTS,
366 - &qe_ic_host_ops, qe_ic);
367 - if (qe_ic->irqhost == NULL) {
368 - kfree(qe_ic);
369 - return;
370 - }
371 -
372 - qe_ic->regs = ioremap(res.start, resource_size(&res));
373 -
374 - qe_ic->hc_irq = qe_ic_irq_chip;
375 -
376 - qe_ic->virq_high = irq_of_parse_and_map(node, 0);
377 - qe_ic->virq_low = irq_of_parse_and_map(node, 1);
378 -
379 - if (qe_ic->virq_low == NO_IRQ) {
380 - printk(KERN_ERR "Failed to map QE_IC low IRQ\n");
381 - kfree(qe_ic);
382 - return;
383 - }
384 -
385 - /* default priority scheme is grouped. If spread mode is */
386 - /* required, configure cicr accordingly. */
387 - if (flags & QE_IC_SPREADMODE_GRP_W)
388 - temp |= CICR_GWCC;
389 - if (flags & QE_IC_SPREADMODE_GRP_X)
390 - temp |= CICR_GXCC;
391 - if (flags & QE_IC_SPREADMODE_GRP_Y)
392 - temp |= CICR_GYCC;
393 - if (flags & QE_IC_SPREADMODE_GRP_Z)
394 - temp |= CICR_GZCC;
395 - if (flags & QE_IC_SPREADMODE_GRP_RISCA)
396 - temp |= CICR_GRTA;
397 - if (flags & QE_IC_SPREADMODE_GRP_RISCB)
398 - temp |= CICR_GRTB;
399 -
400 - /* choose destination signal for highest priority interrupt */
401 - if (flags & QE_IC_HIGH_SIGNAL) {
402 - temp |= (SIGNAL_HIGH << CICR_HPIT_SHIFT);
403 - high_active = 1;
404 - }
405 -
406 - qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
407 -
408 - irq_set_handler_data(qe_ic->virq_low, qe_ic);
409 - irq_set_chained_handler(qe_ic->virq_low, low_handler);
410 -
411 - if (qe_ic->virq_high != NO_IRQ &&
412 - qe_ic->virq_high != qe_ic->virq_low) {
413 - irq_set_handler_data(qe_ic->virq_high, qe_ic);
414 - irq_set_chained_handler(qe_ic->virq_high, high_handler);
415 - }
416 -}
417 -
418 -void qe_ic_set_highest_priority(unsigned int virq, int high)
419 -{
420 - struct qe_ic *qe_ic = qe_ic_from_irq(virq);
421 - unsigned int src = virq_to_hw(virq);
422 - u32 temp = 0;
423 -
424 - temp = qe_ic_read(qe_ic->regs, QEIC_CICR);
425 -
426 - temp &= ~CICR_HP_MASK;
427 - temp |= src << CICR_HP_SHIFT;
428 -
429 - temp &= ~CICR_HPIT_MASK;
430 - temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << CICR_HPIT_SHIFT;
431 -
432 - qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
433 -}
434 -
435 -/* Set Priority level within its group, from 1 to 8 */
436 -int qe_ic_set_priority(unsigned int virq, unsigned int priority)
437 -{
438 - struct qe_ic *qe_ic = qe_ic_from_irq(virq);
439 - unsigned int src = virq_to_hw(virq);
440 - u32 temp;
441 -
442 - if (priority > 8 || priority == 0)
443 - return -EINVAL;
444 - if (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info),
445 - "%s: Invalid hw irq number for QEIC\n", __func__))
446 - return -EINVAL;
447 - if (qe_ic_info[src].pri_reg == 0)
448 - return -EINVAL;
449 -
450 - temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].pri_reg);
451 -
452 - if (priority < 4) {
453 - temp &= ~(0x7 << (32 - priority * 3));
454 - temp |= qe_ic_info[src].pri_code << (32 - priority * 3);
455 - } else {
456 - temp &= ~(0x7 << (24 - priority * 3));
457 - temp |= qe_ic_info[src].pri_code << (24 - priority * 3);
458 - }
459 -
460 - qe_ic_write(qe_ic->regs, qe_ic_info[src].pri_reg, temp);
461 -
462 - return 0;
463 -}
464 -
465 -/* Set a QE priority to use high irq, only priority 1~2 can use high irq */
466 -int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high)
467 -{
468 - struct qe_ic *qe_ic = qe_ic_from_irq(virq);
469 - unsigned int src = virq_to_hw(virq);
470 - u32 temp, control_reg = QEIC_CICNR, shift = 0;
471 -
472 - if (priority > 2 || priority == 0)
473 - return -EINVAL;
474 - if (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info),
475 - "%s: Invalid hw irq number for QEIC\n", __func__))
476 - return -EINVAL;
477 -
478 - switch (qe_ic_info[src].pri_reg) {
479 - case QEIC_CIPZCC:
480 - shift = CICNR_ZCC1T_SHIFT;
481 - break;
482 - case QEIC_CIPWCC:
483 - shift = CICNR_WCC1T_SHIFT;
484 - break;
485 - case QEIC_CIPYCC:
486 - shift = CICNR_YCC1T_SHIFT;
487 - break;
488 - case QEIC_CIPXCC:
489 - shift = CICNR_XCC1T_SHIFT;
490 - break;
491 - case QEIC_CIPRTA:
492 - shift = CRICR_RTA1T_SHIFT;
493 - control_reg = QEIC_CRICR;
494 - break;
495 - case QEIC_CIPRTB:
496 - shift = CRICR_RTB1T_SHIFT;
497 - control_reg = QEIC_CRICR;
498 - break;
499 - default:
500 - return -EINVAL;
501 - }
502 -
503 - shift += (2 - priority) * 2;
504 - temp = qe_ic_read(qe_ic->regs, control_reg);
505 - temp &= ~(SIGNAL_MASK << shift);
506 - temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << shift;
507 - qe_ic_write(qe_ic->regs, control_reg, temp);
508 -
509 - return 0;
510 -}
511 -
512 -static struct bus_type qe_ic_subsys = {
513 - .name = "qe_ic",
514 - .dev_name = "qe_ic",
515 -};
516 -
517 -static struct device device_qe_ic = {
518 - .id = 0,
519 - .bus = &qe_ic_subsys,
520 -};
521 -
522 -static int __init init_qe_ic_sysfs(void)
523 -{
524 - int rc;
525 -
526 - printk(KERN_DEBUG "Registering qe_ic with sysfs...\n");
527 -
528 - rc = subsys_system_register(&qe_ic_subsys, NULL);
529 - if (rc) {
530 - printk(KERN_ERR "Failed registering qe_ic sys class\n");
531 - return -ENODEV;
532 - }
533 - rc = device_register(&device_qe_ic);
534 - if (rc) {
535 - printk(KERN_ERR "Failed registering qe_ic sys device\n");
536 - return -ENODEV;
537 - }
538 - return 0;
539 -}
540 -
541 -subsys_initcall(init_qe_ic_sysfs);
542 --- /dev/null
543 +++ b/drivers/irqchip/irq-qeic.c
544 @@ -0,0 +1,605 @@
545 +/*
546 + * drivers/irqchip/irq-qeic.c
547 + *
548 + * Copyright (C) 2016 Freescale Semiconductor, Inc. All rights reserved.
549 + *
550 + * Author: Li Yang <leoli@freescale.com>
551 + * Based on code from Shlomi Gridish <gridish@freescale.com>
552 + *
553 + * QUICC ENGINE Interrupt Controller
554 + *
555 + * This program is free software; you can redistribute it and/or modify it
556 + * under the terms of the GNU General Public License as published by the
557 + * Free Software Foundation; either version 2 of the License, or (at your
558 + * option) any later version.
559 + */
560 +
561 +#include <linux/of_irq.h>
562 +#include <linux/of_address.h>
563 +#include <linux/kernel.h>
564 +#include <linux/init.h>
565 +#include <linux/irqdomain.h>
566 +#include <linux/irqchip.h>
567 +#include <linux/errno.h>
568 +#include <linux/of_address.h>
569 +#include <linux/of_irq.h>
570 +#include <linux/reboot.h>
571 +#include <linux/slab.h>
572 +#include <linux/stddef.h>
573 +#include <linux/sched.h>
574 +#include <linux/signal.h>
575 +#include <linux/device.h>
576 +#include <linux/spinlock.h>
577 +#include <linux/irq.h>
578 +#include <asm/io.h>
579 +
580 +#define NR_QE_IC_INTS 64
581 +
582 +/* QE IC registers offset */
583 +#define QEIC_CICR 0x00
584 +#define QEIC_CIVEC 0x04
585 +#define QEIC_CRIPNR 0x08
586 +#define QEIC_CIPNR 0x0c
587 +#define QEIC_CIPXCC 0x10
588 +#define QEIC_CIPYCC 0x14
589 +#define QEIC_CIPWCC 0x18
590 +#define QEIC_CIPZCC 0x1c
591 +#define QEIC_CIMR 0x20
592 +#define QEIC_CRIMR 0x24
593 +#define QEIC_CICNR 0x28
594 +#define QEIC_CIPRTA 0x30
595 +#define QEIC_CIPRTB 0x34
596 +#define QEIC_CRICR 0x3c
597 +#define QEIC_CHIVEC 0x60
598 +
599 +/* Interrupt priority registers */
600 +#define CIPCC_SHIFT_PRI0 29
601 +#define CIPCC_SHIFT_PRI1 26
602 +#define CIPCC_SHIFT_PRI2 23
603 +#define CIPCC_SHIFT_PRI3 20
604 +#define CIPCC_SHIFT_PRI4 13
605 +#define CIPCC_SHIFT_PRI5 10
606 +#define CIPCC_SHIFT_PRI6 7
607 +#define CIPCC_SHIFT_PRI7 4
608 +
609 +/* CICR priority modes */
610 +#define CICR_GWCC 0x00040000
611 +#define CICR_GXCC 0x00020000
612 +#define CICR_GYCC 0x00010000
613 +#define CICR_GZCC 0x00080000
614 +#define CICR_GRTA 0x00200000
615 +#define CICR_GRTB 0x00400000
616 +#define CICR_HPIT_SHIFT 8
617 +#define CICR_HPIT_MASK 0x00000300
618 +#define CICR_HP_SHIFT 24
619 +#define CICR_HP_MASK 0x3f000000
620 +
621 +/* CICNR */
622 +#define CICNR_WCC1T_SHIFT 20
623 +#define CICNR_ZCC1T_SHIFT 28
624 +#define CICNR_YCC1T_SHIFT 12
625 +#define CICNR_XCC1T_SHIFT 4
626 +
627 +/* CRICR */
628 +#define CRICR_RTA1T_SHIFT 20
629 +#define CRICR_RTB1T_SHIFT 28
630 +
631 +/* Signal indicator */
632 +#define SIGNAL_MASK 3
633 +#define SIGNAL_HIGH 2
634 +#define SIGNAL_LOW 0
635 +
636 +#define NUM_OF_QE_IC_GROUPS 6
637 +
638 +/* Flags when we init the QE IC */
639 +#define QE_IC_SPREADMODE_GRP_W 0x00000001
640 +#define QE_IC_SPREADMODE_GRP_X 0x00000002
641 +#define QE_IC_SPREADMODE_GRP_Y 0x00000004
642 +#define QE_IC_SPREADMODE_GRP_Z 0x00000008
643 +#define QE_IC_SPREADMODE_GRP_RISCA 0x00000010
644 +#define QE_IC_SPREADMODE_GRP_RISCB 0x00000020
645 +
646 +#define QE_IC_LOW_SIGNAL 0x00000100
647 +#define QE_IC_HIGH_SIGNAL 0x00000200
648 +
649 +#define QE_IC_GRP_W_PRI0_DEST_SIGNAL_HIGH 0x00001000
650 +#define QE_IC_GRP_W_PRI1_DEST_SIGNAL_HIGH 0x00002000
651 +#define QE_IC_GRP_X_PRI0_DEST_SIGNAL_HIGH 0x00004000
652 +#define QE_IC_GRP_X_PRI1_DEST_SIGNAL_HIGH 0x00008000
653 +#define QE_IC_GRP_Y_PRI0_DEST_SIGNAL_HIGH 0x00010000
654 +#define QE_IC_GRP_Y_PRI1_DEST_SIGNAL_HIGH 0x00020000
655 +#define QE_IC_GRP_Z_PRI0_DEST_SIGNAL_HIGH 0x00040000
656 +#define QE_IC_GRP_Z_PRI1_DEST_SIGNAL_HIGH 0x00080000
657 +#define QE_IC_GRP_RISCA_PRI0_DEST_SIGNAL_HIGH 0x00100000
658 +#define QE_IC_GRP_RISCA_PRI1_DEST_SIGNAL_HIGH 0x00200000
659 +#define QE_IC_GRP_RISCB_PRI0_DEST_SIGNAL_HIGH 0x00400000
660 +#define QE_IC_GRP_RISCB_PRI1_DEST_SIGNAL_HIGH 0x00800000
661 +#define QE_IC_GRP_W_DEST_SIGNAL_SHIFT (12)
662 +
663 +/* QE interrupt sources groups */
664 +enum qe_ic_grp_id {
665 + QE_IC_GRP_W = 0, /* QE interrupt controller group W */
666 + QE_IC_GRP_X, /* QE interrupt controller group X */
667 + QE_IC_GRP_Y, /* QE interrupt controller group Y */
668 + QE_IC_GRP_Z, /* QE interrupt controller group Z */
669 + QE_IC_GRP_RISCA, /* QE interrupt controller RISC group A */
670 + QE_IC_GRP_RISCB /* QE interrupt controller RISC group B */
671 +};
672 +
673 +struct qe_ic {
674 + /* Control registers offset */
675 + u32 __iomem *regs;
676 +
677 + /* The remapper for this QEIC */
678 + struct irq_domain *irqhost;
679 +
680 + /* The "linux" controller struct */
681 + struct irq_chip hc_irq;
682 +
683 + /* VIRQ numbers of QE high/low irqs */
684 + unsigned int virq_high;
685 + unsigned int virq_low;
686 +};
687 +
688 +/*
689 + * QE interrupt controller internal structure
690 + */
691 +struct qe_ic_info {
692 + /* location of this source at the QIMR register. */
693 + u32 mask;
694 +
695 + /* Mask register offset */
696 + u32 mask_reg;
697 +
698 + /*
699 + * for grouped interrupts sources - the interrupt
700 + * code as appears at the group priority register
701 + */
702 + u8 pri_code;
703 +
704 + /* Group priority register offset */
705 + u32 pri_reg;
706 +};
707 +
708 +static DEFINE_RAW_SPINLOCK(qe_ic_lock);
709 +
710 +static struct qe_ic_info qe_ic_info[] = {
711 + [1] = {
712 + .mask = 0x00008000,
713 + .mask_reg = QEIC_CIMR,
714 + .pri_code = 0,
715 + .pri_reg = QEIC_CIPWCC,
716 + },
717 + [2] = {
718 + .mask = 0x00004000,
719 + .mask_reg = QEIC_CIMR,
720 + .pri_code = 1,
721 + .pri_reg = QEIC_CIPWCC,
722 + },
723 + [3] = {
724 + .mask = 0x00002000,
725 + .mask_reg = QEIC_CIMR,
726 + .pri_code = 2,
727 + .pri_reg = QEIC_CIPWCC,
728 + },
729 + [10] = {
730 + .mask = 0x00000040,
731 + .mask_reg = QEIC_CIMR,
732 + .pri_code = 1,
733 + .pri_reg = QEIC_CIPZCC,
734 + },
735 + [11] = {
736 + .mask = 0x00000020,
737 + .mask_reg = QEIC_CIMR,
738 + .pri_code = 2,
739 + .pri_reg = QEIC_CIPZCC,
740 + },
741 + [12] = {
742 + .mask = 0x00000010,
743 + .mask_reg = QEIC_CIMR,
744 + .pri_code = 3,
745 + .pri_reg = QEIC_CIPZCC,
746 + },
747 + [13] = {
748 + .mask = 0x00000008,
749 + .mask_reg = QEIC_CIMR,
750 + .pri_code = 4,
751 + .pri_reg = QEIC_CIPZCC,
752 + },
753 + [14] = {
754 + .mask = 0x00000004,
755 + .mask_reg = QEIC_CIMR,
756 + .pri_code = 5,
757 + .pri_reg = QEIC_CIPZCC,
758 + },
759 + [15] = {
760 + .mask = 0x00000002,
761 + .mask_reg = QEIC_CIMR,
762 + .pri_code = 6,
763 + .pri_reg = QEIC_CIPZCC,
764 + },
765 + [20] = {
766 + .mask = 0x10000000,
767 + .mask_reg = QEIC_CRIMR,
768 + .pri_code = 3,
769 + .pri_reg = QEIC_CIPRTA,
770 + },
771 + [25] = {
772 + .mask = 0x00800000,
773 + .mask_reg = QEIC_CRIMR,
774 + .pri_code = 0,
775 + .pri_reg = QEIC_CIPRTB,
776 + },
777 + [26] = {
778 + .mask = 0x00400000,
779 + .mask_reg = QEIC_CRIMR,
780 + .pri_code = 1,
781 + .pri_reg = QEIC_CIPRTB,
782 + },
783 + [27] = {
784 + .mask = 0x00200000,
785 + .mask_reg = QEIC_CRIMR,
786 + .pri_code = 2,
787 + .pri_reg = QEIC_CIPRTB,
788 + },
789 + [28] = {
790 + .mask = 0x00100000,
791 + .mask_reg = QEIC_CRIMR,
792 + .pri_code = 3,
793 + .pri_reg = QEIC_CIPRTB,
794 + },
795 + [32] = {
796 + .mask = 0x80000000,
797 + .mask_reg = QEIC_CIMR,
798 + .pri_code = 0,
799 + .pri_reg = QEIC_CIPXCC,
800 + },
801 + [33] = {
802 + .mask = 0x40000000,
803 + .mask_reg = QEIC_CIMR,
804 + .pri_code = 1,
805 + .pri_reg = QEIC_CIPXCC,
806 + },
807 + [34] = {
808 + .mask = 0x20000000,
809 + .mask_reg = QEIC_CIMR,
810 + .pri_code = 2,
811 + .pri_reg = QEIC_CIPXCC,
812 + },
813 + [35] = {
814 + .mask = 0x10000000,
815 + .mask_reg = QEIC_CIMR,
816 + .pri_code = 3,
817 + .pri_reg = QEIC_CIPXCC,
818 + },
819 + [36] = {
820 + .mask = 0x08000000,
821 + .mask_reg = QEIC_CIMR,
822 + .pri_code = 4,
823 + .pri_reg = QEIC_CIPXCC,
824 + },
825 + [40] = {
826 + .mask = 0x00800000,
827 + .mask_reg = QEIC_CIMR,
828 + .pri_code = 0,
829 + .pri_reg = QEIC_CIPYCC,
830 + },
831 + [41] = {
832 + .mask = 0x00400000,
833 + .mask_reg = QEIC_CIMR,
834 + .pri_code = 1,
835 + .pri_reg = QEIC_CIPYCC,
836 + },
837 + [42] = {
838 + .mask = 0x00200000,
839 + .mask_reg = QEIC_CIMR,
840 + .pri_code = 2,
841 + .pri_reg = QEIC_CIPYCC,
842 + },
843 + [43] = {
844 + .mask = 0x00100000,
845 + .mask_reg = QEIC_CIMR,
846 + .pri_code = 3,
847 + .pri_reg = QEIC_CIPYCC,
848 + },
849 +};
850 +
851 +static inline u32 qe_ic_read(__be32 __iomem *base, unsigned int reg)
852 +{
853 + return ioread32be(base + (reg >> 2));
854 +}
855 +
856 +static inline void qe_ic_write(__be32 __iomem *base, unsigned int reg,
857 + u32 value)
858 +{
859 + iowrite32be(value, base + (reg >> 2));
860 +}
861 +
862 +static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)
863 +{
864 + return irq_get_chip_data(virq);
865 +}
866 +
867 +static inline struct qe_ic *qe_ic_from_irq_data(struct irq_data *d)
868 +{
869 + return irq_data_get_irq_chip_data(d);
870 +}
871 +
872 +static void qe_ic_unmask_irq(struct irq_data *d)
873 +{
874 + struct qe_ic *qe_ic = qe_ic_from_irq_data(d);
875 + unsigned int src = irqd_to_hwirq(d);
876 + unsigned long flags;
877 + u32 temp;
878 +
879 + raw_spin_lock_irqsave(&qe_ic_lock, flags);
880 +
881 + temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);
882 + qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,
883 + temp | qe_ic_info[src].mask);
884 +
885 + raw_spin_unlock_irqrestore(&qe_ic_lock, flags);
886 +}
887 +
888 +static void qe_ic_mask_irq(struct irq_data *d)
889 +{
890 + struct qe_ic *qe_ic = qe_ic_from_irq_data(d);
891 + unsigned int src = irqd_to_hwirq(d);
892 + unsigned long flags;
893 + u32 temp;
894 +
895 + raw_spin_lock_irqsave(&qe_ic_lock, flags);
896 +
897 + temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].mask_reg);
898 + qe_ic_write(qe_ic->regs, qe_ic_info[src].mask_reg,
899 + temp & ~qe_ic_info[src].mask);
900 +
901 + /* Flush the above write before enabling interrupts; otherwise,
902 + * spurious interrupts will sometimes happen. To be 100% sure
903 + * that the write has reached the device before interrupts are
904 + * enabled, the mask register would have to be read back; however,
905 + * this is not required for correctness, only to avoid wasting
906 + * time on a large number of spurious interrupts. In testing,
907 + * a sync reduced the observed spurious interrupts to zero.
908 + */
909 + mb();
910 +
911 + raw_spin_unlock_irqrestore(&qe_ic_lock, flags);
912 +}
913 +
914 +static struct irq_chip qe_ic_irq_chip = {
915 + .name = "QEIC",
916 + .irq_unmask = qe_ic_unmask_irq,
917 + .irq_mask = qe_ic_mask_irq,
918 + .irq_mask_ack = qe_ic_mask_irq,
919 +};
920 +
921 +static int qe_ic_host_match(struct irq_domain *h, struct device_node *node,
922 + enum irq_domain_bus_token bus_token)
923 +{
924 + /* Exact match, unless qe_ic node is NULL */
925 + struct device_node *of_node = irq_domain_get_of_node(h);
926 + return of_node == NULL || of_node == node;
927 +}
928 +
929 +static int qe_ic_host_map(struct irq_domain *h, unsigned int virq,
930 + irq_hw_number_t hw)
931 +{
932 + struct qe_ic *qe_ic = h->host_data;
933 + struct irq_chip *chip;
934 +
935 + if (hw >= ARRAY_SIZE(qe_ic_info)) {
936 + pr_err("%s: Invalid hw irq number for QEIC\n", __func__);
937 + return -EINVAL;
938 + }
939 +
940 + if (qe_ic_info[hw].mask == 0) {
941 + printk(KERN_ERR "Can't map reserved IRQ\n");
942 + return -EINVAL;
943 + }
944 + /* Default chip */
945 + chip = &qe_ic->hc_irq;
946 +
947 + irq_set_chip_data(virq, qe_ic);
948 + irq_set_status_flags(virq, IRQ_LEVEL);
949 +
950 + irq_set_chip_and_handler(virq, chip, handle_level_irq);
951 +
952 + return 0;
953 +}
954 +
955 +static const struct irq_domain_ops qe_ic_host_ops = {
956 + .match = qe_ic_host_match,
957 + .map = qe_ic_host_map,
958 + .xlate = irq_domain_xlate_onetwocell,
959 +};
960 +
961 +/* Return an interrupt vector or 0 if no interrupt is pending. */
962 +static unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
963 +{
964 + int irq;
965 +
966 + BUG_ON(qe_ic == NULL);
967 +
968 + /* get the interrupt source vector. */
969 + irq = qe_ic_read(qe_ic->regs, QEIC_CIVEC) >> 26;
970 +
971 + if (irq == 0)
972 + return 0;
973 +
974 + return irq_linear_revmap(qe_ic->irqhost, irq);
975 +}
976 +
977 +/* Return an interrupt vector or 0 if no interrupt is pending. */
978 +static unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
979 +{
980 + int irq;
981 +
982 + BUG_ON(qe_ic == NULL);
983 +
984 + /* get the interrupt source vector. */
985 + irq = qe_ic_read(qe_ic->regs, QEIC_CHIVEC) >> 26;
986 +
987 + if (irq == 0)
988 + return 0;
989 +
990 + return irq_linear_revmap(qe_ic->irqhost, irq);
991 +}
992 +
993 +static inline void qe_ic_cascade_low_ipic(struct irq_desc *desc)
994 +{
995 + struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
996 + unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
997 +
998 + if (cascade_irq != 0)
999 + generic_handle_irq(cascade_irq);
1000 +}
1001 +
1002 +static inline void qe_ic_cascade_high_ipic(struct irq_desc *desc)
1003 +{
1004 + struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
1005 + unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
1006 +
1007 + if (cascade_irq != 0)
1008 + generic_handle_irq(cascade_irq);
1009 +}
1010 +
1011 +static inline void qe_ic_cascade_low_mpic(struct irq_desc *desc)
1012 +{
1013 + struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
1014 + unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
1015 + struct irq_chip *chip = irq_desc_get_chip(desc);
1016 +
1017 + if (cascade_irq != 0)
1018 + generic_handle_irq(cascade_irq);
1019 +
1020 + chip->irq_eoi(&desc->irq_data);
1021 +}
1022 +
1023 +static inline void qe_ic_cascade_high_mpic(struct irq_desc *desc)
1024 +{
1025 + struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
1026 + unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
1027 + struct irq_chip *chip = irq_desc_get_chip(desc);
1028 +
1029 + if (cascade_irq != 0)
1030 + generic_handle_irq(cascade_irq);
1031 +
1032 + chip->irq_eoi(&desc->irq_data);
1033 +}
1034 +
1035 +static inline void qe_ic_cascade_muxed_mpic(struct irq_desc *desc)
1036 +{
1037 + struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
1038 + unsigned int cascade_irq;
1039 + struct irq_chip *chip = irq_desc_get_chip(desc);
1040 +
1041 + cascade_irq = qe_ic_get_high_irq(qe_ic);
1042 + if (cascade_irq == 0)
1043 + cascade_irq = qe_ic_get_low_irq(qe_ic);
1044 +
1045 + if (cascade_irq != 0)
1046 + generic_handle_irq(cascade_irq);
1047 +
1048 + chip->irq_eoi(&desc->irq_data);
1049 +}
1050 +
1051 +static int __init qe_ic_init(struct device_node *node, unsigned int flags)
1052 +{
1053 + struct qe_ic *qe_ic;
1054 + struct resource res;
1055 + u32 temp = 0, high_active = 0;
1056 + int ret = 0;
1057 +
1058 + if (!node)
1059 + return -ENODEV;
1060 +
1061 + ret = of_address_to_resource(node, 0, &res);
1062 + if (ret) {
1063 + ret = -ENODEV;
1064 + goto err_put_node;
1065 + }
1066 +
1067 + qe_ic = kzalloc(sizeof(*qe_ic), GFP_KERNEL);
1068 + if (qe_ic == NULL) {
1069 + ret = -ENOMEM;
1070 + goto err_put_node;
1071 + }
1072 +
1073 + qe_ic->irqhost = irq_domain_add_linear(node, NR_QE_IC_INTS,
1074 + &qe_ic_host_ops, qe_ic);
1075 + if (qe_ic->irqhost == NULL) {
1076 + ret = -ENOMEM;
1077 + goto err_free_qe_ic;
1078 + }
1079 +
1080 + qe_ic->regs = ioremap(res.start, resource_size(&res));
1081 +
1082 + qe_ic->hc_irq = qe_ic_irq_chip;
1083 +
1084 + qe_ic->virq_high = irq_of_parse_and_map(node, 0);
1085 + qe_ic->virq_low = irq_of_parse_and_map(node, 1);
1086 +
1087 + if (qe_ic->virq_low == 0) {
1088 + pr_err("Failed to map QE_IC low IRQ\n");
1089 + ret = -ENOMEM;
1090 + goto err_domain_remove;
1091 + }
1092 +
1093 + /* default priority scheme is grouped. If spread mode is */
1094 + /* required, configure cicr accordingly. */
1095 + if (flags & QE_IC_SPREADMODE_GRP_W)
1096 + temp |= CICR_GWCC;
1097 + if (flags & QE_IC_SPREADMODE_GRP_X)
1098 + temp |= CICR_GXCC;
1099 + if (flags & QE_IC_SPREADMODE_GRP_Y)
1100 + temp |= CICR_GYCC;
1101 + if (flags & QE_IC_SPREADMODE_GRP_Z)
1102 + temp |= CICR_GZCC;
1103 + if (flags & QE_IC_SPREADMODE_GRP_RISCA)
1104 + temp |= CICR_GRTA;
1105 + if (flags & QE_IC_SPREADMODE_GRP_RISCB)
1106 + temp |= CICR_GRTB;
1107 +
1108 + /* choose destination signal for highest priority interrupt */
1109 + if (flags & QE_IC_HIGH_SIGNAL) {
1110 + temp |= (SIGNAL_HIGH << CICR_HPIT_SHIFT);
1111 + high_active = 1;
1112 + }
1113 +
1114 + qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
1115 +
1116 + irq_set_handler_data(qe_ic->virq_low, qe_ic);
1117 + irq_set_chained_handler(qe_ic->virq_low, qe_ic_cascade_low_mpic);
1118 +
1119 + if (qe_ic->virq_high != 0 &&
1120 + qe_ic->virq_high != qe_ic->virq_low) {
1121 + irq_set_handler_data(qe_ic->virq_high, qe_ic);
1122 + irq_set_chained_handler(qe_ic->virq_high,
1123 + qe_ic_cascade_high_mpic);
1124 + }
1125 + of_node_put(node);
1126 + return 0;
1127 +
1128 +err_domain_remove:
1129 + irq_domain_remove(qe_ic->irqhost);
1130 +err_free_qe_ic:
1131 + kfree(qe_ic);
1132 +err_put_node:
1133 + of_node_put(node);
1134 + return ret;
1135 +}
1136 +
1137 +static int __init init_qe_ic(struct device_node *node,
1138 + struct device_node *parent)
1139 +{
1140 + int ret;
1141 +
1142 + ret = qe_ic_init(node, 0);
1143 + if (ret)
1144 + return ret;
1145 +
1146 + return 0;
1147 +}
1148 +
1149 +IRQCHIP_DECLARE(qeic, "fsl,qe-ic", init_qe_ic);
1150 --- a/drivers/soc/fsl/qe/Kconfig
1151 +++ b/drivers/soc/fsl/qe/Kconfig
1152 @@ -4,7 +4,7 @@
1153  
1154 config QUICC_ENGINE
1155 bool "Freescale QUICC Engine (QE) Support"
1156 - depends on FSL_SOC && PPC32
1157 + depends on OF && HAS_IOMEM
1158 select GENERIC_ALLOCATOR
1159 select CRC32
1160 help
1161 --- a/drivers/soc/fsl/qe/Makefile
1162 +++ b/drivers/soc/fsl/qe/Makefile
1163 @@ -2,7 +2,7 @@
1164 #
1165 # Makefile for the linux ppc-specific parts of QE
1166 #
1167 -obj-$(CONFIG_QUICC_ENGINE)+= qe.o qe_common.o qe_ic.o qe_io.o
1168 +obj-$(CONFIG_QUICC_ENGINE)+= qe.o qe_common.o qe_io.o
1169 obj-$(CONFIG_CPM) += qe_common.o
1170 obj-$(CONFIG_UCC) += ucc.o
1171 obj-$(CONFIG_UCC_SLOW) += ucc_slow.o
1172 --- a/drivers/soc/fsl/qe/qe.c
1173 +++ b/drivers/soc/fsl/qe/qe.c
1174 @@ -33,8 +33,6 @@
1175 #include <asm/pgtable.h>
1176 #include <soc/fsl/qe/immap_qe.h>
1177 #include <soc/fsl/qe/qe.h>
1178 -#include <asm/prom.h>
1179 -#include <asm/rheap.h>
1180  
1181 static void qe_snums_init(void);
1182 static int qe_sdma_init(void);
1183 @@ -107,15 +105,27 @@ void qe_reset(void)
1184 panic("sdma init failed!");
1185 }
1186  
1187 +/* issue commands to QE, return 0 on success while -EIO on error
1188 + *
1189 + * @cmd: the command code, should be QE_INIT_TX_RX, QE_STOP_TX and so on
1190 + * @device: which sub-block will run the command, QE_CR_SUBBLOCK_UCCFAST1 - 8
1191 + * , QE_CR_SUBBLOCK_UCCSLOW1 - 8, QE_CR_SUBBLOCK_MCC1 - 3,
1192 + * QE_CR_SUBBLOCK_IDMA1 - 4 and such on.
1193 + * @mcn_protocol: specifies mode for the command for non-MCC, should be
1194 + * QE_CR_PROTOCOL_HDLC_TRANSPARENT, QE_CR_PROTOCOL_QMC, QE_CR_PROTOCOL_UART
1195 + * and such on.
1196 + * @cmd_input: command related data.
1197 + */
1198 int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
1199 {
1200 unsigned long flags;
1201 u8 mcn_shift = 0, dev_shift = 0;
1202 - u32 ret;
1203 + int ret;
1204 + int i;
1205  
1206 spin_lock_irqsave(&qe_lock, flags);
1207 if (cmd == QE_RESET) {
1208 - out_be32(&qe_immr->cp.cecr, (u32) (cmd | QE_CR_FLG));
1209 + iowrite32be((cmd | QE_CR_FLG), &qe_immr->cp.cecr);
1210 } else {
1211 if (cmd == QE_ASSIGN_PAGE) {
1212 /* Here device is the SNUM, not sub-block */
1213 @@ -132,20 +142,26 @@ int qe_issue_cmd(u32 cmd, u32 device, u8
1214 mcn_shift = QE_CR_MCN_NORMAL_SHIFT;
1215 }
1216  
1217 - out_be32(&qe_immr->cp.cecdr, cmd_input);
1218 - out_be32(&qe_immr->cp.cecr,
1219 - (cmd | QE_CR_FLG | ((u32) device << dev_shift) | (u32)
1220 - mcn_protocol << mcn_shift));
1221 + iowrite32be(cmd_input, &qe_immr->cp.cecdr);
1222 + iowrite32be((cmd | QE_CR_FLG | ((u32)device << dev_shift) |
1223 + (u32)mcn_protocol << mcn_shift), &qe_immr->cp.cecr);
1224 }
1225  
1226 /* wait for the QE_CR_FLG to clear */
1227 - ret = spin_event_timeout((in_be32(&qe_immr->cp.cecr) & QE_CR_FLG) == 0,
1228 - 100, 0);
1229 + ret = -EIO;
1230 + for (i = 0; i < 100; i++) {
1231 + if ((ioread32be(&qe_immr->cp.cecr) & QE_CR_FLG) == 0) {
1232 + ret = 0;
1233 + break;
1234 + }
1235 + udelay(1);
1236 + }
1237 +
1238 /* On timeout (e.g. failure), the expression will be false (ret == 0),
1239 otherwise it will be true (ret == 1). */
1240 spin_unlock_irqrestore(&qe_lock, flags);
1241  
1242 - return ret == 1;
1243 + return ret;
1244 }
1245 EXPORT_SYMBOL(qe_issue_cmd);
1246  
1247 @@ -170,6 +186,8 @@ unsigned int qe_get_brg_clk(void)
1248 int size;
1249 const u32 *prop;
1250 unsigned int mod;
1251 + u32 val;
1252 + int ret;
1253  
1254 if (brg_clk)
1255 return brg_clk;
1256 @@ -181,9 +199,9 @@ unsigned int qe_get_brg_clk(void)
1257 return brg_clk;
1258 }
1259  
1260 - prop = of_get_property(qe, "brg-frequency", &size);
1261 - if (prop && size == sizeof(*prop))
1262 - brg_clk = *prop;
1263 + ret = of_property_read_u32(qe, "brg-frequency", &val);
1264 + if (!ret)
1265 + brg_clk = val;
1266  
1267 of_node_put(qe);
1268  
1269 @@ -236,7 +254,7 @@ int qe_setbrg(enum qe_clock brg, unsigne
1270 tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |
1271 QE_BRGC_ENABLE | div16;
1272  
1273 - out_be32(&qe_immr->brg.brgc[brg - QE_BRG1], tempval);
1274 + iowrite32be(tempval, &qe_immr->brg.brgc[brg - QE_BRG1]);
1275  
1276 return 0;
1277 }
1278 @@ -370,9 +388,9 @@ static int qe_sdma_init(void)
1279 return -ENOMEM;
1280 }
1281  
1282 - out_be32(&sdma->sdebcr, (u32) sdma_buf_offset & QE_SDEBCR_BA_MASK);
1283 - out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK |
1284 - (0x1 << QE_SDMR_CEN_SHIFT)));
1285 + iowrite32be((u32)sdma_buf_offset & QE_SDEBCR_BA_MASK, &sdma->sdebcr);
1286 + iowrite32be((QE_SDMR_GLB_1_MSK | (0x1 << QE_SDMR_CEN_SHIFT)),
1287 + &sdma->sdmr);
1288  
1289 return 0;
1290 }
1291 @@ -410,14 +428,14 @@ static void qe_upload_microcode(const vo
1292 "uploading microcode '%s'\n", ucode->id);
1293  
1294 /* Use auto-increment */
1295 - out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
1296 - QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);
1297 + iowrite32be(be32_to_cpu(ucode->iram_offset) | QE_IRAM_IADD_AIE |
1298 + QE_IRAM_IADD_BADDR, &qe_immr->iram.iadd);
1299  
1300 for (i = 0; i < be32_to_cpu(ucode->count); i++)
1301 - out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));
1302 + iowrite32be(be32_to_cpu(code[i]), &qe_immr->iram.idata);
1303  
1304 /* Set I-RAM Ready Register */
1305 - out_be32(&qe_immr->iram.iready, be32_to_cpu(QE_IRAM_READY));
1306 + iowrite32be(be32_to_cpu(QE_IRAM_READY), &qe_immr->iram.iready);
1307 }
1308  
1309 /*
1310 @@ -502,7 +520,7 @@ int qe_upload_firmware(const struct qe_f
1311 * If the microcode calls for it, split the I-RAM.
1312 */
1313 if (!firmware->split)
1314 - setbits16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR);
1315 + qe_setbits16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR);
1316  
1317 if (firmware->soc.model)
1318 printk(KERN_INFO
1319 @@ -536,11 +554,11 @@ int qe_upload_firmware(const struct qe_f
1320 u32 trap = be32_to_cpu(ucode->traps[j]);
1321  
1322 if (trap)
1323 - out_be32(&qe_immr->rsp[i].tibcr[j], trap);
1324 + iowrite32be(trap, &qe_immr->rsp[i].tibcr[j]);
1325 }
1326  
1327 /* Enable traps */
1328 - out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
1329 + iowrite32be(be32_to_cpu(ucode->eccr), &qe_immr->rsp[i].eccr);
1330 }
1331  
1332 qe_firmware_uploaded = 1;
1333 @@ -659,9 +677,9 @@ EXPORT_SYMBOL(qe_get_num_of_risc);
1334 unsigned int qe_get_num_of_snums(void)
1335 {
1336 struct device_node *qe;
1337 - int size;
1338 unsigned int num_of_snums;
1339 - const u32 *prop;
1340 + u32 val;
1341 + int ret;
1342  
1343 num_of_snums = 28; /* The default number of snum for threads is 28 */
1344 qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
1345 @@ -675,9 +693,9 @@ unsigned int qe_get_num_of_snums(void)
1346 return num_of_snums;
1347 }
1348  
1349 - prop = of_get_property(qe, "fsl,qe-num-snums", &size);
1350 - if (prop && size == sizeof(*prop)) {
1351 - num_of_snums = *prop;
1352 + ret = of_property_read_u32(qe, "fsl,qe-num-snums", &val);
1353 + if (!ret) {
1354 + num_of_snums = val;
1355 if ((num_of_snums < 28) || (num_of_snums > QE_NUM_OF_SNUM)) {
1356 /* No QE ever has fewer than 28 SNUMs */
1357 pr_err("QE: number of snum is invalid\n");
1358 --- a/drivers/soc/fsl/qe/qe_ic.h
1359 +++ /dev/null
1360 @@ -1,103 +0,0 @@
1361 -/*
1362 - * drivers/soc/fsl/qe/qe_ic.h
1363 - *
1364 - * QUICC ENGINE Interrupt Controller Header
1365 - *
1366 - * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
1367 - *
1368 - * Author: Li Yang <leoli@freescale.com>
1369 - * Based on code from Shlomi Gridish <gridish@freescale.com>
1370 - *
1371 - * This program is free software; you can redistribute it and/or modify it
1372 - * under the terms of the GNU General Public License as published by the
1373 - * Free Software Foundation; either version 2 of the License, or (at your
1374 - * option) any later version.
1375 - */
1376 -#ifndef _POWERPC_SYSDEV_QE_IC_H
1377 -#define _POWERPC_SYSDEV_QE_IC_H
1378 -
1379 -#include <soc/fsl/qe/qe_ic.h>
1380 -
1381 -#define NR_QE_IC_INTS 64
1382 -
1383 -/* QE IC registers offset */
1384 -#define QEIC_CICR 0x00
1385 -#define QEIC_CIVEC 0x04
1386 -#define QEIC_CRIPNR 0x08
1387 -#define QEIC_CIPNR 0x0c
1388 -#define QEIC_CIPXCC 0x10
1389 -#define QEIC_CIPYCC 0x14
1390 -#define QEIC_CIPWCC 0x18
1391 -#define QEIC_CIPZCC 0x1c
1392 -#define QEIC_CIMR 0x20
1393 -#define QEIC_CRIMR 0x24
1394 -#define QEIC_CICNR 0x28
1395 -#define QEIC_CIPRTA 0x30
1396 -#define QEIC_CIPRTB 0x34
1397 -#define QEIC_CRICR 0x3c
1398 -#define QEIC_CHIVEC 0x60
1399 -
1400 -/* Interrupt priority registers */
1401 -#define CIPCC_SHIFT_PRI0 29
1402 -#define CIPCC_SHIFT_PRI1 26
1403 -#define CIPCC_SHIFT_PRI2 23
1404 -#define CIPCC_SHIFT_PRI3 20
1405 -#define CIPCC_SHIFT_PRI4 13
1406 -#define CIPCC_SHIFT_PRI5 10
1407 -#define CIPCC_SHIFT_PRI6 7
1408 -#define CIPCC_SHIFT_PRI7 4
1409 -
1410 -/* CICR priority modes */
1411 -#define CICR_GWCC 0x00040000
1412 -#define CICR_GXCC 0x00020000
1413 -#define CICR_GYCC 0x00010000
1414 -#define CICR_GZCC 0x00080000
1415 -#define CICR_GRTA 0x00200000
1416 -#define CICR_GRTB 0x00400000
1417 -#define CICR_HPIT_SHIFT 8
1418 -#define CICR_HPIT_MASK 0x00000300
1419 -#define CICR_HP_SHIFT 24
1420 -#define CICR_HP_MASK 0x3f000000
1421 -
1422 -/* CICNR */
1423 -#define CICNR_WCC1T_SHIFT 20
1424 -#define CICNR_ZCC1T_SHIFT 28
1425 -#define CICNR_YCC1T_SHIFT 12
1426 -#define CICNR_XCC1T_SHIFT 4
1427 -
1428 -/* CRICR */
1429 -#define CRICR_RTA1T_SHIFT 20
1430 -#define CRICR_RTB1T_SHIFT 28
1431 -
1432 -/* Signal indicator */
1433 -#define SIGNAL_MASK 3
1434 -#define SIGNAL_HIGH 2
1435 -#define SIGNAL_LOW 0
1436 -
1437 -struct qe_ic {
1438 - /* Control registers offset */
1439 - volatile u32 __iomem *regs;
1440 -
1441 - /* The remapper for this QEIC */
1442 - struct irq_domain *irqhost;
1443 -
1444 - /* The "linux" controller struct */
1445 - struct irq_chip hc_irq;
1446 -
1447 - /* VIRQ numbers of QE high/low irqs */
1448 - unsigned int virq_high;
1449 - unsigned int virq_low;
1450 -};
1451 -
1452 -/*
1453 - * QE interrupt controller internal structure
1454 - */
1455 -struct qe_ic_info {
1456 - u32 mask; /* location of this source at the QIMR register. */
1457 - u32 mask_reg; /* Mask register offset */
1458 - u8 pri_code; /* for grouped interrupts sources - the interrupt
1459 - code as appears at the group priority register */
1460 - u32 pri_reg; /* Group priority register offset */
1461 -};
1462 -
1463 -#endif /* _POWERPC_SYSDEV_QE_IC_H */
1464 --- a/drivers/soc/fsl/qe/qe_io.c
1465 +++ b/drivers/soc/fsl/qe/qe_io.c
1466 @@ -22,8 +22,6 @@
1467  
1468 #include <asm/io.h>
1469 #include <soc/fsl/qe/qe.h>
1470 -#include <asm/prom.h>
1471 -#include <sysdev/fsl_soc.h>
1472  
1473 #undef DEBUG
1474  
1475 @@ -61,16 +59,16 @@ void __par_io_config_pin(struct qe_pio_r
1476 pin_mask1bit = (u32) (1 << (QE_PIO_PINS - (pin + 1)));
1477  
1478 /* Set open drain, if required */
1479 - tmp_val = in_be32(&par_io->cpodr);
1480 + tmp_val = ioread32be(&par_io->cpodr);
1481 if (open_drain)
1482 - out_be32(&par_io->cpodr, pin_mask1bit | tmp_val);
1483 + iowrite32be(pin_mask1bit | tmp_val, &par_io->cpodr);
1484 else
1485 - out_be32(&par_io->cpodr, ~pin_mask1bit & tmp_val);
1486 + iowrite32be(~pin_mask1bit & tmp_val, &par_io->cpodr);
1487  
1488 /* define direction */
1489 tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ?
1490 - in_be32(&par_io->cpdir2) :
1491 - in_be32(&par_io->cpdir1);
1492 + ioread32be(&par_io->cpdir2) :
1493 + ioread32be(&par_io->cpdir1);
1494  
1495 /* get all bits mask for 2 bit per port */
1496 pin_mask2bits = (u32) (0x3 << (QE_PIO_PINS -
1497 @@ -82,34 +80,30 @@ void __par_io_config_pin(struct qe_pio_r
1498  
1499 /* clear and set 2 bits mask */
1500 if (pin > (QE_PIO_PINS / 2) - 1) {
1501 - out_be32(&par_io->cpdir2,
1502 - ~pin_mask2bits & tmp_val);
1503 + iowrite32be(~pin_mask2bits & tmp_val, &par_io->cpdir2);
1504 tmp_val &= ~pin_mask2bits;
1505 - out_be32(&par_io->cpdir2, new_mask2bits | tmp_val);
1506 + iowrite32be(new_mask2bits | tmp_val, &par_io->cpdir2);
1507 } else {
1508 - out_be32(&par_io->cpdir1,
1509 - ~pin_mask2bits & tmp_val);
1510 + iowrite32be(~pin_mask2bits & tmp_val, &par_io->cpdir1);
1511 tmp_val &= ~pin_mask2bits;
1512 - out_be32(&par_io->cpdir1, new_mask2bits | tmp_val);
1513 + iowrite32be(new_mask2bits | tmp_val, &par_io->cpdir1);
1514 }
1515 /* define pin assignment */
1516 tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ?
1517 - in_be32(&par_io->cppar2) :
1518 - in_be32(&par_io->cppar1);
1519 + ioread32be(&par_io->cppar2) :
1520 + ioread32be(&par_io->cppar1);
1521  
1522 new_mask2bits = (u32) (assignment << (QE_PIO_PINS -
1523 (pin % (QE_PIO_PINS / 2) + 1) * 2));
1524 /* clear and set 2 bits mask */
1525 if (pin > (QE_PIO_PINS / 2) - 1) {
1526 - out_be32(&par_io->cppar2,
1527 - ~pin_mask2bits & tmp_val);
1528 + iowrite32be(~pin_mask2bits & tmp_val, &par_io->cppar2);
1529 tmp_val &= ~pin_mask2bits;
1530 - out_be32(&par_io->cppar2, new_mask2bits | tmp_val);
1531 + iowrite32be(new_mask2bits | tmp_val, &par_io->cppar2);
1532 } else {
1533 - out_be32(&par_io->cppar1,
1534 - ~pin_mask2bits & tmp_val);
1535 + iowrite32be(~pin_mask2bits & tmp_val, &par_io->cppar1);
1536 tmp_val &= ~pin_mask2bits;
1537 - out_be32(&par_io->cppar1, new_mask2bits | tmp_val);
1538 + iowrite32be(new_mask2bits | tmp_val, &par_io->cppar1);
1539 }
1540 }
1541 EXPORT_SYMBOL(__par_io_config_pin);
1542 @@ -137,12 +131,12 @@ int par_io_data_set(u8 port, u8 pin, u8
1543 /* calculate pin location */
1544 pin_mask = (u32) (1 << (QE_PIO_PINS - 1 - pin));
1545  
1546 - tmp_val = in_be32(&par_io[port].cpdata);
1547 + tmp_val = ioread32be(&par_io[port].cpdata);
1548  
1549 if (val == 0) /* clear */
1550 - out_be32(&par_io[port].cpdata, ~pin_mask & tmp_val);
1551 + iowrite32be(~pin_mask & tmp_val, &par_io[port].cpdata);
1552 else /* set */
1553 - out_be32(&par_io[port].cpdata, pin_mask | tmp_val);
1554 + iowrite32be(pin_mask | tmp_val, &par_io[port].cpdata);
1555  
1556 return 0;
1557 }
1558 --- a/drivers/soc/fsl/qe/qe_tdm.c
1559 +++ b/drivers/soc/fsl/qe/qe_tdm.c
1560 @@ -228,10 +228,10 @@ void ucc_tdm_init(struct ucc_tdm *utdm,
1561 &siram[siram_entry_id * 32 + 0x200 + i]);
1562 }
1563  
1564 - setbits16(&siram[(siram_entry_id * 32) + (utdm->num_of_ts - 1)],
1565 - SIR_LAST);
1566 - setbits16(&siram[(siram_entry_id * 32) + 0x200 + (utdm->num_of_ts - 1)],
1567 - SIR_LAST);
1568 + qe_setbits16(&siram[(siram_entry_id * 32) + (utdm->num_of_ts - 1)],
1569 + SIR_LAST);
1570 + qe_setbits16(&siram[(siram_entry_id * 32) + 0x200 +
1571 + (utdm->num_of_ts - 1)], SIR_LAST);
1572  
1573 /* Set SIxMR register */
1574 sixmr = SIMR_SAD(siram_entry_id);
1575 --- a/drivers/soc/fsl/qe/ucc.c
1576 +++ b/drivers/soc/fsl/qe/ucc.c
1577 @@ -39,7 +39,7 @@ int ucc_set_qe_mux_mii_mng(unsigned int
1578 return -EINVAL;
1579  
1580 spin_lock_irqsave(&cmxgcr_lock, flags);
1581 - clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG,
1582 + qe_clrsetbits32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG,
1583 ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT);
1584 spin_unlock_irqrestore(&cmxgcr_lock, flags);
1585  
1586 @@ -84,7 +84,7 @@ int ucc_set_type(unsigned int ucc_num, e
1587 return -EINVAL;
1588 }
1589  
1590 - clrsetbits_8(guemr, UCC_GUEMR_MODE_MASK,
1591 + qe_clrsetbits8(guemr, UCC_GUEMR_MODE_MASK,
1592 UCC_GUEMR_SET_RESERVED3 | speed);
1593  
1594 return 0;
1595 @@ -113,9 +113,9 @@ int ucc_mux_set_grant_tsa_bkpt(unsigned
1596 get_cmxucr_reg(ucc_num, &cmxucr, &reg_num, &shift);
1597  
1598 if (set)
1599 - setbits32(cmxucr, mask << shift);
1600 + qe_setbits32(cmxucr, mask << shift);
1601 else
1602 - clrbits32(cmxucr, mask << shift);
1603 + qe_clrbits32(cmxucr, mask << shift);
1604  
1605 return 0;
1606 }
1607 @@ -211,7 +211,7 @@ int ucc_set_qe_mux_rxtx(unsigned int ucc
1608 if (mode == COMM_DIR_RX)
1609 shift += 4;
1610  
1611 - clrsetbits_be32(cmxucr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,
1612 + qe_clrsetbits32(cmxucr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,
1613 clock_bits << shift);
1614  
1615 return 0;
1616 --- a/drivers/soc/fsl/qe/ucc_fast.c
1617 +++ b/drivers/soc/fsl/qe/ucc_fast.c
1618 @@ -33,41 +33,41 @@ void ucc_fast_dump_regs(struct ucc_fast_
1619 printk(KERN_INFO "Base address: 0x%p\n", uccf->uf_regs);
1620  
1621 printk(KERN_INFO "gumr : addr=0x%p, val=0x%08x\n",
1622 - &uccf->uf_regs->gumr, in_be32(&uccf->uf_regs->gumr));
1623 + &uccf->uf_regs->gumr, ioread32be(&uccf->uf_regs->gumr));
1624 printk(KERN_INFO "upsmr : addr=0x%p, val=0x%08x\n",
1625 - &uccf->uf_regs->upsmr, in_be32(&uccf->uf_regs->upsmr));
1626 + &uccf->uf_regs->upsmr, ioread32be(&uccf->uf_regs->upsmr));
1627 printk(KERN_INFO "utodr : addr=0x%p, val=0x%04x\n",
1628 - &uccf->uf_regs->utodr, in_be16(&uccf->uf_regs->utodr));
1629 + &uccf->uf_regs->utodr, ioread16be(&uccf->uf_regs->utodr));
1630 printk(KERN_INFO "udsr : addr=0x%p, val=0x%04x\n",
1631 - &uccf->uf_regs->udsr, in_be16(&uccf->uf_regs->udsr));
1632 + &uccf->uf_regs->udsr, ioread16be(&uccf->uf_regs->udsr));
1633 printk(KERN_INFO "ucce : addr=0x%p, val=0x%08x\n",
1634 - &uccf->uf_regs->ucce, in_be32(&uccf->uf_regs->ucce));
1635 + &uccf->uf_regs->ucce, ioread32be(&uccf->uf_regs->ucce));
1636 printk(KERN_INFO "uccm : addr=0x%p, val=0x%08x\n",
1637 - &uccf->uf_regs->uccm, in_be32(&uccf->uf_regs->uccm));
1638 + &uccf->uf_regs->uccm, ioread32be(&uccf->uf_regs->uccm));
1639 printk(KERN_INFO "uccs : addr=0x%p, val=0x%02x\n",
1640 - &uccf->uf_regs->uccs, in_8(&uccf->uf_regs->uccs));
1641 + &uccf->uf_regs->uccs, ioread8(&uccf->uf_regs->uccs));
1642 printk(KERN_INFO "urfb : addr=0x%p, val=0x%08x\n",
1643 - &uccf->uf_regs->urfb, in_be32(&uccf->uf_regs->urfb));
1644 + &uccf->uf_regs->urfb, ioread32be(&uccf->uf_regs->urfb));
1645 printk(KERN_INFO "urfs : addr=0x%p, val=0x%04x\n",
1646 - &uccf->uf_regs->urfs, in_be16(&uccf->uf_regs->urfs));
1647 + &uccf->uf_regs->urfs, ioread16be(&uccf->uf_regs->urfs));
1648 printk(KERN_INFO "urfet : addr=0x%p, val=0x%04x\n",
1649 - &uccf->uf_regs->urfet, in_be16(&uccf->uf_regs->urfet));
1650 + &uccf->uf_regs->urfet, ioread16be(&uccf->uf_regs->urfet));
1651 printk(KERN_INFO "urfset: addr=0x%p, val=0x%04x\n",
1652 - &uccf->uf_regs->urfset, in_be16(&uccf->uf_regs->urfset));
1653 + &uccf->uf_regs->urfset, ioread16be(&uccf->uf_regs->urfset));
1654 printk(KERN_INFO "utfb : addr=0x%p, val=0x%08x\n",
1655 - &uccf->uf_regs->utfb, in_be32(&uccf->uf_regs->utfb));
1656 + &uccf->uf_regs->utfb, ioread32be(&uccf->uf_regs->utfb));
1657 printk(KERN_INFO "utfs : addr=0x%p, val=0x%04x\n",
1658 - &uccf->uf_regs->utfs, in_be16(&uccf->uf_regs->utfs));
1659 + &uccf->uf_regs->utfs, ioread16be(&uccf->uf_regs->utfs));
1660 printk(KERN_INFO "utfet : addr=0x%p, val=0x%04x\n",
1661 - &uccf->uf_regs->utfet, in_be16(&uccf->uf_regs->utfet));
1662 + &uccf->uf_regs->utfet, ioread16be(&uccf->uf_regs->utfet));
1663 printk(KERN_INFO "utftt : addr=0x%p, val=0x%04x\n",
1664 - &uccf->uf_regs->utftt, in_be16(&uccf->uf_regs->utftt));
1665 + &uccf->uf_regs->utftt, ioread16be(&uccf->uf_regs->utftt));
1666 printk(KERN_INFO "utpt : addr=0x%p, val=0x%04x\n",
1667 - &uccf->uf_regs->utpt, in_be16(&uccf->uf_regs->utpt));
1668 + &uccf->uf_regs->utpt, ioread16be(&uccf->uf_regs->utpt));
1669 printk(KERN_INFO "urtry : addr=0x%p, val=0x%08x\n",
1670 - &uccf->uf_regs->urtry, in_be32(&uccf->uf_regs->urtry));
1671 + &uccf->uf_regs->urtry, ioread32be(&uccf->uf_regs->urtry));
1672 printk(KERN_INFO "guemr : addr=0x%p, val=0x%02x\n",
1673 - &uccf->uf_regs->guemr, in_8(&uccf->uf_regs->guemr));
1674 + &uccf->uf_regs->guemr, ioread8(&uccf->uf_regs->guemr));
1675 }
1676 EXPORT_SYMBOL(ucc_fast_dump_regs);
1677  
1678 @@ -89,7 +89,7 @@ EXPORT_SYMBOL(ucc_fast_get_qe_cr_subbloc
1679  
1680 void ucc_fast_transmit_on_demand(struct ucc_fast_private * uccf)
1681 {
1682 - out_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD);
1683 + iowrite16be(UCC_FAST_TOD, &uccf->uf_regs->utodr);
1684 }
1685 EXPORT_SYMBOL(ucc_fast_transmit_on_demand);
1686  
1687 @@ -101,7 +101,7 @@ void ucc_fast_enable(struct ucc_fast_pri
1688 uf_regs = uccf->uf_regs;
1689  
1690 /* Enable reception and/or transmission on this UCC. */
1691 - gumr = in_be32(&uf_regs->gumr);
1692 + gumr = ioread32be(&uf_regs->gumr);
1693 if (mode & COMM_DIR_TX) {
1694 gumr |= UCC_FAST_GUMR_ENT;
1695 uccf->enabled_tx = 1;
1696 @@ -110,7 +110,7 @@ void ucc_fast_enable(struct ucc_fast_pri
1697 gumr |= UCC_FAST_GUMR_ENR;
1698 uccf->enabled_rx = 1;
1699 }
1700 - out_be32(&uf_regs->gumr, gumr);
1701 + iowrite32be(gumr, &uf_regs->gumr);
1702 }
1703 EXPORT_SYMBOL(ucc_fast_enable);
1704  
1705 @@ -122,7 +122,7 @@ void ucc_fast_disable(struct ucc_fast_pr
1706 uf_regs = uccf->uf_regs;
1707  
1708 /* Disable reception and/or transmission on this UCC. */
1709 - gumr = in_be32(&uf_regs->gumr);
1710 + gumr = ioread32be(&uf_regs->gumr);
1711 if (mode & COMM_DIR_TX) {
1712 gumr &= ~UCC_FAST_GUMR_ENT;
1713 uccf->enabled_tx = 0;
1714 @@ -131,7 +131,7 @@ void ucc_fast_disable(struct ucc_fast_pr
1715 gumr &= ~UCC_FAST_GUMR_ENR;
1716 uccf->enabled_rx = 0;
1717 }
1718 - out_be32(&uf_regs->gumr, gumr);
1719 + iowrite32be(gumr, &uf_regs->gumr);
1720 }
1721 EXPORT_SYMBOL(ucc_fast_disable);
1722  
1723 @@ -263,12 +263,13 @@ int ucc_fast_init(struct ucc_fast_info *
1724 gumr |= uf_info->tenc;
1725 gumr |= uf_info->tcrc;
1726 gumr |= uf_info->mode;
1727 - out_be32(&uf_regs->gumr, gumr);
1728 + iowrite32be(gumr, &uf_regs->gumr);
1729  
1730 /* Allocate memory for Tx Virtual Fifo */
1731 uccf->ucc_fast_tx_virtual_fifo_base_offset =
1732 qe_muram_alloc(uf_info->utfs, UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
1733 - if (IS_ERR_VALUE(uccf->ucc_fast_tx_virtual_fifo_base_offset)) {
1734 + if (IS_ERR_VALUE((unsigned long)uccf->
1735 + ucc_fast_tx_virtual_fifo_base_offset)) {
1736 printk(KERN_ERR "%s: cannot allocate MURAM for TX FIFO\n",
1737 __func__);
1738 uccf->ucc_fast_tx_virtual_fifo_base_offset = 0;
1739 @@ -281,7 +282,8 @@ int ucc_fast_init(struct ucc_fast_info *
1740 qe_muram_alloc(uf_info->urfs +
1741 UCC_FAST_RECEIVE_VIRTUAL_FIFO_SIZE_FUDGE_FACTOR,
1742 UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
1743 - if (IS_ERR_VALUE(uccf->ucc_fast_rx_virtual_fifo_base_offset)) {
1744 + if (IS_ERR_VALUE((unsigned long)uccf->
1745 + ucc_fast_rx_virtual_fifo_base_offset)) {
1746 printk(KERN_ERR "%s: cannot allocate MURAM for RX FIFO\n",
1747 __func__);
1748 uccf->ucc_fast_rx_virtual_fifo_base_offset = 0;
1749 @@ -290,15 +292,15 @@ int ucc_fast_init(struct ucc_fast_info *
1750 }
1751  
1752 /* Set Virtual Fifo registers */
1753 - out_be16(&uf_regs->urfs, uf_info->urfs);
1754 - out_be16(&uf_regs->urfet, uf_info->urfet);
1755 - out_be16(&uf_regs->urfset, uf_info->urfset);
1756 - out_be16(&uf_regs->utfs, uf_info->utfs);
1757 - out_be16(&uf_regs->utfet, uf_info->utfet);
1758 - out_be16(&uf_regs->utftt, uf_info->utftt);
1759 + iowrite16be(uf_info->urfs, &uf_regs->urfs);
1760 + iowrite16be(uf_info->urfet, &uf_regs->urfet);
1761 + iowrite16be(uf_info->urfset, &uf_regs->urfset);
1762 + iowrite16be(uf_info->utfs, &uf_regs->utfs);
1763 + iowrite16be(uf_info->utfet, &uf_regs->utfet);
1764 + iowrite16be(uf_info->utftt, &uf_regs->utftt);
1765 /* utfb, urfb are offsets from MURAM base */
1766 - out_be32(&uf_regs->utfb, uccf->ucc_fast_tx_virtual_fifo_base_offset);
1767 - out_be32(&uf_regs->urfb, uccf->ucc_fast_rx_virtual_fifo_base_offset);
1768 + iowrite32be(uccf->ucc_fast_tx_virtual_fifo_base_offset, &uf_regs->utfb);
1769 + iowrite32be(uccf->ucc_fast_rx_virtual_fifo_base_offset, &uf_regs->urfb);
1770  
1771 /* Mux clocking */
1772 /* Grant Support */
1773 @@ -366,14 +368,14 @@ int ucc_fast_init(struct ucc_fast_info *
1774 }
1775  
1776 /* Set interrupt mask register at UCC level. */
1777 - out_be32(&uf_regs->uccm, uf_info->uccm_mask);
1778 + iowrite32be(uf_info->uccm_mask, &uf_regs->uccm);
1779  
1780 /* First, clear anything pending at UCC level,
1781 * otherwise, old garbage may come through
1782 * as soon as the dam is opened. */
1783  
1784 /* Writing '1' clears */
1785 - out_be32(&uf_regs->ucce, 0xffffffff);
1786 + iowrite32be(0xffffffff, &uf_regs->ucce);
1787  
1788 *uccf_ret = uccf;
1789 return 0;
1790 --- a/drivers/tty/serial/ucc_uart.c
1791 +++ b/drivers/tty/serial/ucc_uart.c
1792 @@ -34,6 +34,7 @@
1793 #include <soc/fsl/qe/ucc_slow.h>
1794  
1795 #include <linux/firmware.h>
1796 +#include <asm/cpm.h>
1797 #include <asm/reg.h>
1798  
1799 /*
1800 --- a/include/soc/fsl/qe/qe.h
1801 +++ b/include/soc/fsl/qe/qe.h
1802 @@ -21,7 +21,6 @@
1803 #include <linux/spinlock.h>
1804 #include <linux/errno.h>
1805 #include <linux/err.h>
1806 -#include <asm/cpm.h>
1807 #include <soc/fsl/qe/immap_qe.h>
1808 #include <linux/of.h>
1809 #include <linux/of_address.h>
1810 --- a/include/soc/fsl/qe/qe_ic.h
1811 +++ /dev/null
1812 @@ -1,139 +0,0 @@
1813 -/*
1814 - * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
1815 - *
1816 - * Authors: Shlomi Gridish <gridish@freescale.com>
1817 - * Li Yang <leoli@freescale.com>
1818 - *
1819 - * Description:
1820 - * QE IC external definitions and structure.
1821 - *
1822 - * This program is free software; you can redistribute it and/or modify it
1823 - * under the terms of the GNU General Public License as published by the
1824 - * Free Software Foundation; either version 2 of the License, or (at your
1825 - * option) any later version.
1826 - */
1827 -#ifndef _ASM_POWERPC_QE_IC_H
1828 -#define _ASM_POWERPC_QE_IC_H
1829 -
1830 -#include <linux/irq.h>
1831 -
1832 -struct device_node;
1833 -struct qe_ic;
1834 -
1835 -#define NUM_OF_QE_IC_GROUPS 6
1836 -
1837 -/* Flags when we init the QE IC */
1838 -#define QE_IC_SPREADMODE_GRP_W 0x00000001
1839 -#define QE_IC_SPREADMODE_GRP_X 0x00000002
1840 -#define QE_IC_SPREADMODE_GRP_Y 0x00000004
1841 -#define QE_IC_SPREADMODE_GRP_Z 0x00000008
1842 -#define QE_IC_SPREADMODE_GRP_RISCA 0x00000010
1843 -#define QE_IC_SPREADMODE_GRP_RISCB 0x00000020
1844 -
1845 -#define QE_IC_LOW_SIGNAL 0x00000100
1846 -#define QE_IC_HIGH_SIGNAL 0x00000200
1847 -
1848 -#define QE_IC_GRP_W_PRI0_DEST_SIGNAL_HIGH 0x00001000
1849 -#define QE_IC_GRP_W_PRI1_DEST_SIGNAL_HIGH 0x00002000
1850 -#define QE_IC_GRP_X_PRI0_DEST_SIGNAL_HIGH 0x00004000
1851 -#define QE_IC_GRP_X_PRI1_DEST_SIGNAL_HIGH 0x00008000
1852 -#define QE_IC_GRP_Y_PRI0_DEST_SIGNAL_HIGH 0x00010000
1853 -#define QE_IC_GRP_Y_PRI1_DEST_SIGNAL_HIGH 0x00020000
1854 -#define QE_IC_GRP_Z_PRI0_DEST_SIGNAL_HIGH 0x00040000
1855 -#define QE_IC_GRP_Z_PRI1_DEST_SIGNAL_HIGH 0x00080000
1856 -#define QE_IC_GRP_RISCA_PRI0_DEST_SIGNAL_HIGH 0x00100000
1857 -#define QE_IC_GRP_RISCA_PRI1_DEST_SIGNAL_HIGH 0x00200000
1858 -#define QE_IC_GRP_RISCB_PRI0_DEST_SIGNAL_HIGH 0x00400000
1859 -#define QE_IC_GRP_RISCB_PRI1_DEST_SIGNAL_HIGH 0x00800000
1860 -#define QE_IC_GRP_W_DEST_SIGNAL_SHIFT (12)
1861 -
1862 -/* QE interrupt sources groups */
1863 -enum qe_ic_grp_id {
1864 - QE_IC_GRP_W = 0, /* QE interrupt controller group W */
1865 - QE_IC_GRP_X, /* QE interrupt controller group X */
1866 - QE_IC_GRP_Y, /* QE interrupt controller group Y */
1867 - QE_IC_GRP_Z, /* QE interrupt controller group Z */
1868 - QE_IC_GRP_RISCA, /* QE interrupt controller RISC group A */
1869 - QE_IC_GRP_RISCB /* QE interrupt controller RISC group B */
1870 -};
1871 -
1872 -#ifdef CONFIG_QUICC_ENGINE
1873 -void qe_ic_init(struct device_node *node, unsigned int flags,
1874 - void (*low_handler)(struct irq_desc *desc),
1875 - void (*high_handler)(struct irq_desc *desc));
1876 -unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic);
1877 -unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic);
1878 -#else
1879 -static inline void qe_ic_init(struct device_node *node, unsigned int flags,
1880 - void (*low_handler)(struct irq_desc *desc),
1881 - void (*high_handler)(struct irq_desc *desc))
1882 -{}
1883 -static inline unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
1884 -{ return 0; }
1885 -static inline unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
1886 -{ return 0; }
1887 -#endif /* CONFIG_QUICC_ENGINE */
1888 -
1889 -void qe_ic_set_highest_priority(unsigned int virq, int high);
1890 -int qe_ic_set_priority(unsigned int virq, unsigned int priority);
1891 -int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);
1892 -
1893 -static inline void qe_ic_cascade_low_ipic(struct irq_desc *desc)
1894 -{
1895 - struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
1896 - unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
1897 -
1898 - if (cascade_irq != NO_IRQ)
1899 - generic_handle_irq(cascade_irq);
1900 -}
1901 -
1902 -static inline void qe_ic_cascade_high_ipic(struct irq_desc *desc)
1903 -{
1904 - struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
1905 - unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
1906 -
1907 - if (cascade_irq != NO_IRQ)
1908 - generic_handle_irq(cascade_irq);
1909 -}
1910 -
1911 -static inline void qe_ic_cascade_low_mpic(struct irq_desc *desc)
1912 -{
1913 - struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
1914 - unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
1915 - struct irq_chip *chip = irq_desc_get_chip(desc);
1916 -
1917 - if (cascade_irq != NO_IRQ)
1918 - generic_handle_irq(cascade_irq);
1919 -
1920 - chip->irq_eoi(&desc->irq_data);
1921 -}
1922 -
1923 -static inline void qe_ic_cascade_high_mpic(struct irq_desc *desc)
1924 -{
1925 - struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
1926 - unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
1927 - struct irq_chip *chip = irq_desc_get_chip(desc);
1928 -
1929 - if (cascade_irq != NO_IRQ)
1930 - generic_handle_irq(cascade_irq);
1931 -
1932 - chip->irq_eoi(&desc->irq_data);
1933 -}
1934 -
1935 -static inline void qe_ic_cascade_muxed_mpic(struct irq_desc *desc)
1936 -{
1937 - struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
1938 - unsigned int cascade_irq;
1939 - struct irq_chip *chip = irq_desc_get_chip(desc);
1940 -
1941 - cascade_irq = qe_ic_get_high_irq(qe_ic);
1942 - if (cascade_irq == NO_IRQ)
1943 - cascade_irq = qe_ic_get_low_irq(qe_ic);
1944 -
1945 - if (cascade_irq != NO_IRQ)
1946 - generic_handle_irq(cascade_irq);
1947 -
1948 - chip->irq_eoi(&desc->irq_data);
1949 -}
1950 -
1951 -#endif /* _ASM_POWERPC_QE_IC_H */