OpenWrt – Blame information for rev 1

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1 office 1 From 14909c4e4e836925668e74fc6e0e85ba0283cbf9 Mon Sep 17 00:00:00 2001
2 From: Hauke Mehrtens <hauke@hauke-m.de>
3 Date: Fri, 6 Jan 2017 17:40:12 +0100
4 Subject: [PATCH 2/2] MIPS: lantiq: improve USB initialization
5  
6 This adds code to initialize the USB controller and PHY also on Danube,
7 Amazon SE and AR10. This code is based on the Vendor driver from
8 different UGW versions and compared to the hardware documentation.
9  
10 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
11 ---
12 arch/mips/lantiq/xway/sysctrl.c | 20 +++++++
13 2 files changed, 110 insertions(+), 30 deletions(-)
14  
15  
16 --- a/arch/mips/lantiq/xway/sysctrl.c
17 +++ b/arch/mips/lantiq/xway/sysctrl.c
18 @@ -246,6 +246,25 @@ static void pmu_disable(struct clk *clk)
19 pr_warn("deactivating PMU module failed!");
20 }
21  
22 +static void usb_set_clock(void)
23 +{
24 + unsigned int val = ltq_cgu_r32(ifccr);
25 +
26 + if (of_machine_is_compatible("lantiq,ar10") ||
27 + of_machine_is_compatible("lantiq,grx390")) {
28 + val &= ~0x03; /* XTAL divided by 3 */
29 + } else if (of_machine_is_compatible("lantiq,ar9") ||
30 + of_machine_is_compatible("lantiq,vr9")) {
31 + /* TODO: this depends on the XTAL frequency */
32 + val |= 0x03; /* XTAL divided by 3 */
33 + } else if (of_machine_is_compatible("lantiq,ase")) {
34 + val |= 0x20; /* from XTAL */
35 + } else if (of_machine_is_compatible("lantiq,danube")) {
36 + val |= 0x30; /* 12 MHz, generated from 36 MHz */
37 + }
38 + ltq_cgu_w32(val, ifccr);
39 +}
40 +
41 /* the pci enable helper */
42 static int pci_enable(struct clk *clk)
43 {
44 @@ -569,4 +588,5 @@ void __init ltq_soc_init(void)
45 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
46 clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
47 }
48 + usb_set_clock();
49 }