OpenWrt – Blame information for rev 1
?pathlinks?
Rev | Author | Line No. | Line |
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1 | office | 1 | --- a/arch/arm/mach-ixp4xx/Kconfig |
2 | +++ b/arch/arm/mach-ixp4xx/Kconfig |
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3 | @@ -21,6 +21,14 @@ config MACH_AVILA |
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4 | Avila Network Platform. For more information on this platform, |
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5 | see <file:Documentation/arm/IXP4xx>. |
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6 | |||
7 | +config MACH_CAMBRIA |
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8 | + bool "Cambria" |
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9 | + select PCI |
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10 | + help |
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11 | + Say 'Y' here if you want your kernel to support the Gateworks |
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12 | + Cambria series. For more information on this platform, |
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13 | + see <file:Documentation/arm/IXP4xx>. |
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14 | + |
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15 | config MACH_LOFT |
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16 | bool "Loft" |
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17 | depends on MACH_AVILA |
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18 | @@ -218,7 +226,7 @@ config CPU_IXP46X |
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19 | |||
20 | config CPU_IXP43X |
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21 | bool |
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22 | - depends on MACH_KIXRP435 |
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23 | + depends on MACH_KIXRP435 || MACH_CAMBRIA |
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24 | default y |
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25 | |||
26 | config MACH_GTWX5715 |
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27 | --- a/arch/arm/mach-ixp4xx/Makefile |
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28 | +++ b/arch/arm/mach-ixp4xx/Makefile |
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29 | @@ -7,6 +7,7 @@ obj-pci-n := |
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30 | |||
31 | obj-pci-$(CONFIG_ARCH_IXDP4XX) += ixdp425-pci.o |
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32 | obj-pci-$(CONFIG_MACH_AVILA) += avila-pci.o |
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33 | +obj-pci-$(CONFIG_MACH_CAMBRIA) += cambria-pci.o |
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34 | obj-pci-$(CONFIG_MACH_IXDPG425) += ixdpg425-pci.o |
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35 | obj-pci-$(CONFIG_ARCH_ADI_COYOTE) += coyote-pci.o |
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36 | obj-pci-$(CONFIG_MACH_GTWX5715) += gtwx5715-pci.o |
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37 | @@ -31,6 +32,7 @@ obj-y += common.o |
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38 | |||
39 | obj-$(CONFIG_ARCH_IXDP4XX) += ixdp425-setup.o |
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40 | obj-$(CONFIG_MACH_AVILA) += avila-setup.o |
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41 | +obj-$(CONFIG_MACH_CAMBRIA) += cambria-setup.o |
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42 | obj-$(CONFIG_MACH_IXDPG425) += coyote-setup.o |
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43 | obj-$(CONFIG_ARCH_ADI_COYOTE) += coyote-setup.o |
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44 | obj-$(CONFIG_MACH_GTWX5715) += gtwx5715-setup.o |
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45 | --- /dev/null |
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46 | +++ b/arch/arm/mach-ixp4xx/cambria-pci.c |
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47 | @@ -0,0 +1,78 @@ |
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48 | +/* |
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49 | + * arch/arch/mach-ixp4xx/cambria-pci.c |
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50 | + * |
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51 | + * PCI setup routines for Gateworks Cambria series |
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52 | + * |
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53 | + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> |
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54 | + * |
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55 | + * based on coyote-pci.c: |
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56 | + * Copyright (C) 2002 Jungo Software Technologies. |
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57 | + * Copyright (C) 2003 MontaVista Softwrae, Inc. |
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58 | + * |
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59 | + * Maintainer: Imre Kaloz <kaloz@openwrt.org> |
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60 | + * |
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61 | + * This program is free software; you can redistribute it and/or modify |
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62 | + * it under the terms of the GNU General Public License version 2 as |
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63 | + * published by the Free Software Foundation. |
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64 | + * |
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65 | + */ |
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66 | + |
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67 | +#include <linux/kernel.h> |
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68 | +#include <linux/pci.h> |
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69 | +#include <linux/init.h> |
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70 | +#include <linux/irq.h> |
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71 | + |
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72 | +#include <asm/mach-types.h> |
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73 | +#include <mach/hardware.h> |
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74 | +#include <asm/irq.h> |
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75 | + |
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76 | +#include <asm/mach/pci.h> |
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77 | + |
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78 | +extern void ixp4xx_pci_preinit(void); |
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79 | +extern int ixp4xx_setup(int nr, struct pci_sys_data *sys); |
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80 | +extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys); |
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81 | + |
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82 | +void __init cambria_pci_preinit(void) |
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83 | +{ |
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84 | + irq_set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW); |
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85 | + irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW); |
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86 | + irq_set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW); |
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87 | + irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW); |
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88 | + |
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89 | + ixp4xx_pci_preinit(); |
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90 | +} |
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91 | + |
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92 | +static int __init cambria_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
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93 | +{ |
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94 | + if (slot == 1) |
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95 | + return IRQ_IXP4XX_GPIO11; |
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96 | + else if (slot == 2) |
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97 | + return IRQ_IXP4XX_GPIO10; |
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98 | + else if (slot == 3) |
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99 | + return IRQ_IXP4XX_GPIO9; |
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100 | + else if (slot == 4) |
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101 | + return IRQ_IXP4XX_GPIO8; |
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102 | + else if (slot == 6) |
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103 | + return IRQ_IXP4XX_GPIO10; |
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104 | + else if (slot == 15) |
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105 | + return IRQ_IXP4XX_GPIO8; |
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106 | + |
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107 | + else return -1; |
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108 | +} |
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109 | + |
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110 | +struct hw_pci cambria_pci __initdata = { |
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111 | + .nr_controllers = 1, |
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112 | + .preinit = cambria_pci_preinit, |
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113 | + .ops = &ixp4xx_ops, |
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114 | + .setup = ixp4xx_setup, |
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115 | + .map_irq = cambria_map_irq, |
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116 | +}; |
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117 | + |
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118 | +int __init cambria_pci_init(void) |
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119 | +{ |
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120 | + if (machine_is_cambria()) |
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121 | + pci_common_init(&cambria_pci); |
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122 | + return 0; |
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123 | +} |
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124 | + |
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125 | +subsys_initcall(cambria_pci_init); |
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126 | --- /dev/null |
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127 | +++ b/arch/arm/mach-ixp4xx/cambria-setup.c |
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128 | @@ -0,0 +1,1003 @@ |
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129 | +/* |
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130 | + * arch/arm/mach-ixp4xx/cambria-setup.c |
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131 | + * |
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132 | + * Board setup for the Gateworks Cambria series |
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133 | + * |
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134 | + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> |
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135 | + * Copyright (C) 2012 Gateworks Corporation <support@gateworks.com> |
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136 | + * |
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137 | + * based on coyote-setup.c: |
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138 | + * Copyright (C) 2003-2005 MontaVista Software, Inc. |
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139 | + * |
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140 | + * Author: Imre Kaloz <kaloz@openwrt.org> |
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141 | + * Tim Harvey <tharvey@gateworks.com> |
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142 | + */ |
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143 | + |
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144 | +#include <linux/device.h> |
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145 | +#include <linux/gpio_keys.h> |
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146 | +#include <linux/gpio.h> |
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147 | +#include <linux/i2c.h> |
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148 | +#include <linux/i2c-gpio.h> |
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149 | +#include <linux/platform_data/at24.h> |
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150 | +#include <linux/i2c/gw_i2c_pld.h> |
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151 | +#include <linux/platform_data/pca953x.h> |
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152 | +#include <linux/if_ether.h> |
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153 | +#include <linux/init.h> |
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154 | +#include <linux/input.h> |
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155 | +#include <linux/kernel.h> |
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156 | +#include <linux/leds.h> |
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157 | +#include <linux/memory.h> |
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158 | +#include <linux/netdevice.h> |
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159 | +#include <linux/serial.h> |
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160 | +#include <linux/serial_8250.h> |
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161 | +#include <linux/slab.h> |
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162 | +#include <linux/socket.h> |
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163 | +#include <linux/types.h> |
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164 | +#include <linux/tty.h> |
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165 | +#include <linux/irq.h> |
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166 | +#include <linux/usb/ehci_pdriver.h> |
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167 | + |
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168 | +#include <mach/hardware.h> |
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169 | +#include <asm/irq.h> |
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170 | +#include <asm/mach-types.h> |
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171 | +#include <asm/mach/arch.h> |
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172 | +#include <asm/mach/flash.h> |
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173 | +#include <asm/setup.h> |
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174 | + |
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175 | +#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) |
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176 | + |
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177 | +struct cambria_board_info { |
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178 | + unsigned char *model; |
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179 | + void (*setup)(void); |
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180 | +}; |
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181 | + |
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182 | +static struct cambria_board_info *cambria_info __initdata; |
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183 | + |
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184 | +static struct flash_platform_data cambria_flash_data = { |
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185 | + .map_name = "cfi_probe", |
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186 | + .width = 2, |
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187 | +}; |
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188 | + |
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189 | +static struct resource cambria_flash_resource = { |
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190 | + .flags = IORESOURCE_MEM, |
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191 | +}; |
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192 | + |
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193 | +static struct platform_device cambria_flash = { |
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194 | + .name = "IXP4XX-Flash", |
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195 | + .id = 0, |
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196 | + .dev = { |
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197 | + .platform_data = &cambria_flash_data, |
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198 | + }, |
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199 | + .num_resources = 1, |
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200 | + .resource = &cambria_flash_resource, |
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201 | +}; |
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202 | + |
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203 | +static struct i2c_gpio_platform_data cambria_i2c_gpio_data = { |
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204 | + .sda_pin = 7, |
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205 | + .scl_pin = 6, |
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206 | +}; |
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207 | + |
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208 | +static struct platform_device cambria_i2c_gpio = { |
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209 | + .name = "i2c-gpio", |
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210 | + .id = 0, |
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211 | + .dev = { |
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212 | + .platform_data = &cambria_i2c_gpio_data, |
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213 | + }, |
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214 | +}; |
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215 | + |
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216 | +#ifdef SFP_SERIALID |
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217 | +static struct i2c_gpio_platform_data cambria_i2c_gpio_sfpa_data = { |
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218 | + .sda_pin = 113, |
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219 | + .scl_pin = 112, |
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220 | + .sda_is_open_drain = 0, |
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221 | + .scl_is_open_drain = 0, |
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222 | +}; |
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223 | + |
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224 | +static struct platform_device cambria_i2c_gpio_sfpa = { |
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225 | + .name = "i2c-gpio", |
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226 | + .id = 1, |
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227 | + .dev = { |
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228 | + .platform_data = &cambria_i2c_gpio_sfpa_data, |
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229 | + }, |
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230 | +}; |
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231 | + |
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232 | +static struct i2c_gpio_platform_data cambria_i2c_gpio_sfpb_data = { |
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233 | + .sda_pin = 115, |
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234 | + .scl_pin = 114, |
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235 | + .sda_is_open_drain = 0, |
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236 | + .scl_is_open_drain = 0, |
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237 | +}; |
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238 | + |
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239 | +static struct platform_device cambria_i2c_gpio_sfpb = { |
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240 | + .name = "i2c-gpio", |
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241 | + .id = 2, |
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242 | + .dev = { |
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243 | + .platform_data = &cambria_i2c_gpio_sfpb_data, |
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244 | + }, |
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245 | +}; |
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246 | +#endif // #ifdef SFP_SERIALID |
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247 | + |
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248 | +static struct eth_plat_info cambria_npec_data = { |
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249 | + .phy = 1, |
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250 | + .rxq = 4, |
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251 | + .txreadyq = 21, |
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252 | +}; |
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253 | + |
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254 | +static struct eth_plat_info cambria_npea_data = { |
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255 | + .phy = 2, |
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256 | + .rxq = 2, |
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257 | + .txreadyq = 19, |
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258 | +}; |
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259 | + |
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260 | +static struct platform_device cambria_npec_device = { |
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261 | + .name = "ixp4xx_eth", |
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262 | + .id = IXP4XX_ETH_NPEC, |
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263 | + .dev.platform_data = &cambria_npec_data, |
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264 | + .dev.coherent_dma_mask = DMA_BIT_MASK(32), |
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265 | +}; |
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266 | + |
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267 | +static struct platform_device cambria_npea_device = { |
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268 | + .name = "ixp4xx_eth", |
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269 | + .id = IXP4XX_ETH_NPEA, |
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270 | + .dev.platform_data = &cambria_npea_data, |
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271 | + .dev.coherent_dma_mask = DMA_BIT_MASK(32), |
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272 | +}; |
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273 | + |
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274 | +static struct resource cambria_uart_resource = { |
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275 | + .start = IXP4XX_UART1_BASE_PHYS, |
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276 | + .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, |
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277 | + .flags = IORESOURCE_MEM, |
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278 | +}; |
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279 | + |
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280 | +static struct plat_serial8250_port cambria_uart_data[] = { |
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281 | + { |
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282 | + .mapbase = IXP4XX_UART1_BASE_PHYS, |
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283 | + .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET, |
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284 | + .irq = IRQ_IXP4XX_UART1, |
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285 | + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, |
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286 | + .iotype = UPIO_MEM, |
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287 | + .regshift = 2, |
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288 | + .uartclk = IXP4XX_UART_XTAL, |
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289 | + }, |
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290 | + { }, |
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291 | +}; |
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292 | + |
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293 | +static struct platform_device cambria_uart = { |
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294 | + .name = "serial8250", |
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295 | + .id = PLAT8250_DEV_PLATFORM, |
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296 | + .dev = { |
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297 | + .platform_data = cambria_uart_data, |
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298 | + }, |
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299 | + .num_resources = 1, |
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300 | + .resource = &cambria_uart_resource, |
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301 | +}; |
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302 | + |
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303 | +static struct resource cambria_optional_uart_resources[] = { |
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304 | + { |
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305 | + .start = 0x52000000, |
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306 | + .end = 0x52000fff, |
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307 | + .flags = IORESOURCE_MEM |
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308 | + }, |
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309 | + { |
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310 | + .start = 0x53000000, |
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311 | + .end = 0x53000fff, |
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312 | + .flags = IORESOURCE_MEM |
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313 | + }, |
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314 | + { |
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315 | + .start = 0x52000000, |
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316 | + .end = 0x52000fff, |
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317 | + .flags = IORESOURCE_MEM |
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318 | + }, |
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319 | + { |
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320 | + .start = 0x52000000, |
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321 | + .end = 0x52000fff, |
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322 | + .flags = IORESOURCE_MEM |
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323 | + }, |
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324 | + { |
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325 | + .start = 0x52000000, |
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326 | + .end = 0x52000fff, |
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327 | + .flags = IORESOURCE_MEM |
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328 | + }, |
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329 | + { |
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330 | + .start = 0x52000000, |
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331 | + .end = 0x52000fff, |
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332 | + .flags = IORESOURCE_MEM |
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333 | + }, |
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334 | + { |
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335 | + .start = 0x52000000, |
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336 | + .end = 0x52000fff, |
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337 | + .flags = IORESOURCE_MEM |
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338 | + }, |
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339 | + { |
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340 | + .start = 0x53000000, |
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341 | + .end = 0x53000fff, |
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342 | + .flags = IORESOURCE_MEM |
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343 | + } |
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344 | +}; |
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345 | + |
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346 | +static struct plat_serial8250_port cambria_optional_uart_data[] = { |
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347 | + { |
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348 | + .flags = UPF_BOOT_AUTOCONF, |
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349 | + .iotype = UPIO_MEM_DELAY, |
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350 | + .regshift = 0, |
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351 | + .uartclk = 1843200, |
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352 | + .rw_delay = 10, |
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353 | + }, |
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354 | + { |
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355 | + .flags = UPF_BOOT_AUTOCONF, |
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356 | + .iotype = UPIO_MEM_DELAY, |
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357 | + .regshift = 0, |
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358 | + .uartclk = 1843200, |
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359 | + .rw_delay = 10, |
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360 | + }, |
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361 | + { |
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362 | + .flags = UPF_BOOT_AUTOCONF, |
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363 | + .iotype = UPIO_MEM, |
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364 | + .regshift = 0, |
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365 | + .uartclk = 18432000, |
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366 | + }, |
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367 | + { |
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368 | + .flags = UPF_BOOT_AUTOCONF, |
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369 | + .iotype = UPIO_MEM, |
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370 | + .regshift = 0, |
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371 | + .uartclk = 18432000, |
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372 | + }, |
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373 | + { |
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374 | + .flags = UPF_BOOT_AUTOCONF, |
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375 | + .iotype = UPIO_MEM, |
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376 | + .regshift = 0, |
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377 | + .uartclk = 18432000, |
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378 | + }, |
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379 | + { |
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380 | + .flags = UPF_BOOT_AUTOCONF, |
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381 | + .iotype = UPIO_MEM, |
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382 | + .regshift = 0, |
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383 | + .uartclk = 18432000, |
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384 | + }, |
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385 | + { |
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386 | + .flags = UPF_BOOT_AUTOCONF, |
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387 | + .iotype = UPIO_MEM, |
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388 | + .regshift = 0, |
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389 | + .uartclk = 18432000, |
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390 | + }, |
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391 | + { }, |
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392 | +}; |
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393 | + |
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394 | +static struct platform_device cambria_optional_uart = { |
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395 | + .name = "serial8250", |
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396 | + .id = PLAT8250_DEV_PLATFORM1, |
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397 | + .dev.platform_data = cambria_optional_uart_data, |
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398 | + .num_resources = 2, |
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399 | + .resource = cambria_optional_uart_resources, |
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400 | +}; |
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401 | + |
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402 | +static struct resource cambria_pata_resources[] = { |
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403 | + { |
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404 | + .flags = IORESOURCE_MEM |
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405 | + }, |
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406 | + { |
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407 | + .flags = IORESOURCE_MEM, |
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408 | + }, |
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409 | + { |
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410 | + .name = "intrq", |
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411 | + .start = IRQ_IXP4XX_GPIO12, |
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412 | + .end = IRQ_IXP4XX_GPIO12, |
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413 | + .flags = IORESOURCE_IRQ, |
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414 | + }, |
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415 | +}; |
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416 | + |
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417 | +static struct ixp4xx_pata_data cambria_pata_data = { |
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418 | + .cs0_bits = 0xbfff3c03, |
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419 | + .cs1_bits = 0xbfff3c03, |
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420 | +}; |
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421 | + |
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422 | +static struct platform_device cambria_pata = { |
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423 | + .name = "pata_ixp4xx_cf", |
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424 | + .id = 0, |
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425 | + .dev.platform_data = &cambria_pata_data, |
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426 | + .num_resources = ARRAY_SIZE(cambria_pata_resources), |
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427 | + .resource = cambria_pata_resources, |
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428 | +}; |
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429 | + |
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430 | +static struct gpio_led cambria_gpio_leds[] = { |
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431 | + { |
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432 | + .name = "user", |
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433 | + .gpio = 5, |
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434 | + .active_low = 1, |
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435 | + }, |
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436 | + { |
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437 | + .name = "user2", |
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438 | + .gpio = 0, |
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439 | + .active_low = 1, |
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440 | + }, |
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441 | + { |
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442 | + .name = "user3", |
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443 | + .gpio = 0, |
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444 | + .active_low = 1, |
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445 | + }, |
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446 | + { |
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447 | + .name = "user4", |
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448 | + .gpio = 0, |
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449 | + .active_low = 1, |
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450 | + } |
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451 | +}; |
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452 | + |
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453 | +static struct gpio_led_platform_data cambria_gpio_leds_data = { |
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454 | + .num_leds = 1, |
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455 | + .leds = cambria_gpio_leds, |
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456 | +}; |
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457 | + |
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458 | +static struct platform_device cambria_gpio_leds_device = { |
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459 | + .name = "leds-gpio", |
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460 | + .id = -1, |
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461 | + .dev.platform_data = &cambria_gpio_leds_data, |
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462 | +}; |
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463 | + |
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464 | +static struct resource cambria_gpio_resources[] = { |
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465 | + { |
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466 | + .name = "gpio", |
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467 | + .flags = 0, |
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468 | + }, |
||
469 | +}; |
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470 | + |
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471 | +static struct gpio cambria_gpios_gw2350[] = { |
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472 | + // ARM GPIO |
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473 | +#if 0 // configured from bootloader |
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474 | + { 0, GPIOF_IN, "ARM_DIO0" }, |
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475 | + { 1, GPIOF_IN, "ARM_DIO1" }, |
||
476 | + { 2, GPIOF_IN, "ARM_DIO2" }, |
||
477 | + { 3, GPIOF_IN, "ARM_DIO3" }, |
||
478 | + { 4, GPIOF_IN, "ARM_DIO4" }, |
||
479 | + { 5, GPIOF_IN, "ARM_DIO5" }, |
||
480 | + { 12, GPIOF_OUT_INIT_HIGH, "WDOGEN#" }, |
||
481 | +#endif |
||
482 | + { 8, GPIOF_IN, "ARM_DIO8" }, |
||
483 | + { 9, GPIOF_IN, "ARM_DIO9" }, |
||
484 | +}; |
||
485 | + |
||
486 | +static struct gpio cambria_gpios_gw2358[] = { |
||
487 | + // ARM GPIO |
||
488 | +#if 0 // configured from bootloader |
||
489 | + { 0, GPIOF_IN, "*VINLOW#" }, |
||
490 | + { 2, GPIOF_IN, "*GPS_PPS" }, |
||
491 | + { 3, GPIOF_IN, "*GPS_IRQ#" }, |
||
492 | + { 4, GPIOF_IN, "*RS485_IRQ#" }, |
||
493 | + { 5, GPIOF_IN, "*SER_EN#" }, |
||
494 | + { 14, GPIOF_OUT_INIT_HIGH, "*WDOGEN#" }, |
||
495 | +#endif |
||
496 | +}; |
||
497 | + |
||
498 | +static struct gpio cambria_gpios_gw2359[] = { |
||
499 | + // ARM GPIO |
||
500 | +#if 0 // configured from bootloader |
||
501 | + { 0, GPIOF_IN, "*PCA_IRQ#" }, |
||
502 | + { 1, GPIOF_IN, "ARM_DIO1" }, |
||
503 | + { 2, GPIOF_IN, "ARM_DIO2" }, |
||
504 | + { 3, GPIOF_IN, "ARM_DIO3" }, |
||
505 | + { 4, GPIOF_IN, "ARM_DIO4" }, |
||
506 | + { 5, GPIOF_IN, "ARM_DIO5" }, |
||
507 | + { 8, GPIOF_OUT_INIT_HIGH, "*WDOGEN#" }, |
||
508 | +#endif |
||
509 | + { 11, GPIOF_OUT_INIT_HIGH, "*SER_EN" }, // console serial enable |
||
510 | + { 12, GPIOF_IN, "*GSC_IRQ#" }, |
||
511 | + { 13, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#"}, |
||
512 | + // GSC GPIO |
||
513 | +#if !(IS_ENABLED(CONFIG_KEYBOARD_GPIO_POLLED)) |
||
514 | + {100, GPIOF_IN, "*USER_PB#" }, |
||
515 | +#endif |
||
516 | + {103, GPIOF_OUT_INIT_HIGH, "*5V_EN" }, // 5V aux supply enable |
||
517 | + {108, GPIOF_IN, "*SMUXDA0" }, |
||
518 | + {109, GPIOF_IN, "*SMUXDA1" }, |
||
519 | + {110, GPIOF_IN, "*SMUXDA2" }, |
||
520 | + {111, GPIOF_IN, "*SMUXDB0" }, |
||
521 | + {112, GPIOF_IN, "*SMUXDB1" }, |
||
522 | + {113, GPIOF_IN, "*SMUXDB2" }, |
||
523 | + // PCA GPIO |
||
524 | + {118, GPIOF_IN, "*USIM2_DET#"}, // USIM2 Detect |
||
525 | + {120, GPIOF_OUT_INIT_LOW, "*USB1_PCI_SEL"}, // USB1 Select (1=PCI, 0=FP) |
||
526 | + {121, GPIOF_OUT_INIT_LOW, "*USB2_PCI_SEL"}, // USB2 Select (1=PCI, 0=FP) |
||
527 | + {122, GPIOF_IN, "*USIM1_DET#"}, // USIM1 Detect |
||
528 | + {123, GPIOF_OUT_INIT_HIGH, "*COM1_DTR#" }, // J21/J10 |
||
529 | + {124, GPIOF_IN, "*COM1_DSR#" }, // J21/J10 |
||
530 | + {127, GPIOF_IN, "PCA_DIO0" }, |
||
531 | + {128, GPIOF_IN, "PCA_DIO1" }, |
||
532 | + {129, GPIOF_IN, "PCA_DIO2" }, |
||
533 | + {130, GPIOF_IN, "PCA_DIO3" }, |
||
534 | + {131, GPIOF_IN, "PCA_DIO4" }, |
||
535 | +}; |
||
536 | + |
||
537 | +static struct gpio cambria_gpios_gw2360[] = { |
||
538 | + // ARM GPIO |
||
539 | + { 0, GPIOF_IN, "*PCA_IRQ#" }, |
||
540 | + { 11, GPIOF_OUT_INIT_LOW, "*SER0_EN#" }, |
||
541 | + { 12, GPIOF_IN, "*GSC_IRQ#" }, |
||
542 | + { 13, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#"}, |
||
543 | + // GSC GPIO |
||
544 | +#if !(IS_ENABLED(CONFIG_KEYBOARD_GPIO_POLLED)) |
||
545 | + {100, GPIOF_IN, "*USER_PB#" }, |
||
546 | +#endif |
||
547 | + {108, GPIOF_OUT_INIT_LOW, "*ENET1_EN#" }, // ENET1 TX Enable |
||
548 | + {109, GPIOF_IN, "*ENET1_PRES#" }, // ENET1 Detect (0=SFP present) |
||
549 | + {110, GPIOF_OUT_INIT_LOW, "*ENET2_EN#" }, // ENET2 TX Enable |
||
550 | + {111, GPIOF_IN, "*ENET2_PRES#"}, // ENET2 Detect (0=SFP present) |
||
551 | + // PCA GPIO |
||
552 | + {116, GPIOF_OUT_INIT_HIGH, "*USIM2_LOC"}, // USIM2 Select (1=Loc, 0=Rem) |
||
553 | + {117, GPIOF_IN, "*USIM2_DET_LOC#" },// USIM2 Detect (Local Slot) |
||
554 | + {118, GPIOF_IN, "*USIM2_DET_REM#" },// USIM2 Detect (Remote Slot) |
||
555 | + {120, GPIOF_OUT_INIT_LOW, "*USB1_PCI_SEL"}, // USB1 Select (1=PCIe1, 0=J1) |
||
556 | + {121, GPIOF_OUT_INIT_LOW, "*USB2_PCI_SEL"}, // USB2 Select (1=PCIe2, 0=J1) |
||
557 | + {122, GPIOF_IN, "*USIM1_DET#"}, // USIM1 Detect |
||
558 | + {127, GPIOF_IN, "DIO0" }, |
||
559 | + {128, GPIOF_IN, "DIO1" }, |
||
560 | + {129, GPIOF_IN, "DIO2" }, |
||
561 | + {130, GPIOF_IN, "DIO3" }, |
||
562 | + {131, GPIOF_IN, "DIO4" }, |
||
563 | +}; |
||
564 | + |
||
565 | +static struct latch_led cambria_latch_leds[] = { |
||
566 | + { |
||
567 | + .name = "ledA", /* green led */ |
||
568 | + .bit = 0, |
||
569 | + }, |
||
570 | + { |
||
571 | + .name = "ledB", /* green led */ |
||
572 | + .bit = 1, |
||
573 | + }, |
||
574 | + { |
||
575 | + .name = "ledC", /* green led */ |
||
576 | + .bit = 2, |
||
577 | + }, |
||
578 | + { |
||
579 | + .name = "ledD", /* green led */ |
||
580 | + .bit = 3, |
||
581 | + }, |
||
582 | + { |
||
583 | + .name = "ledE", /* green led */ |
||
584 | + .bit = 4, |
||
585 | + }, |
||
586 | + { |
||
587 | + .name = "ledF", /* green led */ |
||
588 | + .bit = 5, |
||
589 | + }, |
||
590 | + { |
||
591 | + .name = "ledG", /* green led */ |
||
592 | + .bit = 6, |
||
593 | + }, |
||
594 | + { |
||
595 | + .name = "ledH", /* green led */ |
||
596 | + .bit = 7, |
||
597 | + } |
||
598 | +}; |
||
599 | + |
||
600 | +static struct latch_led_platform_data cambria_latch_leds_data = { |
||
601 | + .num_leds = 8, |
||
602 | + .leds = cambria_latch_leds, |
||
603 | + .mem = 0x53F40000, |
||
604 | +}; |
||
605 | + |
||
606 | +static struct platform_device cambria_latch_leds_device = { |
||
607 | + .name = "leds-latch", |
||
608 | + .id = -1, |
||
609 | + .dev.platform_data = &cambria_latch_leds_data, |
||
610 | +}; |
||
611 | + |
||
612 | +static struct resource cambria_usb0_resources[] = { |
||
613 | + { |
||
614 | + .start = 0xCD000000, |
||
615 | + .end = 0xCD000300, |
||
616 | + .flags = IORESOURCE_MEM, |
||
617 | + }, |
||
618 | + { |
||
619 | + .start = 32, |
||
620 | + .flags = IORESOURCE_IRQ, |
||
621 | + }, |
||
622 | +}; |
||
623 | + |
||
624 | +static struct resource cambria_usb1_resources[] = { |
||
625 | + { |
||
626 | + .start = 0xCE000000, |
||
627 | + .end = 0xCE000300, |
||
628 | + .flags = IORESOURCE_MEM, |
||
629 | + }, |
||
630 | + { |
||
631 | + .start = 33, |
||
632 | + .flags = IORESOURCE_IRQ, |
||
633 | + }, |
||
634 | +}; |
||
635 | + |
||
636 | +static u64 ehci_dma_mask = ~(u32)0; |
||
637 | + |
||
638 | +static struct usb_ehci_pdata cambria_usb_pdata = { |
||
639 | + .big_endian_desc = 1, |
||
640 | + .big_endian_mmio = 1, |
||
641 | + .has_tt = 1, |
||
642 | + .caps_offset = 0x100, |
||
643 | +}; |
||
644 | + |
||
645 | +static struct platform_device cambria_usb0_device = { |
||
646 | + .name = "ehci-platform", |
||
647 | + .id = 0, |
||
648 | + .resource = cambria_usb0_resources, |
||
649 | + .num_resources = ARRAY_SIZE(cambria_usb0_resources), |
||
650 | + .dev = { |
||
651 | + .dma_mask = &ehci_dma_mask, |
||
652 | + .coherent_dma_mask = 0xffffffff, |
||
653 | + .platform_data = &cambria_usb_pdata, |
||
654 | + }, |
||
655 | +}; |
||
656 | + |
||
657 | +static struct platform_device cambria_usb1_device = { |
||
658 | + .name = "ehci-platform", |
||
659 | + .id = 1, |
||
660 | + .resource = cambria_usb1_resources, |
||
661 | + .num_resources = ARRAY_SIZE(cambria_usb1_resources), |
||
662 | + .dev = { |
||
663 | + .dma_mask = &ehci_dma_mask, |
||
664 | + .coherent_dma_mask = 0xffffffff, |
||
665 | + .platform_data = &cambria_usb_pdata, |
||
666 | + }, |
||
667 | +}; |
||
668 | + |
||
669 | +static struct gw_i2c_pld_platform_data gw_i2c_pld_data0 = { |
||
670 | + .gpio_base = 16, |
||
671 | + .nr_gpio = 8, |
||
672 | +}; |
||
673 | + |
||
674 | +static struct gw_i2c_pld_platform_data gw_i2c_pld_data1 = { |
||
675 | + .gpio_base = 24, |
||
676 | + .nr_gpio = 2, |
||
677 | +}; |
||
678 | + |
||
679 | + |
||
680 | +static struct gpio_keys_button cambria_gpio_buttons[] = { |
||
681 | + { |
||
682 | + .desc = "user", |
||
683 | + .type = EV_KEY, |
||
684 | + .code = BTN_0, |
||
685 | + .debounce_interval = 6, |
||
686 | + .gpio = 25, |
||
687 | + } |
||
688 | +}; |
||
689 | + |
||
690 | +static struct gpio_keys_platform_data cambria_gpio_buttons_data = { |
||
691 | + .poll_interval = 500, |
||
692 | + .nbuttons = 1, |
||
693 | + .buttons = cambria_gpio_buttons, |
||
694 | +}; |
||
695 | + |
||
696 | +static struct platform_device cambria_gpio_buttons_device = { |
||
697 | + .name = "gpio-keys-polled", |
||
698 | + .id = -1, |
||
699 | + .dev.platform_data = &cambria_gpio_buttons_data, |
||
700 | +}; |
||
701 | + |
||
702 | +static struct platform_device *cambria_devices[] __initdata = { |
||
703 | + &cambria_i2c_gpio, |
||
704 | + &cambria_flash, |
||
705 | + &cambria_uart, |
||
706 | +}; |
||
707 | + |
||
708 | +static int cambria_register_gpio(struct gpio *array, size_t num) |
||
709 | +{ |
||
710 | + int i, err, ret; |
||
711 | + |
||
712 | + ret = 0; |
||
713 | + for (i = 0; i < num; i++, array++) { |
||
714 | + const char *label = array->label; |
||
715 | + if (label[0] == '*') |
||
716 | + label++; |
||
717 | + err = gpio_request_one(array->gpio, array->flags, label); |
||
718 | + if (err) |
||
719 | + ret = err; |
||
720 | + else { |
||
721 | + err = gpio_export(array->gpio, array->label[0] != '*'); |
||
722 | + } |
||
723 | + } |
||
724 | + return ret; |
||
725 | +} |
||
726 | + |
||
727 | +static void __init cambria_gw23xx_setup(void) |
||
728 | +{ |
||
729 | + cambria_gpio_resources[0].start = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4) |\ |
||
730 | + (1 << 5) | (1 << 8) | (1 << 9) | (1 << 12); |
||
731 | + cambria_gpio_resources[0].end = cambria_gpio_resources[0].start; |
||
732 | + |
||
733 | + platform_device_register(&cambria_npec_device); |
||
734 | + platform_device_register(&cambria_npea_device); |
||
735 | +} |
||
736 | + |
||
737 | +static void __init cambria_gw2350_setup(void) |
||
738 | +{ |
||
739 | + *IXP4XX_EXP_CS2 = 0xBFFF3C43; |
||
740 | + irq_set_irq_type(IRQ_IXP4XX_GPIO3, IRQ_TYPE_EDGE_RISING); |
||
741 | + cambria_optional_uart_data[0].mapbase = 0x52FF0000; |
||
742 | + cambria_optional_uart_data[0].membase = (void __iomem *)ioremap(0x52FF0000, 0x0fff); |
||
743 | + cambria_optional_uart_data[0].irq = IRQ_IXP4XX_GPIO3; |
||
744 | + |
||
745 | + *IXP4XX_EXP_CS3 = 0xBFFF3C43; |
||
746 | + irq_set_irq_type(IRQ_IXP4XX_GPIO4, IRQ_TYPE_EDGE_RISING); |
||
747 | + cambria_optional_uart_data[1].mapbase = 0x53FF0000; |
||
748 | + cambria_optional_uart_data[1].membase = (void __iomem *)ioremap(0x53FF0000, 0x0fff); |
||
749 | + cambria_optional_uart_data[1].irq = IRQ_IXP4XX_GPIO4; |
||
750 | + |
||
751 | + cambria_gpio_resources[0].start = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4) |\ |
||
752 | + (1 << 5) | (1 << 8) | (1 << 9) | (1 << 12); |
||
753 | + cambria_gpio_resources[0].end = cambria_gpio_resources[0].start; |
||
754 | + |
||
755 | + platform_device_register(&cambria_optional_uart); |
||
756 | + platform_device_register(&cambria_npec_device); |
||
757 | + platform_device_register(&cambria_npea_device); |
||
758 | + |
||
759 | + platform_device_register(&cambria_usb0_device); |
||
760 | + platform_device_register(&cambria_usb1_device); |
||
761 | + |
||
762 | + platform_device_register(&cambria_gpio_leds_device); |
||
763 | + |
||
764 | + /* gpio config (/sys/class/gpio) */ |
||
765 | + cambria_register_gpio(ARRAY_AND_SIZE(cambria_gpios_gw2350)); |
||
766 | +} |
||
767 | + |
||
768 | +static void __init cambria_gw2358_setup(void) |
||
769 | +{ |
||
770 | + *IXP4XX_EXP_CS3 = 0xBFFF3C43; // bit0 = 16bit vs 8bit bus |
||
771 | + irq_set_irq_type(IRQ_IXP4XX_GPIO3, IRQ_TYPE_EDGE_RISING); |
||
772 | + cambria_optional_uart_data[0].mapbase = 0x53FC0000; |
||
773 | + cambria_optional_uart_data[0].membase = (void __iomem *)ioremap(0x53FC0000, 0x0fff); |
||
774 | + cambria_optional_uart_data[0].irq = IRQ_IXP4XX_GPIO3; |
||
775 | + |
||
776 | + irq_set_irq_type(IRQ_IXP4XX_GPIO4, IRQ_TYPE_EDGE_RISING); |
||
777 | + cambria_optional_uart_data[1].mapbase = 0x53F80000; |
||
778 | + cambria_optional_uart_data[1].membase = (void __iomem *)ioremap(0x53F80000, 0x0fff); |
||
779 | + cambria_optional_uart_data[1].irq = IRQ_IXP4XX_GPIO4; |
||
780 | + |
||
781 | + cambria_gpio_resources[0].start = (1 << 14) | (1 << 16) | (1 << 17) | (1 << 18) |\ |
||
782 | + (1 << 19) | (1 << 20) | (1 << 24) | (1 << 25); |
||
783 | + cambria_gpio_resources[0].end = cambria_gpio_resources[0].start; |
||
784 | + |
||
785 | + platform_device_register(&cambria_optional_uart); |
||
786 | + |
||
787 | + platform_device_register(&cambria_npec_device); |
||
788 | + platform_device_register(&cambria_npea_device); |
||
789 | + |
||
790 | + platform_device_register(&cambria_usb0_device); |
||
791 | + platform_device_register(&cambria_usb1_device); |
||
792 | + |
||
793 | + platform_device_register(&cambria_pata); |
||
794 | + |
||
795 | + cambria_gpio_leds[0].gpio = 24; |
||
796 | + platform_device_register(&cambria_gpio_leds_device); |
||
797 | + |
||
798 | + platform_device_register(&cambria_latch_leds_device); |
||
799 | + |
||
800 | + platform_device_register(&cambria_gpio_buttons_device); |
||
801 | + |
||
802 | + /* gpio config (/sys/class/gpio) */ |
||
803 | + cambria_register_gpio(ARRAY_AND_SIZE(cambria_gpios_gw2358)); |
||
804 | +} |
||
805 | + |
||
806 | +static void __init cambria_gw2359_setup(void) |
||
807 | +{ |
||
808 | +#if defined(CONFIG_MVSWITCH_PHY) || defined(CONFIG_MVSWITCH_PHY_MODULE) |
||
809 | + /* The mvswitch driver has some hard-coded values which could |
||
810 | + * easily be turned into a platform resource if needed. For now they |
||
811 | + * match our hardware configuration: |
||
812 | + * MV_BASE 0x10 - phy base address |
||
813 | + * MV_WANPORT 0 - Port0 (ENET2) is WAN (SFP module) |
||
814 | + * MV_CPUPORT 5 - Port5 is CPU NPEA (eth1) |
||
815 | + * |
||
816 | + * The mvswitch driver registers a fixup which forces a driver match |
||
817 | + * if phy_addr matches MV_BASE |
||
818 | + * |
||
819 | + * Two static defautl VLAN's are created: WAN port in 1, and all other ports |
||
820 | + * in the other. |
||
821 | + */ |
||
822 | + cambria_npea_data.phy = 0x10; // mvswitch driver catches this |
||
823 | +#else |
||
824 | + // Switch Port5 to CPU is MII<->MII (no PHY) - this disables the genphy driver |
||
825 | + cambria_npea_data.phy = IXP4XX_ETH_PHY_MAX_ADDR; |
||
826 | + // CPU NPE-C is in bridge bypass mode to Port4 PHY@0x14 |
||
827 | + cambria_npec_data.phy = 0x14; |
||
828 | +#endif |
||
829 | + platform_device_register(&cambria_npec_device); |
||
830 | + platform_device_register(&cambria_npea_device); |
||
831 | + |
||
832 | + platform_device_register(&cambria_usb0_device); |
||
833 | + platform_device_register(&cambria_usb1_device); |
||
834 | + |
||
835 | + cambria_gpio_leds_data.num_leds = 3; |
||
836 | + cambria_gpio_leds[0].name = "user1"; |
||
837 | + cambria_gpio_leds[0].gpio = 125; // PNLLED1# |
||
838 | + cambria_gpio_leds[1].gpio = 126; // PNLLED3# |
||
839 | + cambria_gpio_leds[2].gpio = 119; // PNLLED4# |
||
840 | + platform_device_register(&cambria_gpio_leds_device); |
||
841 | + |
||
842 | +#if (IS_ENABLED(CONFIG_KEYBOARD_GPIO_POLLED)) |
||
843 | + cambria_gpio_buttons[0].gpio = 100; |
||
844 | + platform_device_register(&cambria_gpio_buttons_device); |
||
845 | +#endif |
||
846 | + |
||
847 | + /* gpio config (/sys/class/gpio) */ |
||
848 | + cambria_register_gpio(ARRAY_AND_SIZE(cambria_gpios_gw2359)); |
||
849 | +} |
||
850 | + |
||
851 | +static void __init cambria_gw2360_setup(void) |
||
852 | +{ |
||
853 | + /* The GW2360 has 8 UARTs in addition to the 1 IXP4xxx UART. |
||
854 | + * The chip-selects are expanded via a 3-to-8 decoder and CS2 |
||
855 | + * and they are 8bit devices |
||
856 | + */ |
||
857 | + *IXP4XX_EXP_CS2 = 0xBFFF3C43; |
||
858 | + cambria_optional_uart_data[0].mapbase = 0x52000000; |
||
859 | + cambria_optional_uart_data[0].membase = (void __iomem *)ioremap(0x52000000, 0x0fff); |
||
860 | + cambria_optional_uart_data[0].uartclk = 18432000; |
||
861 | + cambria_optional_uart_data[0].iotype = UPIO_MEM; |
||
862 | + cambria_optional_uart_data[0].irq = IRQ_IXP4XX_GPIO2; |
||
863 | + irq_set_irq_type(IRQ_IXP4XX_GPIO2, IRQ_TYPE_EDGE_RISING); |
||
864 | + |
||
865 | + cambria_optional_uart_data[1].mapbase = 0x52000008; |
||
866 | + cambria_optional_uart_data[1].membase = (void __iomem *)ioremap(0x52000008, 0x0fff); |
||
867 | + cambria_optional_uart_data[1].uartclk = 18432000; |
||
868 | + cambria_optional_uart_data[1].iotype = UPIO_MEM; |
||
869 | + cambria_optional_uart_data[1].irq = IRQ_IXP4XX_GPIO3; |
||
870 | + irq_set_irq_type(IRQ_IXP4XX_GPIO3, IRQ_TYPE_EDGE_RISING); |
||
871 | + |
||
872 | + cambria_optional_uart_data[2].mapbase = 0x52000010; |
||
873 | + cambria_optional_uart_data[2].membase = (void __iomem *)ioremap(0x52000010, 0x0fff); |
||
874 | + cambria_optional_uart_data[2].uartclk = 18432000; |
||
875 | + cambria_optional_uart_data[2].iotype = UPIO_MEM; |
||
876 | + cambria_optional_uart_data[2].irq = IRQ_IXP4XX_GPIO4; |
||
877 | + irq_set_irq_type(IRQ_IXP4XX_GPIO4, IRQ_TYPE_EDGE_RISING); |
||
878 | + |
||
879 | + cambria_optional_uart_data[3].mapbase = 0x52000018; |
||
880 | + cambria_optional_uart_data[3].membase = (void __iomem *)ioremap(0x52000018, 0x0fff); |
||
881 | + cambria_optional_uart_data[3].uartclk = 18432000; |
||
882 | + cambria_optional_uart_data[3].iotype = UPIO_MEM; |
||
883 | + cambria_optional_uart_data[3].irq = IRQ_IXP4XX_GPIO5; |
||
884 | + irq_set_irq_type(IRQ_IXP4XX_GPIO5, IRQ_TYPE_EDGE_RISING); |
||
885 | + |
||
886 | + cambria_optional_uart_data[4].mapbase = 0x52000020; |
||
887 | + cambria_optional_uart_data[4].membase = (void __iomem *)ioremap(0x52000020, 0x0fff); |
||
888 | + cambria_optional_uart_data[4].uartclk = 18432000; |
||
889 | + cambria_optional_uart_data[4].iotype = UPIO_MEM; |
||
890 | + cambria_optional_uart_data[4].irq = IRQ_IXP4XX_GPIO8; |
||
891 | + irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_EDGE_RISING); |
||
892 | + |
||
893 | + cambria_optional_uart_data[5].mapbase = 0x52000028; |
||
894 | + cambria_optional_uart_data[5].membase = (void __iomem *)ioremap(0x52000028, 0x0fff); |
||
895 | + cambria_optional_uart_data[5].uartclk = 18432000; |
||
896 | + cambria_optional_uart_data[5].iotype = UPIO_MEM; |
||
897 | + cambria_optional_uart_data[5].irq = IRQ_IXP4XX_GPIO9; |
||
898 | + irq_set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_EDGE_RISING); |
||
899 | + |
||
900 | + cambria_optional_uart_data[6].mapbase = 0x52000030; |
||
901 | + cambria_optional_uart_data[6].membase = (void __iomem *)ioremap(0x52000030, 0x0fff); |
||
902 | + cambria_optional_uart_data[6].uartclk = 18432000; |
||
903 | + cambria_optional_uart_data[6].iotype = UPIO_MEM; |
||
904 | + cambria_optional_uart_data[6].irq = IRQ_IXP4XX_GPIO10; |
||
905 | + irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_EDGE_RISING); |
||
906 | + |
||
907 | + cambria_optional_uart.num_resources = 7, |
||
908 | + platform_device_register(&cambria_optional_uart); |
||
909 | + |
||
910 | +#if defined(CONFIG_MVSWITCH_PHY) || defined(CONFIG_MVSWITCH_PHY_MODULE) |
||
911 | + /* The mvswitch driver has some hard-coded values which could |
||
912 | + * easily be turned into a platform resource if needed. For now they |
||
913 | + * match our hardware configuration: |
||
914 | + * MV_BASE 0x10 - phy base address |
||
915 | + * MV_WANPORT 0 - Port0 (ENET2) is WAN (SFP module) |
||
916 | + * MV_CPUPORT 5 - Port5 is CPU NPEA (eth1) |
||
917 | + * |
||
918 | + * The mvswitch driver registers a fixup which forces a driver match |
||
919 | + * if phy_addr matches MV_BASE |
||
920 | + * |
||
921 | + * Two static defautl VLAN's are created: WAN port in 1, and all other ports |
||
922 | + * in the other. |
||
923 | + */ |
||
924 | + cambria_npea_data.phy = 0x10; // mvswitch driver catches this |
||
925 | +#else |
||
926 | + // Switch Port5 to CPU is MII<->MII (no PHY) - this disables the generic PHY driver |
||
927 | + cambria_npea_data.phy = IXP4XX_ETH_PHY_MAX_ADDR; |
||
928 | +#endif |
||
929 | + |
||
930 | + // disable genphy autonegotiation on NPE-C PHY (eth1) as its 100BaseFX |
||
931 | + //cambria_npec_data.noautoneg = 1; // disable autoneg |
||
932 | + cambria_npec_data.speed_10 = 0; // 100mbps |
||
933 | + cambria_npec_data.half_duplex = 0; // full-duplex |
||
934 | + platform_device_register(&cambria_npec_device); |
||
935 | + platform_device_register(&cambria_npea_device); |
||
936 | + |
||
937 | + platform_device_register(&cambria_usb0_device); |
||
938 | + platform_device_register(&cambria_usb1_device); |
||
939 | + |
||
940 | + cambria_gpio_leds_data.num_leds = 3; |
||
941 | + cambria_gpio_leds[0].name = "user1"; |
||
942 | + cambria_gpio_leds[0].gpio = 125; |
||
943 | + cambria_gpio_leds[1].gpio = 126; |
||
944 | + cambria_gpio_leds[2].gpio = 119; |
||
945 | + platform_device_register(&cambria_gpio_leds_device); |
||
946 | + |
||
947 | +#if (IS_ENABLED(CONFIG_KEYBOARD_GPIO_POLLED)) |
||
948 | + cambria_gpio_buttons[0].gpio = 100; |
||
949 | + platform_device_register(&cambria_gpio_buttons_device); |
||
950 | +#endif |
||
951 | + |
||
952 | +#ifdef SFP_SERIALID |
||
953 | + /* the SFP modules each have an i2c bus for serial ident via GSC GPIO |
||
954 | + * To use these the i2c-gpio driver must be changed to use the _cansleep |
||
955 | + * varients of gpio_get_value/gpio_set_value (I don't know why it doesn't |
||
956 | + * use that anyway as it doesn't operate in an IRQ context). |
||
957 | + * Additionally the i2c-gpio module must set the gpio to output-high prior |
||
958 | + * to changing direction to an input to enable internal Pullups |
||
959 | + */ |
||
960 | + platform_device_register(&cambria_i2c_gpio_sfpa); |
||
961 | + platform_device_register(&cambria_i2c_gpio_sfpb); |
||
962 | +#endif |
||
963 | + |
||
964 | + /* gpio config (/sys/class/gpio) */ |
||
965 | + cambria_register_gpio(ARRAY_AND_SIZE(cambria_gpios_gw2360)); |
||
966 | +} |
||
967 | + |
||
968 | +static struct cambria_board_info cambria_boards[] __initdata = { |
||
969 | + { |
||
970 | + .model = "GW2350", |
||
971 | + .setup = cambria_gw2350_setup, |
||
972 | + }, { |
||
973 | + .model = "GW2351", |
||
974 | + .setup = cambria_gw2350_setup, |
||
975 | + }, { |
||
976 | + .model = "GW2358", |
||
977 | + .setup = cambria_gw2358_setup, |
||
978 | + }, { |
||
979 | + .model = "GW2359", |
||
980 | + .setup = cambria_gw2359_setup, |
||
981 | + }, { |
||
982 | + .model = "GW2360", |
||
983 | + .setup = cambria_gw2360_setup, |
||
984 | + }, { |
||
985 | + .model = "GW2371", |
||
986 | + .setup = cambria_gw2358_setup, |
||
987 | + } |
||
988 | +}; |
||
989 | + |
||
990 | +static struct cambria_board_info * __init cambria_find_board_info(char *model) |
||
991 | +{ |
||
992 | + int i; |
||
993 | + model[6] = '\0'; |
||
994 | + |
||
995 | + for (i = 0; i < ARRAY_SIZE(cambria_boards); i++) { |
||
996 | + struct cambria_board_info *info = &cambria_boards[i]; |
||
997 | + if (strcmp(info->model, model) == 0) |
||
998 | + return info; |
||
999 | + } |
||
1000 | + |
||
1001 | + return NULL; |
||
1002 | +} |
||
1003 | + |
||
1004 | +static struct nvmem_device *at24_nvmem; |
||
1005 | + |
||
1006 | +static void at24_setup(struct nvmem_device *mem_acc, void *context) |
||
1007 | +{ |
||
1008 | + char mac_addr[ETH_ALEN]; |
||
1009 | + char model[7]; |
||
1010 | + |
||
1011 | + at24_nvmem = mem_acc; |
||
1012 | + |
||
1013 | + /* Read MAC addresses */ |
||
1014 | + if (nvmem_device_read(at24_nvmem, 0x0, 6, mac_addr) == 6) { |
||
1015 | + memcpy(&cambria_npec_data.hwaddr, mac_addr, ETH_ALEN); |
||
1016 | + } |
||
1017 | + if (nvmem_device_read(at24_nvmem, 0x6, 6, mac_addr) == 6) { |
||
1018 | + memcpy(&cambria_npea_data.hwaddr, mac_addr, ETH_ALEN); |
||
1019 | + } |
||
1020 | + |
||
1021 | + /* Read the first 6 bytes of the model number */ |
||
1022 | + if (nvmem_device_read(at24_nvmem, 0x20, 6, model) == 6) { |
||
1023 | + cambria_info = cambria_find_board_info(model); |
||
1024 | + } |
||
1025 | + |
||
1026 | +} |
||
1027 | + |
||
1028 | +static struct at24_platform_data cambria_eeprom_info = { |
||
1029 | + .byte_len = 1024, |
||
1030 | + .page_size = 16, |
||
1031 | + .flags = AT24_FLAG_READONLY, |
||
1032 | + .setup = at24_setup, |
||
1033 | +}; |
||
1034 | + |
||
1035 | +static struct pca953x_platform_data cambria_pca_data = { |
||
1036 | + .gpio_base = 100, |
||
1037 | + .irq_base = -1, |
||
1038 | +}; |
||
1039 | + |
||
1040 | +static struct pca953x_platform_data cambria_pca2_data = { |
||
1041 | + .gpio_base = 116, |
||
1042 | + .irq_base = -1, |
||
1043 | +}; |
||
1044 | + |
||
1045 | +static struct i2c_board_info __initdata cambria_i2c_board_info[] = { |
||
1046 | + { |
||
1047 | + I2C_BOARD_INFO("pca9555", 0x23), |
||
1048 | + .platform_data = &cambria_pca_data, |
||
1049 | + }, |
||
1050 | + { |
||
1051 | + I2C_BOARD_INFO("pca9555", 0x27), |
||
1052 | + .platform_data = &cambria_pca2_data, |
||
1053 | + }, |
||
1054 | + { |
||
1055 | + I2C_BOARD_INFO("ds1672", 0x68), |
||
1056 | + }, |
||
1057 | + { |
||
1058 | + I2C_BOARD_INFO("gsp", 0x29), |
||
1059 | + }, |
||
1060 | + { |
||
1061 | + I2C_BOARD_INFO("ad7418", 0x28), |
||
1062 | + }, |
||
1063 | + { |
||
1064 | + I2C_BOARD_INFO("24c08", 0x51), |
||
1065 | + .platform_data = &cambria_eeprom_info |
||
1066 | + }, |
||
1067 | + { |
||
1068 | + I2C_BOARD_INFO("gw_i2c_pld", 0x56), |
||
1069 | + .platform_data = &gw_i2c_pld_data0, |
||
1070 | + }, |
||
1071 | + { |
||
1072 | + I2C_BOARD_INFO("gw_i2c_pld", 0x57), |
||
1073 | + .platform_data = &gw_i2c_pld_data1, |
||
1074 | + }, |
||
1075 | +}; |
||
1076 | + |
||
1077 | +static void __init cambria_init(void) |
||
1078 | +{ |
||
1079 | + ixp4xx_sys_init(); |
||
1080 | + |
||
1081 | + cambria_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); |
||
1082 | + cambria_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1; |
||
1083 | + |
||
1084 | + *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE; // make sure window is writable |
||
1085 | + *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0; |
||
1086 | + |
||
1087 | + platform_add_devices(ARRAY_AND_SIZE(cambria_devices)); |
||
1088 | + |
||
1089 | + cambria_pata_resources[0].start = 0x53e00000; |
||
1090 | + cambria_pata_resources[0].end = 0x53e3ffff; |
||
1091 | + |
||
1092 | + cambria_pata_resources[1].start = 0x53e40000; |
||
1093 | + cambria_pata_resources[1].end = 0x53e7ffff; |
||
1094 | + |
||
1095 | + cambria_pata_data.cs0_cfg = IXP4XX_EXP_CS3; |
||
1096 | + cambria_pata_data.cs1_cfg = IXP4XX_EXP_CS3; |
||
1097 | + |
||
1098 | + i2c_register_board_info(0, ARRAY_AND_SIZE(cambria_i2c_board_info)); |
||
1099 | +} |
||
1100 | + |
||
1101 | +static int __init cambria_model_setup(void) |
||
1102 | +{ |
||
1103 | + if (!machine_is_cambria()) |
||
1104 | + return 0; |
||
1105 | + |
||
1106 | + if (cambria_info) { |
||
1107 | + printk(KERN_DEBUG "Running on Gateworks Cambria %s\n", |
||
1108 | + cambria_info->model); |
||
1109 | + cambria_info->setup(); |
||
1110 | + } else { |
||
1111 | + printk(KERN_INFO "Unknown/missing Cambria model number" |
||
1112 | + " -- defaults will be used\n"); |
||
1113 | + cambria_gw23xx_setup(); |
||
1114 | + } |
||
1115 | + |
||
1116 | + return 0; |
||
1117 | +} |
||
1118 | +late_initcall(cambria_model_setup); |
||
1119 | + |
||
1120 | +MACHINE_START(CAMBRIA, "Gateworks Cambria series") |
||
1121 | + /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */ |
||
1122 | + .map_io = ixp4xx_map_io, |
||
1123 | + .init_irq = ixp4xx_init_irq, |
||
1124 | + .init_time = ixp4xx_timer_init, |
||
1125 | + .atag_offset = 0x0100, |
||
1126 | + .init_machine = cambria_init, |
||
1127 | +#if defined(CONFIG_PCI) |
||
1128 | + .dma_zone_size = SZ_64M, |
||
1129 | +#endif |
||
1130 | + .restart = ixp4xx_restart, |
||
1131 | +MACHINE_END |