OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | /* |
2 | * ADM6996 switch driver |
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3 | * |
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4 | * Copyright (c) 2008 Felix Fietkau <nbd@nbd.name> |
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5 | * Copyright (c) 2010,2011 Peter Lebbing <peter@digitalbrains.com> |
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6 | * |
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7 | * This program is free software; you can redistribute it and/or modify it |
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8 | * under the terms of the GNU General Public License v2 as published by the |
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9 | * Free Software Foundation |
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10 | */ |
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11 | #ifndef __ADM6996_H |
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12 | #define __ADM6996_H |
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13 | |||
14 | /* |
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15 | * ADM_PHY_PORTS: Number of ports with a PHY. |
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16 | * We only control ports 0 to 3, because if 4 is connected, it is most likely |
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17 | * not connected to the switch but to a separate MII and MAC for the WAN port. |
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18 | */ |
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19 | #define ADM_PHY_PORTS 4 |
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20 | #define ADM_NUM_PORTS 6 |
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21 | #define ADM_CPU_PORT 5 |
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22 | |||
23 | #define ADM_NUM_VLANS 16 |
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24 | #define ADM_VLAN_MAX_ID 4094 |
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25 | |||
26 | enum admreg { |
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27 | ADM_EEPROM_BASE = 0x0, |
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28 | ADM_P0_CFG = ADM_EEPROM_BASE + 1, |
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29 | ADM_P1_CFG = ADM_EEPROM_BASE + 3, |
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30 | ADM_P2_CFG = ADM_EEPROM_BASE + 5, |
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31 | ADM_P3_CFG = ADM_EEPROM_BASE + 7, |
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32 | ADM_P4_CFG = ADM_EEPROM_BASE + 8, |
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33 | ADM_P5_CFG = ADM_EEPROM_BASE + 9, |
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34 | ADM_SYSC0 = ADM_EEPROM_BASE + 0xa, |
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35 | ADM_VLAN_PRIOMAP = ADM_EEPROM_BASE + 0xe, |
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36 | ADM_SYSC3 = ADM_EEPROM_BASE + 0x11, |
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37 | /* Input Force No Tag Enable */ |
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38 | ADM_IFNTE = ADM_EEPROM_BASE + 0x20, |
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39 | ADM_VID_CHECK = ADM_EEPROM_BASE + 0x26, |
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40 | ADM_P0_PVID = ADM_EEPROM_BASE + 0x28, |
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41 | ADM_P1_PVID = ADM_EEPROM_BASE + 0x29, |
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42 | /* Output Tag Bypass Enable and P2 PVID */ |
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43 | ADM_OTBE_P2_PVID = ADM_EEPROM_BASE + 0x2a, |
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44 | ADM_P3_P4_PVID = ADM_EEPROM_BASE + 0x2b, |
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45 | ADM_P5_PVID = ADM_EEPROM_BASE + 0x2c, |
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46 | ADM_EEPROM_EXT_BASE = 0x40, |
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47 | #define ADM_VLAN_FILT_L(n) (ADM_EEPROM_EXT_BASE + 2 * (n)) |
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48 | #define ADM_VLAN_FILT_H(n) (ADM_EEPROM_EXT_BASE + 1 + 2 * (n)) |
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49 | #define ADM_VLAN_MAP(n) (ADM_EEPROM_BASE + 0x13 + n) |
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50 | ADM_COUNTER_BASE = 0xa0, |
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51 | ADM_SIG0 = ADM_COUNTER_BASE + 0, |
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52 | ADM_SIG1 = ADM_COUNTER_BASE + 1, |
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53 | ADM_PS0 = ADM_COUNTER_BASE + 2, |
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54 | ADM_PS1 = ADM_COUNTER_BASE + 3, |
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55 | ADM_PS2 = ADM_COUNTER_BASE + 4, |
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56 | ADM_CL0 = ADM_COUNTER_BASE + 8, /* RxPacket */ |
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57 | ADM_CL6 = ADM_COUNTER_BASE + 0x1a, /* RxByte */ |
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58 | ADM_CL12 = ADM_COUNTER_BASE + 0x2c, /* TxPacket */ |
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59 | ADM_CL18 = ADM_COUNTER_BASE + 0x3e, /* TxByte */ |
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60 | ADM_CL24 = ADM_COUNTER_BASE + 0x50, /* Coll */ |
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61 | ADM_CL30 = ADM_COUNTER_BASE + 0x62, /* Err */ |
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62 | #define ADM_OFFSET_PORT(n) ((n * 4) - (n / 4) * 2 - (n / 5) * 2) |
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63 | ADM_PHY_BASE = 0x200, |
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64 | #define ADM_PHY_PORT(n) (ADM_PHY_BASE + (0x20 * n)) |
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65 | }; |
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66 | |||
67 | /* Chip identification patterns */ |
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68 | #define ADM_SIG0_MASK 0xffff |
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69 | #define ADM_SIG0_VAL 0x1023 |
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70 | #define ADM_SIG1_MASK 0xffff |
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71 | #define ADM_SIG1_VAL 0x0007 |
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72 | |||
73 | enum { |
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74 | ADM_PHYCFG_COLTST = (1 << 7), /* Enable collision test */ |
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75 | ADM_PHYCFG_DPLX = (1 << 8), /* Enable full duplex */ |
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76 | ADM_PHYCFG_ANEN_RST = (1 << 9), /* Restart auto negotiation (self clear) */ |
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77 | ADM_PHYCFG_ISO = (1 << 10), /* Isolate PHY */ |
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78 | ADM_PHYCFG_PDN = (1 << 11), /* Power down PHY */ |
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79 | ADM_PHYCFG_ANEN = (1 << 12), /* Enable auto negotiation */ |
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80 | ADM_PHYCFG_SPEED_100 = (1 << 13), /* Enable 100 Mbit/s */ |
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81 | ADM_PHYCFG_LPBK = (1 << 14), /* Enable loopback operation */ |
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82 | ADM_PHYCFG_RST = (1 << 15), /* Reset the port (self clear) */ |
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83 | ADM_PHYCFG_INIT = ( |
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84 | ADM_PHYCFG_RST | |
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85 | ADM_PHYCFG_SPEED_100 | |
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86 | ADM_PHYCFG_ANEN | |
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87 | ADM_PHYCFG_ANEN_RST |
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88 | ) |
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89 | }; |
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90 | |||
91 | enum { |
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92 | ADM_PORTCFG_FC = (1 << 0), /* Enable 802.x flow control */ |
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93 | ADM_PORTCFG_AN = (1 << 1), /* Enable auto-negotiation */ |
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94 | ADM_PORTCFG_SPEED_100 = (1 << 2), /* Enable 100 Mbit/s */ |
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95 | ADM_PORTCFG_DPLX = (1 << 3), /* Enable full duplex */ |
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96 | ADM_PORTCFG_OT = (1 << 4), /* Output tagged packets */ |
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97 | ADM_PORTCFG_PD = (1 << 5), /* Port disable */ |
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98 | ADM_PORTCFG_TV_PRIO = (1 << 6), /* 0 = VLAN based priority |
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99 | * 1 = TOS based priority */ |
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100 | ADM_PORTCFG_PPE = (1 << 7), /* Port based priority enable */ |
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101 | ADM_PORTCFG_PP_S = (1 << 8), /* Port based priority, 2 bits */ |
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102 | ADM_PORTCFG_PVID_BASE = (1 << 10), /* Primary VLAN id, 4 bits */ |
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103 | ADM_PORTCFG_FSE = (1 << 14), /* Fx select enable */ |
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104 | ADM_PORTCFG_CAM = (1 << 15), /* Crossover Auto MDIX */ |
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105 | |||
106 | ADM_PORTCFG_INIT = ( |
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107 | ADM_PORTCFG_FC | |
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108 | ADM_PORTCFG_AN | |
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109 | ADM_PORTCFG_SPEED_100 | |
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110 | ADM_PORTCFG_DPLX | |
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111 | ADM_PORTCFG_CAM |
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112 | ), |
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113 | ADM_PORTCFG_CPU = ( |
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114 | ADM_PORTCFG_FC | |
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115 | ADM_PORTCFG_SPEED_100 | |
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116 | ADM_PORTCFG_OT | |
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117 | ADM_PORTCFG_DPLX |
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118 | ), |
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119 | }; |
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120 | |||
121 | #define ADM_PORTCFG_PPID(n) ((n & 0x3) << 8) |
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122 | #define ADM_PORTCFG_PVID(n) ((n & 0xf) << 10) |
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123 | #define ADM_PORTCFG_PVID_MASK (0xf << 10) |
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124 | |||
125 | #define ADM_IFNTE_MASK (0x3f << 9) |
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126 | #define ADM_VID_CHECK_MASK (0x3f << 6) |
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127 | |||
128 | #define ADM_P0_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 0) |
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129 | #define ADM_P1_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 0) |
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130 | #define ADM_P2_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 0) |
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131 | #define ADM_P3_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 0) |
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132 | #define ADM_P4_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 8) |
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133 | #define ADM_P5_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 0) |
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134 | #define ADM_P2_PVID_MASK 0xff |
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135 | |||
136 | #define ADM_OTBE(n) (((n) & 0x3f) << 8) |
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137 | #define ADM_OTBE_MASK (0x3f << 8) |
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138 | |||
139 | /* ADM_SYSC0 */ |
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140 | enum { |
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141 | ADM_NTTE = (1 << 2), /* New Tag Transmit Enable */ |
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142 | ADM_RVID1 = (1 << 8) /* Replace VLAN ID 1 */ |
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143 | }; |
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144 | |||
145 | /* Tag Based VLAN in ADM_SYSC3 */ |
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146 | #define ADM_MAC_CLONE BIT(4) |
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147 | #define ADM_TBV BIT(5) |
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148 | |||
149 | static const u8 adm_portcfg[] = { |
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150 | [0] = ADM_P0_CFG, |
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151 | [1] = ADM_P1_CFG, |
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152 | [2] = ADM_P2_CFG, |
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153 | [3] = ADM_P3_CFG, |
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154 | [4] = ADM_P4_CFG, |
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155 | [5] = ADM_P5_CFG, |
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156 | }; |
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157 | |||
158 | /* Fields in ADM_VLAN_FILT_L(x) */ |
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159 | #define ADM_VLAN_FILT_FID(n) (((n) & 0xf) << 12) |
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160 | #define ADM_VLAN_FILT_TAGGED(n) (((n) & 0x3f) << 6) |
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161 | #define ADM_VLAN_FILT_MEMBER(n) (((n) & 0x3f) << 0) |
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162 | #define ADM_VLAN_FILT_MEMBER_MASK 0x3f |
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163 | /* Fields in ADM_VLAN_FILT_H(x) */ |
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164 | #define ADM_VLAN_FILT_VALID (1 << 15) |
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165 | #define ADM_VLAN_FILT_VID(n) (((n) & 0xfff) << 0) |
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166 | |||
167 | /* Convert ports to a form for ADM6996L VLAN map */ |
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168 | #define ADM_VLAN_FILT(ports) ((ports & 0x01) | ((ports & 0x02) << 1) | \ |
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169 | ((ports & 0x04) << 2) | ((ports & 0x08) << 3) | \ |
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170 | ((ports & 0x10) << 3) | ((ports & 0x20) << 3)) |
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171 | |||
172 | /* Port status register */ |
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173 | enum { |
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174 | ADM_PS_LS = (1 << 0), /* Link status */ |
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175 | ADM_PS_SS = (1 << 1), /* Speed status */ |
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176 | ADM_PS_DS = (1 << 2), /* Duplex status */ |
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177 | ADM_PS_FCS = (1 << 3) /* Flow control status */ |
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178 | }; |
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179 | |||
180 | /* |
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181 | * Split the register address in phy id and register |
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182 | * it will get combined again by the mdio bus op |
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183 | */ |
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184 | #define PHYADDR(_reg) ((_reg >> 5) & 0xff), (_reg & 0x1f) |
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185 | |||
186 | #endif |